Commit | Line | Data |
---|---|---|
2f9f7628 | 1 | /* |
fa0a8c71 | 2 | * MTD SPI driver for ST M25Pxx (and similar) serial flash chips |
2f9f7628 ML |
3 | * |
4 | * Author: Mike Lavender, mike@steroidmicros.com | |
5 | * | |
6 | * Copyright (c) 2005, Intec Automation Inc. | |
7 | * | |
8 | * Some parts are based on lart.c by Abraham Van Der Merwe | |
9 | * | |
10 | * Cleaned up and generalized based on mtd_dataflash.c | |
11 | * | |
12 | * This code is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | * | |
16 | */ | |
17 | ||
18 | #include <linux/init.h> | |
9d2c4f3f AV |
19 | #include <linux/err.h> |
20 | #include <linux/errno.h> | |
2f9f7628 ML |
21 | #include <linux/module.h> |
22 | #include <linux/device.h> | |
23 | #include <linux/interrupt.h> | |
7d5230ea | 24 | #include <linux/mutex.h> |
d85316ac | 25 | #include <linux/math64.h> |
5a0e3ad6 | 26 | #include <linux/slab.h> |
d43c36dc | 27 | #include <linux/sched.h> |
b34bc037 | 28 | #include <linux/mod_devicetable.h> |
7d5230ea | 29 | |
aa084653 | 30 | #include <linux/mtd/cfi.h> |
2f9f7628 ML |
31 | #include <linux/mtd/mtd.h> |
32 | #include <linux/mtd/partitions.h> | |
5f949137 | 33 | #include <linux/of_platform.h> |
7d5230ea | 34 | |
2f9f7628 ML |
35 | #include <linux/spi/spi.h> |
36 | #include <linux/spi/flash.h> | |
37 | ||
2f9f7628 | 38 | /* Flash opcodes. */ |
fa0a8c71 DB |
39 | #define OPCODE_WREN 0x06 /* Write enable */ |
40 | #define OPCODE_RDSR 0x05 /* Read status register */ | |
72289824 | 41 | #define OPCODE_WRSR 0x01 /* Write status register 1 byte */ |
2230b76b | 42 | #define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */ |
fa0a8c71 DB |
43 | #define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */ |
44 | #define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */ | |
7854643a | 45 | #define OPCODE_BE_4K 0x20 /* Erase 4KiB block */ |
02d087db | 46 | #define OPCODE_BE_32K 0x52 /* Erase 32KiB block */ |
7854643a | 47 | #define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */ |
02d087db | 48 | #define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */ |
2f9f7628 ML |
49 | #define OPCODE_RDID 0x9f /* Read JEDEC ID */ |
50 | ||
87c9511f BN |
51 | /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */ |
52 | #define OPCODE_NORM_READ_4B 0x13 /* Read data bytes (low frequency) */ | |
53 | #define OPCODE_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */ | |
54 | #define OPCODE_PP_4B 0x12 /* Page program (up to 256 bytes) */ | |
55 | #define OPCODE_SE_4B 0xdc /* Sector erase (usually 64KiB) */ | |
56 | ||
49aac4ae GY |
57 | /* Used for SST flashes only. */ |
58 | #define OPCODE_BP 0x02 /* Byte program */ | |
59 | #define OPCODE_WRDI 0x04 /* Write disable */ | |
60 | #define OPCODE_AAI_WP 0xad /* Auto address increment word program */ | |
61 | ||
caddab0f | 62 | /* Used for Macronix and Winbond flashes. */ |
4b7f7422 KC |
63 | #define OPCODE_EN4B 0xb7 /* Enter 4-byte mode */ |
64 | #define OPCODE_EX4B 0xe9 /* Exit 4-byte mode */ | |
65 | ||
baa9ae3c KC |
66 | /* Used for Spansion flashes only. */ |
67 | #define OPCODE_BRWR 0x17 /* Bank register write */ | |
68 | ||
2f9f7628 ML |
69 | /* Status Register bits. */ |
70 | #define SR_WIP 1 /* Write in progress */ | |
71 | #define SR_WEL 2 /* Write enable latch */ | |
fa0a8c71 | 72 | /* meaning of other SR_* bits may differ between vendors */ |
2f9f7628 ML |
73 | #define SR_BP0 4 /* Block protect 0 */ |
74 | #define SR_BP1 8 /* Block protect 1 */ | |
75 | #define SR_BP2 0x10 /* Block protect 2 */ | |
76 | #define SR_SRWD 0x80 /* SR write protect */ | |
77 | ||
78 | /* Define max times to check status register before we give up. */ | |
89bb871e | 79 | #define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */ |
4b7f7422 | 80 | #define MAX_CMD_SIZE 5 |
2f9f7628 | 81 | |
aa084653 KC |
82 | #define JEDEC_MFR(_jedec_id) ((_jedec_id) >> 16) |
83 | ||
2f9f7628 ML |
84 | /****************************************************************************/ |
85 | ||
86 | struct m25p { | |
87 | struct spi_device *spi; | |
7d5230ea | 88 | struct mutex lock; |
2f9f7628 | 89 | struct mtd_info mtd; |
837479d2 AV |
90 | u16 page_size; |
91 | u16 addr_width; | |
fa0a8c71 | 92 | u8 erase_opcode; |
87c9511f BN |
93 | u8 read_opcode; |
94 | u8 program_opcode; | |
61c3506c | 95 | u8 *command; |
12ad2be9 | 96 | bool fast_read; |
2f9f7628 ML |
97 | }; |
98 | ||
99 | static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd) | |
100 | { | |
101 | return container_of(mtd, struct m25p, mtd); | |
102 | } | |
103 | ||
104 | /****************************************************************************/ | |
105 | ||
106 | /* | |
107 | * Internal helper functions | |
108 | */ | |
109 | ||
110 | /* | |
111 | * Read the status register, returning its value in the location | |
112 | * Return the status register value. | |
113 | * Returns negative if error occurred. | |
114 | */ | |
115 | static int read_sr(struct m25p *flash) | |
116 | { | |
117 | ssize_t retval; | |
118 | u8 code = OPCODE_RDSR; | |
119 | u8 val; | |
120 | ||
121 | retval = spi_write_then_read(flash->spi, &code, 1, &val, 1); | |
122 | ||
123 | if (retval < 0) { | |
124 | dev_err(&flash->spi->dev, "error %d reading SR\n", | |
125 | (int) retval); | |
126 | return retval; | |
127 | } | |
128 | ||
129 | return val; | |
130 | } | |
131 | ||
72289824 MH |
132 | /* |
133 | * Write status register 1 byte | |
134 | * Returns negative if error occurred. | |
135 | */ | |
136 | static int write_sr(struct m25p *flash, u8 val) | |
137 | { | |
138 | flash->command[0] = OPCODE_WRSR; | |
139 | flash->command[1] = val; | |
140 | ||
141 | return spi_write(flash->spi, flash->command, 2); | |
142 | } | |
2f9f7628 ML |
143 | |
144 | /* | |
145 | * Set write enable latch with Write Enable command. | |
146 | * Returns negative if error occurred. | |
147 | */ | |
148 | static inline int write_enable(struct m25p *flash) | |
149 | { | |
150 | u8 code = OPCODE_WREN; | |
151 | ||
8a1a6272 | 152 | return spi_write_then_read(flash->spi, &code, 1, NULL, 0); |
2f9f7628 ML |
153 | } |
154 | ||
49aac4ae GY |
155 | /* |
156 | * Send write disble instruction to the chip. | |
157 | */ | |
158 | static inline int write_disable(struct m25p *flash) | |
159 | { | |
160 | u8 code = OPCODE_WRDI; | |
161 | ||
162 | return spi_write_then_read(flash->spi, &code, 1, NULL, 0); | |
163 | } | |
2f9f7628 | 164 | |
4b7f7422 KC |
165 | /* |
166 | * Enable/disable 4-byte addressing mode. | |
167 | */ | |
baa9ae3c | 168 | static inline int set_4byte(struct m25p *flash, u32 jedec_id, int enable) |
4b7f7422 | 169 | { |
baa9ae3c KC |
170 | switch (JEDEC_MFR(jedec_id)) { |
171 | case CFI_MFR_MACRONIX: | |
eedeac3c | 172 | case CFI_MFR_ST: /* Micron, actually */ |
0aa87b75 | 173 | case 0xEF /* winbond */: |
baa9ae3c KC |
174 | flash->command[0] = enable ? OPCODE_EN4B : OPCODE_EX4B; |
175 | return spi_write(flash->spi, flash->command, 1); | |
176 | default: | |
177 | /* Spansion style */ | |
178 | flash->command[0] = OPCODE_BRWR; | |
179 | flash->command[1] = enable << 7; | |
180 | return spi_write(flash->spi, flash->command, 2); | |
181 | } | |
4b7f7422 KC |
182 | } |
183 | ||
2f9f7628 ML |
184 | /* |
185 | * Service routine to read status register until ready, or timeout occurs. | |
186 | * Returns non-zero if error. | |
187 | */ | |
188 | static int wait_till_ready(struct m25p *flash) | |
189 | { | |
cd1a6de7 | 190 | unsigned long deadline; |
2f9f7628 ML |
191 | int sr; |
192 | ||
cd1a6de7 PH |
193 | deadline = jiffies + MAX_READY_WAIT_JIFFIES; |
194 | ||
195 | do { | |
2f9f7628 ML |
196 | if ((sr = read_sr(flash)) < 0) |
197 | break; | |
198 | else if (!(sr & SR_WIP)) | |
199 | return 0; | |
200 | ||
cd1a6de7 PH |
201 | cond_resched(); |
202 | ||
203 | } while (!time_after_eq(jiffies, deadline)); | |
2f9f7628 ML |
204 | |
205 | return 1; | |
206 | } | |
207 | ||
faff3750 CG |
208 | /* |
209 | * Erase the whole flash memory | |
210 | * | |
211 | * Returns 0 if successful, non-zero otherwise. | |
212 | */ | |
7854643a | 213 | static int erase_chip(struct m25p *flash) |
faff3750 | 214 | { |
0a32a102 BN |
215 | pr_debug("%s: %s %lldKiB\n", dev_name(&flash->spi->dev), __func__, |
216 | (long long)(flash->mtd.size >> 10)); | |
faff3750 CG |
217 | |
218 | /* Wait until finished previous write command. */ | |
219 | if (wait_till_ready(flash)) | |
220 | return 1; | |
221 | ||
222 | /* Send write enable, then erase commands. */ | |
223 | write_enable(flash); | |
224 | ||
225 | /* Set up command buffer. */ | |
7854643a | 226 | flash->command[0] = OPCODE_CHIP_ERASE; |
faff3750 CG |
227 | |
228 | spi_write(flash->spi, flash->command, 1); | |
229 | ||
230 | return 0; | |
231 | } | |
2f9f7628 | 232 | |
837479d2 AV |
233 | static void m25p_addr2cmd(struct m25p *flash, unsigned int addr, u8 *cmd) |
234 | { | |
235 | /* opcode is in cmd[0] */ | |
236 | cmd[1] = addr >> (flash->addr_width * 8 - 8); | |
237 | cmd[2] = addr >> (flash->addr_width * 8 - 16); | |
238 | cmd[3] = addr >> (flash->addr_width * 8 - 24); | |
4b7f7422 | 239 | cmd[4] = addr >> (flash->addr_width * 8 - 32); |
837479d2 AV |
240 | } |
241 | ||
242 | static int m25p_cmdsz(struct m25p *flash) | |
243 | { | |
244 | return 1 + flash->addr_width; | |
245 | } | |
246 | ||
2f9f7628 ML |
247 | /* |
248 | * Erase one sector of flash memory at offset ``offset'' which is any | |
249 | * address within the sector which should be erased. | |
250 | * | |
251 | * Returns 0 if successful, non-zero otherwise. | |
252 | */ | |
253 | static int erase_sector(struct m25p *flash, u32 offset) | |
254 | { | |
0a32a102 BN |
255 | pr_debug("%s: %s %dKiB at 0x%08x\n", dev_name(&flash->spi->dev), |
256 | __func__, flash->mtd.erasesize / 1024, offset); | |
2f9f7628 ML |
257 | |
258 | /* Wait until finished previous write command. */ | |
259 | if (wait_till_ready(flash)) | |
260 | return 1; | |
261 | ||
262 | /* Send write enable, then erase commands. */ | |
263 | write_enable(flash); | |
264 | ||
265 | /* Set up command buffer. */ | |
fa0a8c71 | 266 | flash->command[0] = flash->erase_opcode; |
837479d2 | 267 | m25p_addr2cmd(flash, offset, flash->command); |
2f9f7628 | 268 | |
837479d2 | 269 | spi_write(flash->spi, flash->command, m25p_cmdsz(flash)); |
2f9f7628 ML |
270 | |
271 | return 0; | |
272 | } | |
273 | ||
274 | /****************************************************************************/ | |
275 | ||
276 | /* | |
277 | * MTD implementation | |
278 | */ | |
279 | ||
280 | /* | |
281 | * Erase an address range on the flash chip. The address range may extend | |
282 | * one or more erase sectors. Return an error is there is a problem erasing. | |
283 | */ | |
284 | static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr) | |
285 | { | |
286 | struct m25p *flash = mtd_to_m25p(mtd); | |
287 | u32 addr,len; | |
d85316ac | 288 | uint32_t rem; |
2f9f7628 | 289 | |
0a32a102 BN |
290 | pr_debug("%s: %s at 0x%llx, len %lld\n", dev_name(&flash->spi->dev), |
291 | __func__, (long long)instr->addr, | |
292 | (long long)instr->len); | |
2f9f7628 | 293 | |
d85316ac AB |
294 | div_u64_rem(instr->len, mtd->erasesize, &rem); |
295 | if (rem) | |
2f9f7628 | 296 | return -EINVAL; |
2f9f7628 ML |
297 | |
298 | addr = instr->addr; | |
299 | len = instr->len; | |
300 | ||
7d5230ea | 301 | mutex_lock(&flash->lock); |
2f9f7628 | 302 | |
7854643a | 303 | /* whole-chip erase? */ |
3f33b0aa SF |
304 | if (len == flash->mtd.size) { |
305 | if (erase_chip(flash)) { | |
306 | instr->state = MTD_ERASE_FAILED; | |
307 | mutex_unlock(&flash->lock); | |
308 | return -EIO; | |
309 | } | |
7854643a CG |
310 | |
311 | /* REVISIT in some cases we could speed up erasing large regions | |
312 | * by using OPCODE_SE instead of OPCODE_BE_4K. We may have set up | |
313 | * to use "small sector erase", but that's not always optimal. | |
314 | */ | |
315 | ||
316 | /* "sector"-at-a-time erase */ | |
faff3750 CG |
317 | } else { |
318 | while (len) { | |
319 | if (erase_sector(flash, addr)) { | |
320 | instr->state = MTD_ERASE_FAILED; | |
321 | mutex_unlock(&flash->lock); | |
322 | return -EIO; | |
323 | } | |
324 | ||
325 | addr += mtd->erasesize; | |
326 | len -= mtd->erasesize; | |
2f9f7628 | 327 | } |
2f9f7628 ML |
328 | } |
329 | ||
7d5230ea | 330 | mutex_unlock(&flash->lock); |
2f9f7628 ML |
331 | |
332 | instr->state = MTD_ERASE_DONE; | |
333 | mtd_erase_callback(instr); | |
334 | ||
335 | return 0; | |
336 | } | |
337 | ||
338 | /* | |
339 | * Read an address range from the flash chip. The address range | |
340 | * may be any size provided it is within the physical boundaries. | |
341 | */ | |
342 | static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len, | |
343 | size_t *retlen, u_char *buf) | |
344 | { | |
345 | struct m25p *flash = mtd_to_m25p(mtd); | |
346 | struct spi_transfer t[2]; | |
347 | struct spi_message m; | |
12ad2be9 | 348 | uint8_t opcode; |
2f9f7628 | 349 | |
0a32a102 BN |
350 | pr_debug("%s: %s from 0x%08x, len %zd\n", dev_name(&flash->spi->dev), |
351 | __func__, (u32)from, len); | |
2f9f7628 | 352 | |
8275c642 VW |
353 | spi_message_init(&m); |
354 | memset(t, 0, (sizeof t)); | |
355 | ||
2230b76b BW |
356 | /* NOTE: |
357 | * OPCODE_FAST_READ (if available) is faster. | |
358 | * Should add 1 byte DUMMY_BYTE. | |
359 | */ | |
8275c642 | 360 | t[0].tx_buf = flash->command; |
12ad2be9 | 361 | t[0].len = m25p_cmdsz(flash) + (flash->fast_read ? 1 : 0); |
8275c642 VW |
362 | spi_message_add_tail(&t[0], &m); |
363 | ||
364 | t[1].rx_buf = buf; | |
365 | t[1].len = len; | |
366 | spi_message_add_tail(&t[1], &m); | |
367 | ||
7d5230ea | 368 | mutex_lock(&flash->lock); |
2f9f7628 ML |
369 | |
370 | /* Wait till previous write/erase is done. */ | |
371 | if (wait_till_ready(flash)) { | |
372 | /* REVISIT status return?? */ | |
7d5230ea | 373 | mutex_unlock(&flash->lock); |
2f9f7628 ML |
374 | return 1; |
375 | } | |
376 | ||
fa0a8c71 DB |
377 | /* FIXME switch to OPCODE_FAST_READ. It's required for higher |
378 | * clocks; and at this writing, every chip this driver handles | |
379 | * supports that opcode. | |
380 | */ | |
2f9f7628 ML |
381 | |
382 | /* Set up the write data buffer. */ | |
87c9511f | 383 | opcode = flash->read_opcode; |
12ad2be9 | 384 | flash->command[0] = opcode; |
837479d2 | 385 | m25p_addr2cmd(flash, from, flash->command); |
2f9f7628 | 386 | |
2f9f7628 ML |
387 | spi_sync(flash->spi, &m); |
388 | ||
12ad2be9 MV |
389 | *retlen = m.actual_length - m25p_cmdsz(flash) - |
390 | (flash->fast_read ? 1 : 0); | |
2f9f7628 | 391 | |
7d5230ea | 392 | mutex_unlock(&flash->lock); |
2f9f7628 ML |
393 | |
394 | return 0; | |
395 | } | |
396 | ||
397 | /* | |
398 | * Write an address range to the flash chip. Data must be written in | |
399 | * FLASH_PAGESIZE chunks. The address range may be any size provided | |
400 | * it is within the physical boundaries. | |
401 | */ | |
402 | static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len, | |
403 | size_t *retlen, const u_char *buf) | |
404 | { | |
405 | struct m25p *flash = mtd_to_m25p(mtd); | |
406 | u32 page_offset, page_size; | |
407 | struct spi_transfer t[2]; | |
408 | struct spi_message m; | |
409 | ||
0a32a102 BN |
410 | pr_debug("%s: %s to 0x%08x, len %zd\n", dev_name(&flash->spi->dev), |
411 | __func__, (u32)to, len); | |
2f9f7628 | 412 | |
8275c642 VW |
413 | spi_message_init(&m); |
414 | memset(t, 0, (sizeof t)); | |
415 | ||
416 | t[0].tx_buf = flash->command; | |
837479d2 | 417 | t[0].len = m25p_cmdsz(flash); |
8275c642 VW |
418 | spi_message_add_tail(&t[0], &m); |
419 | ||
420 | t[1].tx_buf = buf; | |
421 | spi_message_add_tail(&t[1], &m); | |
422 | ||
7d5230ea | 423 | mutex_lock(&flash->lock); |
2f9f7628 ML |
424 | |
425 | /* Wait until finished previous write command. */ | |
bc018863 CG |
426 | if (wait_till_ready(flash)) { |
427 | mutex_unlock(&flash->lock); | |
2f9f7628 | 428 | return 1; |
bc018863 | 429 | } |
2f9f7628 ML |
430 | |
431 | write_enable(flash); | |
432 | ||
2f9f7628 | 433 | /* Set up the opcode in the write buffer. */ |
87c9511f | 434 | flash->command[0] = flash->program_opcode; |
837479d2 | 435 | m25p_addr2cmd(flash, to, flash->command); |
2f9f7628 | 436 | |
837479d2 | 437 | page_offset = to & (flash->page_size - 1); |
2f9f7628 ML |
438 | |
439 | /* do all the bytes fit onto one page? */ | |
837479d2 | 440 | if (page_offset + len <= flash->page_size) { |
2f9f7628 ML |
441 | t[1].len = len; |
442 | ||
443 | spi_sync(flash->spi, &m); | |
444 | ||
837479d2 | 445 | *retlen = m.actual_length - m25p_cmdsz(flash); |
2f9f7628 ML |
446 | } else { |
447 | u32 i; | |
448 | ||
449 | /* the size of data remaining on the first page */ | |
837479d2 | 450 | page_size = flash->page_size - page_offset; |
2f9f7628 | 451 | |
2f9f7628 ML |
452 | t[1].len = page_size; |
453 | spi_sync(flash->spi, &m); | |
454 | ||
837479d2 | 455 | *retlen = m.actual_length - m25p_cmdsz(flash); |
2f9f7628 | 456 | |
837479d2 | 457 | /* write everything in flash->page_size chunks */ |
2f9f7628 ML |
458 | for (i = page_size; i < len; i += page_size) { |
459 | page_size = len - i; | |
837479d2 AV |
460 | if (page_size > flash->page_size) |
461 | page_size = flash->page_size; | |
2f9f7628 ML |
462 | |
463 | /* write the next page to flash */ | |
837479d2 | 464 | m25p_addr2cmd(flash, to + i, flash->command); |
2f9f7628 ML |
465 | |
466 | t[1].tx_buf = buf + i; | |
467 | t[1].len = page_size; | |
468 | ||
469 | wait_till_ready(flash); | |
470 | ||
471 | write_enable(flash); | |
472 | ||
473 | spi_sync(flash->spi, &m); | |
474 | ||
b06cd21e | 475 | *retlen += m.actual_length - m25p_cmdsz(flash); |
7d5230ea DB |
476 | } |
477 | } | |
2f9f7628 | 478 | |
7d5230ea | 479 | mutex_unlock(&flash->lock); |
2f9f7628 ML |
480 | |
481 | return 0; | |
482 | } | |
483 | ||
49aac4ae GY |
484 | static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, |
485 | size_t *retlen, const u_char *buf) | |
486 | { | |
487 | struct m25p *flash = mtd_to_m25p(mtd); | |
488 | struct spi_transfer t[2]; | |
489 | struct spi_message m; | |
490 | size_t actual; | |
491 | int cmd_sz, ret; | |
492 | ||
0a32a102 BN |
493 | pr_debug("%s: %s to 0x%08x, len %zd\n", dev_name(&flash->spi->dev), |
494 | __func__, (u32)to, len); | |
dcf12463 | 495 | |
49aac4ae GY |
496 | spi_message_init(&m); |
497 | memset(t, 0, (sizeof t)); | |
498 | ||
499 | t[0].tx_buf = flash->command; | |
837479d2 | 500 | t[0].len = m25p_cmdsz(flash); |
49aac4ae GY |
501 | spi_message_add_tail(&t[0], &m); |
502 | ||
503 | t[1].tx_buf = buf; | |
504 | spi_message_add_tail(&t[1], &m); | |
505 | ||
506 | mutex_lock(&flash->lock); | |
507 | ||
508 | /* Wait until finished previous write command. */ | |
509 | ret = wait_till_ready(flash); | |
510 | if (ret) | |
511 | goto time_out; | |
512 | ||
513 | write_enable(flash); | |
514 | ||
515 | actual = to % 2; | |
516 | /* Start write from odd address. */ | |
517 | if (actual) { | |
518 | flash->command[0] = OPCODE_BP; | |
837479d2 | 519 | m25p_addr2cmd(flash, to, flash->command); |
49aac4ae GY |
520 | |
521 | /* write one byte. */ | |
522 | t[1].len = 1; | |
523 | spi_sync(flash->spi, &m); | |
524 | ret = wait_till_ready(flash); | |
525 | if (ret) | |
526 | goto time_out; | |
837479d2 | 527 | *retlen += m.actual_length - m25p_cmdsz(flash); |
49aac4ae GY |
528 | } |
529 | to += actual; | |
530 | ||
531 | flash->command[0] = OPCODE_AAI_WP; | |
837479d2 | 532 | m25p_addr2cmd(flash, to, flash->command); |
49aac4ae GY |
533 | |
534 | /* Write out most of the data here. */ | |
837479d2 | 535 | cmd_sz = m25p_cmdsz(flash); |
49aac4ae GY |
536 | for (; actual < len - 1; actual += 2) { |
537 | t[0].len = cmd_sz; | |
538 | /* write two bytes. */ | |
539 | t[1].len = 2; | |
540 | t[1].tx_buf = buf + actual; | |
541 | ||
542 | spi_sync(flash->spi, &m); | |
543 | ret = wait_till_ready(flash); | |
544 | if (ret) | |
545 | goto time_out; | |
546 | *retlen += m.actual_length - cmd_sz; | |
547 | cmd_sz = 1; | |
548 | to += 2; | |
549 | } | |
550 | write_disable(flash); | |
551 | ret = wait_till_ready(flash); | |
552 | if (ret) | |
553 | goto time_out; | |
554 | ||
555 | /* Write out trailing byte if it exists. */ | |
556 | if (actual != len) { | |
557 | write_enable(flash); | |
558 | flash->command[0] = OPCODE_BP; | |
837479d2 AV |
559 | m25p_addr2cmd(flash, to, flash->command); |
560 | t[0].len = m25p_cmdsz(flash); | |
49aac4ae GY |
561 | t[1].len = 1; |
562 | t[1].tx_buf = buf + actual; | |
563 | ||
564 | spi_sync(flash->spi, &m); | |
565 | ret = wait_till_ready(flash); | |
566 | if (ret) | |
567 | goto time_out; | |
837479d2 | 568 | *retlen += m.actual_length - m25p_cmdsz(flash); |
49aac4ae GY |
569 | write_disable(flash); |
570 | } | |
571 | ||
572 | time_out: | |
573 | mutex_unlock(&flash->lock); | |
574 | return ret; | |
575 | } | |
2f9f7628 | 576 | |
972e1b7b AB |
577 | static int m25p80_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) |
578 | { | |
579 | struct m25p *flash = mtd_to_m25p(mtd); | |
580 | uint32_t offset = ofs; | |
581 | uint8_t status_old, status_new; | |
582 | int res = 0; | |
583 | ||
584 | mutex_lock(&flash->lock); | |
585 | /* Wait until finished previous command */ | |
586 | if (wait_till_ready(flash)) { | |
587 | res = 1; | |
588 | goto err; | |
589 | } | |
590 | ||
591 | status_old = read_sr(flash); | |
592 | ||
593 | if (offset < flash->mtd.size-(flash->mtd.size/2)) | |
594 | status_new = status_old | SR_BP2 | SR_BP1 | SR_BP0; | |
595 | else if (offset < flash->mtd.size-(flash->mtd.size/4)) | |
596 | status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1; | |
597 | else if (offset < flash->mtd.size-(flash->mtd.size/8)) | |
598 | status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0; | |
599 | else if (offset < flash->mtd.size-(flash->mtd.size/16)) | |
600 | status_new = (status_old & ~(SR_BP0|SR_BP1)) | SR_BP2; | |
601 | else if (offset < flash->mtd.size-(flash->mtd.size/32)) | |
602 | status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0; | |
603 | else if (offset < flash->mtd.size-(flash->mtd.size/64)) | |
604 | status_new = (status_old & ~(SR_BP2|SR_BP0)) | SR_BP1; | |
605 | else | |
606 | status_new = (status_old & ~(SR_BP2|SR_BP1)) | SR_BP0; | |
607 | ||
608 | /* Only modify protection if it will not unlock other areas */ | |
609 | if ((status_new&(SR_BP2|SR_BP1|SR_BP0)) > | |
610 | (status_old&(SR_BP2|SR_BP1|SR_BP0))) { | |
611 | write_enable(flash); | |
612 | if (write_sr(flash, status_new) < 0) { | |
613 | res = 1; | |
614 | goto err; | |
615 | } | |
616 | } | |
617 | ||
618 | err: mutex_unlock(&flash->lock); | |
619 | return res; | |
620 | } | |
621 | ||
622 | static int m25p80_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
623 | { | |
624 | struct m25p *flash = mtd_to_m25p(mtd); | |
625 | uint32_t offset = ofs; | |
626 | uint8_t status_old, status_new; | |
627 | int res = 0; | |
628 | ||
629 | mutex_lock(&flash->lock); | |
630 | /* Wait until finished previous command */ | |
631 | if (wait_till_ready(flash)) { | |
632 | res = 1; | |
633 | goto err; | |
634 | } | |
635 | ||
636 | status_old = read_sr(flash); | |
637 | ||
638 | if (offset+len > flash->mtd.size-(flash->mtd.size/64)) | |
639 | status_new = status_old & ~(SR_BP2|SR_BP1|SR_BP0); | |
640 | else if (offset+len > flash->mtd.size-(flash->mtd.size/32)) | |
641 | status_new = (status_old & ~(SR_BP2|SR_BP1)) | SR_BP0; | |
642 | else if (offset+len > flash->mtd.size-(flash->mtd.size/16)) | |
643 | status_new = (status_old & ~(SR_BP2|SR_BP0)) | SR_BP1; | |
644 | else if (offset+len > flash->mtd.size-(flash->mtd.size/8)) | |
645 | status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0; | |
646 | else if (offset+len > flash->mtd.size-(flash->mtd.size/4)) | |
647 | status_new = (status_old & ~(SR_BP0|SR_BP1)) | SR_BP2; | |
648 | else if (offset+len > flash->mtd.size-(flash->mtd.size/2)) | |
649 | status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0; | |
650 | else | |
651 | status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1; | |
652 | ||
653 | /* Only modify protection if it will not lock other areas */ | |
654 | if ((status_new&(SR_BP2|SR_BP1|SR_BP0)) < | |
655 | (status_old&(SR_BP2|SR_BP1|SR_BP0))) { | |
656 | write_enable(flash); | |
657 | if (write_sr(flash, status_new) < 0) { | |
658 | res = 1; | |
659 | goto err; | |
660 | } | |
661 | } | |
662 | ||
663 | err: mutex_unlock(&flash->lock); | |
664 | return res; | |
665 | } | |
666 | ||
2f9f7628 ML |
667 | /****************************************************************************/ |
668 | ||
669 | /* | |
670 | * SPI device driver setup and teardown | |
671 | */ | |
672 | ||
673 | struct flash_info { | |
fa0a8c71 DB |
674 | /* JEDEC id zero means "no ID" (most older chips); otherwise it has |
675 | * a high byte of zero plus three data bytes: the manufacturer id, | |
676 | * then a two byte device id. | |
677 | */ | |
678 | u32 jedec_id; | |
d0e8c47c | 679 | u16 ext_id; |
fa0a8c71 DB |
680 | |
681 | /* The size listed here is what works with OPCODE_SE, which isn't | |
682 | * necessarily called a "sector" by the vendor. | |
683 | */ | |
2f9f7628 | 684 | unsigned sector_size; |
fa0a8c71 DB |
685 | u16 n_sectors; |
686 | ||
837479d2 AV |
687 | u16 page_size; |
688 | u16 addr_width; | |
689 | ||
fa0a8c71 DB |
690 | u16 flags; |
691 | #define SECT_4K 0x01 /* OPCODE_BE_4K works uniformly */ | |
837479d2 | 692 | #define M25P_NO_ERASE 0x02 /* No erase command needed */ |
e534ee4f | 693 | #define SST_WRITE 0x04 /* use SST byte programming */ |
58146992 | 694 | #define M25P_NO_FR 0x08 /* Can't do fastread */ |
2f9f7628 ML |
695 | }; |
696 | ||
b34bc037 AV |
697 | #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ |
698 | ((kernel_ulong_t)&(struct flash_info) { \ | |
699 | .jedec_id = (_jedec_id), \ | |
700 | .ext_id = (_ext_id), \ | |
701 | .sector_size = (_sector_size), \ | |
702 | .n_sectors = (_n_sectors), \ | |
837479d2 | 703 | .page_size = 256, \ |
b34bc037 AV |
704 | .flags = (_flags), \ |
705 | }) | |
fa0a8c71 | 706 | |
7e7d83b3 | 707 | #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \ |
837479d2 AV |
708 | ((kernel_ulong_t)&(struct flash_info) { \ |
709 | .sector_size = (_sector_size), \ | |
710 | .n_sectors = (_n_sectors), \ | |
711 | .page_size = (_page_size), \ | |
712 | .addr_width = (_addr_width), \ | |
7e7d83b3 | 713 | .flags = (_flags), \ |
837479d2 | 714 | }) |
fa0a8c71 DB |
715 | |
716 | /* NOTE: double check command sets and memory organization when you add | |
717 | * more flash chips. This current list focusses on newer chips, which | |
718 | * have been converging on command sets which including JEDEC ID. | |
719 | */ | |
b34bc037 | 720 | static const struct spi_device_id m25p_ids[] = { |
fa0a8c71 | 721 | /* Atmel -- some are (confusingly) marketed as "DataFlash" */ |
b34bc037 AV |
722 | { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) }, |
723 | { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) }, | |
fa0a8c71 | 724 | |
b34bc037 | 725 | { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) }, |
ada766e9 | 726 | { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) }, |
b34bc037 | 727 | { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) }, |
fa0a8c71 | 728 | |
b34bc037 AV |
729 | { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) }, |
730 | { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) }, | |
731 | { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) }, | |
8fffed8c | 732 | { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) }, |
fa0a8c71 | 733 | |
a5b2d76d CL |
734 | { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) }, |
735 | ||
37a23c20 GJ |
736 | /* EON -- en25xxx */ |
737 | { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) }, | |
60845e72 | 738 | { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) }, |
86a9893d | 739 | { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) }, |
60845e72 | 740 | { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) }, |
58d864ed | 741 | { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) }, |
6b75152b | 742 | { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) }, |
60845e72 | 743 | |
5ca11ca7 | 744 | /* Everspin */ |
58146992 | 745 | { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, M25P_NO_ERASE | M25P_NO_FR) }, |
5ca11ca7 | 746 | |
55bf75b7 MS |
747 | /* GigaDevice */ |
748 | { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K) }, | |
749 | { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) }, | |
750 | ||
f80e521c GJ |
751 | /* Intel/Numonyx -- xxxs33b */ |
752 | { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) }, | |
753 | { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) }, | |
754 | { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) }, | |
755 | ||
ab1ff210 | 756 | /* Macronix */ |
bb08bc10 | 757 | { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) }, |
df0094d7 | 758 | { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) }, |
6175f4a1 | 759 | { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) }, |
9c76b4e5 | 760 | { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) }, |
b34bc037 AV |
761 | { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) }, |
762 | { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) }, | |
763 | { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) }, | |
764 | { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) }, | |
4b7f7422 | 765 | { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) }, |
ac622f58 | 766 | { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) }, |
f9952754 | 767 | { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, 0) }, |
ab1ff210 | 768 | |
8da28681 | 769 | /* Micron */ |
e66e280c | 770 | { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, 0) }, |
98a9e245 LW |
771 | { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, 0) }, |
772 | { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, 0) }, | |
8da28681 VD |
773 | { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K) }, |
774 | ||
fa0a8c71 DB |
775 | /* Spansion -- single (large) sector size only, at least |
776 | * for the chips listed here (without boot sectors). | |
777 | */ | |
b277f77e MV |
778 | { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, 0) }, |
779 | { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, 0) }, | |
baa9ae3c KC |
780 | { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) }, |
781 | { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, 0) }, | |
3d2d2b65 KC |
782 | { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, 0) }, |
783 | { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) }, | |
b34bc037 AV |
784 | { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) }, |
785 | { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) }, | |
786 | { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) }, | |
787 | { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) }, | |
8bb8b85f MV |
788 | { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) }, |
789 | { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) }, | |
790 | { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) }, | |
791 | { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) }, | |
792 | { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) }, | |
f2df1ae3 GH |
793 | { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) }, |
794 | { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, | |
fa0a8c71 DB |
795 | |
796 | /* SST -- large erase sizes are "overlays", "sectors" are 4K */ | |
e534ee4f KM |
797 | { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, |
798 | { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, | |
799 | { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) }, | |
800 | { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) }, | |
89134055 | 801 | { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) }, |
e534ee4f KM |
802 | { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) }, |
803 | { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) }, | |
804 | { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) }, | |
805 | { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, | |
fa0a8c71 DB |
806 | |
807 | /* ST Microelectronics -- newer production may have feature updates */ | |
b34bc037 AV |
808 | { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) }, |
809 | { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) }, | |
810 | { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) }, | |
811 | { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) }, | |
812 | { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) }, | |
813 | { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) }, | |
814 | { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) }, | |
815 | { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) }, | |
816 | { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) }, | |
4800399e | 817 | { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, 0) }, |
b34bc037 | 818 | |
f7b00090 AV |
819 | { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) }, |
820 | { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) }, | |
821 | { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) }, | |
822 | { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) }, | |
823 | { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) }, | |
824 | { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) }, | |
825 | { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) }, | |
826 | { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) }, | |
827 | { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) }, | |
828 | ||
b34bc037 AV |
829 | { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) }, |
830 | { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) }, | |
831 | { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) }, | |
832 | ||
943b35a6 | 833 | { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) }, |
b34bc037 AV |
834 | { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) }, |
835 | { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) }, | |
fa0a8c71 | 836 | |
16004f36 KC |
837 | { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) }, |
838 | { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) }, | |
839 | { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) }, | |
840 | { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) }, | |
d8f90b2c | 841 | |
02d087db | 842 | /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ |
b34bc037 AV |
843 | { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) }, |
844 | { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) }, | |
845 | { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) }, | |
846 | { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) }, | |
847 | { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) }, | |
848 | { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) }, | |
0af18d27 | 849 | { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) }, |
9d6367f4 | 850 | { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K) }, |
b34bc037 | 851 | { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) }, |
d2ac467a | 852 | { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, |
4b6ff7af | 853 | { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) }, |
4fba37ae | 854 | { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) }, |
9b7ef60c | 855 | { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) }, |
001c33ab | 856 | { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) }, |
0aa87b75 | 857 | { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) }, |
837479d2 AV |
858 | |
859 | /* Catalyst / On Semiconductor -- non-JEDEC */ | |
58146992 SH |
860 | { "cat25c11", CAT25_INFO( 16, 8, 16, 1, M25P_NO_ERASE | M25P_NO_FR) }, |
861 | { "cat25c03", CAT25_INFO( 32, 8, 16, 2, M25P_NO_ERASE | M25P_NO_FR) }, | |
862 | { "cat25c09", CAT25_INFO( 128, 8, 32, 2, M25P_NO_ERASE | M25P_NO_FR) }, | |
863 | { "cat25c17", CAT25_INFO( 256, 8, 32, 2, M25P_NO_ERASE | M25P_NO_FR) }, | |
864 | { "cat25128", CAT25_INFO(2048, 8, 64, 2, M25P_NO_ERASE | M25P_NO_FR) }, | |
b34bc037 | 865 | { }, |
2f9f7628 | 866 | }; |
b34bc037 | 867 | MODULE_DEVICE_TABLE(spi, m25p_ids); |
2f9f7628 | 868 | |
06f25510 | 869 | static const struct spi_device_id *jedec_probe(struct spi_device *spi) |
fa0a8c71 DB |
870 | { |
871 | int tmp; | |
872 | u8 code = OPCODE_RDID; | |
daa84735 | 873 | u8 id[5]; |
fa0a8c71 | 874 | u32 jedec; |
d0e8c47c | 875 | u16 ext_jedec; |
fa0a8c71 DB |
876 | struct flash_info *info; |
877 | ||
878 | /* JEDEC also defines an optional "extended device information" | |
879 | * string for after vendor-specific data, after the three bytes | |
880 | * we use here. Supporting some chips might require using it. | |
881 | */ | |
daa84735 | 882 | tmp = spi_write_then_read(spi, &code, 1, id, 5); |
fa0a8c71 | 883 | if (tmp < 0) { |
289c0522 | 884 | pr_debug("%s: error %d reading JEDEC ID\n", |
0a32a102 | 885 | dev_name(&spi->dev), tmp); |
9d2c4f3f | 886 | return ERR_PTR(tmp); |
fa0a8c71 DB |
887 | } |
888 | jedec = id[0]; | |
889 | jedec = jedec << 8; | |
890 | jedec |= id[1]; | |
891 | jedec = jedec << 8; | |
892 | jedec |= id[2]; | |
893 | ||
d0e8c47c CG |
894 | ext_jedec = id[3] << 8 | id[4]; |
895 | ||
b34bc037 AV |
896 | for (tmp = 0; tmp < ARRAY_SIZE(m25p_ids) - 1; tmp++) { |
897 | info = (void *)m25p_ids[tmp].driver_data; | |
a3d3f73c | 898 | if (info->jedec_id == jedec) { |
9168ab86 | 899 | if (info->ext_id != 0 && info->ext_id != ext_jedec) |
d0e8c47c | 900 | continue; |
b34bc037 | 901 | return &m25p_ids[tmp]; |
a3d3f73c | 902 | } |
fa0a8c71 | 903 | } |
f0dff9bd | 904 | dev_err(&spi->dev, "unrecognized JEDEC id %06x\n", jedec); |
9d2c4f3f | 905 | return ERR_PTR(-ENODEV); |
fa0a8c71 DB |
906 | } |
907 | ||
908 | ||
2f9f7628 ML |
909 | /* |
910 | * board specific setup should have ensured the SPI clock used here | |
911 | * matches what the READ command supports, at least until this driver | |
912 | * understands FAST_READ (for clocks over 25 MHz). | |
913 | */ | |
06f25510 | 914 | static int m25p_probe(struct spi_device *spi) |
2f9f7628 | 915 | { |
18c6182b | 916 | const struct spi_device_id *id = spi_get_device_id(spi); |
2f9f7628 ML |
917 | struct flash_platform_data *data; |
918 | struct m25p *flash; | |
919 | struct flash_info *info; | |
920 | unsigned i; | |
ea6a4729 | 921 | struct mtd_part_parser_data ppdata; |
12ad2be9 | 922 | struct device_node __maybe_unused *np = spi->dev.of_node; |
2f9f7628 | 923 | |
5f949137 | 924 | #ifdef CONFIG_MTD_OF_PARTS |
12ad2be9 | 925 | if (!of_device_is_available(np)) |
5f949137 SX |
926 | return -ENODEV; |
927 | #endif | |
928 | ||
2f9f7628 | 929 | /* Platform data helps sort out which chip type we have, as |
fa0a8c71 DB |
930 | * well as how this board partitions it. If we don't have |
931 | * a chip ID, try the JEDEC id commands; they'll work for most | |
932 | * newer chips, even if we don't recognize the particular chip. | |
2f9f7628 | 933 | */ |
0278fd3f | 934 | data = dev_get_platdata(&spi->dev); |
fa0a8c71 | 935 | if (data && data->type) { |
18c6182b | 936 | const struct spi_device_id *plat_id; |
2f9f7628 | 937 | |
b34bc037 | 938 | for (i = 0; i < ARRAY_SIZE(m25p_ids) - 1; i++) { |
18c6182b AV |
939 | plat_id = &m25p_ids[i]; |
940 | if (strcmp(data->type, plat_id->name)) | |
b34bc037 AV |
941 | continue; |
942 | break; | |
fa0a8c71 | 943 | } |
fa0a8c71 | 944 | |
f78ec6b2 | 945 | if (i < ARRAY_SIZE(m25p_ids) - 1) |
18c6182b AV |
946 | id = plat_id; |
947 | else | |
948 | dev_warn(&spi->dev, "unrecognized id %s\n", data->type); | |
b34bc037 | 949 | } |
fa0a8c71 | 950 | |
18c6182b AV |
951 | info = (void *)id->driver_data; |
952 | ||
953 | if (info->jedec_id) { | |
954 | const struct spi_device_id *jid; | |
955 | ||
956 | jid = jedec_probe(spi); | |
9d2c4f3f AV |
957 | if (IS_ERR(jid)) { |
958 | return PTR_ERR(jid); | |
18c6182b AV |
959 | } else if (jid != id) { |
960 | /* | |
961 | * JEDEC knows better, so overwrite platform ID. We | |
962 | * can't trust partitions any longer, but we'll let | |
963 | * mtd apply them anyway, since some partitions may be | |
964 | * marked read-only, and we don't want to lose that | |
965 | * information, even if it's not 100% accurate. | |
966 | */ | |
967 | dev_warn(&spi->dev, "found %s, expected %s\n", | |
968 | jid->name, id->name); | |
969 | id = jid; | |
970 | info = (void *)jid->driver_data; | |
971 | } | |
972 | } | |
2f9f7628 | 973 | |
e94b1766 | 974 | flash = kzalloc(sizeof *flash, GFP_KERNEL); |
2f9f7628 ML |
975 | if (!flash) |
976 | return -ENOMEM; | |
12ad2be9 MV |
977 | flash->command = kmalloc(MAX_CMD_SIZE + (flash->fast_read ? 1 : 0), |
978 | GFP_KERNEL); | |
61c3506c JS |
979 | if (!flash->command) { |
980 | kfree(flash); | |
981 | return -ENOMEM; | |
982 | } | |
2f9f7628 ML |
983 | |
984 | flash->spi = spi; | |
7d5230ea | 985 | mutex_init(&flash->lock); |
975aefc9 | 986 | spi_set_drvdata(spi, flash); |
2f9f7628 | 987 | |
72289824 | 988 | /* |
f80e521c | 989 | * Atmel, SST and Intel/Numonyx serial flash tend to power |
ea60658a | 990 | * up with the software protection bits set |
72289824 MH |
991 | */ |
992 | ||
aa084653 KC |
993 | if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ATMEL || |
994 | JEDEC_MFR(info->jedec_id) == CFI_MFR_INTEL || | |
995 | JEDEC_MFR(info->jedec_id) == CFI_MFR_SST) { | |
72289824 MH |
996 | write_enable(flash); |
997 | write_sr(flash, 0); | |
998 | } | |
999 | ||
fa0a8c71 | 1000 | if (data && data->name) |
2f9f7628 ML |
1001 | flash->mtd.name = data->name; |
1002 | else | |
160bbab3 | 1003 | flash->mtd.name = dev_name(&spi->dev); |
2f9f7628 ML |
1004 | |
1005 | flash->mtd.type = MTD_NORFLASH; | |
783ed81f | 1006 | flash->mtd.writesize = 1; |
2f9f7628 ML |
1007 | flash->mtd.flags = MTD_CAP_NORFLASH; |
1008 | flash->mtd.size = info->sector_size * info->n_sectors; | |
3c3c10bb AB |
1009 | flash->mtd._erase = m25p80_erase; |
1010 | flash->mtd._read = m25p80_read; | |
49aac4ae | 1011 | |
972e1b7b AB |
1012 | /* flash protection support for STmicro chips */ |
1013 | if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ST) { | |
1014 | flash->mtd._lock = m25p80_lock; | |
1015 | flash->mtd._unlock = m25p80_unlock; | |
1016 | } | |
1017 | ||
49aac4ae | 1018 | /* sst flash chips use AAI word program */ |
e534ee4f | 1019 | if (info->flags & SST_WRITE) |
3c3c10bb | 1020 | flash->mtd._write = sst_write; |
49aac4ae | 1021 | else |
3c3c10bb | 1022 | flash->mtd._write = m25p80_write; |
2f9f7628 | 1023 | |
fa0a8c71 DB |
1024 | /* prefer "small sector" erase if possible */ |
1025 | if (info->flags & SECT_4K) { | |
1026 | flash->erase_opcode = OPCODE_BE_4K; | |
1027 | flash->mtd.erasesize = 4096; | |
1028 | } else { | |
1029 | flash->erase_opcode = OPCODE_SE; | |
1030 | flash->mtd.erasesize = info->sector_size; | |
1031 | } | |
1032 | ||
837479d2 AV |
1033 | if (info->flags & M25P_NO_ERASE) |
1034 | flash->mtd.flags |= MTD_NO_ERASE; | |
1035 | ||
ea6a4729 | 1036 | ppdata.of_node = spi->dev.of_node; |
87f39f04 | 1037 | flash->mtd.dev.parent = &spi->dev; |
837479d2 | 1038 | flash->page_size = info->page_size; |
b54f47c8 | 1039 | flash->mtd.writebufsize = flash->page_size; |
4b7f7422 | 1040 | |
12ad2be9 | 1041 | flash->fast_read = false; |
12ad2be9 MV |
1042 | if (np && of_property_read_bool(np, "m25p,fast-read")) |
1043 | flash->fast_read = true; | |
12ad2be9 MV |
1044 | |
1045 | #ifdef CONFIG_M25PXX_USE_FAST_READ | |
1046 | flash->fast_read = true; | |
1047 | #endif | |
58146992 SH |
1048 | if (info->flags & M25P_NO_FR) |
1049 | flash->fast_read = false; | |
12ad2be9 | 1050 | |
87c9511f BN |
1051 | /* Default commands */ |
1052 | if (flash->fast_read) | |
1053 | flash->read_opcode = OPCODE_FAST_READ; | |
1054 | else | |
1055 | flash->read_opcode = OPCODE_NORM_READ; | |
1056 | ||
1057 | flash->program_opcode = OPCODE_PP; | |
1058 | ||
4b7f7422 KC |
1059 | if (info->addr_width) |
1060 | flash->addr_width = info->addr_width; | |
87c9511f | 1061 | else if (flash->mtd.size > 0x1000000) { |
4b7f7422 | 1062 | /* enable 4-byte addressing if the device exceeds 16MiB */ |
87c9511f BN |
1063 | flash->addr_width = 4; |
1064 | if (JEDEC_MFR(info->jedec_id) == CFI_MFR_AMD) { | |
1065 | /* Dedicated 4-byte command set */ | |
1066 | flash->read_opcode = flash->fast_read ? | |
1067 | OPCODE_FAST_READ_4B : | |
1068 | OPCODE_NORM_READ_4B; | |
1069 | flash->program_opcode = OPCODE_PP_4B; | |
1070 | /* No small sector erase for 4-byte command set */ | |
1071 | flash->erase_opcode = OPCODE_SE_4B; | |
1072 | flash->mtd.erasesize = info->sector_size; | |
4b7f7422 | 1073 | } else |
87c9511f BN |
1074 | set_4byte(flash, info->jedec_id, 1); |
1075 | } else { | |
1076 | flash->addr_width = 3; | |
4b7f7422 | 1077 | } |
87f39f04 | 1078 | |
b34bc037 | 1079 | dev_info(&spi->dev, "%s (%lld Kbytes)\n", id->name, |
d85316ac | 1080 | (long long)flash->mtd.size >> 10); |
2f9f7628 | 1081 | |
289c0522 | 1082 | pr_debug("mtd .name = %s, .size = 0x%llx (%lldMiB) " |
02d087db | 1083 | ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n", |
2f9f7628 | 1084 | flash->mtd.name, |
d85316ac | 1085 | (long long)flash->mtd.size, (long long)(flash->mtd.size >> 20), |
2f9f7628 ML |
1086 | flash->mtd.erasesize, flash->mtd.erasesize / 1024, |
1087 | flash->mtd.numeraseregions); | |
1088 | ||
1089 | if (flash->mtd.numeraseregions) | |
1090 | for (i = 0; i < flash->mtd.numeraseregions; i++) | |
289c0522 | 1091 | pr_debug("mtd.eraseregions[%d] = { .offset = 0x%llx, " |
02d087db | 1092 | ".erasesize = 0x%.8x (%uKiB), " |
2f9f7628 | 1093 | ".numblocks = %d }\n", |
d85316ac | 1094 | i, (long long)flash->mtd.eraseregions[i].offset, |
2f9f7628 ML |
1095 | flash->mtd.eraseregions[i].erasesize, |
1096 | flash->mtd.eraseregions[i].erasesize / 1024, | |
1097 | flash->mtd.eraseregions[i].numblocks); | |
1098 | ||
1099 | ||
1100 | /* partitions should match sector boundaries; and it may be good to | |
1101 | * use readonly partitions for writeprotected sectors (BP2..BP0). | |
1102 | */ | |
871770b5 DES |
1103 | return mtd_device_parse_register(&flash->mtd, NULL, &ppdata, |
1104 | data ? data->parts : NULL, | |
1105 | data ? data->nr_parts : 0); | |
2f9f7628 ML |
1106 | } |
1107 | ||
1108 | ||
810b7e06 | 1109 | static int m25p_remove(struct spi_device *spi) |
2f9f7628 | 1110 | { |
975aefc9 | 1111 | struct m25p *flash = spi_get_drvdata(spi); |
2f9f7628 ML |
1112 | int status; |
1113 | ||
1114 | /* Clean up MTD stuff. */ | |
ba52f3a2 | 1115 | status = mtd_device_unregister(&flash->mtd); |
61c3506c JS |
1116 | if (status == 0) { |
1117 | kfree(flash->command); | |
2f9f7628 | 1118 | kfree(flash); |
61c3506c | 1119 | } |
2f9f7628 ML |
1120 | return 0; |
1121 | } | |
1122 | ||
1123 | ||
1124 | static struct spi_driver m25p80_driver = { | |
1125 | .driver = { | |
1126 | .name = "m25p80", | |
2f9f7628 ML |
1127 | .owner = THIS_MODULE, |
1128 | }, | |
b34bc037 | 1129 | .id_table = m25p_ids, |
2f9f7628 | 1130 | .probe = m25p_probe, |
5153b88c | 1131 | .remove = m25p_remove, |
fa0a8c71 DB |
1132 | |
1133 | /* REVISIT: many of these chips have deep power-down modes, which | |
1134 | * should clearly be entered on suspend() to minimize power use. | |
1135 | * And also when they're otherwise idle... | |
1136 | */ | |
2f9f7628 ML |
1137 | }; |
1138 | ||
c9d1b752 | 1139 | module_spi_driver(m25p80_driver); |
2f9f7628 ML |
1140 | |
1141 | MODULE_LICENSE("GPL"); | |
1142 | MODULE_AUTHOR("Mike Lavender"); | |
1143 | MODULE_DESCRIPTION("MTD SPI driver for ST M25Pxx flash chips"); |