Commit | Line | Data |
---|---|---|
2f9f7628 | 1 | /* |
fa0a8c71 | 2 | * MTD SPI driver for ST M25Pxx (and similar) serial flash chips |
2f9f7628 ML |
3 | * |
4 | * Author: Mike Lavender, mike@steroidmicros.com | |
5 | * | |
6 | * Copyright (c) 2005, Intec Automation Inc. | |
7 | * | |
8 | * Some parts are based on lart.c by Abraham Van Der Merwe | |
9 | * | |
10 | * Cleaned up and generalized based on mtd_dataflash.c | |
11 | * | |
12 | * This code is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | * | |
16 | */ | |
17 | ||
18 | #include <linux/init.h> | |
9d2c4f3f AV |
19 | #include <linux/err.h> |
20 | #include <linux/errno.h> | |
2f9f7628 ML |
21 | #include <linux/module.h> |
22 | #include <linux/device.h> | |
23 | #include <linux/interrupt.h> | |
7d5230ea | 24 | #include <linux/mutex.h> |
d85316ac | 25 | #include <linux/math64.h> |
5a0e3ad6 | 26 | #include <linux/slab.h> |
d43c36dc | 27 | #include <linux/sched.h> |
b34bc037 | 28 | #include <linux/mod_devicetable.h> |
7d5230ea | 29 | |
aa084653 | 30 | #include <linux/mtd/cfi.h> |
2f9f7628 ML |
31 | #include <linux/mtd/mtd.h> |
32 | #include <linux/mtd/partitions.h> | |
5f949137 | 33 | #include <linux/of_platform.h> |
7d5230ea | 34 | |
2f9f7628 ML |
35 | #include <linux/spi/spi.h> |
36 | #include <linux/spi/flash.h> | |
37 | ||
2f9f7628 | 38 | /* Flash opcodes. */ |
fa0a8c71 DB |
39 | #define OPCODE_WREN 0x06 /* Write enable */ |
40 | #define OPCODE_RDSR 0x05 /* Read status register */ | |
72289824 | 41 | #define OPCODE_WRSR 0x01 /* Write status register 1 byte */ |
2230b76b | 42 | #define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */ |
fa0a8c71 DB |
43 | #define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */ |
44 | #define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */ | |
7854643a | 45 | #define OPCODE_BE_4K 0x20 /* Erase 4KiB block */ |
02d087db | 46 | #define OPCODE_BE_32K 0x52 /* Erase 32KiB block */ |
7854643a | 47 | #define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */ |
02d087db | 48 | #define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */ |
2f9f7628 ML |
49 | #define OPCODE_RDID 0x9f /* Read JEDEC ID */ |
50 | ||
49aac4ae GY |
51 | /* Used for SST flashes only. */ |
52 | #define OPCODE_BP 0x02 /* Byte program */ | |
53 | #define OPCODE_WRDI 0x04 /* Write disable */ | |
54 | #define OPCODE_AAI_WP 0xad /* Auto address increment word program */ | |
55 | ||
4b7f7422 KC |
56 | /* Used for Macronix flashes only. */ |
57 | #define OPCODE_EN4B 0xb7 /* Enter 4-byte mode */ | |
58 | #define OPCODE_EX4B 0xe9 /* Exit 4-byte mode */ | |
59 | ||
baa9ae3c KC |
60 | /* Used for Spansion flashes only. */ |
61 | #define OPCODE_BRWR 0x17 /* Bank register write */ | |
62 | ||
2f9f7628 ML |
63 | /* Status Register bits. */ |
64 | #define SR_WIP 1 /* Write in progress */ | |
65 | #define SR_WEL 2 /* Write enable latch */ | |
fa0a8c71 | 66 | /* meaning of other SR_* bits may differ between vendors */ |
2f9f7628 ML |
67 | #define SR_BP0 4 /* Block protect 0 */ |
68 | #define SR_BP1 8 /* Block protect 1 */ | |
69 | #define SR_BP2 0x10 /* Block protect 2 */ | |
70 | #define SR_SRWD 0x80 /* SR write protect */ | |
71 | ||
72 | /* Define max times to check status register before we give up. */ | |
89bb871e | 73 | #define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */ |
4b7f7422 | 74 | #define MAX_CMD_SIZE 5 |
2f9f7628 | 75 | |
aa084653 KC |
76 | #define JEDEC_MFR(_jedec_id) ((_jedec_id) >> 16) |
77 | ||
2f9f7628 ML |
78 | /****************************************************************************/ |
79 | ||
80 | struct m25p { | |
81 | struct spi_device *spi; | |
7d5230ea | 82 | struct mutex lock; |
2f9f7628 | 83 | struct mtd_info mtd; |
837479d2 AV |
84 | u16 page_size; |
85 | u16 addr_width; | |
fa0a8c71 | 86 | u8 erase_opcode; |
61c3506c | 87 | u8 *command; |
12ad2be9 | 88 | bool fast_read; |
2f9f7628 ML |
89 | }; |
90 | ||
91 | static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd) | |
92 | { | |
93 | return container_of(mtd, struct m25p, mtd); | |
94 | } | |
95 | ||
96 | /****************************************************************************/ | |
97 | ||
98 | /* | |
99 | * Internal helper functions | |
100 | */ | |
101 | ||
102 | /* | |
103 | * Read the status register, returning its value in the location | |
104 | * Return the status register value. | |
105 | * Returns negative if error occurred. | |
106 | */ | |
107 | static int read_sr(struct m25p *flash) | |
108 | { | |
109 | ssize_t retval; | |
110 | u8 code = OPCODE_RDSR; | |
111 | u8 val; | |
112 | ||
113 | retval = spi_write_then_read(flash->spi, &code, 1, &val, 1); | |
114 | ||
115 | if (retval < 0) { | |
116 | dev_err(&flash->spi->dev, "error %d reading SR\n", | |
117 | (int) retval); | |
118 | return retval; | |
119 | } | |
120 | ||
121 | return val; | |
122 | } | |
123 | ||
72289824 MH |
124 | /* |
125 | * Write status register 1 byte | |
126 | * Returns negative if error occurred. | |
127 | */ | |
128 | static int write_sr(struct m25p *flash, u8 val) | |
129 | { | |
130 | flash->command[0] = OPCODE_WRSR; | |
131 | flash->command[1] = val; | |
132 | ||
133 | return spi_write(flash->spi, flash->command, 2); | |
134 | } | |
2f9f7628 ML |
135 | |
136 | /* | |
137 | * Set write enable latch with Write Enable command. | |
138 | * Returns negative if error occurred. | |
139 | */ | |
140 | static inline int write_enable(struct m25p *flash) | |
141 | { | |
142 | u8 code = OPCODE_WREN; | |
143 | ||
8a1a6272 | 144 | return spi_write_then_read(flash->spi, &code, 1, NULL, 0); |
2f9f7628 ML |
145 | } |
146 | ||
49aac4ae GY |
147 | /* |
148 | * Send write disble instruction to the chip. | |
149 | */ | |
150 | static inline int write_disable(struct m25p *flash) | |
151 | { | |
152 | u8 code = OPCODE_WRDI; | |
153 | ||
154 | return spi_write_then_read(flash->spi, &code, 1, NULL, 0); | |
155 | } | |
2f9f7628 | 156 | |
4b7f7422 KC |
157 | /* |
158 | * Enable/disable 4-byte addressing mode. | |
159 | */ | |
baa9ae3c | 160 | static inline int set_4byte(struct m25p *flash, u32 jedec_id, int enable) |
4b7f7422 | 161 | { |
baa9ae3c KC |
162 | switch (JEDEC_MFR(jedec_id)) { |
163 | case CFI_MFR_MACRONIX: | |
0aa87b75 | 164 | case 0xEF /* winbond */: |
baa9ae3c KC |
165 | flash->command[0] = enable ? OPCODE_EN4B : OPCODE_EX4B; |
166 | return spi_write(flash->spi, flash->command, 1); | |
167 | default: | |
168 | /* Spansion style */ | |
169 | flash->command[0] = OPCODE_BRWR; | |
170 | flash->command[1] = enable << 7; | |
171 | return spi_write(flash->spi, flash->command, 2); | |
172 | } | |
4b7f7422 KC |
173 | } |
174 | ||
2f9f7628 ML |
175 | /* |
176 | * Service routine to read status register until ready, or timeout occurs. | |
177 | * Returns non-zero if error. | |
178 | */ | |
179 | static int wait_till_ready(struct m25p *flash) | |
180 | { | |
cd1a6de7 | 181 | unsigned long deadline; |
2f9f7628 ML |
182 | int sr; |
183 | ||
cd1a6de7 PH |
184 | deadline = jiffies + MAX_READY_WAIT_JIFFIES; |
185 | ||
186 | do { | |
2f9f7628 ML |
187 | if ((sr = read_sr(flash)) < 0) |
188 | break; | |
189 | else if (!(sr & SR_WIP)) | |
190 | return 0; | |
191 | ||
cd1a6de7 PH |
192 | cond_resched(); |
193 | ||
194 | } while (!time_after_eq(jiffies, deadline)); | |
2f9f7628 ML |
195 | |
196 | return 1; | |
197 | } | |
198 | ||
faff3750 CG |
199 | /* |
200 | * Erase the whole flash memory | |
201 | * | |
202 | * Returns 0 if successful, non-zero otherwise. | |
203 | */ | |
7854643a | 204 | static int erase_chip(struct m25p *flash) |
faff3750 | 205 | { |
0a32a102 BN |
206 | pr_debug("%s: %s %lldKiB\n", dev_name(&flash->spi->dev), __func__, |
207 | (long long)(flash->mtd.size >> 10)); | |
faff3750 CG |
208 | |
209 | /* Wait until finished previous write command. */ | |
210 | if (wait_till_ready(flash)) | |
211 | return 1; | |
212 | ||
213 | /* Send write enable, then erase commands. */ | |
214 | write_enable(flash); | |
215 | ||
216 | /* Set up command buffer. */ | |
7854643a | 217 | flash->command[0] = OPCODE_CHIP_ERASE; |
faff3750 CG |
218 | |
219 | spi_write(flash->spi, flash->command, 1); | |
220 | ||
221 | return 0; | |
222 | } | |
2f9f7628 | 223 | |
837479d2 AV |
224 | static void m25p_addr2cmd(struct m25p *flash, unsigned int addr, u8 *cmd) |
225 | { | |
226 | /* opcode is in cmd[0] */ | |
227 | cmd[1] = addr >> (flash->addr_width * 8 - 8); | |
228 | cmd[2] = addr >> (flash->addr_width * 8 - 16); | |
229 | cmd[3] = addr >> (flash->addr_width * 8 - 24); | |
4b7f7422 | 230 | cmd[4] = addr >> (flash->addr_width * 8 - 32); |
837479d2 AV |
231 | } |
232 | ||
233 | static int m25p_cmdsz(struct m25p *flash) | |
234 | { | |
235 | return 1 + flash->addr_width; | |
236 | } | |
237 | ||
2f9f7628 ML |
238 | /* |
239 | * Erase one sector of flash memory at offset ``offset'' which is any | |
240 | * address within the sector which should be erased. | |
241 | * | |
242 | * Returns 0 if successful, non-zero otherwise. | |
243 | */ | |
244 | static int erase_sector(struct m25p *flash, u32 offset) | |
245 | { | |
0a32a102 BN |
246 | pr_debug("%s: %s %dKiB at 0x%08x\n", dev_name(&flash->spi->dev), |
247 | __func__, flash->mtd.erasesize / 1024, offset); | |
2f9f7628 ML |
248 | |
249 | /* Wait until finished previous write command. */ | |
250 | if (wait_till_ready(flash)) | |
251 | return 1; | |
252 | ||
253 | /* Send write enable, then erase commands. */ | |
254 | write_enable(flash); | |
255 | ||
256 | /* Set up command buffer. */ | |
fa0a8c71 | 257 | flash->command[0] = flash->erase_opcode; |
837479d2 | 258 | m25p_addr2cmd(flash, offset, flash->command); |
2f9f7628 | 259 | |
837479d2 | 260 | spi_write(flash->spi, flash->command, m25p_cmdsz(flash)); |
2f9f7628 ML |
261 | |
262 | return 0; | |
263 | } | |
264 | ||
265 | /****************************************************************************/ | |
266 | ||
267 | /* | |
268 | * MTD implementation | |
269 | */ | |
270 | ||
271 | /* | |
272 | * Erase an address range on the flash chip. The address range may extend | |
273 | * one or more erase sectors. Return an error is there is a problem erasing. | |
274 | */ | |
275 | static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr) | |
276 | { | |
277 | struct m25p *flash = mtd_to_m25p(mtd); | |
278 | u32 addr,len; | |
d85316ac | 279 | uint32_t rem; |
2f9f7628 | 280 | |
0a32a102 BN |
281 | pr_debug("%s: %s at 0x%llx, len %lld\n", dev_name(&flash->spi->dev), |
282 | __func__, (long long)instr->addr, | |
283 | (long long)instr->len); | |
2f9f7628 | 284 | |
d85316ac AB |
285 | div_u64_rem(instr->len, mtd->erasesize, &rem); |
286 | if (rem) | |
2f9f7628 | 287 | return -EINVAL; |
2f9f7628 ML |
288 | |
289 | addr = instr->addr; | |
290 | len = instr->len; | |
291 | ||
7d5230ea | 292 | mutex_lock(&flash->lock); |
2f9f7628 | 293 | |
7854643a | 294 | /* whole-chip erase? */ |
3f33b0aa SF |
295 | if (len == flash->mtd.size) { |
296 | if (erase_chip(flash)) { | |
297 | instr->state = MTD_ERASE_FAILED; | |
298 | mutex_unlock(&flash->lock); | |
299 | return -EIO; | |
300 | } | |
7854643a CG |
301 | |
302 | /* REVISIT in some cases we could speed up erasing large regions | |
303 | * by using OPCODE_SE instead of OPCODE_BE_4K. We may have set up | |
304 | * to use "small sector erase", but that's not always optimal. | |
305 | */ | |
306 | ||
307 | /* "sector"-at-a-time erase */ | |
faff3750 CG |
308 | } else { |
309 | while (len) { | |
310 | if (erase_sector(flash, addr)) { | |
311 | instr->state = MTD_ERASE_FAILED; | |
312 | mutex_unlock(&flash->lock); | |
313 | return -EIO; | |
314 | } | |
315 | ||
316 | addr += mtd->erasesize; | |
317 | len -= mtd->erasesize; | |
2f9f7628 | 318 | } |
2f9f7628 ML |
319 | } |
320 | ||
7d5230ea | 321 | mutex_unlock(&flash->lock); |
2f9f7628 ML |
322 | |
323 | instr->state = MTD_ERASE_DONE; | |
324 | mtd_erase_callback(instr); | |
325 | ||
326 | return 0; | |
327 | } | |
328 | ||
329 | /* | |
330 | * Read an address range from the flash chip. The address range | |
331 | * may be any size provided it is within the physical boundaries. | |
332 | */ | |
333 | static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len, | |
334 | size_t *retlen, u_char *buf) | |
335 | { | |
336 | struct m25p *flash = mtd_to_m25p(mtd); | |
337 | struct spi_transfer t[2]; | |
338 | struct spi_message m; | |
12ad2be9 | 339 | uint8_t opcode; |
2f9f7628 | 340 | |
0a32a102 BN |
341 | pr_debug("%s: %s from 0x%08x, len %zd\n", dev_name(&flash->spi->dev), |
342 | __func__, (u32)from, len); | |
2f9f7628 | 343 | |
8275c642 VW |
344 | spi_message_init(&m); |
345 | memset(t, 0, (sizeof t)); | |
346 | ||
2230b76b BW |
347 | /* NOTE: |
348 | * OPCODE_FAST_READ (if available) is faster. | |
349 | * Should add 1 byte DUMMY_BYTE. | |
350 | */ | |
8275c642 | 351 | t[0].tx_buf = flash->command; |
12ad2be9 | 352 | t[0].len = m25p_cmdsz(flash) + (flash->fast_read ? 1 : 0); |
8275c642 VW |
353 | spi_message_add_tail(&t[0], &m); |
354 | ||
355 | t[1].rx_buf = buf; | |
356 | t[1].len = len; | |
357 | spi_message_add_tail(&t[1], &m); | |
358 | ||
7d5230ea | 359 | mutex_lock(&flash->lock); |
2f9f7628 ML |
360 | |
361 | /* Wait till previous write/erase is done. */ | |
362 | if (wait_till_ready(flash)) { | |
363 | /* REVISIT status return?? */ | |
7d5230ea | 364 | mutex_unlock(&flash->lock); |
2f9f7628 ML |
365 | return 1; |
366 | } | |
367 | ||
fa0a8c71 DB |
368 | /* FIXME switch to OPCODE_FAST_READ. It's required for higher |
369 | * clocks; and at this writing, every chip this driver handles | |
370 | * supports that opcode. | |
371 | */ | |
2f9f7628 ML |
372 | |
373 | /* Set up the write data buffer. */ | |
12ad2be9 MV |
374 | opcode = flash->fast_read ? OPCODE_FAST_READ : OPCODE_NORM_READ; |
375 | flash->command[0] = opcode; | |
837479d2 | 376 | m25p_addr2cmd(flash, from, flash->command); |
2f9f7628 | 377 | |
2f9f7628 ML |
378 | spi_sync(flash->spi, &m); |
379 | ||
12ad2be9 MV |
380 | *retlen = m.actual_length - m25p_cmdsz(flash) - |
381 | (flash->fast_read ? 1 : 0); | |
2f9f7628 | 382 | |
7d5230ea | 383 | mutex_unlock(&flash->lock); |
2f9f7628 ML |
384 | |
385 | return 0; | |
386 | } | |
387 | ||
388 | /* | |
389 | * Write an address range to the flash chip. Data must be written in | |
390 | * FLASH_PAGESIZE chunks. The address range may be any size provided | |
391 | * it is within the physical boundaries. | |
392 | */ | |
393 | static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len, | |
394 | size_t *retlen, const u_char *buf) | |
395 | { | |
396 | struct m25p *flash = mtd_to_m25p(mtd); | |
397 | u32 page_offset, page_size; | |
398 | struct spi_transfer t[2]; | |
399 | struct spi_message m; | |
400 | ||
0a32a102 BN |
401 | pr_debug("%s: %s to 0x%08x, len %zd\n", dev_name(&flash->spi->dev), |
402 | __func__, (u32)to, len); | |
2f9f7628 | 403 | |
8275c642 VW |
404 | spi_message_init(&m); |
405 | memset(t, 0, (sizeof t)); | |
406 | ||
407 | t[0].tx_buf = flash->command; | |
837479d2 | 408 | t[0].len = m25p_cmdsz(flash); |
8275c642 VW |
409 | spi_message_add_tail(&t[0], &m); |
410 | ||
411 | t[1].tx_buf = buf; | |
412 | spi_message_add_tail(&t[1], &m); | |
413 | ||
7d5230ea | 414 | mutex_lock(&flash->lock); |
2f9f7628 ML |
415 | |
416 | /* Wait until finished previous write command. */ | |
bc018863 CG |
417 | if (wait_till_ready(flash)) { |
418 | mutex_unlock(&flash->lock); | |
2f9f7628 | 419 | return 1; |
bc018863 | 420 | } |
2f9f7628 ML |
421 | |
422 | write_enable(flash); | |
423 | ||
2f9f7628 ML |
424 | /* Set up the opcode in the write buffer. */ |
425 | flash->command[0] = OPCODE_PP; | |
837479d2 | 426 | m25p_addr2cmd(flash, to, flash->command); |
2f9f7628 | 427 | |
837479d2 | 428 | page_offset = to & (flash->page_size - 1); |
2f9f7628 ML |
429 | |
430 | /* do all the bytes fit onto one page? */ | |
837479d2 | 431 | if (page_offset + len <= flash->page_size) { |
2f9f7628 ML |
432 | t[1].len = len; |
433 | ||
434 | spi_sync(flash->spi, &m); | |
435 | ||
837479d2 | 436 | *retlen = m.actual_length - m25p_cmdsz(flash); |
2f9f7628 ML |
437 | } else { |
438 | u32 i; | |
439 | ||
440 | /* the size of data remaining on the first page */ | |
837479d2 | 441 | page_size = flash->page_size - page_offset; |
2f9f7628 | 442 | |
2f9f7628 ML |
443 | t[1].len = page_size; |
444 | spi_sync(flash->spi, &m); | |
445 | ||
837479d2 | 446 | *retlen = m.actual_length - m25p_cmdsz(flash); |
2f9f7628 | 447 | |
837479d2 | 448 | /* write everything in flash->page_size chunks */ |
2f9f7628 ML |
449 | for (i = page_size; i < len; i += page_size) { |
450 | page_size = len - i; | |
837479d2 AV |
451 | if (page_size > flash->page_size) |
452 | page_size = flash->page_size; | |
2f9f7628 ML |
453 | |
454 | /* write the next page to flash */ | |
837479d2 | 455 | m25p_addr2cmd(flash, to + i, flash->command); |
2f9f7628 ML |
456 | |
457 | t[1].tx_buf = buf + i; | |
458 | t[1].len = page_size; | |
459 | ||
460 | wait_till_ready(flash); | |
461 | ||
462 | write_enable(flash); | |
463 | ||
464 | spi_sync(flash->spi, &m); | |
465 | ||
b06cd21e | 466 | *retlen += m.actual_length - m25p_cmdsz(flash); |
7d5230ea DB |
467 | } |
468 | } | |
2f9f7628 | 469 | |
7d5230ea | 470 | mutex_unlock(&flash->lock); |
2f9f7628 ML |
471 | |
472 | return 0; | |
473 | } | |
474 | ||
49aac4ae GY |
475 | static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, |
476 | size_t *retlen, const u_char *buf) | |
477 | { | |
478 | struct m25p *flash = mtd_to_m25p(mtd); | |
479 | struct spi_transfer t[2]; | |
480 | struct spi_message m; | |
481 | size_t actual; | |
482 | int cmd_sz, ret; | |
483 | ||
0a32a102 BN |
484 | pr_debug("%s: %s to 0x%08x, len %zd\n", dev_name(&flash->spi->dev), |
485 | __func__, (u32)to, len); | |
dcf12463 | 486 | |
49aac4ae GY |
487 | spi_message_init(&m); |
488 | memset(t, 0, (sizeof t)); | |
489 | ||
490 | t[0].tx_buf = flash->command; | |
837479d2 | 491 | t[0].len = m25p_cmdsz(flash); |
49aac4ae GY |
492 | spi_message_add_tail(&t[0], &m); |
493 | ||
494 | t[1].tx_buf = buf; | |
495 | spi_message_add_tail(&t[1], &m); | |
496 | ||
497 | mutex_lock(&flash->lock); | |
498 | ||
499 | /* Wait until finished previous write command. */ | |
500 | ret = wait_till_ready(flash); | |
501 | if (ret) | |
502 | goto time_out; | |
503 | ||
504 | write_enable(flash); | |
505 | ||
506 | actual = to % 2; | |
507 | /* Start write from odd address. */ | |
508 | if (actual) { | |
509 | flash->command[0] = OPCODE_BP; | |
837479d2 | 510 | m25p_addr2cmd(flash, to, flash->command); |
49aac4ae GY |
511 | |
512 | /* write one byte. */ | |
513 | t[1].len = 1; | |
514 | spi_sync(flash->spi, &m); | |
515 | ret = wait_till_ready(flash); | |
516 | if (ret) | |
517 | goto time_out; | |
837479d2 | 518 | *retlen += m.actual_length - m25p_cmdsz(flash); |
49aac4ae GY |
519 | } |
520 | to += actual; | |
521 | ||
522 | flash->command[0] = OPCODE_AAI_WP; | |
837479d2 | 523 | m25p_addr2cmd(flash, to, flash->command); |
49aac4ae GY |
524 | |
525 | /* Write out most of the data here. */ | |
837479d2 | 526 | cmd_sz = m25p_cmdsz(flash); |
49aac4ae GY |
527 | for (; actual < len - 1; actual += 2) { |
528 | t[0].len = cmd_sz; | |
529 | /* write two bytes. */ | |
530 | t[1].len = 2; | |
531 | t[1].tx_buf = buf + actual; | |
532 | ||
533 | spi_sync(flash->spi, &m); | |
534 | ret = wait_till_ready(flash); | |
535 | if (ret) | |
536 | goto time_out; | |
537 | *retlen += m.actual_length - cmd_sz; | |
538 | cmd_sz = 1; | |
539 | to += 2; | |
540 | } | |
541 | write_disable(flash); | |
542 | ret = wait_till_ready(flash); | |
543 | if (ret) | |
544 | goto time_out; | |
545 | ||
546 | /* Write out trailing byte if it exists. */ | |
547 | if (actual != len) { | |
548 | write_enable(flash); | |
549 | flash->command[0] = OPCODE_BP; | |
837479d2 AV |
550 | m25p_addr2cmd(flash, to, flash->command); |
551 | t[0].len = m25p_cmdsz(flash); | |
49aac4ae GY |
552 | t[1].len = 1; |
553 | t[1].tx_buf = buf + actual; | |
554 | ||
555 | spi_sync(flash->spi, &m); | |
556 | ret = wait_till_ready(flash); | |
557 | if (ret) | |
558 | goto time_out; | |
837479d2 | 559 | *retlen += m.actual_length - m25p_cmdsz(flash); |
49aac4ae GY |
560 | write_disable(flash); |
561 | } | |
562 | ||
563 | time_out: | |
564 | mutex_unlock(&flash->lock); | |
565 | return ret; | |
566 | } | |
2f9f7628 ML |
567 | |
568 | /****************************************************************************/ | |
569 | ||
570 | /* | |
571 | * SPI device driver setup and teardown | |
572 | */ | |
573 | ||
574 | struct flash_info { | |
fa0a8c71 DB |
575 | /* JEDEC id zero means "no ID" (most older chips); otherwise it has |
576 | * a high byte of zero plus three data bytes: the manufacturer id, | |
577 | * then a two byte device id. | |
578 | */ | |
579 | u32 jedec_id; | |
d0e8c47c | 580 | u16 ext_id; |
fa0a8c71 DB |
581 | |
582 | /* The size listed here is what works with OPCODE_SE, which isn't | |
583 | * necessarily called a "sector" by the vendor. | |
584 | */ | |
2f9f7628 | 585 | unsigned sector_size; |
fa0a8c71 DB |
586 | u16 n_sectors; |
587 | ||
837479d2 AV |
588 | u16 page_size; |
589 | u16 addr_width; | |
590 | ||
fa0a8c71 DB |
591 | u16 flags; |
592 | #define SECT_4K 0x01 /* OPCODE_BE_4K works uniformly */ | |
837479d2 | 593 | #define M25P_NO_ERASE 0x02 /* No erase command needed */ |
2f9f7628 ML |
594 | }; |
595 | ||
b34bc037 AV |
596 | #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ |
597 | ((kernel_ulong_t)&(struct flash_info) { \ | |
598 | .jedec_id = (_jedec_id), \ | |
599 | .ext_id = (_ext_id), \ | |
600 | .sector_size = (_sector_size), \ | |
601 | .n_sectors = (_n_sectors), \ | |
837479d2 | 602 | .page_size = 256, \ |
b34bc037 AV |
603 | .flags = (_flags), \ |
604 | }) | |
fa0a8c71 | 605 | |
837479d2 AV |
606 | #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width) \ |
607 | ((kernel_ulong_t)&(struct flash_info) { \ | |
608 | .sector_size = (_sector_size), \ | |
609 | .n_sectors = (_n_sectors), \ | |
610 | .page_size = (_page_size), \ | |
611 | .addr_width = (_addr_width), \ | |
612 | .flags = M25P_NO_ERASE, \ | |
613 | }) | |
fa0a8c71 DB |
614 | |
615 | /* NOTE: double check command sets and memory organization when you add | |
616 | * more flash chips. This current list focusses on newer chips, which | |
617 | * have been converging on command sets which including JEDEC ID. | |
618 | */ | |
b34bc037 | 619 | static const struct spi_device_id m25p_ids[] = { |
fa0a8c71 | 620 | /* Atmel -- some are (confusingly) marketed as "DataFlash" */ |
b34bc037 AV |
621 | { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) }, |
622 | { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) }, | |
fa0a8c71 | 623 | |
b34bc037 | 624 | { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) }, |
ada766e9 | 625 | { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) }, |
b34bc037 | 626 | { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) }, |
fa0a8c71 | 627 | |
b34bc037 AV |
628 | { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) }, |
629 | { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) }, | |
630 | { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) }, | |
8fffed8c | 631 | { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) }, |
fa0a8c71 | 632 | |
a5b2d76d CL |
633 | { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) }, |
634 | ||
37a23c20 GJ |
635 | /* EON -- en25xxx */ |
636 | { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) }, | |
60845e72 | 637 | { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) }, |
86a9893d | 638 | { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) }, |
60845e72 | 639 | { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) }, |
58d864ed | 640 | { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) }, |
60845e72 | 641 | |
5ca11ca7 MV |
642 | /* Everspin */ |
643 | { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2) }, | |
644 | ||
f80e521c GJ |
645 | /* Intel/Numonyx -- xxxs33b */ |
646 | { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) }, | |
647 | { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) }, | |
648 | { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) }, | |
95c1b0ce | 649 | { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, 0) }, |
f80e521c | 650 | |
ab1ff210 | 651 | /* Macronix */ |
bb08bc10 | 652 | { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) }, |
df0094d7 | 653 | { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) }, |
6175f4a1 | 654 | { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) }, |
9c76b4e5 | 655 | { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) }, |
b34bc037 AV |
656 | { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) }, |
657 | { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) }, | |
658 | { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) }, | |
659 | { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) }, | |
4b7f7422 | 660 | { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) }, |
ac622f58 | 661 | { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) }, |
ab1ff210 | 662 | |
8da28681 | 663 | /* Micron */ |
3105875f | 664 | { "n25q128", INFO(0x20ba18, 0, 64 * 1024, 256, 0) }, |
8da28681 VD |
665 | { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K) }, |
666 | ||
fa0a8c71 DB |
667 | /* Spansion -- single (large) sector size only, at least |
668 | * for the chips listed here (without boot sectors). | |
669 | */ | |
b277f77e MV |
670 | { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, 0) }, |
671 | { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, 0) }, | |
baa9ae3c KC |
672 | { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) }, |
673 | { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, 0) }, | |
3d2d2b65 KC |
674 | { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, 0) }, |
675 | { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) }, | |
b34bc037 AV |
676 | { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) }, |
677 | { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) }, | |
678 | { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) }, | |
679 | { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) }, | |
8bb8b85f MV |
680 | { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) }, |
681 | { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) }, | |
682 | { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) }, | |
683 | { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) }, | |
684 | { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) }, | |
f2df1ae3 GH |
685 | { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) }, |
686 | { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, | |
fa0a8c71 DB |
687 | |
688 | /* SST -- large erase sizes are "overlays", "sectors" are 4K */ | |
b34bc037 AV |
689 | { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K) }, |
690 | { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K) }, | |
691 | { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K) }, | |
692 | { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K) }, | |
693 | { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K) }, | |
694 | { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K) }, | |
695 | { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K) }, | |
696 | { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K) }, | |
fa0a8c71 DB |
697 | |
698 | /* ST Microelectronics -- newer production may have feature updates */ | |
b34bc037 AV |
699 | { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) }, |
700 | { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) }, | |
701 | { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) }, | |
702 | { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) }, | |
703 | { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) }, | |
704 | { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) }, | |
705 | { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) }, | |
706 | { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) }, | |
707 | { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) }, | |
4800399e | 708 | { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, 0) }, |
b34bc037 | 709 | |
f7b00090 AV |
710 | { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) }, |
711 | { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) }, | |
712 | { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) }, | |
713 | { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) }, | |
714 | { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) }, | |
715 | { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) }, | |
716 | { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) }, | |
717 | { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) }, | |
718 | { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) }, | |
719 | ||
b34bc037 AV |
720 | { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) }, |
721 | { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) }, | |
722 | { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) }, | |
723 | ||
943b35a6 | 724 | { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) }, |
b34bc037 AV |
725 | { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) }, |
726 | { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) }, | |
fa0a8c71 | 727 | |
16004f36 KC |
728 | { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) }, |
729 | { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) }, | |
730 | { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) }, | |
731 | { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) }, | |
d8f90b2c | 732 | |
02d087db | 733 | /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ |
b34bc037 AV |
734 | { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) }, |
735 | { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) }, | |
736 | { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) }, | |
737 | { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) }, | |
738 | { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) }, | |
739 | { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) }, | |
0af18d27 | 740 | { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) }, |
9d6367f4 | 741 | { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K) }, |
b34bc037 | 742 | { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) }, |
d2ac467a | 743 | { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, |
4fba37ae | 744 | { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) }, |
9b7ef60c | 745 | { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) }, |
0aa87b75 | 746 | { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) }, |
837479d2 AV |
747 | |
748 | /* Catalyst / On Semiconductor -- non-JEDEC */ | |
749 | { "cat25c11", CAT25_INFO( 16, 8, 16, 1) }, | |
750 | { "cat25c03", CAT25_INFO( 32, 8, 16, 2) }, | |
751 | { "cat25c09", CAT25_INFO( 128, 8, 32, 2) }, | |
752 | { "cat25c17", CAT25_INFO( 256, 8, 32, 2) }, | |
753 | { "cat25128", CAT25_INFO(2048, 8, 64, 2) }, | |
b34bc037 | 754 | { }, |
2f9f7628 | 755 | }; |
b34bc037 | 756 | MODULE_DEVICE_TABLE(spi, m25p_ids); |
2f9f7628 | 757 | |
06f25510 | 758 | static const struct spi_device_id *jedec_probe(struct spi_device *spi) |
fa0a8c71 DB |
759 | { |
760 | int tmp; | |
761 | u8 code = OPCODE_RDID; | |
daa84735 | 762 | u8 id[5]; |
fa0a8c71 | 763 | u32 jedec; |
d0e8c47c | 764 | u16 ext_jedec; |
fa0a8c71 DB |
765 | struct flash_info *info; |
766 | ||
767 | /* JEDEC also defines an optional "extended device information" | |
768 | * string for after vendor-specific data, after the three bytes | |
769 | * we use here. Supporting some chips might require using it. | |
770 | */ | |
daa84735 | 771 | tmp = spi_write_then_read(spi, &code, 1, id, 5); |
fa0a8c71 | 772 | if (tmp < 0) { |
289c0522 | 773 | pr_debug("%s: error %d reading JEDEC ID\n", |
0a32a102 | 774 | dev_name(&spi->dev), tmp); |
9d2c4f3f | 775 | return ERR_PTR(tmp); |
fa0a8c71 DB |
776 | } |
777 | jedec = id[0]; | |
778 | jedec = jedec << 8; | |
779 | jedec |= id[1]; | |
780 | jedec = jedec << 8; | |
781 | jedec |= id[2]; | |
782 | ||
d0e8c47c CG |
783 | ext_jedec = id[3] << 8 | id[4]; |
784 | ||
b34bc037 AV |
785 | for (tmp = 0; tmp < ARRAY_SIZE(m25p_ids) - 1; tmp++) { |
786 | info = (void *)m25p_ids[tmp].driver_data; | |
a3d3f73c | 787 | if (info->jedec_id == jedec) { |
9168ab86 | 788 | if (info->ext_id != 0 && info->ext_id != ext_jedec) |
d0e8c47c | 789 | continue; |
b34bc037 | 790 | return &m25p_ids[tmp]; |
a3d3f73c | 791 | } |
fa0a8c71 | 792 | } |
f0dff9bd | 793 | dev_err(&spi->dev, "unrecognized JEDEC id %06x\n", jedec); |
9d2c4f3f | 794 | return ERR_PTR(-ENODEV); |
fa0a8c71 DB |
795 | } |
796 | ||
797 | ||
2f9f7628 ML |
798 | /* |
799 | * board specific setup should have ensured the SPI clock used here | |
800 | * matches what the READ command supports, at least until this driver | |
801 | * understands FAST_READ (for clocks over 25 MHz). | |
802 | */ | |
06f25510 | 803 | static int m25p_probe(struct spi_device *spi) |
2f9f7628 | 804 | { |
18c6182b | 805 | const struct spi_device_id *id = spi_get_device_id(spi); |
2f9f7628 ML |
806 | struct flash_platform_data *data; |
807 | struct m25p *flash; | |
808 | struct flash_info *info; | |
809 | unsigned i; | |
ea6a4729 | 810 | struct mtd_part_parser_data ppdata; |
12ad2be9 | 811 | struct device_node __maybe_unused *np = spi->dev.of_node; |
2f9f7628 | 812 | |
5f949137 | 813 | #ifdef CONFIG_MTD_OF_PARTS |
12ad2be9 | 814 | if (!of_device_is_available(np)) |
5f949137 SX |
815 | return -ENODEV; |
816 | #endif | |
817 | ||
2f9f7628 | 818 | /* Platform data helps sort out which chip type we have, as |
fa0a8c71 DB |
819 | * well as how this board partitions it. If we don't have |
820 | * a chip ID, try the JEDEC id commands; they'll work for most | |
821 | * newer chips, even if we don't recognize the particular chip. | |
2f9f7628 ML |
822 | */ |
823 | data = spi->dev.platform_data; | |
fa0a8c71 | 824 | if (data && data->type) { |
18c6182b | 825 | const struct spi_device_id *plat_id; |
2f9f7628 | 826 | |
b34bc037 | 827 | for (i = 0; i < ARRAY_SIZE(m25p_ids) - 1; i++) { |
18c6182b AV |
828 | plat_id = &m25p_ids[i]; |
829 | if (strcmp(data->type, plat_id->name)) | |
b34bc037 AV |
830 | continue; |
831 | break; | |
fa0a8c71 | 832 | } |
fa0a8c71 | 833 | |
f78ec6b2 | 834 | if (i < ARRAY_SIZE(m25p_ids) - 1) |
18c6182b AV |
835 | id = plat_id; |
836 | else | |
837 | dev_warn(&spi->dev, "unrecognized id %s\n", data->type); | |
b34bc037 | 838 | } |
fa0a8c71 | 839 | |
18c6182b AV |
840 | info = (void *)id->driver_data; |
841 | ||
842 | if (info->jedec_id) { | |
843 | const struct spi_device_id *jid; | |
844 | ||
845 | jid = jedec_probe(spi); | |
9d2c4f3f AV |
846 | if (IS_ERR(jid)) { |
847 | return PTR_ERR(jid); | |
18c6182b AV |
848 | } else if (jid != id) { |
849 | /* | |
850 | * JEDEC knows better, so overwrite platform ID. We | |
851 | * can't trust partitions any longer, but we'll let | |
852 | * mtd apply them anyway, since some partitions may be | |
853 | * marked read-only, and we don't want to lose that | |
854 | * information, even if it's not 100% accurate. | |
855 | */ | |
856 | dev_warn(&spi->dev, "found %s, expected %s\n", | |
857 | jid->name, id->name); | |
858 | id = jid; | |
859 | info = (void *)jid->driver_data; | |
860 | } | |
861 | } | |
2f9f7628 | 862 | |
e94b1766 | 863 | flash = kzalloc(sizeof *flash, GFP_KERNEL); |
2f9f7628 ML |
864 | if (!flash) |
865 | return -ENOMEM; | |
12ad2be9 MV |
866 | flash->command = kmalloc(MAX_CMD_SIZE + (flash->fast_read ? 1 : 0), |
867 | GFP_KERNEL); | |
61c3506c JS |
868 | if (!flash->command) { |
869 | kfree(flash); | |
870 | return -ENOMEM; | |
871 | } | |
2f9f7628 ML |
872 | |
873 | flash->spi = spi; | |
7d5230ea | 874 | mutex_init(&flash->lock); |
2f9f7628 ML |
875 | dev_set_drvdata(&spi->dev, flash); |
876 | ||
72289824 | 877 | /* |
f80e521c | 878 | * Atmel, SST and Intel/Numonyx serial flash tend to power |
ea60658a | 879 | * up with the software protection bits set |
72289824 MH |
880 | */ |
881 | ||
aa084653 KC |
882 | if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ATMEL || |
883 | JEDEC_MFR(info->jedec_id) == CFI_MFR_INTEL || | |
884 | JEDEC_MFR(info->jedec_id) == CFI_MFR_SST) { | |
72289824 MH |
885 | write_enable(flash); |
886 | write_sr(flash, 0); | |
887 | } | |
888 | ||
fa0a8c71 | 889 | if (data && data->name) |
2f9f7628 ML |
890 | flash->mtd.name = data->name; |
891 | else | |
160bbab3 | 892 | flash->mtd.name = dev_name(&spi->dev); |
2f9f7628 ML |
893 | |
894 | flash->mtd.type = MTD_NORFLASH; | |
783ed81f | 895 | flash->mtd.writesize = 1; |
2f9f7628 ML |
896 | flash->mtd.flags = MTD_CAP_NORFLASH; |
897 | flash->mtd.size = info->sector_size * info->n_sectors; | |
3c3c10bb AB |
898 | flash->mtd._erase = m25p80_erase; |
899 | flash->mtd._read = m25p80_read; | |
49aac4ae GY |
900 | |
901 | /* sst flash chips use AAI word program */ | |
aa084653 | 902 | if (JEDEC_MFR(info->jedec_id) == CFI_MFR_SST) |
3c3c10bb | 903 | flash->mtd._write = sst_write; |
49aac4ae | 904 | else |
3c3c10bb | 905 | flash->mtd._write = m25p80_write; |
2f9f7628 | 906 | |
fa0a8c71 DB |
907 | /* prefer "small sector" erase if possible */ |
908 | if (info->flags & SECT_4K) { | |
909 | flash->erase_opcode = OPCODE_BE_4K; | |
910 | flash->mtd.erasesize = 4096; | |
911 | } else { | |
912 | flash->erase_opcode = OPCODE_SE; | |
913 | flash->mtd.erasesize = info->sector_size; | |
914 | } | |
915 | ||
837479d2 AV |
916 | if (info->flags & M25P_NO_ERASE) |
917 | flash->mtd.flags |= MTD_NO_ERASE; | |
918 | ||
ea6a4729 | 919 | ppdata.of_node = spi->dev.of_node; |
87f39f04 | 920 | flash->mtd.dev.parent = &spi->dev; |
837479d2 | 921 | flash->page_size = info->page_size; |
b54f47c8 | 922 | flash->mtd.writebufsize = flash->page_size; |
4b7f7422 | 923 | |
12ad2be9 MV |
924 | flash->fast_read = false; |
925 | #ifdef CONFIG_OF | |
926 | if (np && of_property_read_bool(np, "m25p,fast-read")) | |
927 | flash->fast_read = true; | |
928 | #endif | |
929 | ||
930 | #ifdef CONFIG_M25PXX_USE_FAST_READ | |
931 | flash->fast_read = true; | |
932 | #endif | |
933 | ||
4b7f7422 KC |
934 | if (info->addr_width) |
935 | flash->addr_width = info->addr_width; | |
936 | else { | |
937 | /* enable 4-byte addressing if the device exceeds 16MiB */ | |
938 | if (flash->mtd.size > 0x1000000) { | |
939 | flash->addr_width = 4; | |
baa9ae3c | 940 | set_4byte(flash, info->jedec_id, 1); |
4b7f7422 KC |
941 | } else |
942 | flash->addr_width = 3; | |
943 | } | |
87f39f04 | 944 | |
b34bc037 | 945 | dev_info(&spi->dev, "%s (%lld Kbytes)\n", id->name, |
d85316ac | 946 | (long long)flash->mtd.size >> 10); |
2f9f7628 | 947 | |
289c0522 | 948 | pr_debug("mtd .name = %s, .size = 0x%llx (%lldMiB) " |
02d087db | 949 | ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n", |
2f9f7628 | 950 | flash->mtd.name, |
d85316ac | 951 | (long long)flash->mtd.size, (long long)(flash->mtd.size >> 20), |
2f9f7628 ML |
952 | flash->mtd.erasesize, flash->mtd.erasesize / 1024, |
953 | flash->mtd.numeraseregions); | |
954 | ||
955 | if (flash->mtd.numeraseregions) | |
956 | for (i = 0; i < flash->mtd.numeraseregions; i++) | |
289c0522 | 957 | pr_debug("mtd.eraseregions[%d] = { .offset = 0x%llx, " |
02d087db | 958 | ".erasesize = 0x%.8x (%uKiB), " |
2f9f7628 | 959 | ".numblocks = %d }\n", |
d85316ac | 960 | i, (long long)flash->mtd.eraseregions[i].offset, |
2f9f7628 ML |
961 | flash->mtd.eraseregions[i].erasesize, |
962 | flash->mtd.eraseregions[i].erasesize / 1024, | |
963 | flash->mtd.eraseregions[i].numblocks); | |
964 | ||
965 | ||
966 | /* partitions should match sector boundaries; and it may be good to | |
967 | * use readonly partitions for writeprotected sectors (BP2..BP0). | |
968 | */ | |
871770b5 DES |
969 | return mtd_device_parse_register(&flash->mtd, NULL, &ppdata, |
970 | data ? data->parts : NULL, | |
971 | data ? data->nr_parts : 0); | |
2f9f7628 ML |
972 | } |
973 | ||
974 | ||
810b7e06 | 975 | static int m25p_remove(struct spi_device *spi) |
2f9f7628 ML |
976 | { |
977 | struct m25p *flash = dev_get_drvdata(&spi->dev); | |
978 | int status; | |
979 | ||
980 | /* Clean up MTD stuff. */ | |
ba52f3a2 | 981 | status = mtd_device_unregister(&flash->mtd); |
61c3506c JS |
982 | if (status == 0) { |
983 | kfree(flash->command); | |
2f9f7628 | 984 | kfree(flash); |
61c3506c | 985 | } |
2f9f7628 ML |
986 | return 0; |
987 | } | |
988 | ||
989 | ||
990 | static struct spi_driver m25p80_driver = { | |
991 | .driver = { | |
992 | .name = "m25p80", | |
2f9f7628 ML |
993 | .owner = THIS_MODULE, |
994 | }, | |
b34bc037 | 995 | .id_table = m25p_ids, |
2f9f7628 | 996 | .probe = m25p_probe, |
5153b88c | 997 | .remove = m25p_remove, |
fa0a8c71 DB |
998 | |
999 | /* REVISIT: many of these chips have deep power-down modes, which | |
1000 | * should clearly be entered on suspend() to minimize power use. | |
1001 | * And also when they're otherwise idle... | |
1002 | */ | |
2f9f7628 ML |
1003 | }; |
1004 | ||
c9d1b752 | 1005 | module_spi_driver(m25p80_driver); |
2f9f7628 ML |
1006 | |
1007 | MODULE_LICENSE("GPL"); | |
1008 | MODULE_AUTHOR("Mike Lavender"); | |
1009 | MODULE_DESCRIPTION("MTD SPI driver for ST M25Pxx flash chips"); |