Commit | Line | Data |
---|---|---|
2f9f7628 | 1 | /* |
fa0a8c71 | 2 | * MTD SPI driver for ST M25Pxx (and similar) serial flash chips |
2f9f7628 ML |
3 | * |
4 | * Author: Mike Lavender, mike@steroidmicros.com | |
5 | * | |
6 | * Copyright (c) 2005, Intec Automation Inc. | |
7 | * | |
8 | * Some parts are based on lart.c by Abraham Van Der Merwe | |
9 | * | |
10 | * Cleaned up and generalized based on mtd_dataflash.c | |
11 | * | |
12 | * This code is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | * | |
16 | */ | |
17 | ||
18 | #include <linux/init.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/device.h> | |
21 | #include <linux/interrupt.h> | |
7d5230ea | 22 | #include <linux/mutex.h> |
d85316ac | 23 | #include <linux/math64.h> |
d43c36dc | 24 | #include <linux/sched.h> |
7d5230ea | 25 | |
2f9f7628 ML |
26 | #include <linux/mtd/mtd.h> |
27 | #include <linux/mtd/partitions.h> | |
7d5230ea | 28 | |
2f9f7628 ML |
29 | #include <linux/spi/spi.h> |
30 | #include <linux/spi/flash.h> | |
31 | ||
2f9f7628 | 32 | |
2f9f7628 ML |
33 | #define FLASH_PAGESIZE 256 |
34 | ||
35 | /* Flash opcodes. */ | |
fa0a8c71 DB |
36 | #define OPCODE_WREN 0x06 /* Write enable */ |
37 | #define OPCODE_RDSR 0x05 /* Read status register */ | |
72289824 | 38 | #define OPCODE_WRSR 0x01 /* Write status register 1 byte */ |
2230b76b | 39 | #define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */ |
fa0a8c71 DB |
40 | #define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */ |
41 | #define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */ | |
7854643a | 42 | #define OPCODE_BE_4K 0x20 /* Erase 4KiB block */ |
02d087db | 43 | #define OPCODE_BE_32K 0x52 /* Erase 32KiB block */ |
7854643a | 44 | #define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */ |
02d087db | 45 | #define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */ |
2f9f7628 ML |
46 | #define OPCODE_RDID 0x9f /* Read JEDEC ID */ |
47 | ||
49aac4ae GY |
48 | /* Used for SST flashes only. */ |
49 | #define OPCODE_BP 0x02 /* Byte program */ | |
50 | #define OPCODE_WRDI 0x04 /* Write disable */ | |
51 | #define OPCODE_AAI_WP 0xad /* Auto address increment word program */ | |
52 | ||
2f9f7628 ML |
53 | /* Status Register bits. */ |
54 | #define SR_WIP 1 /* Write in progress */ | |
55 | #define SR_WEL 2 /* Write enable latch */ | |
fa0a8c71 | 56 | /* meaning of other SR_* bits may differ between vendors */ |
2f9f7628 ML |
57 | #define SR_BP0 4 /* Block protect 0 */ |
58 | #define SR_BP1 8 /* Block protect 1 */ | |
59 | #define SR_BP2 0x10 /* Block protect 2 */ | |
60 | #define SR_SRWD 0x80 /* SR write protect */ | |
61 | ||
62 | /* Define max times to check status register before we give up. */ | |
89bb871e | 63 | #define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */ |
2230b76b | 64 | #define CMD_SIZE 4 |
2f9f7628 | 65 | |
2230b76b BW |
66 | #ifdef CONFIG_M25PXX_USE_FAST_READ |
67 | #define OPCODE_READ OPCODE_FAST_READ | |
68 | #define FAST_READ_DUMMY_BYTE 1 | |
69 | #else | |
70 | #define OPCODE_READ OPCODE_NORM_READ | |
71 | #define FAST_READ_DUMMY_BYTE 0 | |
72 | #endif | |
2f9f7628 | 73 | |
2f9f7628 ML |
74 | /****************************************************************************/ |
75 | ||
76 | struct m25p { | |
77 | struct spi_device *spi; | |
7d5230ea | 78 | struct mutex lock; |
2f9f7628 | 79 | struct mtd_info mtd; |
fa0a8c71 DB |
80 | unsigned partitioned:1; |
81 | u8 erase_opcode; | |
2230b76b | 82 | u8 command[CMD_SIZE + FAST_READ_DUMMY_BYTE]; |
2f9f7628 ML |
83 | }; |
84 | ||
85 | static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd) | |
86 | { | |
87 | return container_of(mtd, struct m25p, mtd); | |
88 | } | |
89 | ||
90 | /****************************************************************************/ | |
91 | ||
92 | /* | |
93 | * Internal helper functions | |
94 | */ | |
95 | ||
96 | /* | |
97 | * Read the status register, returning its value in the location | |
98 | * Return the status register value. | |
99 | * Returns negative if error occurred. | |
100 | */ | |
101 | static int read_sr(struct m25p *flash) | |
102 | { | |
103 | ssize_t retval; | |
104 | u8 code = OPCODE_RDSR; | |
105 | u8 val; | |
106 | ||
107 | retval = spi_write_then_read(flash->spi, &code, 1, &val, 1); | |
108 | ||
109 | if (retval < 0) { | |
110 | dev_err(&flash->spi->dev, "error %d reading SR\n", | |
111 | (int) retval); | |
112 | return retval; | |
113 | } | |
114 | ||
115 | return val; | |
116 | } | |
117 | ||
72289824 MH |
118 | /* |
119 | * Write status register 1 byte | |
120 | * Returns negative if error occurred. | |
121 | */ | |
122 | static int write_sr(struct m25p *flash, u8 val) | |
123 | { | |
124 | flash->command[0] = OPCODE_WRSR; | |
125 | flash->command[1] = val; | |
126 | ||
127 | return spi_write(flash->spi, flash->command, 2); | |
128 | } | |
2f9f7628 ML |
129 | |
130 | /* | |
131 | * Set write enable latch with Write Enable command. | |
132 | * Returns negative if error occurred. | |
133 | */ | |
134 | static inline int write_enable(struct m25p *flash) | |
135 | { | |
136 | u8 code = OPCODE_WREN; | |
137 | ||
8a1a6272 | 138 | return spi_write_then_read(flash->spi, &code, 1, NULL, 0); |
2f9f7628 ML |
139 | } |
140 | ||
49aac4ae GY |
141 | /* |
142 | * Send write disble instruction to the chip. | |
143 | */ | |
144 | static inline int write_disable(struct m25p *flash) | |
145 | { | |
146 | u8 code = OPCODE_WRDI; | |
147 | ||
148 | return spi_write_then_read(flash->spi, &code, 1, NULL, 0); | |
149 | } | |
2f9f7628 ML |
150 | |
151 | /* | |
152 | * Service routine to read status register until ready, or timeout occurs. | |
153 | * Returns non-zero if error. | |
154 | */ | |
155 | static int wait_till_ready(struct m25p *flash) | |
156 | { | |
cd1a6de7 | 157 | unsigned long deadline; |
2f9f7628 ML |
158 | int sr; |
159 | ||
cd1a6de7 PH |
160 | deadline = jiffies + MAX_READY_WAIT_JIFFIES; |
161 | ||
162 | do { | |
2f9f7628 ML |
163 | if ((sr = read_sr(flash)) < 0) |
164 | break; | |
165 | else if (!(sr & SR_WIP)) | |
166 | return 0; | |
167 | ||
cd1a6de7 PH |
168 | cond_resched(); |
169 | ||
170 | } while (!time_after_eq(jiffies, deadline)); | |
2f9f7628 ML |
171 | |
172 | return 1; | |
173 | } | |
174 | ||
faff3750 CG |
175 | /* |
176 | * Erase the whole flash memory | |
177 | * | |
178 | * Returns 0 if successful, non-zero otherwise. | |
179 | */ | |
7854643a | 180 | static int erase_chip(struct m25p *flash) |
faff3750 | 181 | { |
d85316ac | 182 | DEBUG(MTD_DEBUG_LEVEL3, "%s: %s %lldKiB\n", |
160bbab3 KS |
183 | dev_name(&flash->spi->dev), __func__, |
184 | (long long)(flash->mtd.size >> 10)); | |
faff3750 CG |
185 | |
186 | /* Wait until finished previous write command. */ | |
187 | if (wait_till_ready(flash)) | |
188 | return 1; | |
189 | ||
190 | /* Send write enable, then erase commands. */ | |
191 | write_enable(flash); | |
192 | ||
193 | /* Set up command buffer. */ | |
7854643a | 194 | flash->command[0] = OPCODE_CHIP_ERASE; |
faff3750 CG |
195 | |
196 | spi_write(flash->spi, flash->command, 1); | |
197 | ||
198 | return 0; | |
199 | } | |
2f9f7628 ML |
200 | |
201 | /* | |
202 | * Erase one sector of flash memory at offset ``offset'' which is any | |
203 | * address within the sector which should be erased. | |
204 | * | |
205 | * Returns 0 if successful, non-zero otherwise. | |
206 | */ | |
207 | static int erase_sector(struct m25p *flash, u32 offset) | |
208 | { | |
02d087db | 209 | DEBUG(MTD_DEBUG_LEVEL3, "%s: %s %dKiB at 0x%08x\n", |
160bbab3 | 210 | dev_name(&flash->spi->dev), __func__, |
fa0a8c71 | 211 | flash->mtd.erasesize / 1024, offset); |
2f9f7628 ML |
212 | |
213 | /* Wait until finished previous write command. */ | |
214 | if (wait_till_ready(flash)) | |
215 | return 1; | |
216 | ||
217 | /* Send write enable, then erase commands. */ | |
218 | write_enable(flash); | |
219 | ||
220 | /* Set up command buffer. */ | |
fa0a8c71 | 221 | flash->command[0] = flash->erase_opcode; |
2f9f7628 ML |
222 | flash->command[1] = offset >> 16; |
223 | flash->command[2] = offset >> 8; | |
224 | flash->command[3] = offset; | |
225 | ||
2230b76b | 226 | spi_write(flash->spi, flash->command, CMD_SIZE); |
2f9f7628 ML |
227 | |
228 | return 0; | |
229 | } | |
230 | ||
231 | /****************************************************************************/ | |
232 | ||
233 | /* | |
234 | * MTD implementation | |
235 | */ | |
236 | ||
237 | /* | |
238 | * Erase an address range on the flash chip. The address range may extend | |
239 | * one or more erase sectors. Return an error is there is a problem erasing. | |
240 | */ | |
241 | static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr) | |
242 | { | |
243 | struct m25p *flash = mtd_to_m25p(mtd); | |
244 | u32 addr,len; | |
d85316ac | 245 | uint32_t rem; |
2f9f7628 | 246 | |
d85316ac | 247 | DEBUG(MTD_DEBUG_LEVEL2, "%s: %s %s 0x%llx, len %lld\n", |
160bbab3 KS |
248 | dev_name(&flash->spi->dev), __func__, "at", |
249 | (long long)instr->addr, (long long)instr->len); | |
2f9f7628 ML |
250 | |
251 | /* sanity checks */ | |
252 | if (instr->addr + instr->len > flash->mtd.size) | |
253 | return -EINVAL; | |
d85316ac AB |
254 | div_u64_rem(instr->len, mtd->erasesize, &rem); |
255 | if (rem) | |
2f9f7628 | 256 | return -EINVAL; |
2f9f7628 ML |
257 | |
258 | addr = instr->addr; | |
259 | len = instr->len; | |
260 | ||
7d5230ea | 261 | mutex_lock(&flash->lock); |
2f9f7628 | 262 | |
7854643a | 263 | /* whole-chip erase? */ |
3f33b0aa SF |
264 | if (len == flash->mtd.size) { |
265 | if (erase_chip(flash)) { | |
266 | instr->state = MTD_ERASE_FAILED; | |
267 | mutex_unlock(&flash->lock); | |
268 | return -EIO; | |
269 | } | |
7854643a CG |
270 | |
271 | /* REVISIT in some cases we could speed up erasing large regions | |
272 | * by using OPCODE_SE instead of OPCODE_BE_4K. We may have set up | |
273 | * to use "small sector erase", but that's not always optimal. | |
274 | */ | |
275 | ||
276 | /* "sector"-at-a-time erase */ | |
faff3750 CG |
277 | } else { |
278 | while (len) { | |
279 | if (erase_sector(flash, addr)) { | |
280 | instr->state = MTD_ERASE_FAILED; | |
281 | mutex_unlock(&flash->lock); | |
282 | return -EIO; | |
283 | } | |
284 | ||
285 | addr += mtd->erasesize; | |
286 | len -= mtd->erasesize; | |
2f9f7628 | 287 | } |
2f9f7628 ML |
288 | } |
289 | ||
7d5230ea | 290 | mutex_unlock(&flash->lock); |
2f9f7628 ML |
291 | |
292 | instr->state = MTD_ERASE_DONE; | |
293 | mtd_erase_callback(instr); | |
294 | ||
295 | return 0; | |
296 | } | |
297 | ||
298 | /* | |
299 | * Read an address range from the flash chip. The address range | |
300 | * may be any size provided it is within the physical boundaries. | |
301 | */ | |
302 | static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len, | |
303 | size_t *retlen, u_char *buf) | |
304 | { | |
305 | struct m25p *flash = mtd_to_m25p(mtd); | |
306 | struct spi_transfer t[2]; | |
307 | struct spi_message m; | |
308 | ||
309 | DEBUG(MTD_DEBUG_LEVEL2, "%s: %s %s 0x%08x, len %zd\n", | |
160bbab3 | 310 | dev_name(&flash->spi->dev), __func__, "from", |
2f9f7628 ML |
311 | (u32)from, len); |
312 | ||
313 | /* sanity checks */ | |
314 | if (!len) | |
315 | return 0; | |
316 | ||
317 | if (from + len > flash->mtd.size) | |
318 | return -EINVAL; | |
319 | ||
8275c642 VW |
320 | spi_message_init(&m); |
321 | memset(t, 0, (sizeof t)); | |
322 | ||
2230b76b BW |
323 | /* NOTE: |
324 | * OPCODE_FAST_READ (if available) is faster. | |
325 | * Should add 1 byte DUMMY_BYTE. | |
326 | */ | |
8275c642 | 327 | t[0].tx_buf = flash->command; |
2230b76b | 328 | t[0].len = CMD_SIZE + FAST_READ_DUMMY_BYTE; |
8275c642 VW |
329 | spi_message_add_tail(&t[0], &m); |
330 | ||
331 | t[1].rx_buf = buf; | |
332 | t[1].len = len; | |
333 | spi_message_add_tail(&t[1], &m); | |
334 | ||
335 | /* Byte count starts at zero. */ | |
336 | if (retlen) | |
337 | *retlen = 0; | |
338 | ||
7d5230ea | 339 | mutex_lock(&flash->lock); |
2f9f7628 ML |
340 | |
341 | /* Wait till previous write/erase is done. */ | |
342 | if (wait_till_ready(flash)) { | |
343 | /* REVISIT status return?? */ | |
7d5230ea | 344 | mutex_unlock(&flash->lock); |
2f9f7628 ML |
345 | return 1; |
346 | } | |
347 | ||
fa0a8c71 DB |
348 | /* FIXME switch to OPCODE_FAST_READ. It's required for higher |
349 | * clocks; and at this writing, every chip this driver handles | |
350 | * supports that opcode. | |
351 | */ | |
2f9f7628 ML |
352 | |
353 | /* Set up the write data buffer. */ | |
354 | flash->command[0] = OPCODE_READ; | |
355 | flash->command[1] = from >> 16; | |
356 | flash->command[2] = from >> 8; | |
357 | flash->command[3] = from; | |
358 | ||
2f9f7628 ML |
359 | spi_sync(flash->spi, &m); |
360 | ||
2230b76b | 361 | *retlen = m.actual_length - CMD_SIZE - FAST_READ_DUMMY_BYTE; |
2f9f7628 | 362 | |
7d5230ea | 363 | mutex_unlock(&flash->lock); |
2f9f7628 ML |
364 | |
365 | return 0; | |
366 | } | |
367 | ||
368 | /* | |
369 | * Write an address range to the flash chip. Data must be written in | |
370 | * FLASH_PAGESIZE chunks. The address range may be any size provided | |
371 | * it is within the physical boundaries. | |
372 | */ | |
373 | static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len, | |
374 | size_t *retlen, const u_char *buf) | |
375 | { | |
376 | struct m25p *flash = mtd_to_m25p(mtd); | |
377 | u32 page_offset, page_size; | |
378 | struct spi_transfer t[2]; | |
379 | struct spi_message m; | |
380 | ||
381 | DEBUG(MTD_DEBUG_LEVEL2, "%s: %s %s 0x%08x, len %zd\n", | |
160bbab3 | 382 | dev_name(&flash->spi->dev), __func__, "to", |
2f9f7628 ML |
383 | (u32)to, len); |
384 | ||
385 | if (retlen) | |
386 | *retlen = 0; | |
387 | ||
388 | /* sanity checks */ | |
389 | if (!len) | |
390 | return(0); | |
391 | ||
392 | if (to + len > flash->mtd.size) | |
393 | return -EINVAL; | |
394 | ||
8275c642 VW |
395 | spi_message_init(&m); |
396 | memset(t, 0, (sizeof t)); | |
397 | ||
398 | t[0].tx_buf = flash->command; | |
2230b76b | 399 | t[0].len = CMD_SIZE; |
8275c642 VW |
400 | spi_message_add_tail(&t[0], &m); |
401 | ||
402 | t[1].tx_buf = buf; | |
403 | spi_message_add_tail(&t[1], &m); | |
404 | ||
7d5230ea | 405 | mutex_lock(&flash->lock); |
2f9f7628 ML |
406 | |
407 | /* Wait until finished previous write command. */ | |
bc018863 CG |
408 | if (wait_till_ready(flash)) { |
409 | mutex_unlock(&flash->lock); | |
2f9f7628 | 410 | return 1; |
bc018863 | 411 | } |
2f9f7628 ML |
412 | |
413 | write_enable(flash); | |
414 | ||
2f9f7628 ML |
415 | /* Set up the opcode in the write buffer. */ |
416 | flash->command[0] = OPCODE_PP; | |
417 | flash->command[1] = to >> 16; | |
418 | flash->command[2] = to >> 8; | |
419 | flash->command[3] = to; | |
420 | ||
2f9f7628 ML |
421 | /* what page do we start with? */ |
422 | page_offset = to % FLASH_PAGESIZE; | |
423 | ||
424 | /* do all the bytes fit onto one page? */ | |
425 | if (page_offset + len <= FLASH_PAGESIZE) { | |
2f9f7628 ML |
426 | t[1].len = len; |
427 | ||
428 | spi_sync(flash->spi, &m); | |
429 | ||
2230b76b | 430 | *retlen = m.actual_length - CMD_SIZE; |
2f9f7628 ML |
431 | } else { |
432 | u32 i; | |
433 | ||
434 | /* the size of data remaining on the first page */ | |
435 | page_size = FLASH_PAGESIZE - page_offset; | |
436 | ||
2f9f7628 ML |
437 | t[1].len = page_size; |
438 | spi_sync(flash->spi, &m); | |
439 | ||
2230b76b | 440 | *retlen = m.actual_length - CMD_SIZE; |
2f9f7628 ML |
441 | |
442 | /* write everything in PAGESIZE chunks */ | |
443 | for (i = page_size; i < len; i += page_size) { | |
444 | page_size = len - i; | |
445 | if (page_size > FLASH_PAGESIZE) | |
446 | page_size = FLASH_PAGESIZE; | |
447 | ||
448 | /* write the next page to flash */ | |
449 | flash->command[1] = (to + i) >> 16; | |
450 | flash->command[2] = (to + i) >> 8; | |
451 | flash->command[3] = (to + i); | |
452 | ||
453 | t[1].tx_buf = buf + i; | |
454 | t[1].len = page_size; | |
455 | ||
456 | wait_till_ready(flash); | |
457 | ||
458 | write_enable(flash); | |
459 | ||
460 | spi_sync(flash->spi, &m); | |
461 | ||
7111763d | 462 | if (retlen) |
2230b76b | 463 | *retlen += m.actual_length - CMD_SIZE; |
7d5230ea DB |
464 | } |
465 | } | |
2f9f7628 | 466 | |
7d5230ea | 467 | mutex_unlock(&flash->lock); |
2f9f7628 ML |
468 | |
469 | return 0; | |
470 | } | |
471 | ||
49aac4ae GY |
472 | static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, |
473 | size_t *retlen, const u_char *buf) | |
474 | { | |
475 | struct m25p *flash = mtd_to_m25p(mtd); | |
476 | struct spi_transfer t[2]; | |
477 | struct spi_message m; | |
478 | size_t actual; | |
479 | int cmd_sz, ret; | |
480 | ||
481 | if (retlen) | |
482 | *retlen = 0; | |
483 | ||
484 | /* sanity checks */ | |
485 | if (!len) | |
486 | return 0; | |
487 | ||
488 | if (to + len > flash->mtd.size) | |
489 | return -EINVAL; | |
490 | ||
491 | spi_message_init(&m); | |
492 | memset(t, 0, (sizeof t)); | |
493 | ||
494 | t[0].tx_buf = flash->command; | |
495 | t[0].len = CMD_SIZE; | |
496 | spi_message_add_tail(&t[0], &m); | |
497 | ||
498 | t[1].tx_buf = buf; | |
499 | spi_message_add_tail(&t[1], &m); | |
500 | ||
501 | mutex_lock(&flash->lock); | |
502 | ||
503 | /* Wait until finished previous write command. */ | |
504 | ret = wait_till_ready(flash); | |
505 | if (ret) | |
506 | goto time_out; | |
507 | ||
508 | write_enable(flash); | |
509 | ||
510 | actual = to % 2; | |
511 | /* Start write from odd address. */ | |
512 | if (actual) { | |
513 | flash->command[0] = OPCODE_BP; | |
514 | flash->command[1] = to >> 16; | |
515 | flash->command[2] = to >> 8; | |
516 | flash->command[3] = to; | |
517 | ||
518 | /* write one byte. */ | |
519 | t[1].len = 1; | |
520 | spi_sync(flash->spi, &m); | |
521 | ret = wait_till_ready(flash); | |
522 | if (ret) | |
523 | goto time_out; | |
524 | *retlen += m.actual_length - CMD_SIZE; | |
525 | } | |
526 | to += actual; | |
527 | ||
528 | flash->command[0] = OPCODE_AAI_WP; | |
529 | flash->command[1] = to >> 16; | |
530 | flash->command[2] = to >> 8; | |
531 | flash->command[3] = to; | |
532 | ||
533 | /* Write out most of the data here. */ | |
534 | cmd_sz = CMD_SIZE; | |
535 | for (; actual < len - 1; actual += 2) { | |
536 | t[0].len = cmd_sz; | |
537 | /* write two bytes. */ | |
538 | t[1].len = 2; | |
539 | t[1].tx_buf = buf + actual; | |
540 | ||
541 | spi_sync(flash->spi, &m); | |
542 | ret = wait_till_ready(flash); | |
543 | if (ret) | |
544 | goto time_out; | |
545 | *retlen += m.actual_length - cmd_sz; | |
546 | cmd_sz = 1; | |
547 | to += 2; | |
548 | } | |
549 | write_disable(flash); | |
550 | ret = wait_till_ready(flash); | |
551 | if (ret) | |
552 | goto time_out; | |
553 | ||
554 | /* Write out trailing byte if it exists. */ | |
555 | if (actual != len) { | |
556 | write_enable(flash); | |
557 | flash->command[0] = OPCODE_BP; | |
558 | flash->command[1] = to >> 16; | |
559 | flash->command[2] = to >> 8; | |
560 | flash->command[3] = to; | |
561 | t[0].len = CMD_SIZE; | |
562 | t[1].len = 1; | |
563 | t[1].tx_buf = buf + actual; | |
564 | ||
565 | spi_sync(flash->spi, &m); | |
566 | ret = wait_till_ready(flash); | |
567 | if (ret) | |
568 | goto time_out; | |
569 | *retlen += m.actual_length - CMD_SIZE; | |
570 | write_disable(flash); | |
571 | } | |
572 | ||
573 | time_out: | |
574 | mutex_unlock(&flash->lock); | |
575 | return ret; | |
576 | } | |
2f9f7628 ML |
577 | |
578 | /****************************************************************************/ | |
579 | ||
580 | /* | |
581 | * SPI device driver setup and teardown | |
582 | */ | |
583 | ||
584 | struct flash_info { | |
585 | char *name; | |
fa0a8c71 DB |
586 | |
587 | /* JEDEC id zero means "no ID" (most older chips); otherwise it has | |
588 | * a high byte of zero plus three data bytes: the manufacturer id, | |
589 | * then a two byte device id. | |
590 | */ | |
591 | u32 jedec_id; | |
d0e8c47c | 592 | u16 ext_id; |
fa0a8c71 DB |
593 | |
594 | /* The size listed here is what works with OPCODE_SE, which isn't | |
595 | * necessarily called a "sector" by the vendor. | |
596 | */ | |
2f9f7628 | 597 | unsigned sector_size; |
fa0a8c71 DB |
598 | u16 n_sectors; |
599 | ||
600 | u16 flags; | |
601 | #define SECT_4K 0x01 /* OPCODE_BE_4K works uniformly */ | |
2f9f7628 ML |
602 | }; |
603 | ||
fa0a8c71 DB |
604 | |
605 | /* NOTE: double check command sets and memory organization when you add | |
606 | * more flash chips. This current list focusses on newer chips, which | |
607 | * have been converging on command sets which including JEDEC ID. | |
608 | */ | |
2f9f7628 | 609 | static struct flash_info __devinitdata m25p_data [] = { |
fa0a8c71 DB |
610 | |
611 | /* Atmel -- some are (confusingly) marketed as "DataFlash" */ | |
d0e8c47c CG |
612 | { "at25fs010", 0x1f6601, 0, 32 * 1024, 4, SECT_4K, }, |
613 | { "at25fs040", 0x1f6604, 0, 64 * 1024, 8, SECT_4K, }, | |
fa0a8c71 | 614 | |
d0e8c47c CG |
615 | { "at25df041a", 0x1f4401, 0, 64 * 1024, 8, SECT_4K, }, |
616 | { "at25df641", 0x1f4800, 0, 64 * 1024, 128, SECT_4K, }, | |
fa0a8c71 | 617 | |
d0e8c47c CG |
618 | { "at26f004", 0x1f0400, 0, 64 * 1024, 8, SECT_4K, }, |
619 | { "at26df081a", 0x1f4501, 0, 64 * 1024, 16, SECT_4K, }, | |
620 | { "at26df161a", 0x1f4601, 0, 64 * 1024, 32, SECT_4K, }, | |
621 | { "at26df321", 0x1f4701, 0, 64 * 1024, 64, SECT_4K, }, | |
fa0a8c71 | 622 | |
ab1ff210 | 623 | /* Macronix */ |
b0469ea7 SG |
624 | { "mx25l3205d", 0xc22016, 0, 64 * 1024, 64, }, |
625 | { "mx25l6405d", 0xc22017, 0, 64 * 1024, 128, }, | |
ab1ff210 | 626 | { "mx25l12805d", 0xc22018, 0, 64 * 1024, 256, }, |
b0469ea7 | 627 | { "mx25l12855e", 0xc22618, 0, 64 * 1024, 256, }, |
ab1ff210 | 628 | |
fa0a8c71 DB |
629 | /* Spansion -- single (large) sector size only, at least |
630 | * for the chips listed here (without boot sectors). | |
631 | */ | |
d0e8c47c CG |
632 | { "s25sl004a", 0x010212, 0, 64 * 1024, 8, }, |
633 | { "s25sl008a", 0x010213, 0, 64 * 1024, 16, }, | |
634 | { "s25sl016a", 0x010214, 0, 64 * 1024, 32, }, | |
635 | { "s25sl032a", 0x010215, 0, 64 * 1024, 64, }, | |
636 | { "s25sl064a", 0x010216, 0, 64 * 1024, 128, }, | |
304e6d5f | 637 | { "s25sl12800", 0x012018, 0x0300, 256 * 1024, 64, }, |
d0e8c47c | 638 | { "s25sl12801", 0x012018, 0x0301, 64 * 1024, 256, }, |
304e6d5f KC |
639 | { "s25fl129p0", 0x012018, 0x4d00, 256 * 1024, 64, }, |
640 | { "s25fl129p1", 0x012018, 0x4d01, 64 * 1024, 256, }, | |
fa0a8c71 DB |
641 | |
642 | /* SST -- large erase sizes are "overlays", "sectors" are 4K */ | |
d0e8c47c CG |
643 | { "sst25vf040b", 0xbf258d, 0, 64 * 1024, 8, SECT_4K, }, |
644 | { "sst25vf080b", 0xbf258e, 0, 64 * 1024, 16, SECT_4K, }, | |
645 | { "sst25vf016b", 0xbf2541, 0, 64 * 1024, 32, SECT_4K, }, | |
646 | { "sst25vf032b", 0xbf254a, 0, 64 * 1024, 64, SECT_4K, }, | |
aa3651e4 GY |
647 | { "sst25wf512", 0xbf2501, 0, 64 * 1024, 1, SECT_4K, }, |
648 | { "sst25wf010", 0xbf2502, 0, 64 * 1024, 2, SECT_4K, }, | |
649 | { "sst25wf020", 0xbf2503, 0, 64 * 1024, 4, SECT_4K, }, | |
650 | { "sst25wf040", 0xbf2504, 0, 64 * 1024, 8, SECT_4K, }, | |
fa0a8c71 DB |
651 | |
652 | /* ST Microelectronics -- newer production may have feature updates */ | |
d0e8c47c CG |
653 | { "m25p05", 0x202010, 0, 32 * 1024, 2, }, |
654 | { "m25p10", 0x202011, 0, 32 * 1024, 4, }, | |
655 | { "m25p20", 0x202012, 0, 64 * 1024, 4, }, | |
656 | { "m25p40", 0x202013, 0, 64 * 1024, 8, }, | |
657 | { "m25p80", 0, 0, 64 * 1024, 16, }, | |
658 | { "m25p16", 0x202015, 0, 64 * 1024, 32, }, | |
659 | { "m25p32", 0x202016, 0, 64 * 1024, 64, }, | |
660 | { "m25p64", 0x202017, 0, 64 * 1024, 128, }, | |
661 | { "m25p128", 0x202018, 0, 256 * 1024, 64, }, | |
662 | ||
1e42d142 | 663 | { "m45pe10", 0x204011, 0, 64 * 1024, 2, }, |
d0e8c47c CG |
664 | { "m45pe80", 0x204014, 0, 64 * 1024, 16, }, |
665 | { "m45pe16", 0x204015, 0, 64 * 1024, 32, }, | |
666 | ||
667 | { "m25pe80", 0x208014, 0, 64 * 1024, 16, }, | |
668 | { "m25pe16", 0x208015, 0, 64 * 1024, 32, SECT_4K, }, | |
fa0a8c71 | 669 | |
02d087db | 670 | /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ |
d0e8c47c CG |
671 | { "w25x10", 0xef3011, 0, 64 * 1024, 2, SECT_4K, }, |
672 | { "w25x20", 0xef3012, 0, 64 * 1024, 4, SECT_4K, }, | |
673 | { "w25x40", 0xef3013, 0, 64 * 1024, 8, SECT_4K, }, | |
674 | { "w25x80", 0xef3014, 0, 64 * 1024, 16, SECT_4K, }, | |
675 | { "w25x16", 0xef3015, 0, 64 * 1024, 32, SECT_4K, }, | |
676 | { "w25x32", 0xef3016, 0, 64 * 1024, 64, SECT_4K, }, | |
677 | { "w25x64", 0xef3017, 0, 64 * 1024, 128, SECT_4K, }, | |
2f9f7628 ML |
678 | }; |
679 | ||
fa0a8c71 DB |
680 | static struct flash_info *__devinit jedec_probe(struct spi_device *spi) |
681 | { | |
682 | int tmp; | |
683 | u8 code = OPCODE_RDID; | |
daa84735 | 684 | u8 id[5]; |
fa0a8c71 | 685 | u32 jedec; |
d0e8c47c | 686 | u16 ext_jedec; |
fa0a8c71 DB |
687 | struct flash_info *info; |
688 | ||
689 | /* JEDEC also defines an optional "extended device information" | |
690 | * string for after vendor-specific data, after the three bytes | |
691 | * we use here. Supporting some chips might require using it. | |
692 | */ | |
daa84735 | 693 | tmp = spi_write_then_read(spi, &code, 1, id, 5); |
fa0a8c71 DB |
694 | if (tmp < 0) { |
695 | DEBUG(MTD_DEBUG_LEVEL0, "%s: error %d reading JEDEC ID\n", | |
160bbab3 | 696 | dev_name(&spi->dev), tmp); |
fa0a8c71 DB |
697 | return NULL; |
698 | } | |
699 | jedec = id[0]; | |
700 | jedec = jedec << 8; | |
701 | jedec |= id[1]; | |
702 | jedec = jedec << 8; | |
703 | jedec |= id[2]; | |
704 | ||
d0e8c47c CG |
705 | ext_jedec = id[3] << 8 | id[4]; |
706 | ||
fa0a8c71 DB |
707 | for (tmp = 0, info = m25p_data; |
708 | tmp < ARRAY_SIZE(m25p_data); | |
709 | tmp++, info++) { | |
a3d3f73c | 710 | if (info->jedec_id == jedec) { |
9168ab86 | 711 | if (info->ext_id != 0 && info->ext_id != ext_jedec) |
d0e8c47c | 712 | continue; |
fa0a8c71 | 713 | return info; |
a3d3f73c | 714 | } |
fa0a8c71 DB |
715 | } |
716 | dev_err(&spi->dev, "unrecognized JEDEC id %06x\n", jedec); | |
717 | return NULL; | |
718 | } | |
719 | ||
720 | ||
2f9f7628 ML |
721 | /* |
722 | * board specific setup should have ensured the SPI clock used here | |
723 | * matches what the READ command supports, at least until this driver | |
724 | * understands FAST_READ (for clocks over 25 MHz). | |
725 | */ | |
726 | static int __devinit m25p_probe(struct spi_device *spi) | |
727 | { | |
728 | struct flash_platform_data *data; | |
729 | struct m25p *flash; | |
730 | struct flash_info *info; | |
731 | unsigned i; | |
732 | ||
733 | /* Platform data helps sort out which chip type we have, as | |
fa0a8c71 DB |
734 | * well as how this board partitions it. If we don't have |
735 | * a chip ID, try the JEDEC id commands; they'll work for most | |
736 | * newer chips, even if we don't recognize the particular chip. | |
2f9f7628 ML |
737 | */ |
738 | data = spi->dev.platform_data; | |
fa0a8c71 DB |
739 | if (data && data->type) { |
740 | for (i = 0, info = m25p_data; | |
741 | i < ARRAY_SIZE(m25p_data); | |
742 | i++, info++) { | |
743 | if (strcmp(data->type, info->name) == 0) | |
744 | break; | |
745 | } | |
2f9f7628 | 746 | |
fa0a8c71 DB |
747 | /* unrecognized chip? */ |
748 | if (i == ARRAY_SIZE(m25p_data)) { | |
749 | DEBUG(MTD_DEBUG_LEVEL0, "%s: unrecognized id %s\n", | |
160bbab3 | 750 | dev_name(&spi->dev), data->type); |
fa0a8c71 DB |
751 | info = NULL; |
752 | ||
753 | /* recognized; is that chip really what's there? */ | |
754 | } else if (info->jedec_id) { | |
755 | struct flash_info *chip = jedec_probe(spi); | |
756 | ||
757 | if (!chip || chip != info) { | |
758 | dev_warn(&spi->dev, "found %s, expected %s\n", | |
759 | chip ? chip->name : "UNKNOWN", | |
760 | info->name); | |
761 | info = NULL; | |
762 | } | |
763 | } | |
764 | } else | |
765 | info = jedec_probe(spi); | |
766 | ||
767 | if (!info) | |
2f9f7628 | 768 | return -ENODEV; |
2f9f7628 | 769 | |
e94b1766 | 770 | flash = kzalloc(sizeof *flash, GFP_KERNEL); |
2f9f7628 ML |
771 | if (!flash) |
772 | return -ENOMEM; | |
773 | ||
774 | flash->spi = spi; | |
7d5230ea | 775 | mutex_init(&flash->lock); |
2f9f7628 ML |
776 | dev_set_drvdata(&spi->dev, flash); |
777 | ||
72289824 MH |
778 | /* |
779 | * Atmel serial flash tend to power up | |
780 | * with the software protection bits set | |
781 | */ | |
782 | ||
783 | if (info->jedec_id >> 16 == 0x1f) { | |
784 | write_enable(flash); | |
785 | write_sr(flash, 0); | |
786 | } | |
787 | ||
fa0a8c71 | 788 | if (data && data->name) |
2f9f7628 ML |
789 | flash->mtd.name = data->name; |
790 | else | |
160bbab3 | 791 | flash->mtd.name = dev_name(&spi->dev); |
2f9f7628 ML |
792 | |
793 | flash->mtd.type = MTD_NORFLASH; | |
783ed81f | 794 | flash->mtd.writesize = 1; |
2f9f7628 ML |
795 | flash->mtd.flags = MTD_CAP_NORFLASH; |
796 | flash->mtd.size = info->sector_size * info->n_sectors; | |
2f9f7628 ML |
797 | flash->mtd.erase = m25p80_erase; |
798 | flash->mtd.read = m25p80_read; | |
49aac4ae GY |
799 | |
800 | /* sst flash chips use AAI word program */ | |
801 | if (info->jedec_id >> 16 == 0xbf) | |
802 | flash->mtd.write = sst_write; | |
803 | else | |
804 | flash->mtd.write = m25p80_write; | |
2f9f7628 | 805 | |
fa0a8c71 DB |
806 | /* prefer "small sector" erase if possible */ |
807 | if (info->flags & SECT_4K) { | |
808 | flash->erase_opcode = OPCODE_BE_4K; | |
809 | flash->mtd.erasesize = 4096; | |
810 | } else { | |
811 | flash->erase_opcode = OPCODE_SE; | |
812 | flash->mtd.erasesize = info->sector_size; | |
813 | } | |
814 | ||
87f39f04 DB |
815 | flash->mtd.dev.parent = &spi->dev; |
816 | ||
d85316ac AB |
817 | dev_info(&spi->dev, "%s (%lld Kbytes)\n", info->name, |
818 | (long long)flash->mtd.size >> 10); | |
2f9f7628 ML |
819 | |
820 | DEBUG(MTD_DEBUG_LEVEL2, | |
d85316ac | 821 | "mtd .name = %s, .size = 0x%llx (%lldMiB) " |
02d087db | 822 | ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n", |
2f9f7628 | 823 | flash->mtd.name, |
d85316ac | 824 | (long long)flash->mtd.size, (long long)(flash->mtd.size >> 20), |
2f9f7628 ML |
825 | flash->mtd.erasesize, flash->mtd.erasesize / 1024, |
826 | flash->mtd.numeraseregions); | |
827 | ||
828 | if (flash->mtd.numeraseregions) | |
829 | for (i = 0; i < flash->mtd.numeraseregions; i++) | |
830 | DEBUG(MTD_DEBUG_LEVEL2, | |
d85316ac | 831 | "mtd.eraseregions[%d] = { .offset = 0x%llx, " |
02d087db | 832 | ".erasesize = 0x%.8x (%uKiB), " |
2f9f7628 | 833 | ".numblocks = %d }\n", |
d85316ac | 834 | i, (long long)flash->mtd.eraseregions[i].offset, |
2f9f7628 ML |
835 | flash->mtd.eraseregions[i].erasesize, |
836 | flash->mtd.eraseregions[i].erasesize / 1024, | |
837 | flash->mtd.eraseregions[i].numblocks); | |
838 | ||
839 | ||
840 | /* partitions should match sector boundaries; and it may be good to | |
841 | * use readonly partitions for writeprotected sectors (BP2..BP0). | |
842 | */ | |
843 | if (mtd_has_partitions()) { | |
844 | struct mtd_partition *parts = NULL; | |
845 | int nr_parts = 0; | |
846 | ||
a4b6d516 DB |
847 | if (mtd_has_cmdlinepart()) { |
848 | static const char *part_probes[] | |
849 | = { "cmdlinepart", NULL, }; | |
2f9f7628 | 850 | |
a4b6d516 DB |
851 | nr_parts = parse_mtd_partitions(&flash->mtd, |
852 | part_probes, &parts, 0); | |
853 | } | |
2f9f7628 ML |
854 | |
855 | if (nr_parts <= 0 && data && data->parts) { | |
856 | parts = data->parts; | |
857 | nr_parts = data->nr_parts; | |
858 | } | |
859 | ||
860 | if (nr_parts > 0) { | |
fa0a8c71 | 861 | for (i = 0; i < nr_parts; i++) { |
2f9f7628 | 862 | DEBUG(MTD_DEBUG_LEVEL2, "partitions[%d] = " |
d85316ac AB |
863 | "{.name = %s, .offset = 0x%llx, " |
864 | ".size = 0x%llx (%lldKiB) }\n", | |
fa0a8c71 | 865 | i, parts[i].name, |
d85316ac AB |
866 | (long long)parts[i].offset, |
867 | (long long)parts[i].size, | |
868 | (long long)(parts[i].size >> 10)); | |
2f9f7628 ML |
869 | } |
870 | flash->partitioned = 1; | |
871 | return add_mtd_partitions(&flash->mtd, parts, nr_parts); | |
872 | } | |
edcb3b14 | 873 | } else if (data && data->nr_parts) |
2f9f7628 ML |
874 | dev_warn(&spi->dev, "ignoring %d default partitions on %s\n", |
875 | data->nr_parts, data->name); | |
876 | ||
877 | return add_mtd_device(&flash->mtd) == 1 ? -ENODEV : 0; | |
878 | } | |
879 | ||
880 | ||
881 | static int __devexit m25p_remove(struct spi_device *spi) | |
882 | { | |
883 | struct m25p *flash = dev_get_drvdata(&spi->dev); | |
884 | int status; | |
885 | ||
886 | /* Clean up MTD stuff. */ | |
887 | if (mtd_has_partitions() && flash->partitioned) | |
888 | status = del_mtd_partitions(&flash->mtd); | |
889 | else | |
890 | status = del_mtd_device(&flash->mtd); | |
891 | if (status == 0) | |
892 | kfree(flash); | |
893 | return 0; | |
894 | } | |
895 | ||
896 | ||
897 | static struct spi_driver m25p80_driver = { | |
898 | .driver = { | |
899 | .name = "m25p80", | |
900 | .bus = &spi_bus_type, | |
901 | .owner = THIS_MODULE, | |
902 | }, | |
903 | .probe = m25p_probe, | |
904 | .remove = __devexit_p(m25p_remove), | |
fa0a8c71 DB |
905 | |
906 | /* REVISIT: many of these chips have deep power-down modes, which | |
907 | * should clearly be entered on suspend() to minimize power use. | |
908 | * And also when they're otherwise idle... | |
909 | */ | |
2f9f7628 ML |
910 | }; |
911 | ||
912 | ||
627df23c | 913 | static int __init m25p80_init(void) |
2f9f7628 ML |
914 | { |
915 | return spi_register_driver(&m25p80_driver); | |
916 | } | |
917 | ||
918 | ||
627df23c | 919 | static void __exit m25p80_exit(void) |
2f9f7628 ML |
920 | { |
921 | spi_unregister_driver(&m25p80_driver); | |
922 | } | |
923 | ||
924 | ||
925 | module_init(m25p80_init); | |
926 | module_exit(m25p80_exit); | |
927 | ||
928 | MODULE_LICENSE("GPL"); | |
929 | MODULE_AUTHOR("Mike Lavender"); | |
930 | MODULE_DESCRIPTION("MTD SPI driver for ST M25Pxx flash chips"); |