Commit | Line | Data |
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2f9f7628 | 1 | /* |
fa0a8c71 | 2 | * MTD SPI driver for ST M25Pxx (and similar) serial flash chips |
2f9f7628 ML |
3 | * |
4 | * Author: Mike Lavender, mike@steroidmicros.com | |
5 | * | |
6 | * Copyright (c) 2005, Intec Automation Inc. | |
7 | * | |
8 | * Some parts are based on lart.c by Abraham Van Der Merwe | |
9 | * | |
10 | * Cleaned up and generalized based on mtd_dataflash.c | |
11 | * | |
12 | * This code is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | * | |
16 | */ | |
17 | ||
18 | #include <linux/init.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/device.h> | |
21 | #include <linux/interrupt.h> | |
7d5230ea DB |
22 | #include <linux/mutex.h> |
23 | ||
2f9f7628 ML |
24 | #include <linux/mtd/mtd.h> |
25 | #include <linux/mtd/partitions.h> | |
7d5230ea | 26 | |
2f9f7628 ML |
27 | #include <linux/spi/spi.h> |
28 | #include <linux/spi/flash.h> | |
29 | ||
2f9f7628 | 30 | |
2f9f7628 ML |
31 | #define FLASH_PAGESIZE 256 |
32 | ||
33 | /* Flash opcodes. */ | |
fa0a8c71 DB |
34 | #define OPCODE_WREN 0x06 /* Write enable */ |
35 | #define OPCODE_RDSR 0x05 /* Read status register */ | |
36 | #define OPCODE_READ 0x03 /* Read data bytes (low frequency) */ | |
37 | #define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */ | |
38 | #define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */ | |
39 | #define OPCODE_BE_4K 0x20 /* Erase 4K block */ | |
40 | #define OPCODE_BE_32K 0x52 /* Erase 32K block */ | |
41 | #define OPCODE_SE 0xd8 /* Sector erase (usually 64K) */ | |
2f9f7628 ML |
42 | #define OPCODE_RDID 0x9f /* Read JEDEC ID */ |
43 | ||
44 | /* Status Register bits. */ | |
45 | #define SR_WIP 1 /* Write in progress */ | |
46 | #define SR_WEL 2 /* Write enable latch */ | |
fa0a8c71 | 47 | /* meaning of other SR_* bits may differ between vendors */ |
2f9f7628 ML |
48 | #define SR_BP0 4 /* Block protect 0 */ |
49 | #define SR_BP1 8 /* Block protect 1 */ | |
50 | #define SR_BP2 0x10 /* Block protect 2 */ | |
51 | #define SR_SRWD 0x80 /* SR write protect */ | |
52 | ||
53 | /* Define max times to check status register before we give up. */ | |
54 | #define MAX_READY_WAIT_COUNT 100000 | |
55 | ||
56 | ||
57 | #ifdef CONFIG_MTD_PARTITIONS | |
58 | #define mtd_has_partitions() (1) | |
59 | #else | |
60 | #define mtd_has_partitions() (0) | |
61 | #endif | |
62 | ||
63 | /****************************************************************************/ | |
64 | ||
65 | struct m25p { | |
66 | struct spi_device *spi; | |
7d5230ea | 67 | struct mutex lock; |
2f9f7628 | 68 | struct mtd_info mtd; |
fa0a8c71 DB |
69 | unsigned partitioned:1; |
70 | u8 erase_opcode; | |
2f9f7628 ML |
71 | u8 command[4]; |
72 | }; | |
73 | ||
74 | static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd) | |
75 | { | |
76 | return container_of(mtd, struct m25p, mtd); | |
77 | } | |
78 | ||
79 | /****************************************************************************/ | |
80 | ||
81 | /* | |
82 | * Internal helper functions | |
83 | */ | |
84 | ||
85 | /* | |
86 | * Read the status register, returning its value in the location | |
87 | * Return the status register value. | |
88 | * Returns negative if error occurred. | |
89 | */ | |
90 | static int read_sr(struct m25p *flash) | |
91 | { | |
92 | ssize_t retval; | |
93 | u8 code = OPCODE_RDSR; | |
94 | u8 val; | |
95 | ||
96 | retval = spi_write_then_read(flash->spi, &code, 1, &val, 1); | |
97 | ||
98 | if (retval < 0) { | |
99 | dev_err(&flash->spi->dev, "error %d reading SR\n", | |
100 | (int) retval); | |
101 | return retval; | |
102 | } | |
103 | ||
104 | return val; | |
105 | } | |
106 | ||
107 | ||
108 | /* | |
109 | * Set write enable latch with Write Enable command. | |
110 | * Returns negative if error occurred. | |
111 | */ | |
112 | static inline int write_enable(struct m25p *flash) | |
113 | { | |
114 | u8 code = OPCODE_WREN; | |
115 | ||
116 | return spi_write_then_read(flash->spi, &code, 1, NULL, 0); | |
117 | } | |
118 | ||
119 | ||
120 | /* | |
121 | * Service routine to read status register until ready, or timeout occurs. | |
122 | * Returns non-zero if error. | |
123 | */ | |
124 | static int wait_till_ready(struct m25p *flash) | |
125 | { | |
126 | int count; | |
127 | int sr; | |
128 | ||
129 | /* one chip guarantees max 5 msec wait here after page writes, | |
130 | * but potentially three seconds (!) after page erase. | |
131 | */ | |
132 | for (count = 0; count < MAX_READY_WAIT_COUNT; count++) { | |
133 | if ((sr = read_sr(flash)) < 0) | |
134 | break; | |
135 | else if (!(sr & SR_WIP)) | |
136 | return 0; | |
137 | ||
138 | /* REVISIT sometimes sleeping would be best */ | |
139 | } | |
140 | ||
141 | return 1; | |
142 | } | |
143 | ||
144 | ||
145 | /* | |
146 | * Erase one sector of flash memory at offset ``offset'' which is any | |
147 | * address within the sector which should be erased. | |
148 | * | |
149 | * Returns 0 if successful, non-zero otherwise. | |
150 | */ | |
151 | static int erase_sector(struct m25p *flash, u32 offset) | |
152 | { | |
fa0a8c71 DB |
153 | DEBUG(MTD_DEBUG_LEVEL3, "%s: %s %dK at 0x%08x\n", |
154 | flash->spi->dev.bus_id, __FUNCTION__, | |
155 | flash->mtd.erasesize / 1024, offset); | |
2f9f7628 ML |
156 | |
157 | /* Wait until finished previous write command. */ | |
158 | if (wait_till_ready(flash)) | |
159 | return 1; | |
160 | ||
161 | /* Send write enable, then erase commands. */ | |
162 | write_enable(flash); | |
163 | ||
164 | /* Set up command buffer. */ | |
fa0a8c71 | 165 | flash->command[0] = flash->erase_opcode; |
2f9f7628 ML |
166 | flash->command[1] = offset >> 16; |
167 | flash->command[2] = offset >> 8; | |
168 | flash->command[3] = offset; | |
169 | ||
170 | spi_write(flash->spi, flash->command, sizeof(flash->command)); | |
171 | ||
172 | return 0; | |
173 | } | |
174 | ||
175 | /****************************************************************************/ | |
176 | ||
177 | /* | |
178 | * MTD implementation | |
179 | */ | |
180 | ||
181 | /* | |
182 | * Erase an address range on the flash chip. The address range may extend | |
183 | * one or more erase sectors. Return an error is there is a problem erasing. | |
184 | */ | |
185 | static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr) | |
186 | { | |
187 | struct m25p *flash = mtd_to_m25p(mtd); | |
188 | u32 addr,len; | |
189 | ||
19676ff0 | 190 | DEBUG(MTD_DEBUG_LEVEL2, "%s: %s %s 0x%08x, len %d\n", |
2f9f7628 ML |
191 | flash->spi->dev.bus_id, __FUNCTION__, "at", |
192 | (u32)instr->addr, instr->len); | |
193 | ||
194 | /* sanity checks */ | |
195 | if (instr->addr + instr->len > flash->mtd.size) | |
196 | return -EINVAL; | |
197 | if ((instr->addr % mtd->erasesize) != 0 | |
198 | || (instr->len % mtd->erasesize) != 0) { | |
199 | return -EINVAL; | |
200 | } | |
201 | ||
202 | addr = instr->addr; | |
203 | len = instr->len; | |
204 | ||
7d5230ea | 205 | mutex_lock(&flash->lock); |
2f9f7628 | 206 | |
fa0a8c71 DB |
207 | /* REVISIT in some cases we could speed up erasing large regions |
208 | * by using OPCODE_SE instead of OPCODE_BE_4K | |
209 | */ | |
210 | ||
2f9f7628 ML |
211 | /* now erase those sectors */ |
212 | while (len) { | |
213 | if (erase_sector(flash, addr)) { | |
214 | instr->state = MTD_ERASE_FAILED; | |
7d5230ea | 215 | mutex_unlock(&flash->lock); |
2f9f7628 ML |
216 | return -EIO; |
217 | } | |
218 | ||
219 | addr += mtd->erasesize; | |
220 | len -= mtd->erasesize; | |
221 | } | |
222 | ||
7d5230ea | 223 | mutex_unlock(&flash->lock); |
2f9f7628 ML |
224 | |
225 | instr->state = MTD_ERASE_DONE; | |
226 | mtd_erase_callback(instr); | |
227 | ||
228 | return 0; | |
229 | } | |
230 | ||
231 | /* | |
232 | * Read an address range from the flash chip. The address range | |
233 | * may be any size provided it is within the physical boundaries. | |
234 | */ | |
235 | static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len, | |
236 | size_t *retlen, u_char *buf) | |
237 | { | |
238 | struct m25p *flash = mtd_to_m25p(mtd); | |
239 | struct spi_transfer t[2]; | |
240 | struct spi_message m; | |
241 | ||
242 | DEBUG(MTD_DEBUG_LEVEL2, "%s: %s %s 0x%08x, len %zd\n", | |
243 | flash->spi->dev.bus_id, __FUNCTION__, "from", | |
244 | (u32)from, len); | |
245 | ||
246 | /* sanity checks */ | |
247 | if (!len) | |
248 | return 0; | |
249 | ||
250 | if (from + len > flash->mtd.size) | |
251 | return -EINVAL; | |
252 | ||
8275c642 VW |
253 | spi_message_init(&m); |
254 | memset(t, 0, (sizeof t)); | |
255 | ||
256 | t[0].tx_buf = flash->command; | |
257 | t[0].len = sizeof(flash->command); | |
258 | spi_message_add_tail(&t[0], &m); | |
259 | ||
260 | t[1].rx_buf = buf; | |
261 | t[1].len = len; | |
262 | spi_message_add_tail(&t[1], &m); | |
263 | ||
264 | /* Byte count starts at zero. */ | |
265 | if (retlen) | |
266 | *retlen = 0; | |
267 | ||
7d5230ea | 268 | mutex_lock(&flash->lock); |
2f9f7628 ML |
269 | |
270 | /* Wait till previous write/erase is done. */ | |
271 | if (wait_till_ready(flash)) { | |
272 | /* REVISIT status return?? */ | |
7d5230ea | 273 | mutex_unlock(&flash->lock); |
2f9f7628 ML |
274 | return 1; |
275 | } | |
276 | ||
fa0a8c71 DB |
277 | /* FIXME switch to OPCODE_FAST_READ. It's required for higher |
278 | * clocks; and at this writing, every chip this driver handles | |
279 | * supports that opcode. | |
280 | */ | |
2f9f7628 ML |
281 | |
282 | /* Set up the write data buffer. */ | |
283 | flash->command[0] = OPCODE_READ; | |
284 | flash->command[1] = from >> 16; | |
285 | flash->command[2] = from >> 8; | |
286 | flash->command[3] = from; | |
287 | ||
2f9f7628 ML |
288 | spi_sync(flash->spi, &m); |
289 | ||
290 | *retlen = m.actual_length - sizeof(flash->command); | |
291 | ||
7d5230ea | 292 | mutex_unlock(&flash->lock); |
2f9f7628 ML |
293 | |
294 | return 0; | |
295 | } | |
296 | ||
297 | /* | |
298 | * Write an address range to the flash chip. Data must be written in | |
299 | * FLASH_PAGESIZE chunks. The address range may be any size provided | |
300 | * it is within the physical boundaries. | |
301 | */ | |
302 | static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len, | |
303 | size_t *retlen, const u_char *buf) | |
304 | { | |
305 | struct m25p *flash = mtd_to_m25p(mtd); | |
306 | u32 page_offset, page_size; | |
307 | struct spi_transfer t[2]; | |
308 | struct spi_message m; | |
309 | ||
310 | DEBUG(MTD_DEBUG_LEVEL2, "%s: %s %s 0x%08x, len %zd\n", | |
311 | flash->spi->dev.bus_id, __FUNCTION__, "to", | |
312 | (u32)to, len); | |
313 | ||
314 | if (retlen) | |
315 | *retlen = 0; | |
316 | ||
317 | /* sanity checks */ | |
318 | if (!len) | |
319 | return(0); | |
320 | ||
321 | if (to + len > flash->mtd.size) | |
322 | return -EINVAL; | |
323 | ||
8275c642 VW |
324 | spi_message_init(&m); |
325 | memset(t, 0, (sizeof t)); | |
326 | ||
327 | t[0].tx_buf = flash->command; | |
328 | t[0].len = sizeof(flash->command); | |
329 | spi_message_add_tail(&t[0], &m); | |
330 | ||
331 | t[1].tx_buf = buf; | |
332 | spi_message_add_tail(&t[1], &m); | |
333 | ||
7d5230ea | 334 | mutex_lock(&flash->lock); |
2f9f7628 ML |
335 | |
336 | /* Wait until finished previous write command. */ | |
337 | if (wait_till_ready(flash)) | |
338 | return 1; | |
339 | ||
340 | write_enable(flash); | |
341 | ||
2f9f7628 ML |
342 | /* Set up the opcode in the write buffer. */ |
343 | flash->command[0] = OPCODE_PP; | |
344 | flash->command[1] = to >> 16; | |
345 | flash->command[2] = to >> 8; | |
346 | flash->command[3] = to; | |
347 | ||
2f9f7628 ML |
348 | /* what page do we start with? */ |
349 | page_offset = to % FLASH_PAGESIZE; | |
350 | ||
351 | /* do all the bytes fit onto one page? */ | |
352 | if (page_offset + len <= FLASH_PAGESIZE) { | |
2f9f7628 ML |
353 | t[1].len = len; |
354 | ||
355 | spi_sync(flash->spi, &m); | |
356 | ||
357 | *retlen = m.actual_length - sizeof(flash->command); | |
358 | } else { | |
359 | u32 i; | |
360 | ||
361 | /* the size of data remaining on the first page */ | |
362 | page_size = FLASH_PAGESIZE - page_offset; | |
363 | ||
2f9f7628 ML |
364 | t[1].len = page_size; |
365 | spi_sync(flash->spi, &m); | |
366 | ||
367 | *retlen = m.actual_length - sizeof(flash->command); | |
368 | ||
369 | /* write everything in PAGESIZE chunks */ | |
370 | for (i = page_size; i < len; i += page_size) { | |
371 | page_size = len - i; | |
372 | if (page_size > FLASH_PAGESIZE) | |
373 | page_size = FLASH_PAGESIZE; | |
374 | ||
375 | /* write the next page to flash */ | |
376 | flash->command[1] = (to + i) >> 16; | |
377 | flash->command[2] = (to + i) >> 8; | |
378 | flash->command[3] = (to + i); | |
379 | ||
380 | t[1].tx_buf = buf + i; | |
381 | t[1].len = page_size; | |
382 | ||
383 | wait_till_ready(flash); | |
384 | ||
385 | write_enable(flash); | |
386 | ||
387 | spi_sync(flash->spi, &m); | |
388 | ||
7111763d DB |
389 | if (retlen) |
390 | *retlen += m.actual_length | |
391 | - sizeof(flash->command); | |
7d5230ea DB |
392 | } |
393 | } | |
2f9f7628 | 394 | |
7d5230ea | 395 | mutex_unlock(&flash->lock); |
2f9f7628 ML |
396 | |
397 | return 0; | |
398 | } | |
399 | ||
400 | ||
401 | /****************************************************************************/ | |
402 | ||
403 | /* | |
404 | * SPI device driver setup and teardown | |
405 | */ | |
406 | ||
407 | struct flash_info { | |
408 | char *name; | |
fa0a8c71 DB |
409 | |
410 | /* JEDEC id zero means "no ID" (most older chips); otherwise it has | |
411 | * a high byte of zero plus three data bytes: the manufacturer id, | |
412 | * then a two byte device id. | |
413 | */ | |
414 | u32 jedec_id; | |
415 | ||
416 | /* The size listed here is what works with OPCODE_SE, which isn't | |
417 | * necessarily called a "sector" by the vendor. | |
418 | */ | |
2f9f7628 | 419 | unsigned sector_size; |
fa0a8c71 DB |
420 | u16 n_sectors; |
421 | ||
422 | u16 flags; | |
423 | #define SECT_4K 0x01 /* OPCODE_BE_4K works uniformly */ | |
2f9f7628 ML |
424 | }; |
425 | ||
fa0a8c71 DB |
426 | |
427 | /* NOTE: double check command sets and memory organization when you add | |
428 | * more flash chips. This current list focusses on newer chips, which | |
429 | * have been converging on command sets which including JEDEC ID. | |
430 | */ | |
2f9f7628 | 431 | static struct flash_info __devinitdata m25p_data [] = { |
fa0a8c71 DB |
432 | |
433 | /* Atmel -- some are (confusingly) marketed as "DataFlash" */ | |
434 | { "at25fs010", 0x1f6601, 32 * 1024, 4, SECT_4K, }, | |
435 | { "at25fs040", 0x1f6604, 64 * 1024, 8, SECT_4K, }, | |
436 | ||
437 | { "at25df041a", 0x1f4401, 64 * 1024, 8, SECT_4K, }, | |
438 | ||
439 | { "at26f004", 0x1f0400, 64 * 1024, 8, SECT_4K, }, | |
440 | { "at26df081a", 0x1f4501, 64 * 1024, 16, SECT_4K, }, | |
441 | { "at26df161a", 0x1f4601, 64 * 1024, 32, SECT_4K, }, | |
442 | { "at26df321", 0x1f4701, 64 * 1024, 64, SECT_4K, }, | |
443 | ||
444 | /* Spansion -- single (large) sector size only, at least | |
445 | * for the chips listed here (without boot sectors). | |
446 | */ | |
447 | { "s25sl004a", 0x010212, 64 * 1024, 8, }, | |
448 | { "s25sl008a", 0x010213, 64 * 1024, 16, }, | |
449 | { "s25sl016a", 0x010214, 64 * 1024, 32, }, | |
450 | { "s25sl032a", 0x010215, 64 * 1024, 64, }, | |
451 | { "s25sl064a", 0x010216, 64 * 1024, 128, }, | |
452 | ||
453 | /* SST -- large erase sizes are "overlays", "sectors" are 4K */ | |
454 | { "sst25vf040b", 0xbf258d, 64 * 1024, 8, SECT_4K, }, | |
455 | { "sst25vf080b", 0xbf258e, 64 * 1024, 16, SECT_4K, }, | |
456 | { "sst25vf016b", 0xbf2541, 64 * 1024, 32, SECT_4K, }, | |
457 | { "sst25vf032b", 0xbf254a, 64 * 1024, 64, SECT_4K, }, | |
458 | ||
459 | /* ST Microelectronics -- newer production may have feature updates */ | |
460 | { "m25p05", 0x202010, 32 * 1024, 2, }, | |
461 | { "m25p10", 0x202011, 32 * 1024, 4, }, | |
462 | { "m25p20", 0x202012, 64 * 1024, 4, }, | |
463 | { "m25p40", 0x202013, 64 * 1024, 8, }, | |
464 | { "m25p80", 0, 64 * 1024, 16, }, | |
465 | { "m25p16", 0x202015, 64 * 1024, 32, }, | |
466 | { "m25p32", 0x202016, 64 * 1024, 64, }, | |
467 | { "m25p64", 0x202017, 64 * 1024, 128, }, | |
468 | { "m25p128", 0x202018, 256 * 1024, 64, }, | |
469 | ||
470 | { "m45pe80", 0x204014, 64 * 1024, 16, }, | |
471 | { "m45pe16", 0x204015, 64 * 1024, 32, }, | |
472 | ||
473 | { "m25pe80", 0x208014, 64 * 1024, 16, }, | |
474 | { "m25pe16", 0x208015, 64 * 1024, 32, SECT_4K, }, | |
475 | ||
476 | /* Winbond -- w25x "blocks" are 64K, "sectors" are 4K */ | |
477 | { "w25x10", 0xef3011, 64 * 1024, 2, SECT_4K, }, | |
478 | { "w25x20", 0xef3012, 64 * 1024, 4, SECT_4K, }, | |
479 | { "w25x40", 0xef3013, 64 * 1024, 8, SECT_4K, }, | |
480 | { "w25x80", 0xef3014, 64 * 1024, 16, SECT_4K, }, | |
481 | { "w25x16", 0xef3015, 64 * 1024, 32, SECT_4K, }, | |
482 | { "w25x32", 0xef3016, 64 * 1024, 64, SECT_4K, }, | |
483 | { "w25x64", 0xef3017, 64 * 1024, 128, SECT_4K, }, | |
2f9f7628 ML |
484 | }; |
485 | ||
fa0a8c71 DB |
486 | static struct flash_info *__devinit jedec_probe(struct spi_device *spi) |
487 | { | |
488 | int tmp; | |
489 | u8 code = OPCODE_RDID; | |
490 | u8 id[3]; | |
491 | u32 jedec; | |
492 | struct flash_info *info; | |
493 | ||
494 | /* JEDEC also defines an optional "extended device information" | |
495 | * string for after vendor-specific data, after the three bytes | |
496 | * we use here. Supporting some chips might require using it. | |
497 | */ | |
498 | tmp = spi_write_then_read(spi, &code, 1, id, 3); | |
499 | if (tmp < 0) { | |
500 | DEBUG(MTD_DEBUG_LEVEL0, "%s: error %d reading JEDEC ID\n", | |
501 | spi->dev.bus_id, tmp); | |
502 | return NULL; | |
503 | } | |
504 | jedec = id[0]; | |
505 | jedec = jedec << 8; | |
506 | jedec |= id[1]; | |
507 | jedec = jedec << 8; | |
508 | jedec |= id[2]; | |
509 | ||
510 | for (tmp = 0, info = m25p_data; | |
511 | tmp < ARRAY_SIZE(m25p_data); | |
512 | tmp++, info++) { | |
513 | if (info->jedec_id == jedec) | |
514 | return info; | |
515 | } | |
516 | dev_err(&spi->dev, "unrecognized JEDEC id %06x\n", jedec); | |
517 | return NULL; | |
518 | } | |
519 | ||
520 | ||
2f9f7628 ML |
521 | /* |
522 | * board specific setup should have ensured the SPI clock used here | |
523 | * matches what the READ command supports, at least until this driver | |
524 | * understands FAST_READ (for clocks over 25 MHz). | |
525 | */ | |
526 | static int __devinit m25p_probe(struct spi_device *spi) | |
527 | { | |
528 | struct flash_platform_data *data; | |
529 | struct m25p *flash; | |
530 | struct flash_info *info; | |
531 | unsigned i; | |
532 | ||
533 | /* Platform data helps sort out which chip type we have, as | |
fa0a8c71 DB |
534 | * well as how this board partitions it. If we don't have |
535 | * a chip ID, try the JEDEC id commands; they'll work for most | |
536 | * newer chips, even if we don't recognize the particular chip. | |
2f9f7628 ML |
537 | */ |
538 | data = spi->dev.platform_data; | |
fa0a8c71 DB |
539 | if (data && data->type) { |
540 | for (i = 0, info = m25p_data; | |
541 | i < ARRAY_SIZE(m25p_data); | |
542 | i++, info++) { | |
543 | if (strcmp(data->type, info->name) == 0) | |
544 | break; | |
545 | } | |
2f9f7628 | 546 | |
fa0a8c71 DB |
547 | /* unrecognized chip? */ |
548 | if (i == ARRAY_SIZE(m25p_data)) { | |
549 | DEBUG(MTD_DEBUG_LEVEL0, "%s: unrecognized id %s\n", | |
550 | spi->dev.bus_id, data->type); | |
551 | info = NULL; | |
552 | ||
553 | /* recognized; is that chip really what's there? */ | |
554 | } else if (info->jedec_id) { | |
555 | struct flash_info *chip = jedec_probe(spi); | |
556 | ||
557 | if (!chip || chip != info) { | |
558 | dev_warn(&spi->dev, "found %s, expected %s\n", | |
559 | chip ? chip->name : "UNKNOWN", | |
560 | info->name); | |
561 | info = NULL; | |
562 | } | |
563 | } | |
564 | } else | |
565 | info = jedec_probe(spi); | |
566 | ||
567 | if (!info) | |
2f9f7628 | 568 | return -ENODEV; |
2f9f7628 | 569 | |
e94b1766 | 570 | flash = kzalloc(sizeof *flash, GFP_KERNEL); |
2f9f7628 ML |
571 | if (!flash) |
572 | return -ENOMEM; | |
573 | ||
574 | flash->spi = spi; | |
7d5230ea | 575 | mutex_init(&flash->lock); |
2f9f7628 ML |
576 | dev_set_drvdata(&spi->dev, flash); |
577 | ||
fa0a8c71 | 578 | if (data && data->name) |
2f9f7628 ML |
579 | flash->mtd.name = data->name; |
580 | else | |
581 | flash->mtd.name = spi->dev.bus_id; | |
582 | ||
583 | flash->mtd.type = MTD_NORFLASH; | |
783ed81f | 584 | flash->mtd.writesize = 1; |
2f9f7628 ML |
585 | flash->mtd.flags = MTD_CAP_NORFLASH; |
586 | flash->mtd.size = info->sector_size * info->n_sectors; | |
2f9f7628 ML |
587 | flash->mtd.erase = m25p80_erase; |
588 | flash->mtd.read = m25p80_read; | |
589 | flash->mtd.write = m25p80_write; | |
590 | ||
fa0a8c71 DB |
591 | /* prefer "small sector" erase if possible */ |
592 | if (info->flags & SECT_4K) { | |
593 | flash->erase_opcode = OPCODE_BE_4K; | |
594 | flash->mtd.erasesize = 4096; | |
595 | } else { | |
596 | flash->erase_opcode = OPCODE_SE; | |
597 | flash->mtd.erasesize = info->sector_size; | |
598 | } | |
599 | ||
2f9f7628 ML |
600 | dev_info(&spi->dev, "%s (%d Kbytes)\n", info->name, |
601 | flash->mtd.size / 1024); | |
602 | ||
603 | DEBUG(MTD_DEBUG_LEVEL2, | |
604 | "mtd .name = %s, .size = 0x%.8x (%uM) " | |
605 | ".erasesize = 0x%.8x (%uK) .numeraseregions = %d\n", | |
606 | flash->mtd.name, | |
607 | flash->mtd.size, flash->mtd.size / (1024*1024), | |
608 | flash->mtd.erasesize, flash->mtd.erasesize / 1024, | |
609 | flash->mtd.numeraseregions); | |
610 | ||
611 | if (flash->mtd.numeraseregions) | |
612 | for (i = 0; i < flash->mtd.numeraseregions; i++) | |
613 | DEBUG(MTD_DEBUG_LEVEL2, | |
614 | "mtd.eraseregions[%d] = { .offset = 0x%.8x, " | |
615 | ".erasesize = 0x%.8x (%uK), " | |
616 | ".numblocks = %d }\n", | |
617 | i, flash->mtd.eraseregions[i].offset, | |
618 | flash->mtd.eraseregions[i].erasesize, | |
619 | flash->mtd.eraseregions[i].erasesize / 1024, | |
620 | flash->mtd.eraseregions[i].numblocks); | |
621 | ||
622 | ||
623 | /* partitions should match sector boundaries; and it may be good to | |
624 | * use readonly partitions for writeprotected sectors (BP2..BP0). | |
625 | */ | |
626 | if (mtd_has_partitions()) { | |
627 | struct mtd_partition *parts = NULL; | |
628 | int nr_parts = 0; | |
629 | ||
630 | #ifdef CONFIG_MTD_CMDLINE_PARTS | |
631 | static const char *part_probes[] = { "cmdlinepart", NULL, }; | |
632 | ||
633 | nr_parts = parse_mtd_partitions(&flash->mtd, | |
634 | part_probes, &parts, 0); | |
635 | #endif | |
636 | ||
637 | if (nr_parts <= 0 && data && data->parts) { | |
638 | parts = data->parts; | |
639 | nr_parts = data->nr_parts; | |
640 | } | |
641 | ||
642 | if (nr_parts > 0) { | |
fa0a8c71 | 643 | for (i = 0; i < nr_parts; i++) { |
2f9f7628 ML |
644 | DEBUG(MTD_DEBUG_LEVEL2, "partitions[%d] = " |
645 | "{.name = %s, .offset = 0x%.8x, " | |
646 | ".size = 0x%.8x (%uK) }\n", | |
fa0a8c71 DB |
647 | i, parts[i].name, |
648 | parts[i].offset, | |
649 | parts[i].size, | |
650 | parts[i].size / 1024); | |
2f9f7628 ML |
651 | } |
652 | flash->partitioned = 1; | |
653 | return add_mtd_partitions(&flash->mtd, parts, nr_parts); | |
654 | } | |
655 | } else if (data->nr_parts) | |
656 | dev_warn(&spi->dev, "ignoring %d default partitions on %s\n", | |
657 | data->nr_parts, data->name); | |
658 | ||
659 | return add_mtd_device(&flash->mtd) == 1 ? -ENODEV : 0; | |
660 | } | |
661 | ||
662 | ||
663 | static int __devexit m25p_remove(struct spi_device *spi) | |
664 | { | |
665 | struct m25p *flash = dev_get_drvdata(&spi->dev); | |
666 | int status; | |
667 | ||
668 | /* Clean up MTD stuff. */ | |
669 | if (mtd_has_partitions() && flash->partitioned) | |
670 | status = del_mtd_partitions(&flash->mtd); | |
671 | else | |
672 | status = del_mtd_device(&flash->mtd); | |
673 | if (status == 0) | |
674 | kfree(flash); | |
675 | return 0; | |
676 | } | |
677 | ||
678 | ||
679 | static struct spi_driver m25p80_driver = { | |
680 | .driver = { | |
681 | .name = "m25p80", | |
682 | .bus = &spi_bus_type, | |
683 | .owner = THIS_MODULE, | |
684 | }, | |
685 | .probe = m25p_probe, | |
686 | .remove = __devexit_p(m25p_remove), | |
fa0a8c71 DB |
687 | |
688 | /* REVISIT: many of these chips have deep power-down modes, which | |
689 | * should clearly be entered on suspend() to minimize power use. | |
690 | * And also when they're otherwise idle... | |
691 | */ | |
2f9f7628 ML |
692 | }; |
693 | ||
694 | ||
695 | static int m25p80_init(void) | |
696 | { | |
697 | return spi_register_driver(&m25p80_driver); | |
698 | } | |
699 | ||
700 | ||
701 | static void m25p80_exit(void) | |
702 | { | |
703 | spi_unregister_driver(&m25p80_driver); | |
704 | } | |
705 | ||
706 | ||
707 | module_init(m25p80_init); | |
708 | module_exit(m25p80_exit); | |
709 | ||
710 | MODULE_LICENSE("GPL"); | |
711 | MODULE_AUTHOR("Mike Lavender"); | |
712 | MODULE_DESCRIPTION("MTD SPI driver for ST M25Pxx flash chips"); |