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1d6432fe DB |
1 | /* |
2 | * Atmel AT45xxx DataFlash MTD driver for lightweight SPI framework | |
3 | * | |
4 | * Largely derived from at91_dataflash.c: | |
5 | * Copyright (C) 2003-2005 SAN People (Pty) Ltd | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
11 | */ | |
1d6432fe | 12 | #include <linux/module.h> |
1d6432fe DB |
13 | #include <linux/slab.h> |
14 | #include <linux/delay.h> | |
15 | #include <linux/device.h> | |
ec9ce52e | 16 | #include <linux/mutex.h> |
771999b6 | 17 | #include <linux/err.h> |
5b7f3a50 | 18 | #include <linux/math64.h> |
b94e757c SG |
19 | #include <linux/of.h> |
20 | #include <linux/of_device.h> | |
771999b6 | 21 | |
1d6432fe DB |
22 | #include <linux/spi/spi.h> |
23 | #include <linux/spi/flash.h> | |
24 | ||
25 | #include <linux/mtd/mtd.h> | |
26 | #include <linux/mtd/partitions.h> | |
27 | ||
1d6432fe DB |
28 | /* |
29 | * DataFlash is a kind of SPI flash. Most AT45 chips have two buffers in | |
30 | * each chip, which may be used for double buffered I/O; but this driver | |
31 | * doesn't (yet) use these for any kind of i/o overlap or prefetching. | |
32 | * | |
33 | * Sometimes DataFlash is packaged in MMC-format cards, although the | |
8c64038e | 34 | * MMC stack can't (yet?) distinguish between MMC and DataFlash |
1d6432fe DB |
35 | * protocols during enumeration. |
36 | */ | |
37 | ||
1d6432fe DB |
38 | /* reads can bypass the buffers */ |
39 | #define OP_READ_CONTINUOUS 0xE8 | |
40 | #define OP_READ_PAGE 0xD2 | |
41 | ||
42 | /* group B requests can run even while status reports "busy" */ | |
43 | #define OP_READ_STATUS 0xD7 /* group B */ | |
44 | ||
45 | /* move data between host and buffer */ | |
46 | #define OP_READ_BUFFER1 0xD4 /* group B */ | |
47 | #define OP_READ_BUFFER2 0xD6 /* group B */ | |
48 | #define OP_WRITE_BUFFER1 0x84 /* group B */ | |
49 | #define OP_WRITE_BUFFER2 0x87 /* group B */ | |
50 | ||
51 | /* erasing flash */ | |
52 | #define OP_ERASE_PAGE 0x81 | |
53 | #define OP_ERASE_BLOCK 0x50 | |
54 | ||
55 | /* move data between buffer and flash */ | |
56 | #define OP_TRANSFER_BUF1 0x53 | |
57 | #define OP_TRANSFER_BUF2 0x55 | |
58 | #define OP_MREAD_BUFFER1 0xD4 | |
59 | #define OP_MREAD_BUFFER2 0xD6 | |
60 | #define OP_MWERASE_BUFFER1 0x83 | |
61 | #define OP_MWERASE_BUFFER2 0x86 | |
62 | #define OP_MWRITE_BUFFER1 0x88 /* sector must be pre-erased */ | |
63 | #define OP_MWRITE_BUFFER2 0x89 /* sector must be pre-erased */ | |
64 | ||
65 | /* write to buffer, then write-erase to flash */ | |
66 | #define OP_PROGRAM_VIA_BUF1 0x82 | |
67 | #define OP_PROGRAM_VIA_BUF2 0x85 | |
68 | ||
69 | /* compare buffer to flash */ | |
70 | #define OP_COMPARE_BUF1 0x60 | |
71 | #define OP_COMPARE_BUF2 0x61 | |
72 | ||
73 | /* read flash to buffer, then write-erase to flash */ | |
74 | #define OP_REWRITE_VIA_BUF1 0x58 | |
75 | #define OP_REWRITE_VIA_BUF2 0x59 | |
76 | ||
77 | /* newer chips report JEDEC manufacturer and device IDs; chip | |
78 | * serial number and OTP bits; and per-sector writeprotect. | |
79 | */ | |
80 | #define OP_READ_ID 0x9F | |
81 | #define OP_READ_SECURITY 0x77 | |
34a82443 DB |
82 | #define OP_WRITE_SECURITY_REVC 0x9A |
83 | #define OP_WRITE_SECURITY 0x9B /* revision D */ | |
1d6432fe DB |
84 | |
85 | ||
86 | struct dataflash { | |
271c5c59 | 87 | uint8_t command[4]; |
1d6432fe DB |
88 | char name[24]; |
89 | ||
1d6432fe DB |
90 | unsigned short page_offset; /* offset in flash address */ |
91 | unsigned int page_size; /* of bytes per page */ | |
92 | ||
ec9ce52e | 93 | struct mutex lock; |
1d6432fe DB |
94 | struct spi_device *spi; |
95 | ||
96 | struct mtd_info mtd; | |
97 | }; | |
98 | ||
b94e757c SG |
99 | #ifdef CONFIG_OF |
100 | static const struct of_device_id dataflash_dt_ids[] = { | |
101 | { .compatible = "atmel,at45", }, | |
102 | { .compatible = "atmel,dataflash", }, | |
103 | { /* sentinel */ } | |
104 | }; | |
b94e757c SG |
105 | #endif |
106 | ||
1d6432fe DB |
107 | /* ......................................................................... */ |
108 | ||
109 | /* | |
110 | * Return the status of the DataFlash device. | |
111 | */ | |
112 | static inline int dataflash_status(struct spi_device *spi) | |
113 | { | |
114 | /* NOTE: at45db321c over 25 MHz wants to write | |
115 | * a dummy byte after the opcode... | |
116 | */ | |
117 | return spi_w8r8(spi, OP_READ_STATUS); | |
118 | } | |
119 | ||
120 | /* | |
121 | * Poll the DataFlash device until it is READY. | |
122 | * This usually takes 5-20 msec or so; more for sector erase. | |
123 | */ | |
124 | static int dataflash_waitready(struct spi_device *spi) | |
125 | { | |
126 | int status; | |
127 | ||
128 | for (;;) { | |
129 | status = dataflash_status(spi); | |
130 | if (status < 0) { | |
289c0522 | 131 | pr_debug("%s: status %d?\n", |
160bbab3 | 132 | dev_name(&spi->dev), status); |
1d6432fe DB |
133 | status = 0; |
134 | } | |
135 | ||
136 | if (status & (1 << 7)) /* RDY/nBSY */ | |
137 | return status; | |
138 | ||
139 | msleep(3); | |
140 | } | |
141 | } | |
142 | ||
143 | /* ......................................................................... */ | |
144 | ||
145 | /* | |
146 | * Erase pages of flash. | |
147 | */ | |
148 | static int dataflash_erase(struct mtd_info *mtd, struct erase_info *instr) | |
149 | { | |
42845d2a | 150 | struct dataflash *priv = mtd->priv; |
1d6432fe | 151 | struct spi_device *spi = priv->spi; |
8275c642 | 152 | struct spi_transfer x = { .tx_dma = 0, }; |
1d6432fe DB |
153 | struct spi_message msg; |
154 | unsigned blocksize = priv->page_size << 3; | |
271c5c59 | 155 | uint8_t *command; |
5b7f3a50 | 156 | uint32_t rem; |
1d6432fe | 157 | |
289c0522 | 158 | pr_debug("%s: erase addr=0x%llx len 0x%llx\n", |
160bbab3 KS |
159 | dev_name(&spi->dev), (long long)instr->addr, |
160 | (long long)instr->len); | |
1d6432fe | 161 | |
5b7f3a50 AB |
162 | div_u64_rem(instr->len, priv->page_size, &rem); |
163 | if (rem) | |
164 | return -EINVAL; | |
165 | div_u64_rem(instr->addr, priv->page_size, &rem); | |
166 | if (rem) | |
1d6432fe DB |
167 | return -EINVAL; |
168 | ||
8275c642 VW |
169 | spi_message_init(&msg); |
170 | ||
171 | x.tx_buf = command = priv->command; | |
172 | x.len = 4; | |
173 | spi_message_add_tail(&x, &msg); | |
1d6432fe | 174 | |
ec9ce52e | 175 | mutex_lock(&priv->lock); |
1d6432fe DB |
176 | while (instr->len > 0) { |
177 | unsigned int pageaddr; | |
178 | int status; | |
179 | int do_block; | |
180 | ||
181 | /* Calculate flash page address; use block erase (for speed) if | |
182 | * we're at a block boundary and need to erase the whole block. | |
183 | */ | |
dbf8c11f | 184 | pageaddr = div_u64(instr->addr, priv->page_size); |
3cb4f09f | 185 | do_block = (pageaddr & 0x7) == 0 && instr->len >= blocksize; |
1d6432fe DB |
186 | pageaddr = pageaddr << priv->page_offset; |
187 | ||
188 | command[0] = do_block ? OP_ERASE_BLOCK : OP_ERASE_PAGE; | |
271c5c59 DW |
189 | command[1] = (uint8_t)(pageaddr >> 16); |
190 | command[2] = (uint8_t)(pageaddr >> 8); | |
1d6432fe DB |
191 | command[3] = 0; |
192 | ||
289c0522 | 193 | pr_debug("ERASE %s: (%x) %x %x %x [%i]\n", |
1d6432fe DB |
194 | do_block ? "block" : "page", |
195 | command[0], command[1], command[2], command[3], | |
196 | pageaddr); | |
197 | ||
198 | status = spi_sync(spi, &msg); | |
199 | (void) dataflash_waitready(spi); | |
200 | ||
201 | if (status < 0) { | |
202 | printk(KERN_ERR "%s: erase %x, err %d\n", | |
160bbab3 | 203 | dev_name(&spi->dev), pageaddr, status); |
1d6432fe DB |
204 | /* REVISIT: can retry instr->retries times; or |
205 | * giveup and instr->fail_addr = instr->addr; | |
206 | */ | |
207 | continue; | |
208 | } | |
209 | ||
210 | if (do_block) { | |
211 | instr->addr += blocksize; | |
212 | instr->len -= blocksize; | |
213 | } else { | |
214 | instr->addr += priv->page_size; | |
215 | instr->len -= priv->page_size; | |
216 | } | |
217 | } | |
ec9ce52e | 218 | mutex_unlock(&priv->lock); |
1d6432fe DB |
219 | |
220 | /* Inform MTD subsystem that erase is complete */ | |
221 | instr->state = MTD_ERASE_DONE; | |
222 | mtd_erase_callback(instr); | |
223 | ||
224 | return 0; | |
225 | } | |
226 | ||
227 | /* | |
228 | * Read from the DataFlash device. | |
229 | * from : Start offset in flash device | |
230 | * len : Amount to read | |
231 | * retlen : About of data actually read | |
232 | * buf : Buffer containing the data | |
233 | */ | |
234 | static int dataflash_read(struct mtd_info *mtd, loff_t from, size_t len, | |
235 | size_t *retlen, u_char *buf) | |
236 | { | |
42845d2a | 237 | struct dataflash *priv = mtd->priv; |
1d6432fe DB |
238 | struct spi_transfer x[2] = { { .tx_dma = 0, }, }; |
239 | struct spi_message msg; | |
240 | unsigned int addr; | |
271c5c59 | 241 | uint8_t *command; |
1d6432fe DB |
242 | int status; |
243 | ||
0a32a102 BN |
244 | pr_debug("%s: read 0x%x..0x%x\n", dev_name(&priv->spi->dev), |
245 | (unsigned)from, (unsigned)(from + len)); | |
1d6432fe | 246 | |
1d6432fe DB |
247 | /* Calculate flash page/byte address */ |
248 | addr = (((unsigned)from / priv->page_size) << priv->page_offset) | |
249 | + ((unsigned)from % priv->page_size); | |
250 | ||
251 | command = priv->command; | |
252 | ||
289c0522 | 253 | pr_debug("READ: (%x) %x %x %x\n", |
1d6432fe DB |
254 | command[0], command[1], command[2], command[3]); |
255 | ||
8275c642 VW |
256 | spi_message_init(&msg); |
257 | ||
1d6432fe DB |
258 | x[0].tx_buf = command; |
259 | x[0].len = 8; | |
8275c642 VW |
260 | spi_message_add_tail(&x[0], &msg); |
261 | ||
1d6432fe DB |
262 | x[1].rx_buf = buf; |
263 | x[1].len = len; | |
8275c642 | 264 | spi_message_add_tail(&x[1], &msg); |
1d6432fe | 265 | |
ec9ce52e | 266 | mutex_lock(&priv->lock); |
1d6432fe DB |
267 | |
268 | /* Continuous read, max clock = f(car) which may be less than | |
269 | * the peak rate available. Some chips support commands with | |
270 | * fewer "don't care" bytes. Both buffers stay unchanged. | |
271 | */ | |
272 | command[0] = OP_READ_CONTINUOUS; | |
271c5c59 DW |
273 | command[1] = (uint8_t)(addr >> 16); |
274 | command[2] = (uint8_t)(addr >> 8); | |
275 | command[3] = (uint8_t)(addr >> 0); | |
1d6432fe DB |
276 | /* plus 4 "don't care" bytes */ |
277 | ||
278 | status = spi_sync(priv->spi, &msg); | |
ec9ce52e | 279 | mutex_unlock(&priv->lock); |
1d6432fe DB |
280 | |
281 | if (status >= 0) { | |
282 | *retlen = msg.actual_length - 8; | |
283 | status = 0; | |
284 | } else | |
289c0522 | 285 | pr_debug("%s: read %x..%x --> %d\n", |
160bbab3 | 286 | dev_name(&priv->spi->dev), |
1d6432fe DB |
287 | (unsigned)from, (unsigned)(from + len), |
288 | status); | |
289 | return status; | |
290 | } | |
291 | ||
292 | /* | |
293 | * Write to the DataFlash device. | |
294 | * to : Start offset in flash device | |
295 | * len : Amount to write | |
296 | * retlen : Amount of data actually written | |
297 | * buf : Buffer containing the data | |
298 | */ | |
299 | static int dataflash_write(struct mtd_info *mtd, loff_t to, size_t len, | |
300 | size_t * retlen, const u_char * buf) | |
301 | { | |
42845d2a | 302 | struct dataflash *priv = mtd->priv; |
1d6432fe DB |
303 | struct spi_device *spi = priv->spi; |
304 | struct spi_transfer x[2] = { { .tx_dma = 0, }, }; | |
305 | struct spi_message msg; | |
306 | unsigned int pageaddr, addr, offset, writelen; | |
307 | size_t remaining = len; | |
308 | u_char *writebuf = (u_char *) buf; | |
309 | int status = -EINVAL; | |
271c5c59 | 310 | uint8_t *command; |
1d6432fe | 311 | |
289c0522 | 312 | pr_debug("%s: write 0x%x..0x%x\n", |
160bbab3 | 313 | dev_name(&spi->dev), (unsigned)to, (unsigned)(to + len)); |
1d6432fe | 314 | |
8275c642 VW |
315 | spi_message_init(&msg); |
316 | ||
1d6432fe DB |
317 | x[0].tx_buf = command = priv->command; |
318 | x[0].len = 4; | |
8275c642 | 319 | spi_message_add_tail(&x[0], &msg); |
1d6432fe DB |
320 | |
321 | pageaddr = ((unsigned)to / priv->page_size); | |
322 | offset = ((unsigned)to % priv->page_size); | |
323 | if (offset + len > priv->page_size) | |
324 | writelen = priv->page_size - offset; | |
325 | else | |
326 | writelen = len; | |
327 | ||
ec9ce52e | 328 | mutex_lock(&priv->lock); |
1d6432fe | 329 | while (remaining > 0) { |
289c0522 | 330 | pr_debug("write @ %i:%i len=%i\n", |
1d6432fe DB |
331 | pageaddr, offset, writelen); |
332 | ||
333 | /* REVISIT: | |
334 | * (a) each page in a sector must be rewritten at least | |
335 | * once every 10K sibling erase/program operations. | |
336 | * (b) for pages that are already erased, we could | |
337 | * use WRITE+MWRITE not PROGRAM for ~30% speedup. | |
338 | * (c) WRITE to buffer could be done while waiting for | |
339 | * a previous MWRITE/MWERASE to complete ... | |
340 | * (d) error handling here seems to be mostly missing. | |
341 | * | |
342 | * Two persistent bits per page, plus a per-sector counter, | |
343 | * could support (a) and (b) ... we might consider using | |
344 | * the second half of sector zero, which is just one block, | |
345 | * to track that state. (On AT91, that sector should also | |
346 | * support boot-from-DataFlash.) | |
347 | */ | |
348 | ||
349 | addr = pageaddr << priv->page_offset; | |
350 | ||
351 | /* (1) Maybe transfer partial page to Buffer1 */ | |
352 | if (writelen != priv->page_size) { | |
353 | command[0] = OP_TRANSFER_BUF1; | |
354 | command[1] = (addr & 0x00FF0000) >> 16; | |
355 | command[2] = (addr & 0x0000FF00) >> 8; | |
356 | command[3] = 0; | |
357 | ||
289c0522 | 358 | pr_debug("TRANSFER: (%x) %x %x %x\n", |
1d6432fe DB |
359 | command[0], command[1], command[2], command[3]); |
360 | ||
1d6432fe DB |
361 | status = spi_sync(spi, &msg); |
362 | if (status < 0) | |
0a32a102 | 363 | pr_debug("%s: xfer %u -> %d\n", |
160bbab3 | 364 | dev_name(&spi->dev), addr, status); |
1d6432fe DB |
365 | |
366 | (void) dataflash_waitready(priv->spi); | |
367 | } | |
368 | ||
369 | /* (2) Program full page via Buffer1 */ | |
370 | addr += offset; | |
371 | command[0] = OP_PROGRAM_VIA_BUF1; | |
372 | command[1] = (addr & 0x00FF0000) >> 16; | |
373 | command[2] = (addr & 0x0000FF00) >> 8; | |
374 | command[3] = (addr & 0x000000FF); | |
375 | ||
289c0522 | 376 | pr_debug("PROGRAM: (%x) %x %x %x\n", |
1d6432fe DB |
377 | command[0], command[1], command[2], command[3]); |
378 | ||
379 | x[1].tx_buf = writebuf; | |
380 | x[1].len = writelen; | |
8275c642 | 381 | spi_message_add_tail(x + 1, &msg); |
1d6432fe | 382 | status = spi_sync(spi, &msg); |
8275c642 | 383 | spi_transfer_del(x + 1); |
1d6432fe | 384 | if (status < 0) |
0a32a102 | 385 | pr_debug("%s: pgm %u/%u -> %d\n", |
160bbab3 | 386 | dev_name(&spi->dev), addr, writelen, status); |
1d6432fe DB |
387 | |
388 | (void) dataflash_waitready(priv->spi); | |
389 | ||
8275c642 | 390 | |
05dd1807 | 391 | #ifdef CONFIG_MTD_DATAFLASH_WRITE_VERIFY |
1d6432fe DB |
392 | |
393 | /* (3) Compare to Buffer1 */ | |
394 | addr = pageaddr << priv->page_offset; | |
395 | command[0] = OP_COMPARE_BUF1; | |
396 | command[1] = (addr & 0x00FF0000) >> 16; | |
397 | command[2] = (addr & 0x0000FF00) >> 8; | |
398 | command[3] = 0; | |
399 | ||
289c0522 | 400 | pr_debug("COMPARE: (%x) %x %x %x\n", |
1d6432fe DB |
401 | command[0], command[1], command[2], command[3]); |
402 | ||
1d6432fe DB |
403 | status = spi_sync(spi, &msg); |
404 | if (status < 0) | |
0a32a102 | 405 | pr_debug("%s: compare %u -> %d\n", |
160bbab3 | 406 | dev_name(&spi->dev), addr, status); |
1d6432fe DB |
407 | |
408 | status = dataflash_waitready(priv->spi); | |
409 | ||
410 | /* Check result of the compare operation */ | |
cccb45d4 | 411 | if (status & (1 << 6)) { |
1d6432fe | 412 | printk(KERN_ERR "%s: compare page %u, err %d\n", |
160bbab3 | 413 | dev_name(&spi->dev), pageaddr, status); |
1d6432fe DB |
414 | remaining = 0; |
415 | status = -EIO; | |
416 | break; | |
417 | } else | |
418 | status = 0; | |
419 | ||
05dd1807 | 420 | #endif /* CONFIG_MTD_DATAFLASH_WRITE_VERIFY */ |
1d6432fe DB |
421 | |
422 | remaining = remaining - writelen; | |
423 | pageaddr++; | |
424 | offset = 0; | |
425 | writebuf += writelen; | |
426 | *retlen += writelen; | |
427 | ||
428 | if (remaining > priv->page_size) | |
429 | writelen = priv->page_size; | |
430 | else | |
431 | writelen = remaining; | |
432 | } | |
ec9ce52e | 433 | mutex_unlock(&priv->lock); |
1d6432fe DB |
434 | |
435 | return status; | |
436 | } | |
437 | ||
438 | /* ......................................................................... */ | |
439 | ||
34a82443 DB |
440 | #ifdef CONFIG_MTD_DATAFLASH_OTP |
441 | ||
442 | static int dataflash_get_otp_info(struct mtd_info *mtd, | |
443 | struct otp_info *info, size_t len) | |
444 | { | |
445 | /* Report both blocks as identical: bytes 0..64, locked. | |
446 | * Unless the user block changed from all-ones, we can't | |
447 | * tell whether it's still writable; so we assume it isn't. | |
448 | */ | |
449 | info->start = 0; | |
450 | info->length = 64; | |
451 | info->locked = 1; | |
452 | return sizeof(*info); | |
453 | } | |
454 | ||
455 | static ssize_t otp_read(struct spi_device *spi, unsigned base, | |
456 | uint8_t *buf, loff_t off, size_t len) | |
457 | { | |
458 | struct spi_message m; | |
459 | size_t l; | |
460 | uint8_t *scratch; | |
461 | struct spi_transfer t; | |
462 | int status; | |
463 | ||
464 | if (off > 64) | |
465 | return -EINVAL; | |
466 | ||
467 | if ((off + len) > 64) | |
468 | len = 64 - off; | |
34a82443 DB |
469 | |
470 | spi_message_init(&m); | |
471 | ||
472 | l = 4 + base + off + len; | |
473 | scratch = kzalloc(l, GFP_KERNEL); | |
474 | if (!scratch) | |
475 | return -ENOMEM; | |
476 | ||
477 | /* OUT: OP_READ_SECURITY, 3 don't-care bytes, zeroes | |
478 | * IN: ignore 4 bytes, data bytes 0..N (max 127) | |
479 | */ | |
480 | scratch[0] = OP_READ_SECURITY; | |
481 | ||
482 | memset(&t, 0, sizeof t); | |
483 | t.tx_buf = scratch; | |
484 | t.rx_buf = scratch; | |
485 | t.len = l; | |
486 | spi_message_add_tail(&t, &m); | |
487 | ||
488 | dataflash_waitready(spi); | |
489 | ||
490 | status = spi_sync(spi, &m); | |
491 | if (status >= 0) { | |
492 | memcpy(buf, scratch + 4 + base + off, len); | |
493 | status = len; | |
494 | } | |
495 | ||
496 | kfree(scratch); | |
497 | return status; | |
498 | } | |
499 | ||
500 | static int dataflash_read_fact_otp(struct mtd_info *mtd, | |
501 | loff_t from, size_t len, size_t *retlen, u_char *buf) | |
502 | { | |
42845d2a | 503 | struct dataflash *priv = mtd->priv; |
34a82443 DB |
504 | int status; |
505 | ||
506 | /* 64 bytes, from 0..63 ... start at 64 on-chip */ | |
507 | mutex_lock(&priv->lock); | |
508 | status = otp_read(priv->spi, 64, buf, from, len); | |
509 | mutex_unlock(&priv->lock); | |
510 | ||
511 | if (status < 0) | |
512 | return status; | |
513 | *retlen = status; | |
514 | return 0; | |
515 | } | |
516 | ||
517 | static int dataflash_read_user_otp(struct mtd_info *mtd, | |
518 | loff_t from, size_t len, size_t *retlen, u_char *buf) | |
519 | { | |
42845d2a | 520 | struct dataflash *priv = mtd->priv; |
34a82443 DB |
521 | int status; |
522 | ||
523 | /* 64 bytes, from 0..63 ... start at 0 on-chip */ | |
524 | mutex_lock(&priv->lock); | |
525 | status = otp_read(priv->spi, 0, buf, from, len); | |
526 | mutex_unlock(&priv->lock); | |
527 | ||
528 | if (status < 0) | |
529 | return status; | |
530 | *retlen = status; | |
531 | return 0; | |
532 | } | |
533 | ||
534 | static int dataflash_write_user_otp(struct mtd_info *mtd, | |
535 | loff_t from, size_t len, size_t *retlen, u_char *buf) | |
536 | { | |
537 | struct spi_message m; | |
538 | const size_t l = 4 + 64; | |
539 | uint8_t *scratch; | |
540 | struct spi_transfer t; | |
42845d2a | 541 | struct dataflash *priv = mtd->priv; |
34a82443 DB |
542 | int status; |
543 | ||
544 | if (len > 64) | |
545 | return -EINVAL; | |
546 | ||
547 | /* Strictly speaking, we *could* truncate the write ... but | |
548 | * let's not do that for the only write that's ever possible. | |
549 | */ | |
550 | if ((from + len) > 64) | |
551 | return -EINVAL; | |
552 | ||
553 | /* OUT: OP_WRITE_SECURITY, 3 zeroes, 64 data-or-zero bytes | |
554 | * IN: ignore all | |
555 | */ | |
556 | scratch = kzalloc(l, GFP_KERNEL); | |
557 | if (!scratch) | |
558 | return -ENOMEM; | |
559 | scratch[0] = OP_WRITE_SECURITY; | |
560 | memcpy(scratch + 4 + from, buf, len); | |
561 | ||
562 | spi_message_init(&m); | |
563 | ||
564 | memset(&t, 0, sizeof t); | |
565 | t.tx_buf = scratch; | |
566 | t.len = l; | |
567 | spi_message_add_tail(&t, &m); | |
568 | ||
569 | /* Write the OTP bits, if they've not yet been written. | |
570 | * This modifies SRAM buffer1. | |
571 | */ | |
572 | mutex_lock(&priv->lock); | |
573 | dataflash_waitready(priv->spi); | |
574 | status = spi_sync(priv->spi, &m); | |
575 | mutex_unlock(&priv->lock); | |
576 | ||
577 | kfree(scratch); | |
578 | ||
579 | if (status >= 0) { | |
580 | status = 0; | |
581 | *retlen = len; | |
582 | } | |
583 | return status; | |
584 | } | |
585 | ||
586 | static char *otp_setup(struct mtd_info *device, char revision) | |
587 | { | |
3c3c10bb AB |
588 | device->_get_fact_prot_info = dataflash_get_otp_info; |
589 | device->_read_fact_prot_reg = dataflash_read_fact_otp; | |
590 | device->_get_user_prot_info = dataflash_get_otp_info; | |
591 | device->_read_user_prot_reg = dataflash_read_user_otp; | |
34a82443 DB |
592 | |
593 | /* rev c parts (at45db321c and at45db1281 only!) use a | |
594 | * different write procedure; not (yet?) implemented. | |
595 | */ | |
596 | if (revision > 'c') | |
3c3c10bb | 597 | device->_write_user_prot_reg = dataflash_write_user_otp; |
34a82443 DB |
598 | |
599 | return ", OTP"; | |
600 | } | |
601 | ||
602 | #else | |
603 | ||
cf93ae02 | 604 | static char *otp_setup(struct mtd_info *device, char revision) |
34a82443 DB |
605 | { |
606 | return " (OTP)"; | |
607 | } | |
608 | ||
609 | #endif | |
610 | ||
611 | /* ......................................................................... */ | |
612 | ||
1d6432fe DB |
613 | /* |
614 | * Register DataFlash device with MTD subsystem. | |
615 | */ | |
d8929942 GKH |
616 | static int add_dataflash_otp(struct spi_device *spi, char *name, int nr_pages, |
617 | int pagesize, int pageoffset, char revision) | |
1d6432fe DB |
618 | { |
619 | struct dataflash *priv; | |
620 | struct mtd_info *device; | |
b94e757c | 621 | struct mtd_part_parser_data ppdata; |
0278fd3f | 622 | struct flash_platform_data *pdata = dev_get_platdata(&spi->dev); |
34a82443 | 623 | char *otp_tag = ""; |
d4702669 | 624 | int err = 0; |
1d6432fe | 625 | |
5cbded58 | 626 | priv = kzalloc(sizeof *priv, GFP_KERNEL); |
1d6432fe DB |
627 | if (!priv) |
628 | return -ENOMEM; | |
629 | ||
ec9ce52e | 630 | mutex_init(&priv->lock); |
1d6432fe DB |
631 | priv->spi = spi; |
632 | priv->page_size = pagesize; | |
633 | priv->page_offset = pageoffset; | |
634 | ||
635 | /* name must be usable with cmdlinepart */ | |
636 | sprintf(priv->name, "spi%d.%d-%s", | |
637 | spi->master->bus_num, spi->chip_select, | |
638 | name); | |
639 | ||
640 | device = &priv->mtd; | |
641 | device->name = (pdata && pdata->name) ? pdata->name : priv->name; | |
642 | device->size = nr_pages * pagesize; | |
643 | device->erasesize = pagesize; | |
17ffc7ba | 644 | device->writesize = pagesize; |
1d6432fe DB |
645 | device->owner = THIS_MODULE; |
646 | device->type = MTD_DATAFLASH; | |
6c33cafc | 647 | device->flags = MTD_WRITEABLE; |
3c3c10bb AB |
648 | device->_erase = dataflash_erase; |
649 | device->_read = dataflash_read; | |
650 | device->_write = dataflash_write; | |
1d6432fe DB |
651 | device->priv = priv; |
652 | ||
87f39f04 DB |
653 | device->dev.parent = &spi->dev; |
654 | ||
34a82443 DB |
655 | if (revision >= 'c') |
656 | otp_tag = otp_setup(device, revision); | |
657 | ||
5b7f3a50 AB |
658 | dev_info(&spi->dev, "%s (%lld KBytes) pagesize %d bytes%s\n", |
659 | name, (long long)((device->size + 1023) >> 10), | |
34a82443 | 660 | pagesize, otp_tag); |
5cacbfa9 | 661 | spi_set_drvdata(spi, priv); |
1d6432fe | 662 | |
b94e757c SG |
663 | ppdata.of_node = spi->dev.of_node; |
664 | err = mtd_device_parse_register(device, NULL, &ppdata, | |
3a8fb12a DES |
665 | pdata ? pdata->parts : NULL, |
666 | pdata ? pdata->nr_parts : 0); | |
1d6432fe | 667 | |
d4702669 HS |
668 | if (!err) |
669 | return 0; | |
670 | ||
d4702669 HS |
671 | kfree(priv); |
672 | return err; | |
1d6432fe DB |
673 | } |
674 | ||
d8929942 GKH |
675 | static inline int add_dataflash(struct spi_device *spi, char *name, |
676 | int nr_pages, int pagesize, int pageoffset) | |
34a82443 DB |
677 | { |
678 | return add_dataflash_otp(spi, name, nr_pages, pagesize, | |
679 | pageoffset, 0); | |
680 | } | |
681 | ||
e9d42227 MH |
682 | struct flash_info { |
683 | char *name; | |
684 | ||
771999b6 | 685 | /* JEDEC id has a high byte of zero plus three data bytes: |
686 | * the manufacturer id, then a two byte device id. | |
e9d42227 | 687 | */ |
271c5c59 | 688 | uint32_t jedec_id; |
e9d42227 | 689 | |
771999b6 | 690 | /* The size listed here is what works with OP_ERASE_PAGE. */ |
e9d42227 | 691 | unsigned nr_pages; |
271c5c59 DW |
692 | uint16_t pagesize; |
693 | uint16_t pageoffset; | |
e9d42227 | 694 | |
271c5c59 | 695 | uint16_t flags; |
771999b6 | 696 | #define SUP_POW2PS 0x0002 /* supports 2^N byte pages */ |
697 | #define IS_POW2PS 0x0001 /* uses 2^N byte pages */ | |
e9d42227 MH |
698 | }; |
699 | ||
7bf350b7 | 700 | static struct flash_info dataflash_data[] = { |
e9d42227 | 701 | |
771999b6 | 702 | /* |
703 | * NOTE: chips with SUP_POW2PS (rev D and up) need two entries, | |
704 | * one with IS_POW2PS and the other without. The entry with the | |
705 | * non-2^N byte page size can't name exact chip revisions without | |
706 | * losing backwards compatibility for cmdlinepart. | |
707 | * | |
708 | * These newer chips also support 128-byte security registers (with | |
709 | * 64 bytes one-time-programmable) and software write-protection. | |
710 | */ | |
711 | { "AT45DB011B", 0x1f2200, 512, 264, 9, SUP_POW2PS}, | |
e9d42227 MH |
712 | { "at45db011d", 0x1f2200, 512, 256, 8, SUP_POW2PS | IS_POW2PS}, |
713 | ||
771999b6 | 714 | { "AT45DB021B", 0x1f2300, 1024, 264, 9, SUP_POW2PS}, |
e9d42227 MH |
715 | { "at45db021d", 0x1f2300, 1024, 256, 8, SUP_POW2PS | IS_POW2PS}, |
716 | ||
771999b6 | 717 | { "AT45DB041x", 0x1f2400, 2048, 264, 9, SUP_POW2PS}, |
e9d42227 MH |
718 | { "at45db041d", 0x1f2400, 2048, 256, 8, SUP_POW2PS | IS_POW2PS}, |
719 | ||
771999b6 | 720 | { "AT45DB081B", 0x1f2500, 4096, 264, 9, SUP_POW2PS}, |
e9d42227 MH |
721 | { "at45db081d", 0x1f2500, 4096, 256, 8, SUP_POW2PS | IS_POW2PS}, |
722 | ||
771999b6 | 723 | { "AT45DB161x", 0x1f2600, 4096, 528, 10, SUP_POW2PS}, |
e9d42227 MH |
724 | { "at45db161d", 0x1f2600, 4096, 512, 9, SUP_POW2PS | IS_POW2PS}, |
725 | ||
771999b6 | 726 | { "AT45DB321x", 0x1f2700, 8192, 528, 10, 0}, /* rev C */ |
e9d42227 | 727 | |
771999b6 | 728 | { "AT45DB321x", 0x1f2701, 8192, 528, 10, SUP_POW2PS}, |
e9d42227 MH |
729 | { "at45db321d", 0x1f2701, 8192, 512, 9, SUP_POW2PS | IS_POW2PS}, |
730 | ||
771999b6 | 731 | { "AT45DB642x", 0x1f2800, 8192, 1056, 11, SUP_POW2PS}, |
732 | { "at45db642d", 0x1f2800, 8192, 1024, 10, SUP_POW2PS | IS_POW2PS}, | |
e9d42227 MH |
733 | }; |
734 | ||
06f25510 | 735 | static struct flash_info *jedec_probe(struct spi_device *spi) |
e9d42227 MH |
736 | { |
737 | int tmp; | |
271c5c59 DW |
738 | uint8_t code = OP_READ_ID; |
739 | uint8_t id[3]; | |
740 | uint32_t jedec; | |
e9d42227 MH |
741 | struct flash_info *info; |
742 | int status; | |
743 | ||
e9d42227 MH |
744 | /* JEDEC also defines an optional "extended device information" |
745 | * string for after vendor-specific data, after the three bytes | |
746 | * we use here. Supporting some chips might require using it. | |
771999b6 | 747 | * |
748 | * If the vendor ID isn't Atmel's (0x1f), assume this call failed. | |
749 | * That's not an error; only rev C and newer chips handle it, and | |
750 | * only Atmel sells these chips. | |
e9d42227 MH |
751 | */ |
752 | tmp = spi_write_then_read(spi, &code, 1, id, 3); | |
753 | if (tmp < 0) { | |
289c0522 | 754 | pr_debug("%s: error %d reading JEDEC ID\n", |
160bbab3 | 755 | dev_name(&spi->dev), tmp); |
771999b6 | 756 | return ERR_PTR(tmp); |
e9d42227 | 757 | } |
771999b6 | 758 | if (id[0] != 0x1f) |
759 | return NULL; | |
760 | ||
e9d42227 MH |
761 | jedec = id[0]; |
762 | jedec = jedec << 8; | |
763 | jedec |= id[1]; | |
764 | jedec = jedec << 8; | |
765 | jedec |= id[2]; | |
766 | ||
767 | for (tmp = 0, info = dataflash_data; | |
768 | tmp < ARRAY_SIZE(dataflash_data); | |
769 | tmp++, info++) { | |
770 | if (info->jedec_id == jedec) { | |
289c0522 | 771 | pr_debug("%s: OTP, sector protect%s\n", |
771999b6 | 772 | dev_name(&spi->dev), |
773 | (info->flags & SUP_POW2PS) | |
774 | ? ", binary pagesize" : "" | |
775 | ); | |
e9d42227 MH |
776 | if (info->flags & SUP_POW2PS) { |
777 | status = dataflash_status(spi); | |
771999b6 | 778 | if (status < 0) { |
289c0522 | 779 | pr_debug("%s: status error %d\n", |
771999b6 | 780 | dev_name(&spi->dev), status); |
781 | return ERR_PTR(status); | |
782 | } | |
783 | if (status & 0x1) { | |
784 | if (info->flags & IS_POW2PS) | |
785 | return info; | |
786 | } else { | |
787 | if (!(info->flags & IS_POW2PS)) | |
788 | return info; | |
789 | } | |
229cc58b WN |
790 | } else |
791 | return info; | |
e9d42227 MH |
792 | } |
793 | } | |
771999b6 | 794 | |
795 | /* | |
796 | * Treat other chips as errors ... we won't know the right page | |
797 | * size (it might be binary) even when we can tell which density | |
798 | * class is involved (legacy chip id scheme). | |
799 | */ | |
800 | dev_warn(&spi->dev, "JEDEC id %06x not handled\n", jedec); | |
801 | return ERR_PTR(-ENODEV); | |
e9d42227 MH |
802 | } |
803 | ||
771999b6 | 804 | /* |
805 | * Detect and initialize DataFlash device, using JEDEC IDs on newer chips | |
806 | * or else the ID code embedded in the status bits: | |
807 | * | |
808 | * Device Density ID code #Pages PageSize Offset | |
809 | * AT45DB011B 1Mbit (128K) xx0011xx (0x0c) 512 264 9 | |
810 | * AT45DB021B 2Mbit (256K) xx0101xx (0x14) 1024 264 9 | |
811 | * AT45DB041B 4Mbit (512K) xx0111xx (0x1c) 2048 264 9 | |
812 | * AT45DB081B 8Mbit (1M) xx1001xx (0x24) 4096 264 9 | |
813 | * AT45DB0161B 16Mbit (2M) xx1011xx (0x2c) 4096 528 10 | |
814 | * AT45DB0321B 32Mbit (4M) xx1101xx (0x34) 8192 528 10 | |
815 | * AT45DB0642 64Mbit (8M) xx111xxx (0x3c) 8192 1056 11 | |
816 | * AT45DB1282 128Mbit (16M) xx0100xx (0x10) 16384 1056 11 | |
817 | */ | |
06f25510 | 818 | static int dataflash_probe(struct spi_device *spi) |
1d6432fe DB |
819 | { |
820 | int status; | |
e9d42227 MH |
821 | struct flash_info *info; |
822 | ||
823 | /* | |
824 | * Try to detect dataflash by JEDEC ID. | |
825 | * If it succeeds we know we have either a C or D part. | |
826 | * D will support power of 2 pagesize option. | |
34a82443 DB |
827 | * Both support the security register, though with different |
828 | * write procedures. | |
e9d42227 | 829 | */ |
e9d42227 | 830 | info = jedec_probe(spi); |
771999b6 | 831 | if (IS_ERR(info)) |
832 | return PTR_ERR(info); | |
e9d42227 | 833 | if (info != NULL) |
34a82443 DB |
834 | return add_dataflash_otp(spi, info->name, info->nr_pages, |
835 | info->pagesize, info->pageoffset, | |
836 | (info->flags & SUP_POW2PS) ? 'd' : 'c'); | |
e9d42227 | 837 | |
771999b6 | 838 | /* |
839 | * Older chips support only legacy commands, identifing | |
840 | * capacity using bits in the status byte. | |
841 | */ | |
1d6432fe DB |
842 | status = dataflash_status(spi); |
843 | if (status <= 0 || status == 0xff) { | |
289c0522 | 844 | pr_debug("%s: status error %d\n", |
160bbab3 | 845 | dev_name(&spi->dev), status); |
de4fa992 | 846 | if (status == 0 || status == 0xff) |
1d6432fe DB |
847 | status = -ENODEV; |
848 | return status; | |
849 | } | |
850 | ||
851 | /* if there's a device there, assume it's dataflash. | |
852 | * board setup should have set spi->max_speed_max to | |
853 | * match f(car) for continuous reads, mode 0 or 3. | |
854 | */ | |
855 | switch (status & 0x3c) { | |
856 | case 0x0c: /* 0 0 1 1 x x */ | |
857 | status = add_dataflash(spi, "AT45DB011B", 512, 264, 9); | |
858 | break; | |
859 | case 0x14: /* 0 1 0 1 x x */ | |
e9d42227 | 860 | status = add_dataflash(spi, "AT45DB021B", 1024, 264, 9); |
1d6432fe DB |
861 | break; |
862 | case 0x1c: /* 0 1 1 1 x x */ | |
771999b6 | 863 | status = add_dataflash(spi, "AT45DB041x", 2048, 264, 9); |
1d6432fe DB |
864 | break; |
865 | case 0x24: /* 1 0 0 1 x x */ | |
866 | status = add_dataflash(spi, "AT45DB081B", 4096, 264, 9); | |
867 | break; | |
868 | case 0x2c: /* 1 0 1 1 x x */ | |
771999b6 | 869 | status = add_dataflash(spi, "AT45DB161x", 4096, 528, 10); |
1d6432fe DB |
870 | break; |
871 | case 0x34: /* 1 1 0 1 x x */ | |
872 | status = add_dataflash(spi, "AT45DB321x", 8192, 528, 10); | |
873 | break; | |
874 | case 0x38: /* 1 1 1 x x x */ | |
875 | case 0x3c: | |
876 | status = add_dataflash(spi, "AT45DB642x", 8192, 1056, 11); | |
877 | break; | |
878 | /* obsolete AT45DB1282 not (yet?) supported */ | |
879 | default: | |
cb85b7e7 | 880 | dev_info(&spi->dev, "unsupported device (%x)\n", |
0a32a102 | 881 | status & 0x3c); |
1d6432fe DB |
882 | status = -ENODEV; |
883 | } | |
884 | ||
885 | if (status < 0) | |
0a32a102 BN |
886 | pr_debug("%s: add_dataflash --> %d\n", dev_name(&spi->dev), |
887 | status); | |
1d6432fe DB |
888 | |
889 | return status; | |
890 | } | |
891 | ||
810b7e06 | 892 | static int dataflash_remove(struct spi_device *spi) |
1d6432fe | 893 | { |
5cacbfa9 | 894 | struct dataflash *flash = spi_get_drvdata(spi); |
1d6432fe DB |
895 | int status; |
896 | ||
289c0522 | 897 | pr_debug("%s: remove\n", dev_name(&spi->dev)); |
1d6432fe | 898 | |
436c06da | 899 | status = mtd_device_unregister(&flash->mtd); |
1ba80c9e | 900 | if (status == 0) |
1d6432fe DB |
901 | kfree(flash); |
902 | return status; | |
903 | } | |
904 | ||
905 | static struct spi_driver dataflash_driver = { | |
906 | .driver = { | |
907 | .name = "mtd_dataflash", | |
1d6432fe | 908 | .owner = THIS_MODULE, |
19d69b86 | 909 | .of_match_table = of_match_ptr(dataflash_dt_ids), |
1d6432fe DB |
910 | }, |
911 | ||
912 | .probe = dataflash_probe, | |
5153b88c | 913 | .remove = dataflash_remove, |
1d6432fe DB |
914 | |
915 | /* FIXME: investigate suspend and resume... */ | |
916 | }; | |
917 | ||
c9d1b752 | 918 | module_spi_driver(dataflash_driver); |
1d6432fe DB |
919 | |
920 | MODULE_LICENSE("GPL"); | |
921 | MODULE_AUTHOR("Andrew Victor, David Brownell"); | |
922 | MODULE_DESCRIPTION("MTD DataFlash driver"); | |
e0626e38 | 923 | MODULE_ALIAS("spi:mtd_dataflash"); |