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1d6432fe DB |
1 | /* |
2 | * Atmel AT45xxx DataFlash MTD driver for lightweight SPI framework | |
3 | * | |
4 | * Largely derived from at91_dataflash.c: | |
5 | * Copyright (C) 2003-2005 SAN People (Pty) Ltd | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
11 | */ | |
1d6432fe DB |
12 | #include <linux/module.h> |
13 | #include <linux/init.h> | |
14 | #include <linux/slab.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/device.h> | |
ec9ce52e | 17 | #include <linux/mutex.h> |
771999b6 | 18 | #include <linux/err.h> |
19 | ||
1d6432fe DB |
20 | #include <linux/spi/spi.h> |
21 | #include <linux/spi/flash.h> | |
22 | ||
23 | #include <linux/mtd/mtd.h> | |
24 | #include <linux/mtd/partitions.h> | |
25 | ||
26 | ||
27 | /* | |
28 | * DataFlash is a kind of SPI flash. Most AT45 chips have two buffers in | |
29 | * each chip, which may be used for double buffered I/O; but this driver | |
30 | * doesn't (yet) use these for any kind of i/o overlap or prefetching. | |
31 | * | |
32 | * Sometimes DataFlash is packaged in MMC-format cards, although the | |
33 | * MMC stack can't use SPI (yet), or distinguish between MMC and DataFlash | |
34 | * protocols during enumeration. | |
35 | */ | |
36 | ||
37 | #define CONFIG_DATAFLASH_WRITE_VERIFY | |
38 | ||
39 | /* reads can bypass the buffers */ | |
40 | #define OP_READ_CONTINUOUS 0xE8 | |
41 | #define OP_READ_PAGE 0xD2 | |
42 | ||
43 | /* group B requests can run even while status reports "busy" */ | |
44 | #define OP_READ_STATUS 0xD7 /* group B */ | |
45 | ||
46 | /* move data between host and buffer */ | |
47 | #define OP_READ_BUFFER1 0xD4 /* group B */ | |
48 | #define OP_READ_BUFFER2 0xD6 /* group B */ | |
49 | #define OP_WRITE_BUFFER1 0x84 /* group B */ | |
50 | #define OP_WRITE_BUFFER2 0x87 /* group B */ | |
51 | ||
52 | /* erasing flash */ | |
53 | #define OP_ERASE_PAGE 0x81 | |
54 | #define OP_ERASE_BLOCK 0x50 | |
55 | ||
56 | /* move data between buffer and flash */ | |
57 | #define OP_TRANSFER_BUF1 0x53 | |
58 | #define OP_TRANSFER_BUF2 0x55 | |
59 | #define OP_MREAD_BUFFER1 0xD4 | |
60 | #define OP_MREAD_BUFFER2 0xD6 | |
61 | #define OP_MWERASE_BUFFER1 0x83 | |
62 | #define OP_MWERASE_BUFFER2 0x86 | |
63 | #define OP_MWRITE_BUFFER1 0x88 /* sector must be pre-erased */ | |
64 | #define OP_MWRITE_BUFFER2 0x89 /* sector must be pre-erased */ | |
65 | ||
66 | /* write to buffer, then write-erase to flash */ | |
67 | #define OP_PROGRAM_VIA_BUF1 0x82 | |
68 | #define OP_PROGRAM_VIA_BUF2 0x85 | |
69 | ||
70 | /* compare buffer to flash */ | |
71 | #define OP_COMPARE_BUF1 0x60 | |
72 | #define OP_COMPARE_BUF2 0x61 | |
73 | ||
74 | /* read flash to buffer, then write-erase to flash */ | |
75 | #define OP_REWRITE_VIA_BUF1 0x58 | |
76 | #define OP_REWRITE_VIA_BUF2 0x59 | |
77 | ||
78 | /* newer chips report JEDEC manufacturer and device IDs; chip | |
79 | * serial number and OTP bits; and per-sector writeprotect. | |
80 | */ | |
81 | #define OP_READ_ID 0x9F | |
82 | #define OP_READ_SECURITY 0x77 | |
83 | #define OP_WRITE_SECURITY 0x9A /* OTP bits */ | |
84 | ||
85 | ||
86 | struct dataflash { | |
271c5c59 | 87 | uint8_t command[4]; |
1d6432fe DB |
88 | char name[24]; |
89 | ||
90 | unsigned partitioned:1; | |
91 | ||
92 | unsigned short page_offset; /* offset in flash address */ | |
93 | unsigned int page_size; /* of bytes per page */ | |
94 | ||
ec9ce52e | 95 | struct mutex lock; |
1d6432fe DB |
96 | struct spi_device *spi; |
97 | ||
98 | struct mtd_info mtd; | |
99 | }; | |
100 | ||
101 | #ifdef CONFIG_MTD_PARTITIONS | |
102 | #define mtd_has_partitions() (1) | |
103 | #else | |
104 | #define mtd_has_partitions() (0) | |
105 | #endif | |
106 | ||
107 | /* ......................................................................... */ | |
108 | ||
109 | /* | |
110 | * Return the status of the DataFlash device. | |
111 | */ | |
112 | static inline int dataflash_status(struct spi_device *spi) | |
113 | { | |
114 | /* NOTE: at45db321c over 25 MHz wants to write | |
115 | * a dummy byte after the opcode... | |
116 | */ | |
117 | return spi_w8r8(spi, OP_READ_STATUS); | |
118 | } | |
119 | ||
120 | /* | |
121 | * Poll the DataFlash device until it is READY. | |
122 | * This usually takes 5-20 msec or so; more for sector erase. | |
123 | */ | |
124 | static int dataflash_waitready(struct spi_device *spi) | |
125 | { | |
126 | int status; | |
127 | ||
128 | for (;;) { | |
129 | status = dataflash_status(spi); | |
130 | if (status < 0) { | |
131 | DEBUG(MTD_DEBUG_LEVEL1, "%s: status %d?\n", | |
132 | spi->dev.bus_id, status); | |
133 | status = 0; | |
134 | } | |
135 | ||
136 | if (status & (1 << 7)) /* RDY/nBSY */ | |
137 | return status; | |
138 | ||
139 | msleep(3); | |
140 | } | |
141 | } | |
142 | ||
143 | /* ......................................................................... */ | |
144 | ||
145 | /* | |
146 | * Erase pages of flash. | |
147 | */ | |
148 | static int dataflash_erase(struct mtd_info *mtd, struct erase_info *instr) | |
149 | { | |
150 | struct dataflash *priv = (struct dataflash *)mtd->priv; | |
151 | struct spi_device *spi = priv->spi; | |
8275c642 | 152 | struct spi_transfer x = { .tx_dma = 0, }; |
1d6432fe DB |
153 | struct spi_message msg; |
154 | unsigned blocksize = priv->page_size << 3; | |
271c5c59 | 155 | uint8_t *command; |
1d6432fe DB |
156 | |
157 | DEBUG(MTD_DEBUG_LEVEL2, "%s: erase addr=0x%x len 0x%x\n", | |
158 | spi->dev.bus_id, | |
159 | instr->addr, instr->len); | |
160 | ||
161 | /* Sanity checks */ | |
162 | if ((instr->addr + instr->len) > mtd->size | |
163 | || (instr->len % priv->page_size) != 0 | |
164 | || (instr->addr % priv->page_size) != 0) | |
165 | return -EINVAL; | |
166 | ||
8275c642 VW |
167 | spi_message_init(&msg); |
168 | ||
169 | x.tx_buf = command = priv->command; | |
170 | x.len = 4; | |
171 | spi_message_add_tail(&x, &msg); | |
1d6432fe | 172 | |
ec9ce52e | 173 | mutex_lock(&priv->lock); |
1d6432fe DB |
174 | while (instr->len > 0) { |
175 | unsigned int pageaddr; | |
176 | int status; | |
177 | int do_block; | |
178 | ||
179 | /* Calculate flash page address; use block erase (for speed) if | |
180 | * we're at a block boundary and need to erase the whole block. | |
181 | */ | |
182 | pageaddr = instr->addr / priv->page_size; | |
3cb4f09f | 183 | do_block = (pageaddr & 0x7) == 0 && instr->len >= blocksize; |
1d6432fe DB |
184 | pageaddr = pageaddr << priv->page_offset; |
185 | ||
186 | command[0] = do_block ? OP_ERASE_BLOCK : OP_ERASE_PAGE; | |
271c5c59 DW |
187 | command[1] = (uint8_t)(pageaddr >> 16); |
188 | command[2] = (uint8_t)(pageaddr >> 8); | |
1d6432fe DB |
189 | command[3] = 0; |
190 | ||
191 | DEBUG(MTD_DEBUG_LEVEL3, "ERASE %s: (%x) %x %x %x [%i]\n", | |
192 | do_block ? "block" : "page", | |
193 | command[0], command[1], command[2], command[3], | |
194 | pageaddr); | |
195 | ||
196 | status = spi_sync(spi, &msg); | |
197 | (void) dataflash_waitready(spi); | |
198 | ||
199 | if (status < 0) { | |
200 | printk(KERN_ERR "%s: erase %x, err %d\n", | |
201 | spi->dev.bus_id, pageaddr, status); | |
202 | /* REVISIT: can retry instr->retries times; or | |
203 | * giveup and instr->fail_addr = instr->addr; | |
204 | */ | |
205 | continue; | |
206 | } | |
207 | ||
208 | if (do_block) { | |
209 | instr->addr += blocksize; | |
210 | instr->len -= blocksize; | |
211 | } else { | |
212 | instr->addr += priv->page_size; | |
213 | instr->len -= priv->page_size; | |
214 | } | |
215 | } | |
ec9ce52e | 216 | mutex_unlock(&priv->lock); |
1d6432fe DB |
217 | |
218 | /* Inform MTD subsystem that erase is complete */ | |
219 | instr->state = MTD_ERASE_DONE; | |
220 | mtd_erase_callback(instr); | |
221 | ||
222 | return 0; | |
223 | } | |
224 | ||
225 | /* | |
226 | * Read from the DataFlash device. | |
227 | * from : Start offset in flash device | |
228 | * len : Amount to read | |
229 | * retlen : About of data actually read | |
230 | * buf : Buffer containing the data | |
231 | */ | |
232 | static int dataflash_read(struct mtd_info *mtd, loff_t from, size_t len, | |
233 | size_t *retlen, u_char *buf) | |
234 | { | |
235 | struct dataflash *priv = (struct dataflash *)mtd->priv; | |
236 | struct spi_transfer x[2] = { { .tx_dma = 0, }, }; | |
237 | struct spi_message msg; | |
238 | unsigned int addr; | |
271c5c59 | 239 | uint8_t *command; |
1d6432fe DB |
240 | int status; |
241 | ||
242 | DEBUG(MTD_DEBUG_LEVEL2, "%s: read 0x%x..0x%x\n", | |
243 | priv->spi->dev.bus_id, (unsigned)from, (unsigned)(from + len)); | |
244 | ||
245 | *retlen = 0; | |
246 | ||
247 | /* Sanity checks */ | |
248 | if (!len) | |
249 | return 0; | |
250 | if (from + len > mtd->size) | |
251 | return -EINVAL; | |
252 | ||
253 | /* Calculate flash page/byte address */ | |
254 | addr = (((unsigned)from / priv->page_size) << priv->page_offset) | |
255 | + ((unsigned)from % priv->page_size); | |
256 | ||
257 | command = priv->command; | |
258 | ||
259 | DEBUG(MTD_DEBUG_LEVEL3, "READ: (%x) %x %x %x\n", | |
260 | command[0], command[1], command[2], command[3]); | |
261 | ||
8275c642 VW |
262 | spi_message_init(&msg); |
263 | ||
1d6432fe DB |
264 | x[0].tx_buf = command; |
265 | x[0].len = 8; | |
8275c642 VW |
266 | spi_message_add_tail(&x[0], &msg); |
267 | ||
1d6432fe DB |
268 | x[1].rx_buf = buf; |
269 | x[1].len = len; | |
8275c642 | 270 | spi_message_add_tail(&x[1], &msg); |
1d6432fe | 271 | |
ec9ce52e | 272 | mutex_lock(&priv->lock); |
1d6432fe DB |
273 | |
274 | /* Continuous read, max clock = f(car) which may be less than | |
275 | * the peak rate available. Some chips support commands with | |
276 | * fewer "don't care" bytes. Both buffers stay unchanged. | |
277 | */ | |
278 | command[0] = OP_READ_CONTINUOUS; | |
271c5c59 DW |
279 | command[1] = (uint8_t)(addr >> 16); |
280 | command[2] = (uint8_t)(addr >> 8); | |
281 | command[3] = (uint8_t)(addr >> 0); | |
1d6432fe DB |
282 | /* plus 4 "don't care" bytes */ |
283 | ||
284 | status = spi_sync(priv->spi, &msg); | |
ec9ce52e | 285 | mutex_unlock(&priv->lock); |
1d6432fe DB |
286 | |
287 | if (status >= 0) { | |
288 | *retlen = msg.actual_length - 8; | |
289 | status = 0; | |
290 | } else | |
291 | DEBUG(MTD_DEBUG_LEVEL1, "%s: read %x..%x --> %d\n", | |
292 | priv->spi->dev.bus_id, | |
293 | (unsigned)from, (unsigned)(from + len), | |
294 | status); | |
295 | return status; | |
296 | } | |
297 | ||
298 | /* | |
299 | * Write to the DataFlash device. | |
300 | * to : Start offset in flash device | |
301 | * len : Amount to write | |
302 | * retlen : Amount of data actually written | |
303 | * buf : Buffer containing the data | |
304 | */ | |
305 | static int dataflash_write(struct mtd_info *mtd, loff_t to, size_t len, | |
306 | size_t * retlen, const u_char * buf) | |
307 | { | |
308 | struct dataflash *priv = (struct dataflash *)mtd->priv; | |
309 | struct spi_device *spi = priv->spi; | |
310 | struct spi_transfer x[2] = { { .tx_dma = 0, }, }; | |
311 | struct spi_message msg; | |
312 | unsigned int pageaddr, addr, offset, writelen; | |
313 | size_t remaining = len; | |
314 | u_char *writebuf = (u_char *) buf; | |
315 | int status = -EINVAL; | |
271c5c59 | 316 | uint8_t *command; |
1d6432fe DB |
317 | |
318 | DEBUG(MTD_DEBUG_LEVEL2, "%s: write 0x%x..0x%x\n", | |
319 | spi->dev.bus_id, (unsigned)to, (unsigned)(to + len)); | |
320 | ||
321 | *retlen = 0; | |
322 | ||
323 | /* Sanity checks */ | |
324 | if (!len) | |
325 | return 0; | |
326 | if ((to + len) > mtd->size) | |
327 | return -EINVAL; | |
328 | ||
8275c642 VW |
329 | spi_message_init(&msg); |
330 | ||
1d6432fe DB |
331 | x[0].tx_buf = command = priv->command; |
332 | x[0].len = 4; | |
8275c642 | 333 | spi_message_add_tail(&x[0], &msg); |
1d6432fe DB |
334 | |
335 | pageaddr = ((unsigned)to / priv->page_size); | |
336 | offset = ((unsigned)to % priv->page_size); | |
337 | if (offset + len > priv->page_size) | |
338 | writelen = priv->page_size - offset; | |
339 | else | |
340 | writelen = len; | |
341 | ||
ec9ce52e | 342 | mutex_lock(&priv->lock); |
1d6432fe DB |
343 | while (remaining > 0) { |
344 | DEBUG(MTD_DEBUG_LEVEL3, "write @ %i:%i len=%i\n", | |
345 | pageaddr, offset, writelen); | |
346 | ||
347 | /* REVISIT: | |
348 | * (a) each page in a sector must be rewritten at least | |
349 | * once every 10K sibling erase/program operations. | |
350 | * (b) for pages that are already erased, we could | |
351 | * use WRITE+MWRITE not PROGRAM for ~30% speedup. | |
352 | * (c) WRITE to buffer could be done while waiting for | |
353 | * a previous MWRITE/MWERASE to complete ... | |
354 | * (d) error handling here seems to be mostly missing. | |
355 | * | |
356 | * Two persistent bits per page, plus a per-sector counter, | |
357 | * could support (a) and (b) ... we might consider using | |
358 | * the second half of sector zero, which is just one block, | |
359 | * to track that state. (On AT91, that sector should also | |
360 | * support boot-from-DataFlash.) | |
361 | */ | |
362 | ||
363 | addr = pageaddr << priv->page_offset; | |
364 | ||
365 | /* (1) Maybe transfer partial page to Buffer1 */ | |
366 | if (writelen != priv->page_size) { | |
367 | command[0] = OP_TRANSFER_BUF1; | |
368 | command[1] = (addr & 0x00FF0000) >> 16; | |
369 | command[2] = (addr & 0x0000FF00) >> 8; | |
370 | command[3] = 0; | |
371 | ||
372 | DEBUG(MTD_DEBUG_LEVEL3, "TRANSFER: (%x) %x %x %x\n", | |
373 | command[0], command[1], command[2], command[3]); | |
374 | ||
1d6432fe DB |
375 | status = spi_sync(spi, &msg); |
376 | if (status < 0) | |
377 | DEBUG(MTD_DEBUG_LEVEL1, "%s: xfer %u -> %d \n", | |
378 | spi->dev.bus_id, addr, status); | |
379 | ||
380 | (void) dataflash_waitready(priv->spi); | |
381 | } | |
382 | ||
383 | /* (2) Program full page via Buffer1 */ | |
384 | addr += offset; | |
385 | command[0] = OP_PROGRAM_VIA_BUF1; | |
386 | command[1] = (addr & 0x00FF0000) >> 16; | |
387 | command[2] = (addr & 0x0000FF00) >> 8; | |
388 | command[3] = (addr & 0x000000FF); | |
389 | ||
390 | DEBUG(MTD_DEBUG_LEVEL3, "PROGRAM: (%x) %x %x %x\n", | |
391 | command[0], command[1], command[2], command[3]); | |
392 | ||
393 | x[1].tx_buf = writebuf; | |
394 | x[1].len = writelen; | |
8275c642 | 395 | spi_message_add_tail(x + 1, &msg); |
1d6432fe | 396 | status = spi_sync(spi, &msg); |
8275c642 | 397 | spi_transfer_del(x + 1); |
1d6432fe DB |
398 | if (status < 0) |
399 | DEBUG(MTD_DEBUG_LEVEL1, "%s: pgm %u/%u -> %d \n", | |
400 | spi->dev.bus_id, addr, writelen, status); | |
401 | ||
402 | (void) dataflash_waitready(priv->spi); | |
403 | ||
8275c642 | 404 | |
1d6432fe DB |
405 | #ifdef CONFIG_DATAFLASH_WRITE_VERIFY |
406 | ||
407 | /* (3) Compare to Buffer1 */ | |
408 | addr = pageaddr << priv->page_offset; | |
409 | command[0] = OP_COMPARE_BUF1; | |
410 | command[1] = (addr & 0x00FF0000) >> 16; | |
411 | command[2] = (addr & 0x0000FF00) >> 8; | |
412 | command[3] = 0; | |
413 | ||
414 | DEBUG(MTD_DEBUG_LEVEL3, "COMPARE: (%x) %x %x %x\n", | |
415 | command[0], command[1], command[2], command[3]); | |
416 | ||
1d6432fe DB |
417 | status = spi_sync(spi, &msg); |
418 | if (status < 0) | |
419 | DEBUG(MTD_DEBUG_LEVEL1, "%s: compare %u -> %d \n", | |
420 | spi->dev.bus_id, addr, status); | |
421 | ||
422 | status = dataflash_waitready(priv->spi); | |
423 | ||
424 | /* Check result of the compare operation */ | |
cccb45d4 | 425 | if (status & (1 << 6)) { |
1d6432fe DB |
426 | printk(KERN_ERR "%s: compare page %u, err %d\n", |
427 | spi->dev.bus_id, pageaddr, status); | |
428 | remaining = 0; | |
429 | status = -EIO; | |
430 | break; | |
431 | } else | |
432 | status = 0; | |
433 | ||
434 | #endif /* CONFIG_DATAFLASH_WRITE_VERIFY */ | |
435 | ||
436 | remaining = remaining - writelen; | |
437 | pageaddr++; | |
438 | offset = 0; | |
439 | writebuf += writelen; | |
440 | *retlen += writelen; | |
441 | ||
442 | if (remaining > priv->page_size) | |
443 | writelen = priv->page_size; | |
444 | else | |
445 | writelen = remaining; | |
446 | } | |
ec9ce52e | 447 | mutex_unlock(&priv->lock); |
1d6432fe DB |
448 | |
449 | return status; | |
450 | } | |
451 | ||
452 | /* ......................................................................... */ | |
453 | ||
454 | /* | |
455 | * Register DataFlash device with MTD subsystem. | |
456 | */ | |
457 | static int __devinit | |
458 | add_dataflash(struct spi_device *spi, char *name, | |
459 | int nr_pages, int pagesize, int pageoffset) | |
460 | { | |
461 | struct dataflash *priv; | |
462 | struct mtd_info *device; | |
463 | struct flash_platform_data *pdata = spi->dev.platform_data; | |
464 | ||
5cbded58 | 465 | priv = kzalloc(sizeof *priv, GFP_KERNEL); |
1d6432fe DB |
466 | if (!priv) |
467 | return -ENOMEM; | |
468 | ||
ec9ce52e | 469 | mutex_init(&priv->lock); |
1d6432fe DB |
470 | priv->spi = spi; |
471 | priv->page_size = pagesize; | |
472 | priv->page_offset = pageoffset; | |
473 | ||
474 | /* name must be usable with cmdlinepart */ | |
475 | sprintf(priv->name, "spi%d.%d-%s", | |
476 | spi->master->bus_num, spi->chip_select, | |
477 | name); | |
478 | ||
479 | device = &priv->mtd; | |
480 | device->name = (pdata && pdata->name) ? pdata->name : priv->name; | |
481 | device->size = nr_pages * pagesize; | |
482 | device->erasesize = pagesize; | |
17ffc7ba | 483 | device->writesize = pagesize; |
1d6432fe DB |
484 | device->owner = THIS_MODULE; |
485 | device->type = MTD_DATAFLASH; | |
6c33cafc | 486 | device->flags = MTD_WRITEABLE; |
1d6432fe DB |
487 | device->erase = dataflash_erase; |
488 | device->read = dataflash_read; | |
489 | device->write = dataflash_write; | |
490 | device->priv = priv; | |
491 | ||
771999b6 | 492 | dev_info(&spi->dev, "%s (%d KBytes) pagesize %d bytes\n", |
493 | name, DIV_ROUND_UP(device->size, 1024), pagesize); | |
1d6432fe DB |
494 | dev_set_drvdata(&spi->dev, priv); |
495 | ||
496 | if (mtd_has_partitions()) { | |
497 | struct mtd_partition *parts; | |
498 | int nr_parts = 0; | |
499 | ||
500 | #ifdef CONFIG_MTD_CMDLINE_PARTS | |
501 | static const char *part_probes[] = { "cmdlinepart", NULL, }; | |
502 | ||
503 | nr_parts = parse_mtd_partitions(device, part_probes, &parts, 0); | |
504 | #endif | |
505 | ||
506 | if (nr_parts <= 0 && pdata && pdata->parts) { | |
507 | parts = pdata->parts; | |
508 | nr_parts = pdata->nr_parts; | |
509 | } | |
510 | ||
511 | if (nr_parts > 0) { | |
512 | priv->partitioned = 1; | |
513 | return add_mtd_partitions(device, parts, nr_parts); | |
514 | } | |
7111763d | 515 | } else if (pdata && pdata->nr_parts) |
1d6432fe DB |
516 | dev_warn(&spi->dev, "ignoring %d default partitions on %s\n", |
517 | pdata->nr_parts, device->name); | |
518 | ||
519 | return add_mtd_device(device) == 1 ? -ENODEV : 0; | |
520 | } | |
521 | ||
e9d42227 MH |
522 | struct flash_info { |
523 | char *name; | |
524 | ||
771999b6 | 525 | /* JEDEC id has a high byte of zero plus three data bytes: |
526 | * the manufacturer id, then a two byte device id. | |
e9d42227 | 527 | */ |
271c5c59 | 528 | uint32_t jedec_id; |
e9d42227 | 529 | |
771999b6 | 530 | /* The size listed here is what works with OP_ERASE_PAGE. */ |
e9d42227 | 531 | unsigned nr_pages; |
271c5c59 DW |
532 | uint16_t pagesize; |
533 | uint16_t pageoffset; | |
e9d42227 | 534 | |
271c5c59 | 535 | uint16_t flags; |
771999b6 | 536 | #define SUP_POW2PS 0x0002 /* supports 2^N byte pages */ |
537 | #define IS_POW2PS 0x0001 /* uses 2^N byte pages */ | |
e9d42227 MH |
538 | }; |
539 | ||
540 | static struct flash_info __devinitdata dataflash_data [] = { | |
541 | ||
771999b6 | 542 | /* |
543 | * NOTE: chips with SUP_POW2PS (rev D and up) need two entries, | |
544 | * one with IS_POW2PS and the other without. The entry with the | |
545 | * non-2^N byte page size can't name exact chip revisions without | |
546 | * losing backwards compatibility for cmdlinepart. | |
547 | * | |
548 | * These newer chips also support 128-byte security registers (with | |
549 | * 64 bytes one-time-programmable) and software write-protection. | |
550 | */ | |
551 | { "AT45DB011B", 0x1f2200, 512, 264, 9, SUP_POW2PS}, | |
e9d42227 MH |
552 | { "at45db011d", 0x1f2200, 512, 256, 8, SUP_POW2PS | IS_POW2PS}, |
553 | ||
771999b6 | 554 | { "AT45DB021B", 0x1f2300, 1024, 264, 9, SUP_POW2PS}, |
e9d42227 MH |
555 | { "at45db021d", 0x1f2300, 1024, 256, 8, SUP_POW2PS | IS_POW2PS}, |
556 | ||
771999b6 | 557 | { "AT45DB041x", 0x1f2400, 2048, 264, 9, SUP_POW2PS}, |
e9d42227 MH |
558 | { "at45db041d", 0x1f2400, 2048, 256, 8, SUP_POW2PS | IS_POW2PS}, |
559 | ||
771999b6 | 560 | { "AT45DB081B", 0x1f2500, 4096, 264, 9, SUP_POW2PS}, |
e9d42227 MH |
561 | { "at45db081d", 0x1f2500, 4096, 256, 8, SUP_POW2PS | IS_POW2PS}, |
562 | ||
771999b6 | 563 | { "AT45DB161x", 0x1f2600, 4096, 528, 10, SUP_POW2PS}, |
e9d42227 MH |
564 | { "at45db161d", 0x1f2600, 4096, 512, 9, SUP_POW2PS | IS_POW2PS}, |
565 | ||
771999b6 | 566 | { "AT45DB321x", 0x1f2700, 8192, 528, 10, 0}, /* rev C */ |
e9d42227 | 567 | |
771999b6 | 568 | { "AT45DB321x", 0x1f2701, 8192, 528, 10, SUP_POW2PS}, |
e9d42227 MH |
569 | { "at45db321d", 0x1f2701, 8192, 512, 9, SUP_POW2PS | IS_POW2PS}, |
570 | ||
771999b6 | 571 | { "AT45DB642x", 0x1f2800, 8192, 1056, 11, SUP_POW2PS}, |
572 | { "at45db642d", 0x1f2800, 8192, 1024, 10, SUP_POW2PS | IS_POW2PS}, | |
e9d42227 MH |
573 | }; |
574 | ||
575 | static struct flash_info *__devinit jedec_probe(struct spi_device *spi) | |
576 | { | |
577 | int tmp; | |
271c5c59 DW |
578 | uint8_t code = OP_READ_ID; |
579 | uint8_t id[3]; | |
580 | uint32_t jedec; | |
e9d42227 MH |
581 | struct flash_info *info; |
582 | int status; | |
583 | ||
e9d42227 MH |
584 | /* JEDEC also defines an optional "extended device information" |
585 | * string for after vendor-specific data, after the three bytes | |
586 | * we use here. Supporting some chips might require using it. | |
771999b6 | 587 | * |
588 | * If the vendor ID isn't Atmel's (0x1f), assume this call failed. | |
589 | * That's not an error; only rev C and newer chips handle it, and | |
590 | * only Atmel sells these chips. | |
e9d42227 MH |
591 | */ |
592 | tmp = spi_write_then_read(spi, &code, 1, id, 3); | |
593 | if (tmp < 0) { | |
594 | DEBUG(MTD_DEBUG_LEVEL0, "%s: error %d reading JEDEC ID\n", | |
595 | spi->dev.bus_id, tmp); | |
771999b6 | 596 | return ERR_PTR(tmp); |
e9d42227 | 597 | } |
771999b6 | 598 | if (id[0] != 0x1f) |
599 | return NULL; | |
600 | ||
e9d42227 MH |
601 | jedec = id[0]; |
602 | jedec = jedec << 8; | |
603 | jedec |= id[1]; | |
604 | jedec = jedec << 8; | |
605 | jedec |= id[2]; | |
606 | ||
607 | for (tmp = 0, info = dataflash_data; | |
608 | tmp < ARRAY_SIZE(dataflash_data); | |
609 | tmp++, info++) { | |
610 | if (info->jedec_id == jedec) { | |
771999b6 | 611 | DEBUG(MTD_DEBUG_LEVEL1, "%s: OTP, sector protect%s\n", |
612 | dev_name(&spi->dev), | |
613 | (info->flags & SUP_POW2PS) | |
614 | ? ", binary pagesize" : "" | |
615 | ); | |
e9d42227 MH |
616 | if (info->flags & SUP_POW2PS) { |
617 | status = dataflash_status(spi); | |
771999b6 | 618 | if (status < 0) { |
619 | DEBUG(MTD_DEBUG_LEVEL1, | |
620 | "%s: status error %d\n", | |
621 | dev_name(&spi->dev), status); | |
622 | return ERR_PTR(status); | |
623 | } | |
624 | if (status & 0x1) { | |
625 | if (info->flags & IS_POW2PS) | |
626 | return info; | |
627 | } else { | |
628 | if (!(info->flags & IS_POW2PS)) | |
629 | return info; | |
630 | } | |
e9d42227 MH |
631 | } |
632 | } | |
633 | } | |
771999b6 | 634 | |
635 | /* | |
636 | * Treat other chips as errors ... we won't know the right page | |
637 | * size (it might be binary) even when we can tell which density | |
638 | * class is involved (legacy chip id scheme). | |
639 | */ | |
640 | dev_warn(&spi->dev, "JEDEC id %06x not handled\n", jedec); | |
641 | return ERR_PTR(-ENODEV); | |
e9d42227 MH |
642 | } |
643 | ||
771999b6 | 644 | /* |
645 | * Detect and initialize DataFlash device, using JEDEC IDs on newer chips | |
646 | * or else the ID code embedded in the status bits: | |
647 | * | |
648 | * Device Density ID code #Pages PageSize Offset | |
649 | * AT45DB011B 1Mbit (128K) xx0011xx (0x0c) 512 264 9 | |
650 | * AT45DB021B 2Mbit (256K) xx0101xx (0x14) 1024 264 9 | |
651 | * AT45DB041B 4Mbit (512K) xx0111xx (0x1c) 2048 264 9 | |
652 | * AT45DB081B 8Mbit (1M) xx1001xx (0x24) 4096 264 9 | |
653 | * AT45DB0161B 16Mbit (2M) xx1011xx (0x2c) 4096 528 10 | |
654 | * AT45DB0321B 32Mbit (4M) xx1101xx (0x34) 8192 528 10 | |
655 | * AT45DB0642 64Mbit (8M) xx111xxx (0x3c) 8192 1056 11 | |
656 | * AT45DB1282 128Mbit (16M) xx0100xx (0x10) 16384 1056 11 | |
657 | */ | |
1d6432fe DB |
658 | static int __devinit dataflash_probe(struct spi_device *spi) |
659 | { | |
660 | int status; | |
e9d42227 MH |
661 | struct flash_info *info; |
662 | ||
663 | /* | |
664 | * Try to detect dataflash by JEDEC ID. | |
665 | * If it succeeds we know we have either a C or D part. | |
666 | * D will support power of 2 pagesize option. | |
667 | */ | |
e9d42227 | 668 | info = jedec_probe(spi); |
771999b6 | 669 | if (IS_ERR(info)) |
670 | return PTR_ERR(info); | |
e9d42227 MH |
671 | if (info != NULL) |
672 | return add_dataflash(spi, info->name, info->nr_pages, | |
673 | info->pagesize, info->pageoffset); | |
674 | ||
771999b6 | 675 | /* |
676 | * Older chips support only legacy commands, identifing | |
677 | * capacity using bits in the status byte. | |
678 | */ | |
1d6432fe DB |
679 | status = dataflash_status(spi); |
680 | if (status <= 0 || status == 0xff) { | |
681 | DEBUG(MTD_DEBUG_LEVEL1, "%s: status error %d\n", | |
682 | spi->dev.bus_id, status); | |
de4fa992 | 683 | if (status == 0 || status == 0xff) |
1d6432fe DB |
684 | status = -ENODEV; |
685 | return status; | |
686 | } | |
687 | ||
688 | /* if there's a device there, assume it's dataflash. | |
689 | * board setup should have set spi->max_speed_max to | |
690 | * match f(car) for continuous reads, mode 0 or 3. | |
691 | */ | |
692 | switch (status & 0x3c) { | |
693 | case 0x0c: /* 0 0 1 1 x x */ | |
694 | status = add_dataflash(spi, "AT45DB011B", 512, 264, 9); | |
695 | break; | |
696 | case 0x14: /* 0 1 0 1 x x */ | |
e9d42227 | 697 | status = add_dataflash(spi, "AT45DB021B", 1024, 264, 9); |
1d6432fe DB |
698 | break; |
699 | case 0x1c: /* 0 1 1 1 x x */ | |
771999b6 | 700 | status = add_dataflash(spi, "AT45DB041x", 2048, 264, 9); |
1d6432fe DB |
701 | break; |
702 | case 0x24: /* 1 0 0 1 x x */ | |
703 | status = add_dataflash(spi, "AT45DB081B", 4096, 264, 9); | |
704 | break; | |
705 | case 0x2c: /* 1 0 1 1 x x */ | |
771999b6 | 706 | status = add_dataflash(spi, "AT45DB161x", 4096, 528, 10); |
1d6432fe DB |
707 | break; |
708 | case 0x34: /* 1 1 0 1 x x */ | |
709 | status = add_dataflash(spi, "AT45DB321x", 8192, 528, 10); | |
710 | break; | |
711 | case 0x38: /* 1 1 1 x x x */ | |
712 | case 0x3c: | |
713 | status = add_dataflash(spi, "AT45DB642x", 8192, 1056, 11); | |
714 | break; | |
715 | /* obsolete AT45DB1282 not (yet?) supported */ | |
716 | default: | |
717 | DEBUG(MTD_DEBUG_LEVEL1, "%s: unsupported device (%x)\n", | |
718 | spi->dev.bus_id, status & 0x3c); | |
719 | status = -ENODEV; | |
720 | } | |
721 | ||
722 | if (status < 0) | |
723 | DEBUG(MTD_DEBUG_LEVEL1, "%s: add_dataflash --> %d\n", | |
724 | spi->dev.bus_id, status); | |
725 | ||
726 | return status; | |
727 | } | |
728 | ||
729 | static int __devexit dataflash_remove(struct spi_device *spi) | |
730 | { | |
731 | struct dataflash *flash = dev_get_drvdata(&spi->dev); | |
732 | int status; | |
733 | ||
734 | DEBUG(MTD_DEBUG_LEVEL1, "%s: remove\n", spi->dev.bus_id); | |
735 | ||
736 | if (mtd_has_partitions() && flash->partitioned) | |
737 | status = del_mtd_partitions(&flash->mtd); | |
738 | else | |
739 | status = del_mtd_device(&flash->mtd); | |
740 | if (status == 0) | |
741 | kfree(flash); | |
742 | return status; | |
743 | } | |
744 | ||
745 | static struct spi_driver dataflash_driver = { | |
746 | .driver = { | |
747 | .name = "mtd_dataflash", | |
748 | .bus = &spi_bus_type, | |
749 | .owner = THIS_MODULE, | |
750 | }, | |
751 | ||
752 | .probe = dataflash_probe, | |
753 | .remove = __devexit_p(dataflash_remove), | |
754 | ||
755 | /* FIXME: investigate suspend and resume... */ | |
756 | }; | |
757 | ||
758 | static int __init dataflash_init(void) | |
759 | { | |
760 | return spi_register_driver(&dataflash_driver); | |
761 | } | |
762 | module_init(dataflash_init); | |
763 | ||
764 | static void __exit dataflash_exit(void) | |
765 | { | |
766 | spi_unregister_driver(&dataflash_driver); | |
767 | } | |
768 | module_exit(dataflash_exit); | |
769 | ||
770 | ||
771 | MODULE_LICENSE("GPL"); | |
772 | MODULE_AUTHOR("Andrew Victor, David Brownell"); | |
773 | MODULE_DESCRIPTION("MTD DataFlash driver"); |