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[MTD] we don't need no misc devices
[deliverable/linux.git] / drivers / mtd / devices / mtd_dataflash.c
CommitLineData
1d6432fe
DB		 1/*
2 * Atmel AT45xxx DataFlash MTD driver for lightweight SPI framework
3 *
4 * Largely derived from at91_dataflash.c:
5 * Copyright (C) 2003-2005 SAN People (Pty) Ltd
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11*/
1d6432fe
DB		 12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/slab.h>
15#include <linux/delay.h>
16#include <linux/device.h>
ec9ce52e 17#include <linux/mutex.h>
771999b6 18#include <linux/err.h>
5b7f3a50 19#include <linux/math64.h>
771999b6 20
1d6432fe
DB		 21#include <linux/spi/spi.h>
22#include <linux/spi/flash.h>
23
24#include <linux/mtd/mtd.h>
25#include <linux/mtd/partitions.h>
26
27
28/*
29 * DataFlash is a kind of SPI flash. Most AT45 chips have two buffers in
30 * each chip, which may be used for double buffered I/O; but this driver
31 * doesn't (yet) use these for any kind of i/o overlap or prefetching.
32 *
33 * Sometimes DataFlash is packaged in MMC-format cards, although the
8c64038e 34 * MMC stack can't (yet?) distinguish between MMC and DataFlash
1d6432fe
DB		 35 * protocols during enumeration.
36 */
37
1d6432fe
DB		 38/* reads can bypass the buffers */
39#define OP_READ_CONTINUOUS 0xE8
40#define OP_READ_PAGE 0xD2
41
42/* group B requests can run even while status reports "busy" */
43#define OP_READ_STATUS 0xD7 /* group B */
44
45/* move data between host and buffer */
46#define OP_READ_BUFFER1 0xD4 /* group B */
47#define OP_READ_BUFFER2 0xD6 /* group B */
48#define OP_WRITE_BUFFER1 0x84 /* group B */
49#define OP_WRITE_BUFFER2 0x87 /* group B */
50
51/* erasing flash */
52#define OP_ERASE_PAGE 0x81
53#define OP_ERASE_BLOCK 0x50
54
55/* move data between buffer and flash */
56#define OP_TRANSFER_BUF1 0x53
57#define OP_TRANSFER_BUF2 0x55
58#define OP_MREAD_BUFFER1 0xD4
59#define OP_MREAD_BUFFER2 0xD6
60#define OP_MWERASE_BUFFER1 0x83
61#define OP_MWERASE_BUFFER2 0x86
62#define OP_MWRITE_BUFFER1 0x88 /* sector must be pre-erased */
63#define OP_MWRITE_BUFFER2 0x89 /* sector must be pre-erased */
64
65/* write to buffer, then write-erase to flash */
66#define OP_PROGRAM_VIA_BUF1 0x82
67#define OP_PROGRAM_VIA_BUF2 0x85
68
69/* compare buffer to flash */
70#define OP_COMPARE_BUF1 0x60
71#define OP_COMPARE_BUF2 0x61
72
73/* read flash to buffer, then write-erase to flash */
74#define OP_REWRITE_VIA_BUF1 0x58
75#define OP_REWRITE_VIA_BUF2 0x59
76
77/* newer chips report JEDEC manufacturer and device IDs; chip
78 * serial number and OTP bits; and per-sector writeprotect.
79 */
80#define OP_READ_ID 0x9F
81#define OP_READ_SECURITY 0x77
34a82443
DB		 82#define OP_WRITE_SECURITY_REVC 0x9A
83#define OP_WRITE_SECURITY 0x9B /* revision D */
1d6432fe
DB		 84
85
86struct dataflash {
271c5c59 87 uint8_t command[4];
1d6432fe
DB		 88 char name[24];
89
90 unsigned partitioned:1;
91
92 unsigned short page_offset; /* offset in flash address */
93 unsigned int page_size; /* of bytes per page */
94
ec9ce52e 95 struct mutex lock;
1d6432fe
DB		 96 struct spi_device *spi;
97
98 struct mtd_info mtd;
99};
100
101#ifdef CONFIG_MTD_PARTITIONS
102#define mtd_has_partitions() (1)
103#else
104#define mtd_has_partitions() (0)
105#endif
106
107/* ......................................................................... */
108
109/*
110 * Return the status of the DataFlash device.
111 */
112static inline int dataflash_status(struct spi_device *spi)
113{
114 /* NOTE: at45db321c over 25 MHz wants to write
115 * a dummy byte after the opcode...
116 */
117 return spi_w8r8(spi, OP_READ_STATUS);
118}
119
120/*
121 * Poll the DataFlash device until it is READY.
122 * This usually takes 5-20 msec or so; more for sector erase.
123 */
124static int dataflash_waitready(struct spi_device *spi)
125{
126 int status;
127
128 for (;;) {
129 status = dataflash_status(spi);
130 if (status < 0) {
131 DEBUG(MTD_DEBUG_LEVEL1, "%s: status %d?\n",
160bbab3 132 dev_name(&spi->dev), status);
1d6432fe
DB		 133 status = 0;
134 }
135
136 if (status & (1 << 7)) /* RDY/nBSY */
137 return status;
138
139 msleep(3);
140 }
141}
142
143/* ......................................................................... */
144
145/*
146 * Erase pages of flash.
147 */
148static int dataflash_erase(struct mtd_info *mtd, struct erase_info *instr)
149{
150 struct dataflash *priv = (struct dataflash *)mtd->priv;
151 struct spi_device *spi = priv->spi;
8275c642 152 struct spi_transfer x = { .tx_dma = 0, };
1d6432fe
DB		 153 struct spi_message msg;
154 unsigned blocksize = priv->page_size << 3;
271c5c59 155 uint8_t *command;
5b7f3a50 156 uint32_t rem;
1d6432fe 157
5b7f3a50 158 DEBUG(MTD_DEBUG_LEVEL2, "%s: erase addr=0x%llx len 0x%llx\n",
160bbab3
KS		 159 dev_name(&spi->dev), (long long)instr->addr,
160 (long long)instr->len);
1d6432fe
DB		 161
162 /* Sanity checks */
5b7f3a50
AB		 163 if (instr->addr + instr->len > mtd->size)
164 return -EINVAL;
165 div_u64_rem(instr->len, priv->page_size, &rem);
166 if (rem)
167 return -EINVAL;
168 div_u64_rem(instr->addr, priv->page_size, &rem);
169 if (rem)
1d6432fe
DB		 170 return -EINVAL;
171
8275c642
VW		 172 spi_message_init(&msg);
173
174 x.tx_buf = command = priv->command;
175 x.len = 4;
176 spi_message_add_tail(&x, &msg);
1d6432fe 177
ec9ce52e 178 mutex_lock(&priv->lock);
1d6432fe
DB		 179 while (instr->len > 0) {
180 unsigned int pageaddr;
181 int status;
182 int do_block;
183
184 /* Calculate flash page address; use block erase (for speed) if
185 * we're at a block boundary and need to erase the whole block.
186 */
5b7f3a50 187 pageaddr = div_u64(instr->len, priv->page_size);
3cb4f09f 188 do_block = (pageaddr & 0x7) == 0 && instr->len >= blocksize;
1d6432fe
DB		 189 pageaddr = pageaddr << priv->page_offset;
190
191 command[0] = do_block ? OP_ERASE_BLOCK : OP_ERASE_PAGE;
271c5c59
DW		 192 command[1] = (uint8_t)(pageaddr >> 16);
193 command[2] = (uint8_t)(pageaddr >> 8);
1d6432fe
DB		 194 command[3] = 0;
195
196 DEBUG(MTD_DEBUG_LEVEL3, "ERASE %s: (%x) %x %x %x [%i]\n",
197 do_block ? "block" : "page",
198 command[0], command[1], command[2], command[3],
199 pageaddr);
200
201 status = spi_sync(spi, &msg);
202 (void) dataflash_waitready(spi);
203
204 if (status < 0) {
205 printk(KERN_ERR "%s: erase %x, err %d\n",
160bbab3 206 dev_name(&spi->dev), pageaddr, status);
1d6432fe
DB		 207 /* REVISIT: can retry instr->retries times; or
208 * giveup and instr->fail_addr = instr->addr;
209 */
210 continue;
211 }
212
213 if (do_block) {
214 instr->addr += blocksize;
215 instr->len -= blocksize;
216 } else {
217 instr->addr += priv->page_size;
218 instr->len -= priv->page_size;
219 }
220 }
ec9ce52e 221 mutex_unlock(&priv->lock);
1d6432fe
DB		 222
223 /* Inform MTD subsystem that erase is complete */
224 instr->state = MTD_ERASE_DONE;
225 mtd_erase_callback(instr);
226
227 return 0;
228}
229
230/*
231 * Read from the DataFlash device.
232 * from : Start offset in flash device
233 * len : Amount to read
234 * retlen : About of data actually read
235 * buf : Buffer containing the data
236 */
237static int dataflash_read(struct mtd_info *mtd, loff_t from, size_t len,
238 size_t *retlen, u_char *buf)
239{
240 struct dataflash *priv = (struct dataflash *)mtd->priv;
241 struct spi_transfer x[2] = { { .tx_dma = 0, }, };
242 struct spi_message msg;
243 unsigned int addr;
271c5c59 244 uint8_t *command;
1d6432fe
DB		 245 int status;
246
247 DEBUG(MTD_DEBUG_LEVEL2, "%s: read 0x%x..0x%x\n",
160bbab3 248 dev_name(&priv->spi->dev), (unsigned)from, (unsigned)(from + len));
1d6432fe
DB		 249
250 *retlen = 0;
251
252 /* Sanity checks */
253 if (!len)
254 return 0;
255 if (from + len > mtd->size)
256 return -EINVAL;
257
258 /* Calculate flash page/byte address */
259 addr = (((unsigned)from / priv->page_size) << priv->page_offset)
260 + ((unsigned)from % priv->page_size);
261
262 command = priv->command;
263
264 DEBUG(MTD_DEBUG_LEVEL3, "READ: (%x) %x %x %x\n",
265 command[0], command[1], command[2], command[3]);
266
8275c642
VW		 267 spi_message_init(&msg);
268
1d6432fe
DB		 269 x[0].tx_buf = command;
270 x[0].len = 8;
8275c642
VW		 271 spi_message_add_tail(&x[0], &msg);
272
1d6432fe
DB		 273 x[1].rx_buf = buf;
274 x[1].len = len;
8275c642 275 spi_message_add_tail(&x[1], &msg);
1d6432fe 276
ec9ce52e 277 mutex_lock(&priv->lock);
1d6432fe
DB		 278
279 /* Continuous read, max clock = f(car) which may be less than
280 * the peak rate available. Some chips support commands with
281 * fewer "don't care" bytes. Both buffers stay unchanged.
282 */
283 command[0] = OP_READ_CONTINUOUS;
271c5c59
DW		 284 command[1] = (uint8_t)(addr >> 16);
285 command[2] = (uint8_t)(addr >> 8);
286 command[3] = (uint8_t)(addr >> 0);
1d6432fe
DB		 287 /* plus 4 "don't care" bytes */
288
289 status = spi_sync(priv->spi, &msg);
ec9ce52e 290 mutex_unlock(&priv->lock);
1d6432fe
DB		 291
292 if (status >= 0) {
293 *retlen = msg.actual_length - 8;
294 status = 0;
295 } else
296 DEBUG(MTD_DEBUG_LEVEL1, "%s: read %x..%x --> %d\n",
160bbab3 297 dev_name(&priv->spi->dev),
1d6432fe
DB		 298 (unsigned)from, (unsigned)(from + len),
299 status);
300 return status;
301}
302
303/*
304 * Write to the DataFlash device.
305 * to : Start offset in flash device
306 * len : Amount to write
307 * retlen : Amount of data actually written
308 * buf : Buffer containing the data
309 */
310static int dataflash_write(struct mtd_info *mtd, loff_t to, size_t len,
311 size_t * retlen, const u_char * buf)
312{
313 struct dataflash *priv = (struct dataflash *)mtd->priv;
314 struct spi_device *spi = priv->spi;
315 struct spi_transfer x[2] = { { .tx_dma = 0, }, };
316 struct spi_message msg;
317 unsigned int pageaddr, addr, offset, writelen;
318 size_t remaining = len;
319 u_char *writebuf = (u_char *) buf;
320 int status = -EINVAL;
271c5c59 321 uint8_t *command;
1d6432fe
DB		 322
323 DEBUG(MTD_DEBUG_LEVEL2, "%s: write 0x%x..0x%x\n",
160bbab3 324 dev_name(&spi->dev), (unsigned)to, (unsigned)(to + len));
1d6432fe
DB		 325
326 *retlen = 0;
327
328 /* Sanity checks */
329 if (!len)
330 return 0;
331 if ((to + len) > mtd->size)
332 return -EINVAL;
333
8275c642
VW		 334 spi_message_init(&msg);
335
1d6432fe
DB		 336 x[0].tx_buf = command = priv->command;
337 x[0].len = 4;
8275c642 338 spi_message_add_tail(&x[0], &msg);
1d6432fe
DB		 339
340 pageaddr = ((unsigned)to / priv->page_size);
341 offset = ((unsigned)to % priv->page_size);
342 if (offset + len > priv->page_size)
343 writelen = priv->page_size - offset;
344 else
345 writelen = len;
346
ec9ce52e 347 mutex_lock(&priv->lock);
1d6432fe
DB		 348 while (remaining > 0) {
349 DEBUG(MTD_DEBUG_LEVEL3, "write @ %i:%i len=%i\n",
350 pageaddr, offset, writelen);
351
352 /* REVISIT:
353 * (a) each page in a sector must be rewritten at least
354 * once every 10K sibling erase/program operations.
355 * (b) for pages that are already erased, we could
356 * use WRITE+MWRITE not PROGRAM for ~30% speedup.
357 * (c) WRITE to buffer could be done while waiting for
358 * a previous MWRITE/MWERASE to complete ...
359 * (d) error handling here seems to be mostly missing.
360 *
361 * Two persistent bits per page, plus a per-sector counter,
362 * could support (a) and (b) ... we might consider using
363 * the second half of sector zero, which is just one block,
364 * to track that state. (On AT91, that sector should also
365 * support boot-from-DataFlash.)
366 */
367
368 addr = pageaddr << priv->page_offset;
369
370 /* (1) Maybe transfer partial page to Buffer1 */
371 if (writelen != priv->page_size) {
372 command[0] = OP_TRANSFER_BUF1;
373 command[1] = (addr & 0x00FF0000) >> 16;
374 command[2] = (addr & 0x0000FF00) >> 8;
375 command[3] = 0;
376
377 DEBUG(MTD_DEBUG_LEVEL3, "TRANSFER: (%x) %x %x %x\n",
378 command[0], command[1], command[2], command[3]);
379
1d6432fe
DB		 380 status = spi_sync(spi, &msg);
381 if (status < 0)
382 DEBUG(MTD_DEBUG_LEVEL1, "%s: xfer %u -> %d \n",
160bbab3 383 dev_name(&spi->dev), addr, status);
1d6432fe
DB		 384
385 (void) dataflash_waitready(priv->spi);
386 }
387
388 /* (2) Program full page via Buffer1 */
389 addr += offset;
390 command[0] = OP_PROGRAM_VIA_BUF1;
391 command[1] = (addr & 0x00FF0000) >> 16;
392 command[2] = (addr & 0x0000FF00) >> 8;
393 command[3] = (addr & 0x000000FF);
394
395 DEBUG(MTD_DEBUG_LEVEL3, "PROGRAM: (%x) %x %x %x\n",
396 command[0], command[1], command[2], command[3]);
397
398 x[1].tx_buf = writebuf;
399 x[1].len = writelen;
8275c642 400 spi_message_add_tail(x + 1, &msg);
1d6432fe 401 status = spi_sync(spi, &msg);
8275c642 402 spi_transfer_del(x + 1);
1d6432fe
DB		 403 if (status < 0)
404 DEBUG(MTD_DEBUG_LEVEL1, "%s: pgm %u/%u -> %d \n",
160bbab3 405 dev_name(&spi->dev), addr, writelen, status);
1d6432fe
DB		 406
407 (void) dataflash_waitready(priv->spi);
408
8275c642 409
8c64038e 410#ifdef CONFIG_MTD_DATAFLASH_VERIFY_WRITE
1d6432fe
DB		 411
412 /* (3) Compare to Buffer1 */
413 addr = pageaddr << priv->page_offset;
414 command[0] = OP_COMPARE_BUF1;
415 command[1] = (addr & 0x00FF0000) >> 16;
416 command[2] = (addr & 0x0000FF00) >> 8;
417 command[3] = 0;
418
419 DEBUG(MTD_DEBUG_LEVEL3, "COMPARE: (%x) %x %x %x\n",
420 command[0], command[1], command[2], command[3]);
421
1d6432fe
DB		 422 status = spi_sync(spi, &msg);
423 if (status < 0)
424 DEBUG(MTD_DEBUG_LEVEL1, "%s: compare %u -> %d \n",
160bbab3 425 dev_name(&spi->dev), addr, status);
1d6432fe
DB		 426
427 status = dataflash_waitready(priv->spi);
428
429 /* Check result of the compare operation */
cccb45d4 430 if (status & (1 << 6)) {
1d6432fe 431 printk(KERN_ERR "%s: compare page %u, err %d\n",
160bbab3 432 dev_name(&spi->dev), pageaddr, status);
1d6432fe
DB		 433 remaining = 0;
434 status = -EIO;
435 break;
436 } else
437 status = 0;
438
8c64038e 439#endif /* CONFIG_MTD_DATAFLASH_VERIFY_WRITE */
1d6432fe
DB		 440
441 remaining = remaining - writelen;
442 pageaddr++;
443 offset = 0;
444 writebuf += writelen;
445 *retlen += writelen;
446
447 if (remaining > priv->page_size)
448 writelen = priv->page_size;
449 else
450 writelen = remaining;
451 }
ec9ce52e 452 mutex_unlock(&priv->lock);
1d6432fe
DB		 453
454 return status;
455}
456
457/* ......................................................................... */
458
34a82443
DB		 459#ifdef CONFIG_MTD_DATAFLASH_OTP
460
461static int dataflash_get_otp_info(struct mtd_info *mtd,
462 struct otp_info *info, size_t len)
463{
464 /* Report both blocks as identical: bytes 0..64, locked.
465 * Unless the user block changed from all-ones, we can't
466 * tell whether it's still writable; so we assume it isn't.
467 */
468 info->start = 0;
469 info->length = 64;
470 info->locked = 1;
471 return sizeof(*info);
472}
473
474static ssize_t otp_read(struct spi_device *spi, unsigned base,
475 uint8_t *buf, loff_t off, size_t len)
476{
477 struct spi_message m;
478 size_t l;
479 uint8_t *scratch;
480 struct spi_transfer t;
481 int status;
482
483 if (off > 64)
484 return -EINVAL;
485
486 if ((off + len) > 64)
487 len = 64 - off;
488 if (len == 0)
489 return len;
490
491 spi_message_init(&m);
492
493 l = 4 + base + off + len;
494 scratch = kzalloc(l, GFP_KERNEL);
495 if (!scratch)
496 return -ENOMEM;
497
498 /* OUT: OP_READ_SECURITY, 3 don't-care bytes, zeroes
499 * IN: ignore 4 bytes, data bytes 0..N (max 127)
500 */
501 scratch[0] = OP_READ_SECURITY;
502
503 memset(&t, 0, sizeof t);
504 t.tx_buf = scratch;
505 t.rx_buf = scratch;
506 t.len = l;
507 spi_message_add_tail(&t, &m);
508
509 dataflash_waitready(spi);
510
511 status = spi_sync(spi, &m);
512 if (status >= 0) {
513 memcpy(buf, scratch + 4 + base + off, len);
514 status = len;
515 }
516
517 kfree(scratch);
518 return status;
519}
520
521static int dataflash_read_fact_otp(struct mtd_info *mtd,
522 loff_t from, size_t len, size_t *retlen, u_char *buf)
523{
524 struct dataflash *priv = (struct dataflash *)mtd->priv;
525 int status;
526
527 /* 64 bytes, from 0..63 ... start at 64 on-chip */
528 mutex_lock(&priv->lock);
529 status = otp_read(priv->spi, 64, buf, from, len);
530 mutex_unlock(&priv->lock);
531
532 if (status < 0)
533 return status;
534 *retlen = status;
535 return 0;
536}
537
538static int dataflash_read_user_otp(struct mtd_info *mtd,
539 loff_t from, size_t len, size_t *retlen, u_char *buf)
540{
541 struct dataflash *priv = (struct dataflash *)mtd->priv;
542 int status;
543
544 /* 64 bytes, from 0..63 ... start at 0 on-chip */
545 mutex_lock(&priv->lock);
546 status = otp_read(priv->spi, 0, buf, from, len);
547 mutex_unlock(&priv->lock);
548
549 if (status < 0)
550 return status;
551 *retlen = status;
552 return 0;
553}
554
555static int dataflash_write_user_otp(struct mtd_info *mtd,
556 loff_t from, size_t len, size_t *retlen, u_char *buf)
557{
558 struct spi_message m;
559 const size_t l = 4 + 64;
560 uint8_t *scratch;
561 struct spi_transfer t;
562 struct dataflash *priv = (struct dataflash *)mtd->priv;
563 int status;
564
565 if (len > 64)
566 return -EINVAL;
567
568 /* Strictly speaking, we *could* truncate the write ... but
569 * let's not do that for the only write that's ever possible.
570 */
571 if ((from + len) > 64)
572 return -EINVAL;
573
574 /* OUT: OP_WRITE_SECURITY, 3 zeroes, 64 data-or-zero bytes
575 * IN: ignore all
576 */
577 scratch = kzalloc(l, GFP_KERNEL);
578 if (!scratch)
579 return -ENOMEM;
580 scratch[0] = OP_WRITE_SECURITY;
581 memcpy(scratch + 4 + from, buf, len);
582
583 spi_message_init(&m);
584
585 memset(&t, 0, sizeof t);
586 t.tx_buf = scratch;
587 t.len = l;
588 spi_message_add_tail(&t, &m);
589
590 /* Write the OTP bits, if they've not yet been written.
591 * This modifies SRAM buffer1.
592 */
593 mutex_lock(&priv->lock);
594 dataflash_waitready(priv->spi);
595 status = spi_sync(priv->spi, &m);
596 mutex_unlock(&priv->lock);
597
598 kfree(scratch);
599
600 if (status >= 0) {
601 status = 0;
602 *retlen = len;
603 }
604 return status;
605}
606
607static char *otp_setup(struct mtd_info *device, char revision)
608{
609 device->get_fact_prot_info = dataflash_get_otp_info;
610 device->read_fact_prot_reg = dataflash_read_fact_otp;
611 device->get_user_prot_info = dataflash_get_otp_info;
612 device->read_user_prot_reg = dataflash_read_user_otp;
613
614 /* rev c parts (at45db321c and at45db1281 only!) use a
615 * different write procedure; not (yet?) implemented.
616 */
617 if (revision > 'c')
618 device->write_user_prot_reg = dataflash_write_user_otp;
619
620 return ", OTP";
621}
622
623#else
624
cf93ae02 625static char *otp_setup(struct mtd_info *device, char revision)
34a82443
DB		 626{
627 return " (OTP)";
628}
629
630#endif
631
632/* ......................................................................... */
633
1d6432fe
DB		 634/*
635 * Register DataFlash device with MTD subsystem.
636 */
637static int __devinit
34a82443
DB		 638add_dataflash_otp(struct spi_device *spi, char *name,
639 int nr_pages, int pagesize, int pageoffset, char revision)
1d6432fe
DB		 640{
641 struct dataflash *priv;
642 struct mtd_info *device;
643 struct flash_platform_data *pdata = spi->dev.platform_data;
34a82443 644 char *otp_tag = "";
1d6432fe 645
5cbded58 646 priv = kzalloc(sizeof *priv, GFP_KERNEL);
1d6432fe
DB		 647 if (!priv)
648 return -ENOMEM;
649
ec9ce52e 650 mutex_init(&priv->lock);
1d6432fe
DB		 651 priv->spi = spi;
652 priv->page_size = pagesize;
653 priv->page_offset = pageoffset;
654
655 /* name must be usable with cmdlinepart */
656 sprintf(priv->name, "spi%d.%d-%s",
657 spi->master->bus_num, spi->chip_select,
658 name);
659
660 device = &priv->mtd;
661 device->name = (pdata && pdata->name) ? pdata->name : priv->name;
662 device->size = nr_pages * pagesize;
663 device->erasesize = pagesize;
17ffc7ba 664 device->writesize = pagesize;
1d6432fe
DB		 665 device->owner = THIS_MODULE;
666 device->type = MTD_DATAFLASH;
6c33cafc 667 device->flags = MTD_WRITEABLE;
1d6432fe
DB		 668 device->erase = dataflash_erase;
669 device->read = dataflash_read;
670 device->write = dataflash_write;
671 device->priv = priv;
672
34a82443
DB		 673 if (revision >= 'c')
674 otp_tag = otp_setup(device, revision);
675
5b7f3a50
AB		 676 dev_info(&spi->dev, "%s (%lld KBytes) pagesize %d bytes%s\n",
677 name, (long long)((device->size + 1023) >> 10),
34a82443 678 pagesize, otp_tag);
1d6432fe
DB		 679 dev_set_drvdata(&spi->dev, priv);
680
681 if (mtd_has_partitions()) {
682 struct mtd_partition *parts;
683 int nr_parts = 0;
684
685#ifdef CONFIG_MTD_CMDLINE_PARTS
686 static const char *part_probes[] = { "cmdlinepart", NULL, };
687
688 nr_parts = parse_mtd_partitions(device, part_probes, &parts, 0);
689#endif
690
691 if (nr_parts <= 0 && pdata && pdata->parts) {
692 parts = pdata->parts;
693 nr_parts = pdata->nr_parts;
694 }
695
696 if (nr_parts > 0) {
697 priv->partitioned = 1;
698 return add_mtd_partitions(device, parts, nr_parts);
699 }
7111763d 700 } else if (pdata && pdata->nr_parts)
1d6432fe
DB		 701 dev_warn(&spi->dev, "ignoring %d default partitions on %s\n",
702 pdata->nr_parts, device->name);
703
704 return add_mtd_device(device) == 1 ? -ENODEV : 0;
705}
706
34a82443
DB		 707static inline int __devinit
708add_dataflash(struct spi_device *spi, char *name,
709 int nr_pages, int pagesize, int pageoffset)
710{
711 return add_dataflash_otp(spi, name, nr_pages, pagesize,
712 pageoffset, 0);
713}
714
e9d42227
MH		 715struct flash_info {
716 char *name;
717
771999b6 718 /* JEDEC id has a high byte of zero plus three data bytes:
719 * the manufacturer id, then a two byte device id.
e9d42227 720 */
271c5c59 721 uint32_t jedec_id;
e9d42227 722
771999b6 723 /* The size listed here is what works with OP_ERASE_PAGE. */
e9d42227 724 unsigned nr_pages;
271c5c59
DW		 725 uint16_t pagesize;
726 uint16_t pageoffset;
e9d42227 727
271c5c59 728 uint16_t flags;
771999b6 729#define SUP_POW2PS 0x0002 /* supports 2^N byte pages */
730#define IS_POW2PS 0x0001 /* uses 2^N byte pages */
e9d42227
MH		 731};
732
733static struct flash_info __devinitdata dataflash_data [] = {
734
771999b6 735 /*
736 * NOTE: chips with SUP_POW2PS (rev D and up) need two entries,
737 * one with IS_POW2PS and the other without. The entry with the
738 * non-2^N byte page size can't name exact chip revisions without
739 * losing backwards compatibility for cmdlinepart.
740 *
741 * These newer chips also support 128-byte security registers (with
742 * 64 bytes one-time-programmable) and software write-protection.
743 */
744 { "AT45DB011B", 0x1f2200, 512, 264, 9, SUP_POW2PS},
e9d42227
MH		 745 { "at45db011d", 0x1f2200, 512, 256, 8, SUP_POW2PS | IS_POW2PS},
746
771999b6 747 { "AT45DB021B", 0x1f2300, 1024, 264, 9, SUP_POW2PS},
e9d42227
MH		 748 { "at45db021d", 0x1f2300, 1024, 256, 8, SUP_POW2PS | IS_POW2PS},
749
771999b6 750 { "AT45DB041x", 0x1f2400, 2048, 264, 9, SUP_POW2PS},
e9d42227
MH		 751 { "at45db041d", 0x1f2400, 2048, 256, 8, SUP_POW2PS | IS_POW2PS},
752
771999b6 753 { "AT45DB081B", 0x1f2500, 4096, 264, 9, SUP_POW2PS},
e9d42227
MH		 754 { "at45db081d", 0x1f2500, 4096, 256, 8, SUP_POW2PS | IS_POW2PS},
755
771999b6 756 { "AT45DB161x", 0x1f2600, 4096, 528, 10, SUP_POW2PS},
e9d42227
MH		 757 { "at45db161d", 0x1f2600, 4096, 512, 9, SUP_POW2PS | IS_POW2PS},
758
771999b6 759 { "AT45DB321x", 0x1f2700, 8192, 528, 10, 0}, /* rev C */
e9d42227 760
771999b6 761 { "AT45DB321x", 0x1f2701, 8192, 528, 10, SUP_POW2PS},
e9d42227
MH		 762 { "at45db321d", 0x1f2701, 8192, 512, 9, SUP_POW2PS | IS_POW2PS},
763
771999b6 764 { "AT45DB642x", 0x1f2800, 8192, 1056, 11, SUP_POW2PS},
765 { "at45db642d", 0x1f2800, 8192, 1024, 10, SUP_POW2PS | IS_POW2PS},
e9d42227
MH		 766};
767
768static struct flash_info *__devinit jedec_probe(struct spi_device *spi)
769{
770 int tmp;
271c5c59
DW		 771 uint8_t code = OP_READ_ID;
772 uint8_t id[3];
773 uint32_t jedec;
e9d42227
MH		 774 struct flash_info *info;
775 int status;
776
e9d42227
MH		 777 /* JEDEC also defines an optional "extended device information"
778 * string for after vendor-specific data, after the three bytes
779 * we use here. Supporting some chips might require using it.
771999b6 780 *
781 * If the vendor ID isn't Atmel's (0x1f), assume this call failed.
782 * That's not an error; only rev C and newer chips handle it, and
783 * only Atmel sells these chips.
e9d42227
MH		 784 */
785 tmp = spi_write_then_read(spi, &code, 1, id, 3);
786 if (tmp < 0) {
787 DEBUG(MTD_DEBUG_LEVEL0, "%s: error %d reading JEDEC ID\n",
160bbab3 788 dev_name(&spi->dev), tmp);
771999b6 789 return ERR_PTR(tmp);
e9d42227 790 }
771999b6 791 if (id[0] != 0x1f)
792 return NULL;
793
e9d42227
MH		 794 jedec = id[0];
795 jedec = jedec << 8;
796 jedec |= id[1];
797 jedec = jedec << 8;
798 jedec |= id[2];
799
800 for (tmp = 0, info = dataflash_data;
801 tmp < ARRAY_SIZE(dataflash_data);
802 tmp++, info++) {
803 if (info->jedec_id == jedec) {
771999b6 804 DEBUG(MTD_DEBUG_LEVEL1, "%s: OTP, sector protect%s\n",
805 dev_name(&spi->dev),
806 (info->flags & SUP_POW2PS)
807 ? ", binary pagesize" : ""
808 );
e9d42227
MH		 809 if (info->flags & SUP_POW2PS) {
810 status = dataflash_status(spi);
771999b6 811 if (status < 0) {
812 DEBUG(MTD_DEBUG_LEVEL1,
813 "%s: status error %d\n",
814 dev_name(&spi->dev), status);
815 return ERR_PTR(status);
816 }
817 if (status & 0x1) {
818 if (info->flags & IS_POW2PS)
819 return info;
820 } else {
821 if (!(info->flags & IS_POW2PS))
822 return info;
823 }
229cc58b
WN		 824 } else
825 return info;
e9d42227
MH		 826 }
827 }
771999b6 828
829 /*
830 * Treat other chips as errors ... we won't know the right page
831 * size (it might be binary) even when we can tell which density
832 * class is involved (legacy chip id scheme).
833 */
834 dev_warn(&spi->dev, "JEDEC id %06x not handled\n", jedec);
835 return ERR_PTR(-ENODEV);
e9d42227
MH		 836}
837
771999b6 838/*
839 * Detect and initialize DataFlash device, using JEDEC IDs on newer chips
840 * or else the ID code embedded in the status bits:
841 *
842 * Device Density ID code #Pages PageSize Offset
843 * AT45DB011B 1Mbit (128K) xx0011xx (0x0c) 512 264 9
844 * AT45DB021B 2Mbit (256K) xx0101xx (0x14) 1024 264 9
845 * AT45DB041B 4Mbit (512K) xx0111xx (0x1c) 2048 264 9
846 * AT45DB081B 8Mbit (1M) xx1001xx (0x24) 4096 264 9
847 * AT45DB0161B 16Mbit (2M) xx1011xx (0x2c) 4096 528 10
848 * AT45DB0321B 32Mbit (4M) xx1101xx (0x34) 8192 528 10
849 * AT45DB0642 64Mbit (8M) xx111xxx (0x3c) 8192 1056 11
850 * AT45DB1282 128Mbit (16M) xx0100xx (0x10) 16384 1056 11
851 */
1d6432fe
DB		 852static int __devinit dataflash_probe(struct spi_device *spi)
853{
854 int status;
e9d42227
MH		 855 struct flash_info *info;
856
857 /*
858 * Try to detect dataflash by JEDEC ID.
859 * If it succeeds we know we have either a C or D part.
860 * D will support power of 2 pagesize option.
34a82443
DB		 861 * Both support the security register, though with different
862 * write procedures.
e9d42227 863 */
e9d42227 864 info = jedec_probe(spi);
771999b6 865 if (IS_ERR(info))
866 return PTR_ERR(info);
e9d42227 867 if (info != NULL)
34a82443
DB		 868 return add_dataflash_otp(spi, info->name, info->nr_pages,
869 info->pagesize, info->pageoffset,
870 (info->flags & SUP_POW2PS) ? 'd' : 'c');
e9d42227 871
771999b6 872 /*
873 * Older chips support only legacy commands, identifing
874 * capacity using bits in the status byte.
875 */
1d6432fe
DB		 876 status = dataflash_status(spi);
877 if (status <= 0 || status == 0xff) {
878 DEBUG(MTD_DEBUG_LEVEL1, "%s: status error %d\n",
160bbab3 879 dev_name(&spi->dev), status);
de4fa992 880 if (status == 0 || status == 0xff)
1d6432fe
DB		 881 status = -ENODEV;
882 return status;
883 }
884
885 /* if there's a device there, assume it's dataflash.
886 * board setup should have set spi->max_speed_max to
887 * match f(car) for continuous reads, mode 0 or 3.
888 */
889 switch (status & 0x3c) {
890 case 0x0c: /* 0 0 1 1 x x */
891 status = add_dataflash(spi, "AT45DB011B", 512, 264, 9);
892 break;
893 case 0x14: /* 0 1 0 1 x x */
e9d42227 894 status = add_dataflash(spi, "AT45DB021B", 1024, 264, 9);
1d6432fe
DB		 895 break;
896 case 0x1c: /* 0 1 1 1 x x */
771999b6 897 status = add_dataflash(spi, "AT45DB041x", 2048, 264, 9);
1d6432fe
DB		 898 break;
899 case 0x24: /* 1 0 0 1 x x */
900 status = add_dataflash(spi, "AT45DB081B", 4096, 264, 9);
901 break;
902 case 0x2c: /* 1 0 1 1 x x */
771999b6 903 status = add_dataflash(spi, "AT45DB161x", 4096, 528, 10);
1d6432fe
DB		 904 break;
905 case 0x34: /* 1 1 0 1 x x */
906 status = add_dataflash(spi, "AT45DB321x", 8192, 528, 10);
907 break;
908 case 0x38: /* 1 1 1 x x x */
909 case 0x3c:
910 status = add_dataflash(spi, "AT45DB642x", 8192, 1056, 11);
911 break;
912 /* obsolete AT45DB1282 not (yet?) supported */
913 default:
914 DEBUG(MTD_DEBUG_LEVEL1, "%s: unsupported device (%x)\n",
160bbab3 915 dev_name(&spi->dev), status & 0x3c);
1d6432fe
DB		 916 status = -ENODEV;
917 }
918
919 if (status < 0)
920 DEBUG(MTD_DEBUG_LEVEL1, "%s: add_dataflash --> %d\n",
160bbab3 921 dev_name(&spi->dev), status);
1d6432fe
DB		 922
923 return status;
924}
925
926static int __devexit dataflash_remove(struct spi_device *spi)
927{
928 struct dataflash *flash = dev_get_drvdata(&spi->dev);
929 int status;
930
160bbab3 931 DEBUG(MTD_DEBUG_LEVEL1, "%s: remove\n", dev_name(&spi->dev));
1d6432fe
DB		 932
933 if (mtd_has_partitions() && flash->partitioned)
934 status = del_mtd_partitions(&flash->mtd);
935 else
936 status = del_mtd_device(&flash->mtd);
937 if (status == 0)
938 kfree(flash);
939 return status;
940}
941
942static struct spi_driver dataflash_driver = {
943 .driver = {
944 .name = "mtd_dataflash",
945 .bus = &spi_bus_type,
946 .owner = THIS_MODULE,
947 },
948
949 .probe = dataflash_probe,
950 .remove = __devexit_p(dataflash_remove),
951
952 /* FIXME: investigate suspend and resume... */
953};
954
955static int __init dataflash_init(void)
956{
957 return spi_register_driver(&dataflash_driver);
958}
959module_init(dataflash_init);
960
961static void __exit dataflash_exit(void)
962{
963 spi_unregister_driver(&dataflash_driver);
964}
965module_exit(dataflash_exit);
966
967
968MODULE_LICENSE("GPL");
969MODULE_AUTHOR("Andrew Victor, David Brownell");
970MODULE_DESCRIPTION("MTD DataFlash driver");
Linux kernel - Deliverables
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