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f18dbbb1 SH |
1 | /* |
2 | * SMI (Serial Memory Controller) device driver for Serial NOR Flash on | |
3 | * SPEAr platform | |
4 | * The serial nor interface is largely based on drivers/mtd/m25p80.c, | |
5 | * however the SPI interface has been replaced by SMI. | |
6 | * | |
7 | * Copyright © 2010 STMicroelectronics. | |
8 | * Ashish Priyadarshi | |
9 | * Shiraz Hashim <shiraz.hashim@st.com> | |
10 | * | |
11 | * This file is licensed under the terms of the GNU General Public | |
12 | * License version 2. This program is licensed "as is" without any | |
13 | * warranty of any kind, whether express or implied. | |
14 | */ | |
15 | ||
16 | #include <linux/clk.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/device.h> | |
19 | #include <linux/err.h> | |
20 | #include <linux/errno.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/io.h> | |
23 | #include <linux/ioport.h> | |
24 | #include <linux/jiffies.h> | |
25 | #include <linux/kernel.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/param.h> | |
28 | #include <linux/platform_device.h> | |
29 | #include <linux/mtd/mtd.h> | |
30 | #include <linux/mtd/partitions.h> | |
31 | #include <linux/mtd/spear_smi.h> | |
32 | #include <linux/mutex.h> | |
33 | #include <linux/sched.h> | |
34 | #include <linux/slab.h> | |
35 | #include <linux/wait.h> | |
36 | ||
37 | /* max possible slots for serial-nor flash chip in the SMI controller */ | |
38 | #define MAX_NUM_FLASH_CHIP 4 | |
39 | ||
40 | /* SMI clock rate */ | |
41 | #define SMI_MAX_CLOCK_FREQ 50000000 /* 50 MHz */ | |
42 | ||
43 | /* MAX time out to safely come out of a erase or write busy conditions */ | |
44 | #define SMI_PROBE_TIMEOUT (HZ / 10) | |
45 | #define SMI_MAX_TIME_OUT (3 * HZ) | |
46 | ||
47 | /* timeout for command completion */ | |
48 | #define SMI_CMD_TIMEOUT (HZ / 10) | |
49 | ||
50 | /* registers of smi */ | |
51 | #define SMI_CR1 0x0 /* SMI control register 1 */ | |
52 | #define SMI_CR2 0x4 /* SMI control register 2 */ | |
53 | #define SMI_SR 0x8 /* SMI status register */ | |
54 | #define SMI_TR 0xC /* SMI transmit register */ | |
55 | #define SMI_RR 0x10 /* SMI receive register */ | |
56 | ||
57 | /* defines for control_reg 1 */ | |
58 | #define BANK_EN (0xF << 0) /* enables all banks */ | |
59 | #define DSEL_TIME (0x6 << 4) /* Deselect time 6 + 1 SMI_CK periods */ | |
60 | #define SW_MODE (0x1 << 28) /* enables SW Mode */ | |
61 | #define WB_MODE (0x1 << 29) /* Write Burst Mode */ | |
62 | #define FAST_MODE (0x1 << 15) /* Fast Mode */ | |
63 | #define HOLD1 (0x1 << 16) /* Clock Hold period selection */ | |
64 | ||
65 | /* defines for control_reg 2 */ | |
66 | #define SEND (0x1 << 7) /* Send data */ | |
67 | #define TFIE (0x1 << 8) /* Transmission Flag Interrupt Enable */ | |
68 | #define WCIE (0x1 << 9) /* Write Complete Interrupt Enable */ | |
69 | #define RD_STATUS_REG (0x1 << 10) /* reads status reg */ | |
70 | #define WE (0x1 << 11) /* Write Enable */ | |
71 | ||
72 | #define TX_LEN_SHIFT 0 | |
73 | #define RX_LEN_SHIFT 4 | |
74 | #define BANK_SHIFT 12 | |
75 | ||
76 | /* defines for status register */ | |
77 | #define SR_WIP 0x1 /* Write in progress */ | |
78 | #define SR_WEL 0x2 /* Write enable latch */ | |
79 | #define SR_BP0 0x4 /* Block protect 0 */ | |
80 | #define SR_BP1 0x8 /* Block protect 1 */ | |
81 | #define SR_BP2 0x10 /* Block protect 2 */ | |
82 | #define SR_SRWD 0x80 /* SR write protect */ | |
83 | #define TFF 0x100 /* Transfer Finished Flag */ | |
84 | #define WCF 0x200 /* Transfer Finished Flag */ | |
85 | #define ERF1 0x400 /* Forbidden Write Request */ | |
86 | #define ERF2 0x800 /* Forbidden Access */ | |
87 | ||
88 | #define WM_SHIFT 12 | |
89 | ||
90 | /* flash opcodes */ | |
91 | #define OPCODE_RDID 0x9f /* Read JEDEC ID */ | |
92 | ||
93 | /* Flash Device Ids maintenance section */ | |
94 | ||
95 | /* data structure to maintain flash ids from different vendors */ | |
96 | struct flash_device { | |
97 | char *name; | |
98 | u8 erase_cmd; | |
99 | u32 device_id; | |
100 | u32 pagesize; | |
101 | unsigned long sectorsize; | |
102 | unsigned long size_in_bytes; | |
103 | }; | |
104 | ||
105 | #define FLASH_ID(n, es, id, psize, ssize, size) \ | |
106 | { \ | |
107 | .name = n, \ | |
108 | .erase_cmd = es, \ | |
109 | .device_id = id, \ | |
110 | .pagesize = psize, \ | |
111 | .sectorsize = ssize, \ | |
112 | .size_in_bytes = size \ | |
113 | } | |
114 | ||
115 | static struct flash_device flash_devices[] = { | |
116 | FLASH_ID("st m25p16" , 0xd8, 0x00152020, 0x100, 0x10000, 0x200000), | |
117 | FLASH_ID("st m25p32" , 0xd8, 0x00162020, 0x100, 0x10000, 0x400000), | |
118 | FLASH_ID("st m25p64" , 0xd8, 0x00172020, 0x100, 0x10000, 0x800000), | |
119 | FLASH_ID("st m25p128" , 0xd8, 0x00182020, 0x100, 0x40000, 0x1000000), | |
120 | FLASH_ID("st m25p05" , 0xd8, 0x00102020, 0x80 , 0x8000 , 0x10000), | |
121 | FLASH_ID("st m25p10" , 0xd8, 0x00112020, 0x80 , 0x8000 , 0x20000), | |
122 | FLASH_ID("st m25p20" , 0xd8, 0x00122020, 0x100, 0x10000, 0x40000), | |
123 | FLASH_ID("st m25p40" , 0xd8, 0x00132020, 0x100, 0x10000, 0x80000), | |
124 | FLASH_ID("st m25p80" , 0xd8, 0x00142020, 0x100, 0x10000, 0x100000), | |
125 | FLASH_ID("st m45pe10" , 0xd8, 0x00114020, 0x100, 0x10000, 0x20000), | |
126 | FLASH_ID("st m45pe20" , 0xd8, 0x00124020, 0x100, 0x10000, 0x40000), | |
127 | FLASH_ID("st m45pe40" , 0xd8, 0x00134020, 0x100, 0x10000, 0x80000), | |
128 | FLASH_ID("st m45pe80" , 0xd8, 0x00144020, 0x100, 0x10000, 0x100000), | |
129 | FLASH_ID("sp s25fl004" , 0xd8, 0x00120201, 0x100, 0x10000, 0x80000), | |
130 | FLASH_ID("sp s25fl008" , 0xd8, 0x00130201, 0x100, 0x10000, 0x100000), | |
131 | FLASH_ID("sp s25fl016" , 0xd8, 0x00140201, 0x100, 0x10000, 0x200000), | |
132 | FLASH_ID("sp s25fl032" , 0xd8, 0x00150201, 0x100, 0x10000, 0x400000), | |
133 | FLASH_ID("sp s25fl064" , 0xd8, 0x00160201, 0x100, 0x10000, 0x800000), | |
134 | FLASH_ID("atmel 25f512" , 0x52, 0x0065001F, 0x80 , 0x8000 , 0x10000), | |
135 | FLASH_ID("atmel 25f1024" , 0x52, 0x0060001F, 0x100, 0x8000 , 0x20000), | |
136 | FLASH_ID("atmel 25f2048" , 0x52, 0x0063001F, 0x100, 0x10000, 0x40000), | |
137 | FLASH_ID("atmel 25f4096" , 0x52, 0x0064001F, 0x100, 0x10000, 0x80000), | |
138 | FLASH_ID("atmel 25fs040" , 0xd7, 0x0004661F, 0x100, 0x10000, 0x80000), | |
139 | FLASH_ID("mac 25l512" , 0xd8, 0x001020C2, 0x010, 0x10000, 0x10000), | |
140 | FLASH_ID("mac 25l1005" , 0xd8, 0x001120C2, 0x010, 0x10000, 0x20000), | |
141 | FLASH_ID("mac 25l2005" , 0xd8, 0x001220C2, 0x010, 0x10000, 0x40000), | |
142 | FLASH_ID("mac 25l4005" , 0xd8, 0x001320C2, 0x010, 0x10000, 0x80000), | |
143 | FLASH_ID("mac 25l4005a" , 0xd8, 0x001320C2, 0x010, 0x10000, 0x80000), | |
144 | FLASH_ID("mac 25l8005" , 0xd8, 0x001420C2, 0x010, 0x10000, 0x100000), | |
145 | FLASH_ID("mac 25l1605" , 0xd8, 0x001520C2, 0x100, 0x10000, 0x200000), | |
146 | FLASH_ID("mac 25l1605a" , 0xd8, 0x001520C2, 0x010, 0x10000, 0x200000), | |
147 | FLASH_ID("mac 25l3205" , 0xd8, 0x001620C2, 0x100, 0x10000, 0x400000), | |
148 | FLASH_ID("mac 25l3205a" , 0xd8, 0x001620C2, 0x100, 0x10000, 0x400000), | |
149 | FLASH_ID("mac 25l6405" , 0xd8, 0x001720C2, 0x100, 0x10000, 0x800000), | |
150 | }; | |
151 | ||
152 | /* These partitions would be used if platform doesn't pass one */ | |
153 | static struct mtd_partition part_info_8M[] = { | |
154 | DEFINE_PARTS("Xloader", 0x00, 0x10000), | |
155 | DEFINE_PARTS("UBoot", MTDPART_OFS_APPEND, 0x40000), | |
156 | DEFINE_PARTS("Kernel", MTDPART_OFS_APPEND, 0x2C0000), | |
157 | DEFINE_PARTS("Root File System", MTDPART_OFS_APPEND, MTDPART_SIZ_FULL), | |
158 | }; | |
159 | ||
160 | static struct mtd_partition part_info_16M[] = { | |
161 | DEFINE_PARTS("Xloader", 0x00, 0x40000), | |
162 | DEFINE_PARTS("UBoot", MTDPART_OFS_APPEND, 0x100000), | |
163 | DEFINE_PARTS("Kernel", MTDPART_OFS_APPEND, 0x300000), | |
164 | DEFINE_PARTS("Root File System", MTDPART_OFS_APPEND, MTDPART_SIZ_FULL), | |
165 | }; | |
166 | ||
167 | /* Define spear specific structures */ | |
168 | ||
169 | struct spear_snor_flash; | |
170 | ||
171 | /** | |
172 | * struct spear_smi - Structure for SMI Device | |
173 | * | |
174 | * @clk: functional clock | |
175 | * @status: current status register of SMI. | |
176 | * @clk_rate: functional clock rate of SMI (default: SMI_MAX_CLOCK_FREQ) | |
177 | * @lock: lock to prevent parallel access of SMI. | |
178 | * @io_base: base address for registers of SMI. | |
179 | * @pdev: platform device | |
180 | * @cmd_complete: queue to wait for command completion of NOR-flash. | |
181 | * @num_flashes: number of flashes actually present on board. | |
182 | * @flash: separate structure for each Serial NOR-flash attached to SMI. | |
183 | */ | |
184 | struct spear_smi { | |
185 | struct clk *clk; | |
186 | u32 status; | |
187 | unsigned long clk_rate; | |
188 | struct mutex lock; | |
189 | void __iomem *io_base; | |
190 | struct platform_device *pdev; | |
191 | wait_queue_head_t cmd_complete; | |
192 | u32 num_flashes; | |
193 | struct spear_snor_flash *flash[MAX_NUM_FLASH_CHIP]; | |
194 | }; | |
195 | ||
196 | /** | |
197 | * struct spear_snor_flash - Structure for Serial NOR Flash | |
198 | * | |
199 | * @bank: Bank number(0, 1, 2, 3) for each NOR-flash. | |
200 | * @dev_id: Device ID of NOR-flash. | |
201 | * @lock: lock to manage flash read, write and erase operations | |
202 | * @mtd: MTD info for each NOR-flash. | |
203 | * @num_parts: Total number of partition in each bank of NOR-flash. | |
204 | * @parts: Partition info for each bank of NOR-flash. | |
205 | * @page_size: Page size of NOR-flash. | |
206 | * @base_addr: Base address of NOR-flash. | |
207 | * @erase_cmd: erase command may vary on different flash types | |
208 | * @fast_mode: flash supports read in fast mode | |
209 | */ | |
210 | struct spear_snor_flash { | |
211 | u32 bank; | |
212 | u32 dev_id; | |
213 | struct mutex lock; | |
214 | struct mtd_info mtd; | |
215 | u32 num_parts; | |
216 | struct mtd_partition *parts; | |
217 | u32 page_size; | |
218 | void __iomem *base_addr; | |
219 | u8 erase_cmd; | |
220 | u8 fast_mode; | |
221 | }; | |
222 | ||
223 | static inline struct spear_snor_flash *get_flash_data(struct mtd_info *mtd) | |
224 | { | |
225 | return container_of(mtd, struct spear_snor_flash, mtd); | |
226 | } | |
227 | ||
228 | /** | |
229 | * spear_smi_read_sr - Read status register of flash through SMI | |
230 | * @dev: structure of SMI information. | |
231 | * @bank: bank to which flash is connected | |
232 | * | |
233 | * This routine will return the status register of the flash chip present at the | |
234 | * given bank. | |
235 | */ | |
236 | static int spear_smi_read_sr(struct spear_smi *dev, u32 bank) | |
237 | { | |
238 | int ret; | |
239 | u32 ctrlreg1; | |
240 | ||
241 | mutex_lock(&dev->lock); | |
242 | dev->status = 0; /* Will be set in interrupt handler */ | |
243 | ||
244 | ctrlreg1 = readl(dev->io_base + SMI_CR1); | |
245 | /* program smi in hw mode */ | |
246 | writel(ctrlreg1 & ~(SW_MODE | WB_MODE), dev->io_base + SMI_CR1); | |
247 | ||
248 | /* performing a rsr instruction in hw mode */ | |
249 | writel((bank << BANK_SHIFT) | RD_STATUS_REG | TFIE, | |
250 | dev->io_base + SMI_CR2); | |
251 | ||
252 | /* wait for tff */ | |
253 | ret = wait_event_interruptible_timeout(dev->cmd_complete, | |
254 | dev->status & TFF, SMI_CMD_TIMEOUT); | |
255 | ||
256 | /* copy dev->status (lower 16 bits) in order to release lock */ | |
257 | if (ret > 0) | |
258 | ret = dev->status & 0xffff; | |
259 | else | |
260 | ret = -EIO; | |
261 | ||
262 | /* restore the ctrl regs state */ | |
263 | writel(ctrlreg1, dev->io_base + SMI_CR1); | |
264 | writel(0, dev->io_base + SMI_CR2); | |
265 | mutex_unlock(&dev->lock); | |
266 | ||
267 | return ret; | |
268 | } | |
269 | ||
270 | /** | |
271 | * spear_smi_wait_till_ready - wait till flash is ready | |
272 | * @dev: structure of SMI information. | |
273 | * @bank: flash corresponding to this bank | |
274 | * @timeout: timeout for busy wait condition | |
275 | * | |
276 | * This routine checks for WIP (write in progress) bit in Status register | |
277 | * If successful the routine returns 0 else -EBUSY | |
278 | */ | |
279 | static int spear_smi_wait_till_ready(struct spear_smi *dev, u32 bank, | |
280 | unsigned long timeout) | |
281 | { | |
282 | unsigned long finish; | |
283 | int status; | |
284 | ||
285 | finish = jiffies + timeout; | |
286 | do { | |
287 | status = spear_smi_read_sr(dev, bank); | |
288 | if (status < 0) | |
289 | continue; /* try till timeout */ | |
290 | else if (!(status & SR_WIP)) | |
291 | return 0; | |
292 | ||
293 | cond_resched(); | |
294 | } while (!time_after_eq(jiffies, finish)); | |
295 | ||
296 | dev_err(&dev->pdev->dev, "smi controller is busy, timeout\n"); | |
297 | return status; | |
298 | } | |
299 | ||
300 | /** | |
301 | * spear_smi_int_handler - SMI Interrupt Handler. | |
302 | * @irq: irq number | |
303 | * @dev_id: structure of SMI device, embedded in dev_id. | |
304 | * | |
305 | * The handler clears all interrupt conditions and records the status in | |
306 | * dev->status which is used by the driver later. | |
307 | */ | |
308 | static irqreturn_t spear_smi_int_handler(int irq, void *dev_id) | |
309 | { | |
310 | u32 status = 0; | |
311 | struct spear_smi *dev = dev_id; | |
312 | ||
313 | status = readl(dev->io_base + SMI_SR); | |
314 | ||
315 | if (unlikely(!status)) | |
316 | return IRQ_NONE; | |
317 | ||
318 | /* clear all interrupt conditions */ | |
319 | writel(0, dev->io_base + SMI_SR); | |
320 | ||
321 | /* copy the status register in dev->status */ | |
322 | dev->status |= status; | |
323 | ||
324 | /* send the completion */ | |
325 | wake_up_interruptible(&dev->cmd_complete); | |
326 | ||
327 | return IRQ_HANDLED; | |
328 | } | |
329 | ||
330 | /** | |
331 | * spear_smi_hw_init - initializes the smi controller. | |
332 | * @dev: structure of smi device | |
333 | * | |
334 | * this routine initializes the smi controller wit the default values | |
335 | */ | |
336 | static void spear_smi_hw_init(struct spear_smi *dev) | |
337 | { | |
338 | unsigned long rate = 0; | |
339 | u32 prescale = 0; | |
340 | u32 val; | |
341 | ||
342 | rate = clk_get_rate(dev->clk); | |
343 | ||
344 | /* functional clock of smi */ | |
345 | prescale = DIV_ROUND_UP(rate, dev->clk_rate); | |
346 | ||
347 | /* | |
348 | * setting the standard values, fast mode, prescaler for | |
349 | * SMI_MAX_CLOCK_FREQ (50MHz) operation and bank enable | |
350 | */ | |
351 | val = HOLD1 | BANK_EN | DSEL_TIME | (prescale << 8); | |
352 | ||
353 | mutex_lock(&dev->lock); | |
354 | writel(val, dev->io_base + SMI_CR1); | |
355 | mutex_unlock(&dev->lock); | |
356 | } | |
357 | ||
358 | /** | |
359 | * get_flash_index - match chip id from a flash list. | |
360 | * @flash_id: a valid nor flash chip id obtained from board. | |
361 | * | |
362 | * try to validate the chip id by matching from a list, if not found then simply | |
363 | * returns negative. In case of success returns index in to the flash devices | |
364 | * array. | |
365 | */ | |
366 | static int get_flash_index(u32 flash_id) | |
367 | { | |
368 | int index; | |
369 | ||
370 | /* Matches chip-id to entire list of 'serial-nor flash' ids */ | |
371 | for (index = 0; index < ARRAY_SIZE(flash_devices); index++) { | |
372 | if (flash_devices[index].device_id == flash_id) | |
373 | return index; | |
374 | } | |
375 | ||
376 | /* Memory chip is not listed and not supported */ | |
377 | return -ENODEV; | |
378 | } | |
379 | ||
380 | /** | |
381 | * spear_smi_write_enable - Enable the flash to do write operation | |
382 | * @dev: structure of SMI device | |
383 | * @bank: enable write for flash connected to this bank | |
384 | * | |
385 | * Set write enable latch with Write Enable command. | |
386 | * Returns 0 on success. | |
387 | */ | |
388 | static int spear_smi_write_enable(struct spear_smi *dev, u32 bank) | |
389 | { | |
390 | int ret; | |
391 | u32 ctrlreg1; | |
392 | ||
393 | mutex_lock(&dev->lock); | |
394 | dev->status = 0; /* Will be set in interrupt handler */ | |
395 | ||
396 | ctrlreg1 = readl(dev->io_base + SMI_CR1); | |
397 | /* program smi in h/w mode */ | |
398 | writel(ctrlreg1 & ~SW_MODE, dev->io_base + SMI_CR1); | |
399 | ||
400 | /* give the flash, write enable command */ | |
401 | writel((bank << BANK_SHIFT) | WE | TFIE, dev->io_base + SMI_CR2); | |
402 | ||
403 | ret = wait_event_interruptible_timeout(dev->cmd_complete, | |
404 | dev->status & TFF, SMI_CMD_TIMEOUT); | |
405 | ||
406 | /* restore the ctrl regs state */ | |
407 | writel(ctrlreg1, dev->io_base + SMI_CR1); | |
408 | writel(0, dev->io_base + SMI_CR2); | |
409 | ||
410 | if (ret <= 0) { | |
411 | ret = -EIO; | |
412 | dev_err(&dev->pdev->dev, | |
413 | "smi controller failed on write enable\n"); | |
414 | } else { | |
415 | /* check whether write mode status is set for required bank */ | |
416 | if (dev->status & (1 << (bank + WM_SHIFT))) | |
417 | ret = 0; | |
418 | else { | |
419 | dev_err(&dev->pdev->dev, "couldn't enable write\n"); | |
420 | ret = -EIO; | |
421 | } | |
422 | } | |
423 | ||
424 | mutex_unlock(&dev->lock); | |
425 | return ret; | |
426 | } | |
427 | ||
428 | static inline u32 | |
429 | get_sector_erase_cmd(struct spear_snor_flash *flash, u32 offset) | |
430 | { | |
431 | u32 cmd; | |
432 | u8 *x = (u8 *)&cmd; | |
433 | ||
434 | x[0] = flash->erase_cmd; | |
435 | x[1] = offset >> 16; | |
436 | x[2] = offset >> 8; | |
437 | x[3] = offset; | |
438 | ||
439 | return cmd; | |
440 | } | |
441 | ||
442 | /** | |
443 | * spear_smi_erase_sector - erase one sector of flash | |
444 | * @dev: structure of SMI information | |
445 | * @command: erase command to be send | |
446 | * @bank: bank to which this command needs to be send | |
447 | * @bytes: size of command | |
448 | * | |
449 | * Erase one sector of flash memory at offset ``offset'' which is any | |
450 | * address within the sector which should be erased. | |
451 | * Returns 0 if successful, non-zero otherwise. | |
452 | */ | |
453 | static int spear_smi_erase_sector(struct spear_smi *dev, | |
454 | u32 bank, u32 command, u32 bytes) | |
455 | { | |
456 | u32 ctrlreg1 = 0; | |
457 | int ret; | |
458 | ||
459 | ret = spear_smi_wait_till_ready(dev, bank, SMI_MAX_TIME_OUT); | |
460 | if (ret) | |
461 | return ret; | |
462 | ||
463 | ret = spear_smi_write_enable(dev, bank); | |
464 | if (ret) | |
465 | return ret; | |
466 | ||
467 | mutex_lock(&dev->lock); | |
468 | ||
469 | ctrlreg1 = readl(dev->io_base + SMI_CR1); | |
470 | writel((ctrlreg1 | SW_MODE) & ~WB_MODE, dev->io_base + SMI_CR1); | |
471 | ||
472 | /* send command in sw mode */ | |
473 | writel(command, dev->io_base + SMI_TR); | |
474 | ||
475 | writel((bank << BANK_SHIFT) | SEND | TFIE | (bytes << TX_LEN_SHIFT), | |
476 | dev->io_base + SMI_CR2); | |
477 | ||
478 | ret = wait_event_interruptible_timeout(dev->cmd_complete, | |
479 | dev->status & TFF, SMI_CMD_TIMEOUT); | |
480 | ||
481 | if (ret <= 0) { | |
482 | ret = -EIO; | |
483 | dev_err(&dev->pdev->dev, "sector erase failed\n"); | |
484 | } else | |
485 | ret = 0; /* success */ | |
486 | ||
487 | /* restore ctrl regs */ | |
488 | writel(ctrlreg1, dev->io_base + SMI_CR1); | |
489 | writel(0, dev->io_base + SMI_CR2); | |
490 | ||
491 | mutex_unlock(&dev->lock); | |
492 | return ret; | |
493 | } | |
494 | ||
495 | /** | |
496 | * spear_mtd_erase - perform flash erase operation as requested by user | |
497 | * @mtd: Provides the memory characteristics | |
498 | * @e_info: Provides the erase information | |
499 | * | |
500 | * Erase an address range on the flash chip. The address range may extend | |
501 | * one or more erase sectors. Return an error is there is a problem erasing. | |
502 | */ | |
503 | static int spear_mtd_erase(struct mtd_info *mtd, struct erase_info *e_info) | |
504 | { | |
505 | struct spear_snor_flash *flash = get_flash_data(mtd); | |
506 | struct spear_smi *dev = mtd->priv; | |
507 | u32 addr, command, bank; | |
508 | int len, ret; | |
509 | ||
510 | if (!flash || !dev) | |
511 | return -ENODEV; | |
512 | ||
f18dbbb1 SH |
513 | bank = flash->bank; |
514 | if (bank > dev->num_flashes - 1) { | |
515 | dev_err(&dev->pdev->dev, "Invalid Bank Num"); | |
516 | return -EINVAL; | |
517 | } | |
518 | ||
519 | addr = e_info->addr; | |
520 | len = e_info->len; | |
521 | ||
522 | mutex_lock(&flash->lock); | |
523 | ||
524 | /* now erase sectors in loop */ | |
525 | while (len) { | |
526 | command = get_sector_erase_cmd(flash, addr); | |
527 | /* preparing the command for flash */ | |
528 | ret = spear_smi_erase_sector(dev, bank, command, 4); | |
529 | if (ret) { | |
530 | e_info->state = MTD_ERASE_FAILED; | |
531 | mutex_unlock(&flash->lock); | |
532 | return ret; | |
533 | } | |
534 | addr += mtd->erasesize; | |
535 | len -= mtd->erasesize; | |
536 | } | |
537 | ||
538 | mutex_unlock(&flash->lock); | |
539 | e_info->state = MTD_ERASE_DONE; | |
540 | mtd_erase_callback(e_info); | |
541 | ||
542 | return 0; | |
543 | } | |
544 | ||
545 | /** | |
546 | * spear_mtd_read - performs flash read operation as requested by the user | |
547 | * @mtd: MTD information of the memory bank | |
548 | * @from: Address from which to start read | |
549 | * @len: Number of bytes to be read | |
550 | * @retlen: Fills the Number of bytes actually read | |
551 | * @buf: Fills this after reading | |
552 | * | |
553 | * Read an address range from the flash chip. The address range | |
554 | * may be any size provided it is within the physical boundaries. | |
555 | * Returns 0 on success, non zero otherwise | |
556 | */ | |
557 | static int spear_mtd_read(struct mtd_info *mtd, loff_t from, size_t len, | |
558 | size_t *retlen, u8 *buf) | |
559 | { | |
560 | struct spear_snor_flash *flash = get_flash_data(mtd); | |
561 | struct spear_smi *dev = mtd->priv; | |
562 | void *src; | |
563 | u32 ctrlreg1, val; | |
564 | int ret; | |
565 | ||
f18dbbb1 SH |
566 | if (!flash || !dev) |
567 | return -ENODEV; | |
568 | ||
f18dbbb1 SH |
569 | if (flash->bank > dev->num_flashes - 1) { |
570 | dev_err(&dev->pdev->dev, "Invalid Bank Num"); | |
571 | return -EINVAL; | |
572 | } | |
573 | ||
f18dbbb1 SH |
574 | /* select address as per bank number */ |
575 | src = flash->base_addr + from; | |
576 | ||
577 | mutex_lock(&flash->lock); | |
578 | ||
579 | /* wait till previous write/erase is done. */ | |
580 | ret = spear_smi_wait_till_ready(dev, flash->bank, SMI_MAX_TIME_OUT); | |
581 | if (ret) { | |
582 | mutex_unlock(&flash->lock); | |
583 | return ret; | |
584 | } | |
585 | ||
586 | mutex_lock(&dev->lock); | |
587 | /* put smi in hw mode not wbt mode */ | |
588 | ctrlreg1 = val = readl(dev->io_base + SMI_CR1); | |
589 | val &= ~(SW_MODE | WB_MODE); | |
590 | if (flash->fast_mode) | |
591 | val |= FAST_MODE; | |
592 | ||
593 | writel(val, dev->io_base + SMI_CR1); | |
594 | ||
595 | memcpy_fromio(buf, (u8 *)src, len); | |
596 | ||
597 | /* restore ctrl reg1 */ | |
598 | writel(ctrlreg1, dev->io_base + SMI_CR1); | |
599 | mutex_unlock(&dev->lock); | |
600 | ||
601 | *retlen = len; | |
602 | mutex_unlock(&flash->lock); | |
603 | ||
604 | return 0; | |
605 | } | |
606 | ||
607 | static inline int spear_smi_cpy_toio(struct spear_smi *dev, u32 bank, | |
608 | void *dest, const void *src, size_t len) | |
609 | { | |
610 | int ret; | |
611 | u32 ctrlreg1; | |
612 | ||
613 | /* wait until finished previous write command. */ | |
614 | ret = spear_smi_wait_till_ready(dev, bank, SMI_MAX_TIME_OUT); | |
615 | if (ret) | |
616 | return ret; | |
617 | ||
618 | /* put smi in write enable */ | |
619 | ret = spear_smi_write_enable(dev, bank); | |
620 | if (ret) | |
621 | return ret; | |
622 | ||
623 | /* put smi in hw, write burst mode */ | |
624 | mutex_lock(&dev->lock); | |
625 | ||
626 | ctrlreg1 = readl(dev->io_base + SMI_CR1); | |
627 | writel((ctrlreg1 | WB_MODE) & ~SW_MODE, dev->io_base + SMI_CR1); | |
628 | ||
629 | memcpy_toio(dest, src, len); | |
630 | ||
631 | writel(ctrlreg1, dev->io_base + SMI_CR1); | |
632 | ||
633 | mutex_unlock(&dev->lock); | |
634 | return 0; | |
635 | } | |
636 | ||
637 | /** | |
638 | * spear_mtd_write - performs write operation as requested by the user. | |
639 | * @mtd: MTD information of the memory bank. | |
640 | * @to: Address to write. | |
641 | * @len: Number of bytes to be written. | |
642 | * @retlen: Number of bytes actually wrote. | |
643 | * @buf: Buffer from which the data to be taken. | |
644 | * | |
645 | * Write an address range to the flash chip. Data must be written in | |
646 | * flash_page_size chunks. The address range may be any size provided | |
647 | * it is within the physical boundaries. | |
648 | * Returns 0 on success, non zero otherwise | |
649 | */ | |
650 | static int spear_mtd_write(struct mtd_info *mtd, loff_t to, size_t len, | |
651 | size_t *retlen, const u8 *buf) | |
652 | { | |
653 | struct spear_snor_flash *flash = get_flash_data(mtd); | |
654 | struct spear_smi *dev = mtd->priv; | |
655 | void *dest; | |
656 | u32 page_offset, page_size; | |
657 | int ret; | |
658 | ||
659 | if (!flash || !dev) | |
660 | return -ENODEV; | |
661 | ||
f18dbbb1 SH |
662 | if (flash->bank > dev->num_flashes - 1) { |
663 | dev_err(&dev->pdev->dev, "Invalid Bank Num"); | |
664 | return -EINVAL; | |
665 | } | |
666 | ||
f18dbbb1 SH |
667 | /* select address as per bank number */ |
668 | dest = flash->base_addr + to; | |
669 | mutex_lock(&flash->lock); | |
670 | ||
671 | page_offset = (u32)to % flash->page_size; | |
672 | ||
673 | /* do if all the bytes fit onto one page */ | |
674 | if (page_offset + len <= flash->page_size) { | |
675 | ret = spear_smi_cpy_toio(dev, flash->bank, dest, buf, len); | |
676 | if (!ret) | |
677 | *retlen += len; | |
678 | } else { | |
679 | u32 i; | |
680 | ||
681 | /* the size of data remaining on the first page */ | |
682 | page_size = flash->page_size - page_offset; | |
683 | ||
684 | ret = spear_smi_cpy_toio(dev, flash->bank, dest, buf, | |
685 | page_size); | |
686 | if (ret) | |
687 | goto err_write; | |
688 | else | |
689 | *retlen += page_size; | |
690 | ||
691 | /* write everything in pagesize chunks */ | |
692 | for (i = page_size; i < len; i += page_size) { | |
693 | page_size = len - i; | |
694 | if (page_size > flash->page_size) | |
695 | page_size = flash->page_size; | |
696 | ||
697 | ret = spear_smi_cpy_toio(dev, flash->bank, dest + i, | |
698 | buf + i, page_size); | |
699 | if (ret) | |
700 | break; | |
701 | else | |
702 | *retlen += page_size; | |
703 | } | |
704 | } | |
705 | ||
706 | err_write: | |
707 | mutex_unlock(&flash->lock); | |
708 | ||
709 | return ret; | |
710 | } | |
711 | ||
712 | /** | |
713 | * spear_smi_probe_flash - Detects the NOR Flash chip. | |
714 | * @dev: structure of SMI information. | |
715 | * @bank: bank on which flash must be probed | |
716 | * | |
717 | * This routine will check whether there exists a flash chip on a given memory | |
718 | * bank ID. | |
719 | * Return index of the probed flash in flash devices structure | |
720 | */ | |
721 | static int spear_smi_probe_flash(struct spear_smi *dev, u32 bank) | |
722 | { | |
723 | int ret; | |
724 | u32 val = 0; | |
725 | ||
726 | ret = spear_smi_wait_till_ready(dev, bank, SMI_PROBE_TIMEOUT); | |
727 | if (ret) | |
728 | return ret; | |
729 | ||
730 | mutex_lock(&dev->lock); | |
731 | ||
732 | dev->status = 0; /* Will be set in interrupt handler */ | |
733 | /* put smi in sw mode */ | |
734 | val = readl(dev->io_base + SMI_CR1); | |
735 | writel(val | SW_MODE, dev->io_base + SMI_CR1); | |
736 | ||
737 | /* send readid command in sw mode */ | |
738 | writel(OPCODE_RDID, dev->io_base + SMI_TR); | |
739 | ||
740 | val = (bank << BANK_SHIFT) | SEND | (1 << TX_LEN_SHIFT) | | |
741 | (3 << RX_LEN_SHIFT) | TFIE; | |
742 | writel(val, dev->io_base + SMI_CR2); | |
743 | ||
744 | /* wait for TFF */ | |
745 | ret = wait_event_interruptible_timeout(dev->cmd_complete, | |
746 | dev->status & TFF, SMI_CMD_TIMEOUT); | |
747 | if (ret <= 0) { | |
748 | ret = -ENODEV; | |
749 | goto err_probe; | |
750 | } | |
751 | ||
752 | /* get memory chip id */ | |
753 | val = readl(dev->io_base + SMI_RR); | |
754 | val &= 0x00ffffff; | |
755 | ret = get_flash_index(val); | |
756 | ||
757 | err_probe: | |
758 | /* clear sw mode */ | |
759 | val = readl(dev->io_base + SMI_CR1); | |
760 | writel(val & ~SW_MODE, dev->io_base + SMI_CR1); | |
761 | ||
762 | mutex_unlock(&dev->lock); | |
763 | return ret; | |
764 | } | |
765 | ||
766 | static int spear_smi_setup_banks(struct platform_device *pdev, u32 bank) | |
767 | { | |
768 | struct spear_smi *dev = platform_get_drvdata(pdev); | |
769 | struct spear_smi_flash_info *flash_info; | |
770 | struct spear_smi_plat_data *pdata; | |
771 | struct spear_snor_flash *flash; | |
772 | struct mtd_partition *parts; | |
773 | int count; | |
774 | int flash_index; | |
775 | int ret = 0; | |
776 | ||
777 | pdata = dev_get_platdata(&pdev->dev); | |
778 | if (bank > pdata->num_flashes - 1) | |
779 | return -EINVAL; | |
780 | ||
781 | flash_info = &pdata->board_flash_info[bank]; | |
782 | if (!flash_info) | |
783 | return -ENODEV; | |
784 | ||
785 | flash = kzalloc(sizeof(*flash), GFP_ATOMIC); | |
786 | if (!flash) | |
787 | return -ENOMEM; | |
788 | flash->bank = bank; | |
789 | flash->fast_mode = flash_info->fast_mode ? 1 : 0; | |
790 | mutex_init(&flash->lock); | |
791 | ||
792 | /* verify whether nor flash is really present on board */ | |
793 | flash_index = spear_smi_probe_flash(dev, bank); | |
794 | if (flash_index < 0) { | |
795 | dev_info(&dev->pdev->dev, "smi-nor%d not found\n", bank); | |
796 | ret = flash_index; | |
797 | goto err_probe; | |
798 | } | |
799 | /* map the memory for nor flash chip */ | |
800 | flash->base_addr = ioremap(flash_info->mem_base, flash_info->size); | |
801 | if (!flash->base_addr) { | |
802 | ret = -EIO; | |
803 | goto err_probe; | |
804 | } | |
805 | ||
806 | dev->flash[bank] = flash; | |
807 | flash->mtd.priv = dev; | |
808 | ||
809 | if (flash_info->name) | |
810 | flash->mtd.name = flash_info->name; | |
811 | else | |
812 | flash->mtd.name = flash_devices[flash_index].name; | |
813 | ||
814 | flash->mtd.type = MTD_NORFLASH; | |
815 | flash->mtd.writesize = 1; | |
816 | flash->mtd.flags = MTD_CAP_NORFLASH; | |
817 | flash->mtd.size = flash_info->size; | |
818 | flash->mtd.erasesize = flash_devices[flash_index].sectorsize; | |
819 | flash->page_size = flash_devices[flash_index].pagesize; | |
81fefdf2 | 820 | flash->mtd.writebufsize = flash->page_size; |
f18dbbb1 | 821 | flash->erase_cmd = flash_devices[flash_index].erase_cmd; |
3c3c10bb AB |
822 | flash->mtd._erase = spear_mtd_erase; |
823 | flash->mtd._read = spear_mtd_read; | |
824 | flash->mtd._write = spear_mtd_write; | |
f18dbbb1 SH |
825 | flash->dev_id = flash_devices[flash_index].device_id; |
826 | ||
827 | dev_info(&dev->pdev->dev, "mtd .name=%s .size=%llx(%lluM)\n", | |
828 | flash->mtd.name, flash->mtd.size, | |
829 | flash->mtd.size / (1024 * 1024)); | |
830 | ||
831 | dev_info(&dev->pdev->dev, ".erasesize = 0x%x(%uK)\n", | |
832 | flash->mtd.erasesize, flash->mtd.erasesize / 1024); | |
833 | ||
834 | if (flash_info->partitions) { | |
835 | parts = flash_info->partitions; | |
836 | count = flash_info->nr_partitions; | |
837 | } else { | |
838 | /* choose from default ones */ | |
839 | switch (flash->mtd.size) { | |
840 | case 0x800000:/* 8MB */ | |
841 | parts = part_info_8M; | |
842 | count = ARRAY_SIZE(part_info_8M); | |
843 | break; | |
844 | case 0x1000000:/* 16MB */ | |
845 | parts = part_info_16M; | |
846 | count = ARRAY_SIZE(part_info_16M); | |
847 | break; | |
848 | default: | |
849 | dev_err(&pdev->dev, "undefined partition\n"); | |
850 | ret = ENODEV; | |
851 | goto err_map; | |
852 | } | |
853 | } | |
42d7fbe2 | 854 | ret = mtd_device_parse_register(&flash->mtd, NULL, NULL, parts, count); |
f18dbbb1 SH |
855 | if (ret) |
856 | dev_err(&dev->pdev->dev, "Err MTD partition=%d\n", ret); | |
857 | ||
858 | return ret; | |
859 | ||
860 | err_map: | |
861 | iounmap(flash->base_addr); | |
862 | ||
863 | err_probe: | |
864 | kfree(flash); | |
865 | return ret; | |
866 | } | |
867 | ||
868 | /** | |
869 | * spear_smi_probe - Entry routine | |
870 | * @pdev: platform device structure | |
871 | * | |
872 | * This is the first routine which gets invoked during booting and does all | |
873 | * initialization/allocation work. The routine looks for available memory banks, | |
874 | * and do proper init for any found one. | |
875 | * Returns 0 on success, non zero otherwise | |
876 | */ | |
877 | static int __devinit spear_smi_probe(struct platform_device *pdev) | |
878 | { | |
879 | struct spear_smi_plat_data *pdata; | |
880 | struct spear_smi *dev; | |
881 | struct resource *smi_base; | |
882 | int irq, ret = 0; | |
883 | int i; | |
884 | ||
885 | pdata = dev_get_platdata(&pdev->dev); | |
886 | if (pdata < 0) { | |
887 | ret = -ENODEV; | |
888 | dev_err(&pdev->dev, "no platform data\n"); | |
889 | goto err; | |
890 | } | |
891 | ||
892 | smi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
893 | if (!smi_base) { | |
894 | ret = -ENODEV; | |
895 | dev_err(&pdev->dev, "invalid smi base address\n"); | |
896 | goto err; | |
897 | } | |
898 | ||
899 | irq = platform_get_irq(pdev, 0); | |
900 | if (irq < 0) { | |
901 | ret = -ENODEV; | |
902 | dev_err(&pdev->dev, "invalid smi irq\n"); | |
903 | goto err; | |
904 | } | |
905 | ||
906 | dev = kzalloc(sizeof(*dev), GFP_ATOMIC); | |
907 | if (!dev) { | |
908 | ret = -ENOMEM; | |
909 | dev_err(&pdev->dev, "mem alloc fail\n"); | |
910 | goto err; | |
911 | } | |
912 | ||
913 | smi_base = request_mem_region(smi_base->start, resource_size(smi_base), | |
914 | pdev->name); | |
915 | if (!smi_base) { | |
916 | ret = -EBUSY; | |
917 | dev_err(&pdev->dev, "request mem region fail\n"); | |
918 | goto err_mem; | |
919 | } | |
920 | ||
921 | dev->io_base = ioremap(smi_base->start, resource_size(smi_base)); | |
922 | if (!dev->io_base) { | |
923 | ret = -EIO; | |
924 | dev_err(&pdev->dev, "ioremap fail\n"); | |
925 | goto err_ioremap; | |
926 | } | |
927 | ||
928 | dev->pdev = pdev; | |
929 | dev->clk_rate = pdata->clk_rate; | |
930 | ||
931 | if (dev->clk_rate < 0 || dev->clk_rate > SMI_MAX_CLOCK_FREQ) | |
932 | dev->clk_rate = SMI_MAX_CLOCK_FREQ; | |
933 | ||
934 | dev->num_flashes = pdata->num_flashes; | |
935 | ||
936 | if (dev->num_flashes > MAX_NUM_FLASH_CHIP) { | |
937 | dev_err(&pdev->dev, "exceeding max number of flashes\n"); | |
938 | dev->num_flashes = MAX_NUM_FLASH_CHIP; | |
939 | } | |
940 | ||
941 | dev->clk = clk_get(&pdev->dev, NULL); | |
942 | if (IS_ERR(dev->clk)) { | |
943 | ret = PTR_ERR(dev->clk); | |
944 | goto err_clk; | |
945 | } | |
946 | ||
947 | ret = clk_enable(dev->clk); | |
948 | if (ret) | |
949 | goto err_clk_enable; | |
950 | ||
951 | ret = request_irq(irq, spear_smi_int_handler, 0, pdev->name, dev); | |
952 | if (ret) { | |
953 | dev_err(&dev->pdev->dev, "SMI IRQ allocation failed\n"); | |
954 | goto err_irq; | |
955 | } | |
956 | ||
957 | mutex_init(&dev->lock); | |
958 | init_waitqueue_head(&dev->cmd_complete); | |
959 | spear_smi_hw_init(dev); | |
960 | platform_set_drvdata(pdev, dev); | |
961 | ||
962 | /* loop for each serial nor-flash which is connected to smi */ | |
963 | for (i = 0; i < dev->num_flashes; i++) { | |
964 | ret = spear_smi_setup_banks(pdev, i); | |
965 | if (ret) { | |
966 | dev_err(&dev->pdev->dev, "bank setup failed\n"); | |
967 | goto err_bank_setup; | |
968 | } | |
969 | } | |
970 | ||
971 | return 0; | |
972 | ||
973 | err_bank_setup: | |
974 | free_irq(irq, dev); | |
975 | platform_set_drvdata(pdev, NULL); | |
976 | err_irq: | |
977 | clk_disable(dev->clk); | |
978 | err_clk_enable: | |
979 | clk_put(dev->clk); | |
980 | err_clk: | |
981 | iounmap(dev->io_base); | |
982 | err_ioremap: | |
983 | release_mem_region(smi_base->start, resource_size(smi_base)); | |
984 | err_mem: | |
985 | kfree(dev); | |
986 | err: | |
987 | return ret; | |
988 | } | |
989 | ||
990 | /** | |
991 | * spear_smi_remove - Exit routine | |
992 | * @pdev: platform device structure | |
993 | * | |
994 | * free all allocations and delete the partitions. | |
995 | */ | |
996 | static int __devexit spear_smi_remove(struct platform_device *pdev) | |
997 | { | |
998 | struct spear_smi *dev; | |
999 | struct spear_snor_flash *flash; | |
495c47d7 | 1000 | struct resource *smi_base; |
f18dbbb1 SH |
1001 | int ret; |
1002 | int i, irq; | |
1003 | ||
1004 | dev = platform_get_drvdata(pdev); | |
1005 | if (!dev) { | |
1006 | dev_err(&pdev->dev, "dev is null\n"); | |
1007 | return -ENODEV; | |
1008 | } | |
1009 | ||
1010 | /* clean up for all nor flash */ | |
1011 | for (i = 0; i < dev->num_flashes; i++) { | |
1012 | flash = dev->flash[i]; | |
1013 | if (!flash) | |
1014 | continue; | |
1015 | ||
1016 | /* clean up mtd stuff */ | |
1017 | ret = mtd_device_unregister(&flash->mtd); | |
1018 | if (ret) | |
1019 | dev_err(&pdev->dev, "error removing mtd\n"); | |
1020 | ||
1021 | iounmap(flash->base_addr); | |
1022 | kfree(flash); | |
1023 | } | |
1024 | ||
1025 | irq = platform_get_irq(pdev, 0); | |
1026 | free_irq(irq, dev); | |
1027 | ||
1028 | clk_disable(dev->clk); | |
1029 | clk_put(dev->clk); | |
1030 | iounmap(dev->io_base); | |
1031 | kfree(dev); | |
495c47d7 SH |
1032 | |
1033 | smi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1034 | release_mem_region(smi_base->start, resource_size(smi_base)); | |
f18dbbb1 SH |
1035 | platform_set_drvdata(pdev, NULL); |
1036 | ||
1037 | return 0; | |
1038 | } | |
1039 | ||
1040 | int spear_smi_suspend(struct platform_device *pdev, pm_message_t state) | |
1041 | { | |
1042 | struct spear_smi *dev = platform_get_drvdata(pdev); | |
1043 | ||
1044 | if (dev && dev->clk) | |
1045 | clk_disable(dev->clk); | |
1046 | ||
1047 | return 0; | |
1048 | } | |
1049 | ||
1050 | int spear_smi_resume(struct platform_device *pdev) | |
1051 | { | |
1052 | struct spear_smi *dev = platform_get_drvdata(pdev); | |
1053 | int ret = -EPERM; | |
1054 | ||
1055 | if (dev && dev->clk) | |
1056 | ret = clk_enable(dev->clk); | |
1057 | ||
1058 | if (!ret) | |
1059 | spear_smi_hw_init(dev); | |
1060 | return ret; | |
1061 | } | |
1062 | ||
1063 | static struct platform_driver spear_smi_driver = { | |
1064 | .driver = { | |
1065 | .name = "smi", | |
1066 | .bus = &platform_bus_type, | |
1067 | .owner = THIS_MODULE, | |
1068 | }, | |
1069 | .probe = spear_smi_probe, | |
1070 | .remove = __devexit_p(spear_smi_remove), | |
1071 | .suspend = spear_smi_suspend, | |
1072 | .resume = spear_smi_resume, | |
1073 | }; | |
1074 | ||
1075 | static int spear_smi_init(void) | |
1076 | { | |
1077 | return platform_driver_register(&spear_smi_driver); | |
1078 | } | |
1079 | module_init(spear_smi_init); | |
1080 | ||
1081 | static void spear_smi_exit(void) | |
1082 | { | |
1083 | platform_driver_unregister(&spear_smi_driver); | |
1084 | } | |
1085 | module_exit(spear_smi_exit); | |
1086 | ||
1087 | MODULE_LICENSE("GPL"); | |
1088 | MODULE_AUTHOR("Ashish Priyadarshi, Shiraz Hashim <shiraz.hashim@st.com>"); | |
1089 | MODULE_DESCRIPTION("MTD SMI driver for serial nor flash chips"); |