[deliverable/linux.git] / drivers / mtd / maps / dc21285.c

/*
 * MTD map driver for flash on the DC21285 (the StrongARM-110 companion chip)
 *
 * (C) 2000  Nicolas Pitre <nico@fluxnic.net>
 *
 * This code is GPL
 */
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/slab.h>

#include <linux/mtd/mtd.h>
#include <linux/mtd/map.h>
#include <linux/mtd/partitions.h>

#include <asm/io.h>
#include <asm/hardware/dec21285.h>
#include <asm/mach-types.h>


static struct mtd_info *dc21285_mtd;

#ifdef CONFIG_ARCH_NETWINDER
/*
 * This is really ugly, but it seams to be the only
 * realiable way to do it, as the cpld state machine
 * is unpredictible. So we have a 25us penalty per
 * write access.
 */
static void nw_en_write(void)
{
	unsigned long flags;

	/*
	 * we want to write a bit pattern XXX1 to Xilinx to enable
	 * the write gate, which will be open for about the next 2ms.
	 */
	spin_lock_irqsave(&nw_gpio_lock, flags);
	nw_cpld_modify(CPLD_FLASH_WR_ENABLE, CPLD_FLASH_WR_ENABLE);
	spin_unlock_irqrestore(&nw_gpio_lock, flags);

	/*
	 * let the ISA bus to catch on...
	 */
	udelay(25);
}
#else
#define nw_en_write() do { } while (0)
#endif

static map_word dc21285_read8(struct map_info *map, unsigned long ofs)
{
	map_word val;
	val.x[0] = *(uint8_t*)(map->virt + ofs);
	return val;
}

static map_word dc21285_read16(struct map_info *map, unsigned long ofs)
{
	map_word val;
	val.x[0] = *(uint16_t*)(map->virt + ofs);
	return val;
}

static map_word dc21285_read32(struct map_info *map, unsigned long ofs)
{
	map_word val;
	val.x[0] = *(uint32_t*)(map->virt + ofs);
	return val;
}

static void dc21285_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len)
{
	memcpy(to, (void*)(map->virt + from), len);
}

static void dc21285_write8(struct map_info *map, const map_word d, unsigned long adr)
{
	if (machine_is_netwinder())
		nw_en_write();
	*CSR_ROMWRITEREG = adr & 3;
	adr &= ~3;
	*(uint8_t*)(map->virt + adr) = d.x[0];
}

static void dc21285_write16(struct map_info *map, const map_word d, unsigned long adr)
{
	if (machine_is_netwinder())
		nw_en_write();
	*CSR_ROMWRITEREG = adr & 3;
	adr &= ~3;
	*(uint16_t*)(map->virt + adr) = d.x[0];
}

static void dc21285_write32(struct map_info *map, const map_word d, unsigned long adr)
{
	if (machine_is_netwinder())
		nw_en_write();
	*(uint32_t*)(map->virt + adr) = d.x[0];
}

static void dc21285_copy_to_32(struct map_info *map, unsigned long to, const void *from, ssize_t len)
{
	while (len > 0) {
		map_word d;
		d.x[0] = *((uint32_t*)from);
		dc21285_write32(map, d, to);
		from += 4;
		to += 4;
		len -= 4;
	}
}

static void dc21285_copy_to_16(struct map_info *map, unsigned long to, const void *from, ssize_t len)
{
	while (len > 0) {
		map_word d;
		d.x[0] = *((uint16_t*)from);
		dc21285_write16(map, d, to);
		from += 2;
		to += 2;
		len -= 2;
	}
}

static void dc21285_copy_to_8(struct map_info *map, unsigned long to, const void *from, ssize_t len)
{
	map_word d;
	d.x[0] = *((uint8_t*)from);
	dc21285_write8(map, d, to);
	from++;
	to++;
	len--;
}

static struct map_info dc21285_map = {
	.name = "DC21285 flash",
	.phys = NO_XIP,
	.size = 16*1024*1024,
	.copy_from = dc21285_copy_from,
};


/* Partition stuff */
#ifdef CONFIG_MTD_PARTITIONS
static struct mtd_partition *dc21285_parts;
static const char *probes[] = { "RedBoot", "cmdlinepart", NULL };
#endif

static int __init init_dc21285(void)
{

#ifdef CONFIG_MTD_PARTITIONS
	int nrparts;
#endif

	/* Determine bankwidth */
	switch (*CSR_SA110_CNTL & (3<<14)) {
		case SA110_CNTL_ROMWIDTH_8:
			dc21285_map.bankwidth = 1;
			dc21285_map.read = dc21285_read8;
			dc21285_map.write = dc21285_write8;
			dc21285_map.copy_to = dc21285_copy_to_8;
			break;
		case SA110_CNTL_ROMWIDTH_16:
			dc21285_map.bankwidth = 2;
			dc21285_map.read = dc21285_read16;
			dc21285_map.write = dc21285_write16;
			dc21285_map.copy_to = dc21285_copy_to_16;
			break;
		case SA110_CNTL_ROMWIDTH_32:
			dc21285_map.bankwidth = 4;
			dc21285_map.read = dc21285_read32;
			dc21285_map.write = dc21285_write32;
			dc21285_map.copy_to = dc21285_copy_to_32;
			break;
		default:
			printk (KERN_ERR "DC21285 flash: undefined bankwidth\n");
			return -ENXIO;
	}
	printk (KERN_NOTICE "DC21285 flash support (%d-bit bankwidth)\n",
		dc21285_map.bankwidth*8);

	/* Let's map the flash area */
	dc21285_map.virt = ioremap(DC21285_FLASH, 16*1024*1024);
	if (!dc21285_map.virt) {
		printk("Failed to ioremap\n");
		return -EIO;
	}

	if (machine_is_ebsa285()) {
		dc21285_mtd = do_map_probe("cfi_probe", &dc21285_map);
	} else {
		dc21285_mtd = do_map_probe("jedec_probe", &dc21285_map);
	}

	if (!dc21285_mtd) {
		iounmap(dc21285_map.virt);
		return -ENXIO;
	}

	dc21285_mtd->owner = THIS_MODULE;

#ifdef CONFIG_MTD_PARTITIONS
	nrparts = parse_mtd_partitions(dc21285_mtd, probes, &dc21285_parts, 0);
	if (nrparts > 0)
		add_mtd_partitions(dc21285_mtd, dc21285_parts, nrparts);
	else
#endif
		add_mtd_device(dc21285_mtd);

	if(machine_is_ebsa285()) {
		/*
		 * Flash timing is determined with bits 19-16 of the
		 * CSR_SA110_CNTL.  The value is the number of wait cycles, or
		 * 0 for 16 cycles (the default).  Cycles are 20 ns.
		 * Here we use 7 for 140 ns flash chips.
		 */
		/* access time */
		*CSR_SA110_CNTL = ((*CSR_SA110_CNTL & ~0x000f0000) | (7 << 16));
		/* burst time */
		*CSR_SA110_CNTL = ((*CSR_SA110_CNTL & ~0x00f00000) | (7 << 20));
		/* tristate time */
		*CSR_SA110_CNTL = ((*CSR_SA110_CNTL & ~0x0f000000) | (7 << 24));
	}

	return 0;
}

static void __exit cleanup_dc21285(void)
{
#ifdef CONFIG_MTD_PARTITIONS
	if (dc21285_parts) {
		del_mtd_partitions(dc21285_mtd);
		kfree(dc21285_parts);
	} else
#endif
		del_mtd_device(dc21285_mtd);

	map_destroy(dc21285_mtd);
	iounmap(dc21285_map.virt);
}

module_init(init_dc21285);
module_exit(cleanup_dc21285);


MODULE_LICENSE("GPL");
MODULE_AUTHOR("Nicolas Pitre <nico@fluxnic.net>");
MODULE_DESCRIPTION("MTD map driver for DC21285 boards");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* MTD map driver for flash on the DC21285 (the StrongARM-110 companion chip)
	3	*
2f82af08	4	* (C) 2000 Nicolas Pitre <nico@fluxnic.net>
1da177e4 LT	5	*
1da177e4 LT	6	* This code is GPL
1da177e4	7	*/
1da177e4 LT	8	#include <linux/module.h>
	9	#include <linux/types.h>
	10	#include <linux/kernel.h>
	11	#include <linux/init.h>
	12	#include <linux/delay.h>
4e57b681	13	#include <linux/slab.h>
1da177e4 LT	14
	15	#include <linux/mtd/mtd.h>
	16	#include <linux/mtd/map.h>
	17	#include <linux/mtd/partitions.h>
	18
	19	#include <asm/io.h>
	20	#include <asm/hardware/dec21285.h>
	21	#include <asm/mach-types.h>
	22
	23
	24	static struct mtd_info *dc21285_mtd;
	25
	26	#ifdef CONFIG_ARCH_NETWINDER
69f34c98	27	/*
1da177e4	28	* This is really ugly, but it seams to be the only
69f34c98	29	* realiable way to do it, as the cpld state machine
1da177e4 LT	30	* is unpredictible. So we have a 25us penalty per
	31	* write access.
	32	*/
	33	static void nw_en_write(void)
	34	{
1da177e4 LT	35	unsigned long flags;
	36
	37	/*
	38	* we want to write a bit pattern XXX1 to Xilinx to enable
	39	* the write gate, which will be open for about the next 2ms.
	40	*/
70d13e08 RK	41	spin_lock_irqsave(&nw_gpio_lock, flags);
	42	nw_cpld_modify(CPLD_FLASH_WR_ENABLE, CPLD_FLASH_WR_ENABLE);
	43	spin_unlock_irqrestore(&nw_gpio_lock, flags);
1da177e4 LT	44
	45	/*
	46	* let the ISA bus to catch on...
	47	*/
	48	udelay(25);
	49	}
	50	#else
	51	#define nw_en_write() do { } while (0)
	52	#endif
	53
	54	static map_word dc21285_read8(struct map_info *map, unsigned long ofs)
	55	{
	56	map_word val;
	57	val.x[0] = (uint8_t)(map->virt + ofs);
	58	return val;
	59	}
	60
	61	static map_word dc21285_read16(struct map_info *map, unsigned long ofs)
	62	{
	63	map_word val;
	64	val.x[0] = (uint16_t)(map->virt + ofs);
	65	return val;
	66	}
	67
	68	static map_word dc21285_read32(struct map_info *map, unsigned long ofs)
	69	{
	70	map_word val;
	71	val.x[0] = (uint32_t)(map->virt + ofs);
	72	return val;
	73	}
	74
	75	static void dc21285_copy_from(struct map_info map, void to, unsigned long from, ssize_t len)
	76	{
	77	memcpy(to, (void*)(map->virt + from), len);
	78	}
	79
	80	static void dc21285_write8(struct map_info *map, const map_word d, unsigned long adr)
	81	{
	82	if (machine_is_netwinder())
	83	nw_en_write();
	84	*CSR_ROMWRITEREG = adr & 3;
	85	adr &= ~3;
	86	(uint8_t)(map->virt + adr) = d.x[0];
	87	}
	88
	89	static void dc21285_write16(struct map_info *map, const map_word d, unsigned long adr)
	90	{
	91	if (machine_is_netwinder())
	92	nw_en_write();
	93	*CSR_ROMWRITEREG = adr & 3;
	94	adr &= ~3;
	95	(uint16_t)(map->virt + adr) = d.x[0];
	96	}
	97
	98	static void dc21285_write32(struct map_info *map, const map_word d, unsigned long adr)
	99	{
	100	if (machine_is_netwinder())
	101	nw_en_write();
	102	(uint32_t)(map->virt + adr) = d.x[0];
	103	}
	104
	105	static void dc21285_copy_to_32(struct map_info map, unsigned long to, const void from, ssize_t len)
	106	{
	107	while (len > 0) {
108	map_word d;
75b84e94	109	d.x[0] = ((uint32_t)from);
1da177e4	110	dc21285_write32(map, d, to);
75b84e94	111	from += 4;
1da177e4 LT	112	to += 4;
	113	len -= 4;
	114	}
	115	}
	116
	117	static void dc21285_copy_to_16(struct map_info map, unsigned long to, const void from, ssize_t len)
	118	{
	119	while (len > 0) {
	120	map_word d;
75b84e94	121	d.x[0] = ((uint16_t)from);
1da177e4	122	dc21285_write16(map, d, to);
75b84e94	123	from += 2;
1da177e4 LT	124	to += 2;
	125	len -= 2;
	126	}
	127	}
	128
	129	static void dc21285_copy_to_8(struct map_info map, unsigned long to, const void from, ssize_t len)
	130	{
	131	map_word d;
75b84e94	132	d.x[0] = ((uint8_t)from);
1da177e4	133	dc21285_write8(map, d, to);
75b84e94	134	from++;
1da177e4 LT	135	to++;
	136	len--;
	137	}
	138
	139	static struct map_info dc21285_map = {
	140	.name = "DC21285 flash",
	141	.phys = NO_XIP,
	142	.size = 1610241024,
	143	.copy_from = dc21285_copy_from,
	144	};
	145
	146
	147	/* Partition stuff */
	148	#ifdef CONFIG_MTD_PARTITIONS
	149	static struct mtd_partition *dc21285_parts;
	150	static const char *probes[] = { "RedBoot", "cmdlinepart", NULL };
	151	#endif
69f34c98	152
1da177e4 LT	153	static int __init init_dc21285(void)
	154	{
	155
	156	#ifdef CONFIG_MTD_PARTITIONS
	157	int nrparts;
	158	#endif
	159
	160	/* Determine bankwidth */
	161	switch (*CSR_SA110_CNTL & (3<<14)) {
69f34c98	162	case SA110_CNTL_ROMWIDTH_8:
1da177e4 LT	163	dc21285_map.bankwidth = 1;
	164	dc21285_map.read = dc21285_read8;
	165	dc21285_map.write = dc21285_write8;
	166	dc21285_map.copy_to = dc21285_copy_to_8;
	167	break;
69f34c98 TG	168	case SA110_CNTL_ROMWIDTH_16:
69f34c98 TG	169	dc21285_map.bankwidth = 2;
1da177e4 LT	170	dc21285_map.read = dc21285_read16;
	171	dc21285_map.write = dc21285_write16;
	172	dc21285_map.copy_to = dc21285_copy_to_16;
	173	break;
69f34c98 TG	174	case SA110_CNTL_ROMWIDTH_32:
69f34c98 TG	175	dc21285_map.bankwidth = 4;
1da177e4 LT	176	dc21285_map.read = dc21285_read32;
	177	dc21285_map.write = dc21285_write32;
	178	dc21285_map.copy_to = dc21285_copy_to_32;
	179	break;
	180	default:
	181	printk (KERN_ERR "DC21285 flash: undefined bankwidth\n");
	182	return -ENXIO;
	183	}
	184	printk (KERN_NOTICE "DC21285 flash support (%d-bit bankwidth)\n",
	185	dc21285_map.bankwidth*8);
	186
	187	/* Let's map the flash area */
	188	dc21285_map.virt = ioremap(DC21285_FLASH, 1610241024);
	189	if (!dc21285_map.virt) {
	190	printk("Failed to ioremap\n");
	191	return -EIO;
	192	}
	193
	194	if (machine_is_ebsa285()) {
	195	dc21285_mtd = do_map_probe("cfi_probe", &dc21285_map);
	196	} else {
	197	dc21285_mtd = do_map_probe("jedec_probe", &dc21285_map);
	198	}
	199
	200	if (!dc21285_mtd) {
	201	iounmap(dc21285_map.virt);
	202	return -ENXIO;
69f34c98 TG	203	}
69f34c98 TG	204
1da177e4 LT	205	dc21285_mtd->owner = THIS_MODULE;
	206
	207	#ifdef CONFIG_MTD_PARTITIONS
	208	nrparts = parse_mtd_partitions(dc21285_mtd, probes, &dc21285_parts, 0);
	209	if (nrparts > 0)
	210	add_mtd_partitions(dc21285_mtd, dc21285_parts, nrparts);
69f34c98 TG	211	else
69f34c98 TG	212	#endif
1da177e4	213	add_mtd_device(dc21285_mtd);
69f34c98	214
1da177e4	215	if(machine_is_ebsa285()) {
69f34c98	216	/*
1da177e4 LT	217	* Flash timing is determined with bits 19-16 of the
	218	* CSR_SA110_CNTL. The value is the number of wait cycles, or
	219	* 0 for 16 cycles (the default). Cycles are 20 ns.
	220	* Here we use 7 for 140 ns flash chips.
	221	*/
	222	/* access time */
	223	CSR_SA110_CNTL = ((CSR_SA110_CNTL & ~0x000f0000) \| (7 << 16));
	224	/* burst time */
	225	CSR_SA110_CNTL = ((CSR_SA110_CNTL & ~0x00f00000) \| (7 << 20));
	226	/* tristate time */
	227	CSR_SA110_CNTL = ((CSR_SA110_CNTL & ~0x0f000000) \| (7 << 24));
	228	}
69f34c98	229
1da177e4 LT	230	return 0;
	231	}
	232
	233	static void __exit cleanup_dc21285(void)
	234	{
	235	#ifdef CONFIG_MTD_PARTITIONS
	236	if (dc21285_parts) {
	237	del_mtd_partitions(dc21285_mtd);
	238	kfree(dc21285_parts);
	239	} else
	240	#endif
	241	del_mtd_device(dc21285_mtd);
	242
	243	map_destroy(dc21285_mtd);
	244	iounmap(dc21285_map.virt);
	245	}
	246
	247	module_init(init_dc21285);
	248	module_exit(cleanup_dc21285);
	249
	250
	251	MODULE_LICENSE("GPL");
2f82af08	252	MODULE_AUTHOR("Nicolas Pitre <nico@fluxnic.net>");
1da177e4	253	MODULE_DESCRIPTION("MTD map driver for DC21285 boards");