[deliverable/linux.git] / drivers / mtd / maps / intel_vr_nor.c

/*
 * drivers/mtd/maps/intel_vr_nor.c
 *
 * An MTD map driver for a NOR flash bank on the Expansion Bus of the Intel
 * Vermilion Range chipset.
 *
 * The Vermilion Range Expansion Bus supports four chip selects, each of which
 * has 64MiB of address space.  The 2nd BAR of the Expansion Bus PCI Device
 * is a 256MiB memory region containing the address spaces for all four of the
 * chip selects, with start addresses hardcoded on 64MiB boundaries.
 *
 * This map driver only supports NOR flash on chip select 0.  The buswidth
 * (either 8 bits or 16 bits) is determined by reading the Expansion Bus Timing
 * and Control Register for Chip Select 0 (EXP_TIMING_CS0).  This driver does
 * not modify the value in the EXP_TIMING_CS0 register except to enable writing
 * and disable boot acceleration.  The timing parameters in the register are
 * assumed to have been properly initialized by the BIOS.  The reset default
 * timing parameters are maximally conservative (slow), so access to the flash
 * will be slower than it should be if the BIOS has not initialized the timing
 * parameters.
 *
 * Author: Andy Lowe <alowe@mvista.com>
 *
 * 2006 (c) MontaVista Software, Inc. This file is licensed under
 * the terms of the GNU General Public License version 2. This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/map.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/cfi.h>
#include <linux/mtd/flashchip.h>

#define DRV_NAME "vr_nor"

struct vr_nor_mtd {
	void __iomem *csr_base;
	struct map_info map;
	struct mtd_info *info;
	int nr_parts;
	struct pci_dev *dev;
};

/* Expansion Bus Configuration and Status Registers are in BAR 0 */
#define EXP_CSR_MBAR 0
/* Expansion Bus Memory Window is BAR 1 */
#define EXP_WIN_MBAR 1
/* Maximum address space for Chip Select 0 is 64MiB */
#define CS0_SIZE 0x04000000
/* Chip Select 0 is at offset 0 in the Memory Window */
#define CS0_START 0x0
/* Chip Select 0 Timing Register is at offset 0 in CSR */
#define EXP_TIMING_CS0 0x00
#define TIMING_CS_EN		(1 << 31)	/* Chip Select Enable */
#define TIMING_BOOT_ACCEL_DIS	(1 <<  8)	/* Boot Acceleration Disable */
#define TIMING_WR_EN		(1 <<  1)	/* Write Enable */
#define TIMING_BYTE_EN		(1 <<  0)	/* 8-bit vs 16-bit bus */
#define TIMING_MASK		0x3FFF0000

static void __devexit vr_nor_destroy_partitions(struct vr_nor_mtd *p)
{
	mtd_device_unregister(p->info);
}

static int __devinit vr_nor_init_partitions(struct vr_nor_mtd *p)
{
	struct mtd_partition *parts;

	/* register the flash bank */
	/* partition the flash bank */
	p->nr_parts = parse_mtd_partitions(p->info, NULL, &parts, 0);
	return mtd_device_register(p->info, parts, p->nr_parts);
}

static void __devexit vr_nor_destroy_mtd_setup(struct vr_nor_mtd *p)
{
	map_destroy(p->info);
}

static int __devinit vr_nor_mtd_setup(struct vr_nor_mtd *p)
{
	static const char *probe_types[] =
	    { "cfi_probe", "jedec_probe", NULL };
	const char **type;

	for (type = probe_types; !p->info && *type; type++)
		p->info = do_map_probe(*type, &p->map);
	if (!p->info)
		return -ENODEV;

	p->info->owner = THIS_MODULE;

	return 0;
}

static void __devexit vr_nor_destroy_maps(struct vr_nor_mtd *p)
{
	unsigned int exp_timing_cs0;

	/* write-protect the flash bank */
	exp_timing_cs0 = readl(p->csr_base + EXP_TIMING_CS0);
	exp_timing_cs0 &= ~TIMING_WR_EN;
	writel(exp_timing_cs0, p->csr_base + EXP_TIMING_CS0);

	/* unmap the flash window */
	iounmap(p->map.virt);

	/* unmap the csr window */
	iounmap(p->csr_base);
}

/*
 * Initialize the map_info structure and map the flash.
 * Returns 0 on success, nonzero otherwise.
 */
static int __devinit vr_nor_init_maps(struct vr_nor_mtd *p)
{
	unsigned long csr_phys, csr_len;
	unsigned long win_phys, win_len;
	unsigned int exp_timing_cs0;
	int err;

	csr_phys = pci_resource_start(p->dev, EXP_CSR_MBAR);
	csr_len = pci_resource_len(p->dev, EXP_CSR_MBAR);
	win_phys = pci_resource_start(p->dev, EXP_WIN_MBAR);
	win_len = pci_resource_len(p->dev, EXP_WIN_MBAR);

	if (!csr_phys || !csr_len || !win_phys || !win_len)
		return -ENODEV;

	if (win_len < (CS0_START + CS0_SIZE))
		return -ENXIO;

	p->csr_base = ioremap_nocache(csr_phys, csr_len);
	if (!p->csr_base)
		return -ENOMEM;

	exp_timing_cs0 = readl(p->csr_base + EXP_TIMING_CS0);
	if (!(exp_timing_cs0 & TIMING_CS_EN)) {
		dev_warn(&p->dev->dev, "Expansion Bus Chip Select 0 "
		       "is disabled.\n");
		err = -ENODEV;
		goto release;
	}
	if ((exp_timing_cs0 & TIMING_MASK) == TIMING_MASK) {
		dev_warn(&p->dev->dev, "Expansion Bus Chip Select 0 "
		       "is configured for maximally slow access times.\n");
	}
	p->map.name = DRV_NAME;
	p->map.bankwidth = (exp_timing_cs0 & TIMING_BYTE_EN) ? 1 : 2;
	p->map.phys = win_phys + CS0_START;
	p->map.size = CS0_SIZE;
	p->map.virt = ioremap_nocache(p->map.phys, p->map.size);
	if (!p->map.virt) {
		err = -ENOMEM;
		goto release;
	}
	simple_map_init(&p->map);

	/* Enable writes to flash bank */
	exp_timing_cs0 |= TIMING_BOOT_ACCEL_DIS | TIMING_WR_EN;
	writel(exp_timing_cs0, p->csr_base + EXP_TIMING_CS0);

	return 0;

      release:
	iounmap(p->csr_base);
	return err;
}

static struct pci_device_id vr_nor_pci_ids[] = {
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x500D)},
	{0,}
};

static void __devexit vr_nor_pci_remove(struct pci_dev *dev)
{
	struct vr_nor_mtd *p = pci_get_drvdata(dev);

	pci_set_drvdata(dev, NULL);
	vr_nor_destroy_partitions(p);
	vr_nor_destroy_mtd_setup(p);
	vr_nor_destroy_maps(p);
	kfree(p);
	pci_release_regions(dev);
	pci_disable_device(dev);
}

static int __devinit
vr_nor_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct vr_nor_mtd *p = NULL;
	unsigned int exp_timing_cs0;
	int err;

	err = pci_enable_device(dev);
	if (err)
		goto out;

	err = pci_request_regions(dev, DRV_NAME);
	if (err)
		goto disable_dev;

	p = kzalloc(sizeof(*p), GFP_KERNEL);
	err = -ENOMEM;
	if (!p)
		goto release;

	p->dev = dev;

	err = vr_nor_init_maps(p);
	if (err)
		goto release;

	err = vr_nor_mtd_setup(p);
	if (err)
		goto destroy_maps;

	err = vr_nor_init_partitions(p);
	if (err)
		goto destroy_mtd_setup;

	pci_set_drvdata(dev, p);

	return 0;

      destroy_mtd_setup:
	map_destroy(p->info);

      destroy_maps:
	/* write-protect the flash bank */
	exp_timing_cs0 = readl(p->csr_base + EXP_TIMING_CS0);
	exp_timing_cs0 &= ~TIMING_WR_EN;
	writel(exp_timing_cs0, p->csr_base + EXP_TIMING_CS0);

	/* unmap the flash window */
	iounmap(p->map.virt);

	/* unmap the csr window */
	iounmap(p->csr_base);

      release:
	kfree(p);
	pci_release_regions(dev);

      disable_dev:
	pci_disable_device(dev);

      out:
	return err;
}

static struct pci_driver vr_nor_pci_driver = {
	.name = DRV_NAME,
	.probe = vr_nor_pci_probe,
	.remove = __devexit_p(vr_nor_pci_remove),
	.id_table = vr_nor_pci_ids,
};

static int __init vr_nor_mtd_init(void)
{
	return pci_register_driver(&vr_nor_pci_driver);
}

static void __exit vr_nor_mtd_exit(void)
{
	pci_unregister_driver(&vr_nor_pci_driver);
}

module_init(vr_nor_mtd_init);
module_exit(vr_nor_mtd_exit);

MODULE_AUTHOR("Andy Lowe");
MODULE_DESCRIPTION("MTD map driver for NOR flash on Intel Vermilion Range");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, vr_nor_pci_ids);
Commit	Line	Data
0bac5111 DW	1	/*
	2	* drivers/mtd/maps/intel_vr_nor.c
	3	*
	4	* An MTD map driver for a NOR flash bank on the Expansion Bus of the Intel
	5	* Vermilion Range chipset.
	6	*
	7	* The Vermilion Range Expansion Bus supports four chip selects, each of which
	8	* has 64MiB of address space. The 2nd BAR of the Expansion Bus PCI Device
	9	* is a 256MiB memory region containing the address spaces for all four of the
	10	* chip selects, with start addresses hardcoded on 64MiB boundaries.
	11	*
	12	* This map driver only supports NOR flash on chip select 0. The buswidth
	13	* (either 8 bits or 16 bits) is determined by reading the Expansion Bus Timing
	14	* and Control Register for Chip Select 0 (EXP_TIMING_CS0). This driver does
	15	* not modify the value in the EXP_TIMING_CS0 register except to enable writing
	16	* and disable boot acceleration. The timing parameters in the register are
	17	* assumed to have been properly initialized by the BIOS. The reset default
	18	* timing parameters are maximally conservative (slow), so access to the flash
	19	* will be slower than it should be if the BIOS has not initialized the timing
	20	* parameters.
	21	*
	22	* Author: Andy Lowe <alowe@mvista.com>
	23	*
	24	* 2006 (c) MontaVista Software, Inc. This file is licensed under
	25	* the terms of the GNU General Public License version 2. This program
	26	* is licensed "as is" without any warranty of any kind, whether express
	27	* or implied.
	28	*/
	29
	30	#include <linux/module.h>
	31	#include <linux/kernel.h>
5a0e3ad6	32	#include <linux/slab.h>
0bac5111 DW	33	#include <linux/pci.h>
	34	#include <linux/init.h>
	35	#include <linux/mtd/mtd.h>
	36	#include <linux/mtd/map.h>
	37	#include <linux/mtd/partitions.h>
	38	#include <linux/mtd/cfi.h>
	39	#include <linux/mtd/flashchip.h>
	40
	41	#define DRV_NAME "vr_nor"
	42
	43	struct vr_nor_mtd {
	44	void __iomem *csr_base;
	45	struct map_info map;
	46	struct mtd_info *info;
	47	int nr_parts;
	48	struct pci_dev *dev;
	49	};
	50
	51	/* Expansion Bus Configuration and Status Registers are in BAR 0 */
	52	#define EXP_CSR_MBAR 0
	53	/* Expansion Bus Memory Window is BAR 1 */
	54	#define EXP_WIN_MBAR 1
	55	/* Maximum address space for Chip Select 0 is 64MiB */
	56	#define CS0_SIZE 0x04000000
	57	/* Chip Select 0 is at offset 0 in the Memory Window */
	58	#define CS0_START 0x0
	59	/* Chip Select 0 Timing Register is at offset 0 in CSR */
	60	#define EXP_TIMING_CS0 0x00
	61	#define TIMING_CS_EN (1 << 31) /* Chip Select Enable */
	62	#define TIMING_BOOT_ACCEL_DIS (1 << 8) /* Boot Acceleration Disable */
	63	#define TIMING_WR_EN (1 << 1) /* Write Enable */
	64	#define TIMING_BYTE_EN (1 << 0) /* 8-bit vs 16-bit bus */
	65	#define TIMING_MASK 0x3FFF0000
	66
	67	static void __devexit vr_nor_destroy_partitions(struct vr_nor_mtd *p)
	68	{
95bf224f	69	mtd_device_unregister(p->info);
0bac5111 DW	70	}
	71
	72	static int __devinit vr_nor_init_partitions(struct vr_nor_mtd *p)
	73	{
0bac5111	74	struct mtd_partition *parts;
0bac5111 DW	75
0bac5111 DW	76	/* register the flash bank */
0bac5111	77	/* partition the flash bank */
8d130a74	78	p->nr_parts = parse_mtd_partitions(p->info, NULL, &parts, 0);
95bf224f	79	return mtd_device_register(p->info, parts, p->nr_parts);
0bac5111 DW	80	}
	81
	82	static void __devexit vr_nor_destroy_mtd_setup(struct vr_nor_mtd *p)
	83	{
	84	map_destroy(p->info);
	85	}
	86
	87	static int __devinit vr_nor_mtd_setup(struct vr_nor_mtd *p)
	88	{
	89	static const char *probe_types[] =
	90	{ "cfi_probe", "jedec_probe", NULL };
	91	const char **type;
	92
	93	for (type = probe_types; !p->info && *type; type++)
	94	p->info = do_map_probe(*type, &p->map);
	95	if (!p->info)
	96	return -ENODEV;
	97
	98	p->info->owner = THIS_MODULE;
	99
	100	return 0;
	101	}
	102
	103	static void __devexit vr_nor_destroy_maps(struct vr_nor_mtd *p)
	104	{
	105	unsigned int exp_timing_cs0;
	106
	107	/* write-protect the flash bank */
	108	exp_timing_cs0 = readl(p->csr_base + EXP_TIMING_CS0);
	109	exp_timing_cs0 &= ~TIMING_WR_EN;
	110	writel(exp_timing_cs0, p->csr_base + EXP_TIMING_CS0);
	111
	112	/* unmap the flash window */
	113	iounmap(p->map.virt);
	114
	115	/* unmap the csr window */
	116	iounmap(p->csr_base);
	117	}
	118
	119	/*
	120	* Initialize the map_info structure and map the flash.
	121	* Returns 0 on success, nonzero otherwise.
	122	*/
	123	static int __devinit vr_nor_init_maps(struct vr_nor_mtd *p)
	124	{
	125	unsigned long csr_phys, csr_len;
	126	unsigned long win_phys, win_len;
	127	unsigned int exp_timing_cs0;
	128	int err;
	129
	130	csr_phys = pci_resource_start(p->dev, EXP_CSR_MBAR);
	131	csr_len = pci_resource_len(p->dev, EXP_CSR_MBAR);
	132	win_phys = pci_resource_start(p->dev, EXP_WIN_MBAR);
	133	win_len = pci_resource_len(p->dev, EXP_WIN_MBAR);
	134
	135	if (!csr_phys \|\| !csr_len \|\| !win_phys \|\| !win_len)
	136	return -ENODEV;
	137
	138	if (win_len < (CS0_START + CS0_SIZE))
	139	return -ENXIO;
	140
	141	p->csr_base = ioremap_nocache(csr_phys, csr_len);
	142	if (!p->csr_base)
	143	return -ENOMEM;
144
145	exp_timing_cs0 = readl(p->csr_base + EXP_TIMING_CS0);
146	if (!(exp_timing_cs0 & TIMING_CS_EN)) {
147	dev_warn(&p->dev->dev, "Expansion Bus Chip Select 0 "
148	"is disabled.\n");
149	err = -ENODEV;
150	goto release;
151	}
152	if ((exp_timing_cs0 & TIMING_MASK) == TIMING_MASK) {
153	dev_warn(&p->dev->dev, "Expansion Bus Chip Select 0 "
154	"is configured for maximally slow access times.\n");
155	}
156	p->map.name = DRV_NAME;
157	p->map.bankwidth = (exp_timing_cs0 & TIMING_BYTE_EN) ? 1 : 2;
158	p->map.phys = win_phys + CS0_START;
159	p->map.size = CS0_SIZE;
160	p->map.virt = ioremap_nocache(p->map.phys, p->map.size);
161	if (!p->map.virt) {
162	err = -ENOMEM;
163	goto release;
164	}
165	simple_map_init(&p->map);
166
167	/* Enable writes to flash bank */
168	exp_timing_cs0 \|= TIMING_BOOT_ACCEL_DIS \| TIMING_WR_EN;
169	writel(exp_timing_cs0, p->csr_base + EXP_TIMING_CS0);
170
171	return 0;
172
173	release:
174	iounmap(p->csr_base);
175	return err;
176	}
177
178	static struct pci_device_id vr_nor_pci_ids[] = {
179	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x500D)},
180	{0,}
181	};
182
183	static void __devexit vr_nor_pci_remove(struct pci_dev *dev)
184	{
185	struct vr_nor_mtd *p = pci_get_drvdata(dev);
186
187	pci_set_drvdata(dev, NULL);
188	vr_nor_destroy_partitions(p);
189	vr_nor_destroy_mtd_setup(p);
190	vr_nor_destroy_maps(p);
191	kfree(p);
192	pci_release_regions(dev);
193	pci_disable_device(dev);
194	}
195
196	static int __devinit
197	vr_nor_pci_probe(struct pci_dev dev, const struct pci_device_id id)
198	{
199	struct vr_nor_mtd *p = NULL;
200	unsigned int exp_timing_cs0;
201	int err;
202
203	err = pci_enable_device(dev);
204	if (err)
205	goto out;
206
207	err = pci_request_regions(dev, DRV_NAME);
208	if (err)
209	goto disable_dev;
210
211	p = kzalloc(sizeof(*p), GFP_KERNEL);
212	err = -ENOMEM;
213	if (!p)
214	goto release;
215
216	p->dev = dev;
217
218	err = vr_nor_init_maps(p);
219	if (err)
220	goto release;
221
222	err = vr_nor_mtd_setup(p);
223	if (err)
224	goto destroy_maps;
225
226	err = vr_nor_init_partitions(p);
227	if (err)
228	goto destroy_mtd_setup;
229
230	pci_set_drvdata(dev, p);
231
232	return 0;
233
234	destroy_mtd_setup:
235	map_destroy(p->info);
236
237	destroy_maps:
238	/* write-protect the flash bank */
239	exp_timing_cs0 = readl(p->csr_base + EXP_TIMING_CS0);
240	exp_timing_cs0 &= ~TIMING_WR_EN;
241	writel(exp_timing_cs0, p->csr_base + EXP_TIMING_CS0);
242
243	/* unmap the flash window */
244	iounmap(p->map.virt);
245
246	/* unmap the csr window */
247	iounmap(p->csr_base);
248
249	release:
250	kfree(p);
251	pci_release_regions(dev);
252
253	disable_dev:
254	pci_disable_device(dev);
255
256	out:
257	return err;
258	}
259
260	static struct pci_driver vr_nor_pci_driver = {
261	.name = DRV_NAME,
262	.probe = vr_nor_pci_probe,
263	.remove = __devexit_p(vr_nor_pci_remove),
264	.id_table = vr_nor_pci_ids,
265	};
266
267	static int __init vr_nor_mtd_init(void)
268	{
269	return pci_register_driver(&vr_nor_pci_driver);
270	}
271
272	static void __exit vr_nor_mtd_exit(void)
273	{
274	pci_unregister_driver(&vr_nor_pci_driver);
275	}
276
277	module_init(vr_nor_mtd_init);
278	module_exit(vr_nor_mtd_exit);
279
280	MODULE_AUTHOR("Andy Lowe");
281	MODULE_DESCRIPTION("MTD map driver for NOR flash on Intel Vermilion Range");
282	MODULE_LICENSE("GPL");
283	MODULE_DEVICE_TABLE(pci, vr_nor_pci_ids);