[deliverable/linux.git] / drivers / mtd / nand / ams-delta.c

/*
 *  drivers/mtd/nand/ams-delta.c
 *
 *  Copyright (C) 2006 Jonathan McDowell <noodles@earth.li>
 *
 *  Derived from drivers/mtd/toto.c
 *  Converted to platform driver by Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
 *  Partially stolen from drivers/mtd/nand/plat_nand.c
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  Overview:
 *   This is a device driver for the NAND flash device found on the
 *   Amstrad E3 (Delta).
 */

#include <linux/slab.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/gpio.h>
#include <linux/platform_data/gpio-omap.h>

#include <asm/io.h>
#include <asm/sizes.h>

#include <mach/board-ams-delta.h>

#include <mach/hardware.h>

/*
 * MTD structure for E3 (Delta)
 */
static struct mtd_info *ams_delta_mtd = NULL;

/*
 * Define partitions for flash devices
 */

static struct mtd_partition partition_info[] = {
	{ .name		= "Kernel",
	  .offset	= 0,
	  .size		= 3 * SZ_1M + SZ_512K },
	{ .name		= "u-boot",
	  .offset	= 3 * SZ_1M + SZ_512K,
	  .size		= SZ_256K },
	{ .name		= "u-boot params",
	  .offset	= 3 * SZ_1M + SZ_512K + SZ_256K,
	  .size		= SZ_256K },
	{ .name		= "Amstrad LDR",
	  .offset	= 4 * SZ_1M,
	  .size		= SZ_256K },
	{ .name		= "File system",
	  .offset	= 4 * SZ_1M + 1 * SZ_256K,
	  .size		= 27 * SZ_1M },
	{ .name		= "PBL reserved",
	  .offset	= 32 * SZ_1M - 3 * SZ_256K,
	  .size		=  3 * SZ_256K },
};

static void ams_delta_write_byte(struct mtd_info *mtd, u_char byte)
{
	struct nand_chip *this = mtd_to_nand(mtd);
	void __iomem *io_base = (void __iomem *)nand_get_controller_data(this);

	writew(0, io_base + OMAP_MPUIO_IO_CNTL);
	writew(byte, this->IO_ADDR_W);
	gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NWE, 0);
	ndelay(40);
	gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NWE, 1);
}

static u_char ams_delta_read_byte(struct mtd_info *mtd)
{
	u_char res;
	struct nand_chip *this = mtd_to_nand(mtd);
	void __iomem *io_base = (void __iomem *)nand_get_controller_data(this);

	gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NRE, 0);
	ndelay(40);
	writew(~0, io_base + OMAP_MPUIO_IO_CNTL);
	res = readw(this->IO_ADDR_R);
	gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NRE, 1);

	return res;
}

static void ams_delta_write_buf(struct mtd_info *mtd, const u_char *buf,
				int len)
{
	int i;

	for (i=0; i<len; i++)
		ams_delta_write_byte(mtd, buf[i]);
}

static void ams_delta_read_buf(struct mtd_info *mtd, u_char *buf, int len)
{
	int i;

	for (i=0; i<len; i++)
		buf[i] = ams_delta_read_byte(mtd);
}

/*
 * Command control function
 *
 * ctrl:
 * NAND_NCE: bit 0 -> bit 2
 * NAND_CLE: bit 1 -> bit 7
 * NAND_ALE: bit 2 -> bit 6
 */
static void ams_delta_hwcontrol(struct mtd_info *mtd, int cmd,
				unsigned int ctrl)
{

	if (ctrl & NAND_CTRL_CHANGE) {
		gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NCE,
				(ctrl & NAND_NCE) == 0);
		gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_CLE,
				(ctrl & NAND_CLE) != 0);
		gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_ALE,
				(ctrl & NAND_ALE) != 0);
	}

	if (cmd != NAND_CMD_NONE)
		ams_delta_write_byte(mtd, cmd);
}

static int ams_delta_nand_ready(struct mtd_info *mtd)
{
	return gpio_get_value(AMS_DELTA_GPIO_PIN_NAND_RB);
}

static const struct gpio _mandatory_gpio[] = {
	{
		.gpio	= AMS_DELTA_GPIO_PIN_NAND_NCE,
		.flags	= GPIOF_OUT_INIT_HIGH,
		.label	= "nand_nce",
	},
	{
		.gpio	= AMS_DELTA_GPIO_PIN_NAND_NRE,
		.flags	= GPIOF_OUT_INIT_HIGH,
		.label	= "nand_nre",
	},
	{
		.gpio	= AMS_DELTA_GPIO_PIN_NAND_NWP,
		.flags	= GPIOF_OUT_INIT_HIGH,
		.label	= "nand_nwp",
	},
	{
		.gpio	= AMS_DELTA_GPIO_PIN_NAND_NWE,
		.flags	= GPIOF_OUT_INIT_HIGH,
		.label	= "nand_nwe",
	},
	{
		.gpio	= AMS_DELTA_GPIO_PIN_NAND_ALE,
		.flags	= GPIOF_OUT_INIT_LOW,
		.label	= "nand_ale",
	},
	{
		.gpio	= AMS_DELTA_GPIO_PIN_NAND_CLE,
		.flags	= GPIOF_OUT_INIT_LOW,
		.label	= "nand_cle",
	},
};

/*
 * Main initialization routine
 */
static int ams_delta_init(struct platform_device *pdev)
{
	struct nand_chip *this;
	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	void __iomem *io_base;
	int err = 0;

	if (!res)
		return -ENXIO;

	/* Allocate memory for MTD device structure and private data */
	this = kzalloc(sizeof(struct nand_chip), GFP_KERNEL);
	if (!this) {
		printk (KERN_WARNING "Unable to allocate E3 NAND MTD device structure.\n");
		err = -ENOMEM;
		goto out;
	}

	ams_delta_mtd = nand_to_mtd(this);
	ams_delta_mtd->owner = THIS_MODULE;

	/*
	 * Don't try to request the memory region from here,
	 * it should have been already requested from the
	 * gpio-omap driver and requesting it again would fail.
	 */

	io_base = ioremap(res->start, resource_size(res));
	if (io_base == NULL) {
		dev_err(&pdev->dev, "ioremap failed\n");
		err = -EIO;
		goto out_free;
	}

	nand_set_controller_data(this, (void *)io_base);

	/* Set address of NAND IO lines */
	this->IO_ADDR_R = io_base + OMAP_MPUIO_INPUT_LATCH;
	this->IO_ADDR_W = io_base + OMAP_MPUIO_OUTPUT;
	this->read_byte = ams_delta_read_byte;
	this->write_buf = ams_delta_write_buf;
	this->read_buf = ams_delta_read_buf;
	this->cmd_ctrl = ams_delta_hwcontrol;
	if (gpio_request(AMS_DELTA_GPIO_PIN_NAND_RB, "nand_rdy") == 0) {
		this->dev_ready = ams_delta_nand_ready;
	} else {
		this->dev_ready = NULL;
		printk(KERN_NOTICE "Couldn't request gpio for Delta NAND ready.\n");
	}
	/* 25 us command delay time */
	this->chip_delay = 30;
	this->ecc.mode = NAND_ECC_SOFT;
	this->ecc.algo = NAND_ECC_HAMMING;

	platform_set_drvdata(pdev, io_base);

	/* Set chip enabled, but  */
	err = gpio_request_array(_mandatory_gpio, ARRAY_SIZE(_mandatory_gpio));
	if (err)
		goto out_gpio;

	/* Scan to find existence of the device */
	if (nand_scan(ams_delta_mtd, 1)) {
		err = -ENXIO;
		goto out_mtd;
	}

	/* Register the partitions */
	mtd_device_register(ams_delta_mtd, partition_info,
			    ARRAY_SIZE(partition_info));

	goto out;

 out_mtd:
	gpio_free_array(_mandatory_gpio, ARRAY_SIZE(_mandatory_gpio));
out_gpio:
	gpio_free(AMS_DELTA_GPIO_PIN_NAND_RB);
	iounmap(io_base);
out_free:
	kfree(this);
 out:
	return err;
}

/*
 * Clean up routine
 */
static int ams_delta_cleanup(struct platform_device *pdev)
{
	void __iomem *io_base = platform_get_drvdata(pdev);

	/* Release resources, unregister device */
	nand_release(ams_delta_mtd);

	gpio_free_array(_mandatory_gpio, ARRAY_SIZE(_mandatory_gpio));
	gpio_free(AMS_DELTA_GPIO_PIN_NAND_RB);
	iounmap(io_base);

	/* Free the MTD device structure */
	kfree(mtd_to_nand(ams_delta_mtd));

	return 0;
}

static struct platform_driver ams_delta_nand_driver = {
	.probe		= ams_delta_init,
	.remove		= ams_delta_cleanup,
	.driver		= {
		.name	= "ams-delta-nand",
	},
};

module_platform_driver(ams_delta_nand_driver);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Jonathan McDowell <noodles@earth.li>");
MODULE_DESCRIPTION("Glue layer for NAND flash on Amstrad E3 (Delta)");
Commit	Line	Data
3d12c0c7 JM	1	/*
	2	* drivers/mtd/nand/ams-delta.c
	3	*
	4	* Copyright (C) 2006 Jonathan McDowell <noodles@earth.li>
	5	*
	6	* Derived from drivers/mtd/toto.c
7e95d1f1	7	* Converted to platform driver by Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
eaca491f	8	* Partially stolen from drivers/mtd/nand/plat_nand.c
3d12c0c7 JM	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*
	14	* Overview:
	15	* This is a device driver for the NAND flash device found on the
	16	* Amstrad E3 (Delta).
	17	*/
	18
	19	#include <linux/slab.h>
3d12c0c7 JM	20	#include <linux/module.h>
	21	#include <linux/delay.h>
	22	#include <linux/mtd/mtd.h>
	23	#include <linux/mtd/nand.h>
	24	#include <linux/mtd/partitions.h>
4b25408f TL	25	#include <linux/gpio.h>
	26	#include <linux/platform_data/gpio-omap.h>
	27
3d12c0c7	28	#include <asm/io.h>
3d12c0c7	29	#include <asm/sizes.h>
4b25408f	30
e27e35ec	31	#include <mach/board-ams-delta.h>
3d12c0c7	32
4b25408f	33	#include <mach/hardware.h>
3d12c0c7 JM	34
	35	/*
	36	* MTD structure for E3 (Delta)
	37	*/
	38	static struct mtd_info *ams_delta_mtd = NULL;
	39
3d12c0c7 JM	40	/*
	41	* Define partitions for flash devices
	42	*/
	43
	44	static struct mtd_partition partition_info[] = {
	45	{ .name = "Kernel",
	46	.offset = 0,
	47	.size = 3 * SZ_1M + SZ_512K },
	48	{ .name = "u-boot",
	49	.offset = 3 * SZ_1M + SZ_512K,
	50	.size = SZ_256K },
	51	{ .name = "u-boot params",
	52	.offset = 3 * SZ_1M + SZ_512K + SZ_256K,
	53	.size = SZ_256K },
	54	{ .name = "Amstrad LDR",
	55	.offset = 4 * SZ_1M,
	56	.size = SZ_256K },
	57	{ .name = "File system",
	58	.offset = 4 * SZ_1M + 1 * SZ_256K,
	59	.size = 27 * SZ_1M },
	60	{ .name = "PBL reserved",
	61	.offset = 32 * SZ_1M - 3 * SZ_256K,
	62	.size = 3 * SZ_256K },
	63	};
	64
3d12c0c7 JM	65	static void ams_delta_write_byte(struct mtd_info *mtd, u_char byte)
3d12c0c7 JM	66	{
4bd4ebcc	67	struct nand_chip *this = mtd_to_nand(mtd);
d699ed25	68	void __iomem io_base = (void __iomem )nand_get_controller_data(this);
3d12c0c7	69
eaca491f JK	70	writew(0, io_base + OMAP_MPUIO_IO_CNTL);
eaca491f JK	71	writew(byte, this->IO_ADDR_W);
68f06766	72	gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NWE, 0);
3d12c0c7	73	ndelay(40);
68f06766	74	gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NWE, 1);
3d12c0c7 JM	75	}
	76
	77	static u_char ams_delta_read_byte(struct mtd_info *mtd)
	78	{
	79	u_char res;
4bd4ebcc	80	struct nand_chip *this = mtd_to_nand(mtd);
d699ed25	81	void __iomem io_base = (void __iomem )nand_get_controller_data(this);
3d12c0c7	82
68f06766	83	gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NRE, 0);
3d12c0c7	84	ndelay(40);
eaca491f JK	85	writew(~0, io_base + OMAP_MPUIO_IO_CNTL);
eaca491f JK	86	res = readw(this->IO_ADDR_R);
68f06766	87	gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NRE, 1);
3d12c0c7 JM	88
	89	return res;
	90	}
	91
	92	static void ams_delta_write_buf(struct mtd_info mtd, const u_char buf,
	93	int len)
	94	{
	95	int i;
	96
	97	for (i=0; i<len; i++)
	98	ams_delta_write_byte(mtd, buf[i]);
	99	}
	100
	101	static void ams_delta_read_buf(struct mtd_info mtd, u_char buf, int len)
	102	{
	103	int i;
	104
	105	for (i=0; i<len; i++)
	106	buf[i] = ams_delta_read_byte(mtd);
	107	}
	108
7abd3ef9 TG	109	/*
	110	* Command control function
	111	*
	112	* ctrl:
	113	* NAND_NCE: bit 0 -> bit 2
	114	* NAND_CLE: bit 1 -> bit 7
	115	* NAND_ALE: bit 2 -> bit 6
	116	*/
	117	static void ams_delta_hwcontrol(struct mtd_info *mtd, int cmd,
	118	unsigned int ctrl)
	119	{
	120
	121	if (ctrl & NAND_CTRL_CHANGE) {
68f06766 JK	122	gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NCE,
	123	(ctrl & NAND_NCE) == 0);
	124	gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_CLE,
	125	(ctrl & NAND_CLE) != 0);
	126	gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_ALE,
	127	(ctrl & NAND_ALE) != 0);
7abd3ef9 TG	128	}
	129
	130	if (cmd != NAND_CMD_NONE)
	131	ams_delta_write_byte(mtd, cmd);
	132	}
	133
3d12c0c7 JM	134	static int ams_delta_nand_ready(struct mtd_info *mtd)
3d12c0c7 JM	135	{
93a22f8b	136	return gpio_get_value(AMS_DELTA_GPIO_PIN_NAND_RB);
3d12c0c7 JM	137	}
3d12c0c7 JM	138
da564a05	139	static const struct gpio _mandatory_gpio[] = {
68f06766 JK	140	{
	141	.gpio = AMS_DELTA_GPIO_PIN_NAND_NCE,
	142	.flags = GPIOF_OUT_INIT_HIGH,
	143	.label = "nand_nce",
	144	},
	145	{
	146	.gpio = AMS_DELTA_GPIO_PIN_NAND_NRE,
	147	.flags = GPIOF_OUT_INIT_HIGH,
	148	.label = "nand_nre",
	149	},
	150	{
	151	.gpio = AMS_DELTA_GPIO_PIN_NAND_NWP,
	152	.flags = GPIOF_OUT_INIT_HIGH,
	153	.label = "nand_nwp",
	154	},
	155	{
	156	.gpio = AMS_DELTA_GPIO_PIN_NAND_NWE,
	157	.flags = GPIOF_OUT_INIT_HIGH,
	158	.label = "nand_nwe",
	159	},
	160	{
	161	.gpio = AMS_DELTA_GPIO_PIN_NAND_ALE,
	162	.flags = GPIOF_OUT_INIT_LOW,
	163	.label = "nand_ale",
	164	},
	165	{
	166	.gpio = AMS_DELTA_GPIO_PIN_NAND_CLE,
	167	.flags = GPIOF_OUT_INIT_LOW,
	168	.label = "nand_cle",
	169	},
	170	};
	171
3d12c0c7 JM	172	/*
	173	* Main initialization routine
	174	*/
06f25510	175	static int ams_delta_init(struct platform_device *pdev)
3d12c0c7 JM	176	{
3d12c0c7 JM	177	struct nand_chip *this;
eaca491f JK	178	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
eaca491f JK	179	void __iomem *io_base;
3d12c0c7 JM	180	int err = 0;
3d12c0c7 JM	181
eaca491f JK	182	if (!res)
	183	return -ENXIO;
	184
3d12c0c7	185	/* Allocate memory for MTD device structure and private data */
187d6ada BB	186	this = kzalloc(sizeof(struct nand_chip), GFP_KERNEL);
187d6ada BB	187	if (!this) {
3d12c0c7 JM	188	printk (KERN_WARNING "Unable to allocate E3 NAND MTD device structure.\n");
	189	err = -ENOMEM;
	190	goto out;
	191	}
	192
187d6ada	193	ams_delta_mtd = nand_to_mtd(this);
3d12c0c7 JM	194	ams_delta_mtd->owner = THIS_MODULE;
3d12c0c7 JM	195
b027274d JK	196	/*
	197	* Don't try to request the memory region from here,
	198	* it should have been already requested from the
	199	* gpio-omap driver and requesting it again would fail.
	200	*/
eaca491f JK	201
	202	io_base = ioremap(res->start, resource_size(res));
	203	if (io_base == NULL) {
	204	dev_err(&pdev->dev, "ioremap failed\n");
	205	err = -EIO;
b027274d	206	goto out_free;
eaca491f JK	207	}
eaca491f JK	208
d699ed25	209	nand_set_controller_data(this, (void *)io_base);
eaca491f	210
3d12c0c7	211	/* Set address of NAND IO lines */
eaca491f JK	212	this->IO_ADDR_R = io_base + OMAP_MPUIO_INPUT_LATCH;
eaca491f JK	213	this->IO_ADDR_W = io_base + OMAP_MPUIO_OUTPUT;
3d12c0c7	214	this->read_byte = ams_delta_read_byte;
3d12c0c7 JM	215	this->write_buf = ams_delta_write_buf;
3d12c0c7 JM	216	this->read_buf = ams_delta_read_buf;
7abd3ef9	217	this->cmd_ctrl = ams_delta_hwcontrol;
93a22f8b	218	if (gpio_request(AMS_DELTA_GPIO_PIN_NAND_RB, "nand_rdy") == 0) {
3d12c0c7 JM	219	this->dev_ready = ams_delta_nand_ready;
	220	} else {
	221	this->dev_ready = NULL;
	222	printk(KERN_NOTICE "Couldn't request gpio for Delta NAND ready.\n");
	223	}
	224	/* 25 us command delay time */
	225	this->chip_delay = 30;
6dfc6d25	226	this->ecc.mode = NAND_ECC_SOFT;
e58dd3c3	227	this->ecc.algo = NAND_ECC_HAMMING;
3d12c0c7	228
eaca491f JK	229	platform_set_drvdata(pdev, io_base);
eaca491f JK	230
3d12c0c7	231	/* Set chip enabled, but */
68f06766 JK	232	err = gpio_request_array(_mandatory_gpio, ARRAY_SIZE(_mandatory_gpio));
	233	if (err)
	234	goto out_gpio;
3d12c0c7	235
25985edc	236	/* Scan to find existence of the device */
3d12c0c7 JM	237	if (nand_scan(ams_delta_mtd, 1)) {
	238	err = -ENXIO;
	239	goto out_mtd;
	240	}
	241
	242	/* Register the partitions */
ee0e87b1 JI	243	mtd_device_register(ams_delta_mtd, partition_info,
ee0e87b1 JI	244	ARRAY_SIZE(partition_info));
3d12c0c7 JM	245
	246	goto out;
	247
	248	out_mtd:
68f06766 JK	249	gpio_free_array(_mandatory_gpio, ARRAY_SIZE(_mandatory_gpio));
68f06766 JK	250	out_gpio:
68f06766	251	gpio_free(AMS_DELTA_GPIO_PIN_NAND_RB);
eaca491f	252	iounmap(io_base);
eaca491f	253	out_free:
187d6ada	254	kfree(this);
3d12c0c7 JM	255	out:
	256	return err;
	257	}
	258
3d12c0c7 JM	259	/*
	260	* Clean up routine
	261	*/
810b7e06	262	static int ams_delta_cleanup(struct platform_device *pdev)
3d12c0c7	263	{
eaca491f	264	void __iomem *io_base = platform_get_drvdata(pdev);
eaca491f	265
3d12c0c7 JM	266	/* Release resources, unregister device */
	267	nand_release(ams_delta_mtd);
	268
68f06766 JK	269	gpio_free_array(_mandatory_gpio, ARRAY_SIZE(_mandatory_gpio));
68f06766 JK	270	gpio_free(AMS_DELTA_GPIO_PIN_NAND_RB);
eaca491f	271	iounmap(io_base);
eaca491f	272
3d12c0c7	273	/* Free the MTD device structure */
187d6ada	274	kfree(mtd_to_nand(ams_delta_mtd));
7e95d1f1 JK	275
	276	return 0;
	277	}
	278
	279	static struct platform_driver ams_delta_nand_driver = {
	280	.probe = ams_delta_init,
5153b88c	281	.remove = ams_delta_cleanup,
7e95d1f1 JK	282	.driver = {
7e95d1f1 JK	283	.name = "ams-delta-nand",
7e95d1f1 JK	284	},
	285	};
	286
f99640de	287	module_platform_driver(ams_delta_nand_driver);
3d12c0c7 JM	288
	289	MODULE_LICENSE("GPL");
	290	MODULE_AUTHOR("Jonathan McDowell <noodles@earth.li>");
	291	MODULE_DESCRIPTION("Glue layer for NAND flash on Amstrad E3 (Delta)");