Commit | Line | Data |
---|---|---|
42cb1403 | 1 | /* |
1c7b874d | 2 | * Copyright © 2003 Rick Bronson |
42cb1403 AV |
3 | * |
4 | * Derived from drivers/mtd/nand/autcpu12.c | |
1c7b874d | 5 | * Copyright © 2001 Thomas Gleixner (gleixner@autronix.de) |
42cb1403 AV |
6 | * |
7 | * Derived from drivers/mtd/spia.c | |
1c7b874d | 8 | * Copyright © 2000 Steven J. Hill (sjhill@cotw.com) |
42cb1403 | 9 | * |
77f5492c RG |
10 | * |
11 | * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263 | |
1c7b874d | 12 | * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright © 2007 |
77f5492c RG |
13 | * |
14 | * Derived from Das U-Boot source code | |
15 | * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c) | |
1c7b874d | 16 | * © Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas |
77f5492c | 17 | * |
1c7b874d JW |
18 | * Add Programmable Multibit ECC support for various AT91 SoC |
19 | * © Copyright 2012 ATMEL, Hong Xu | |
77f5492c | 20 | * |
7dc37de7 JW |
21 | * Add Nand Flash Controller support for SAMA5 SoC |
22 | * © Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com) | |
23 | * | |
42cb1403 AV |
24 | * This program is free software; you can redistribute it and/or modify |
25 | * it under the terms of the GNU General Public License version 2 as | |
26 | * published by the Free Software Foundation. | |
27 | * | |
28 | */ | |
29 | ||
b7f080cf | 30 | #include <linux/dma-mapping.h> |
42cb1403 AV |
31 | #include <linux/slab.h> |
32 | #include <linux/module.h> | |
f4fa697c | 33 | #include <linux/moduleparam.h> |
42cb1403 | 34 | #include <linux/platform_device.h> |
d6a01661 JCPV |
35 | #include <linux/of.h> |
36 | #include <linux/of_device.h> | |
37 | #include <linux/of_gpio.h> | |
38 | #include <linux/of_mtd.h> | |
42cb1403 AV |
39 | #include <linux/mtd/mtd.h> |
40 | #include <linux/mtd/nand.h> | |
41 | #include <linux/mtd/partitions.h> | |
42 | ||
7dc37de7 | 43 | #include <linux/delay.h> |
5c39c4c5 | 44 | #include <linux/dmaengine.h> |
90574d0a | 45 | #include <linux/gpio.h> |
7dc37de7 | 46 | #include <linux/interrupt.h> |
90574d0a | 47 | #include <linux/io.h> |
bf4289cb | 48 | #include <linux/platform_data/atmel.h> |
42cb1403 | 49 | |
cbc6c5e7 HX |
50 | static int use_dma = 1; |
51 | module_param(use_dma, int, 0); | |
52 | ||
f4fa697c SP |
53 | static int on_flash_bbt = 0; |
54 | module_param(on_flash_bbt, int, 0); | |
55 | ||
77f5492c RG |
56 | /* Register access macros */ |
57 | #define ecc_readl(add, reg) \ | |
3c3796cc | 58 | __raw_readl(add + ATMEL_ECC_##reg) |
77f5492c | 59 | #define ecc_writel(add, reg, value) \ |
3c3796cc | 60 | __raw_writel((value), add + ATMEL_ECC_##reg) |
77f5492c | 61 | |
d4f4c0aa | 62 | #include "atmel_nand_ecc.h" /* Hardware ECC registers */ |
7dc37de7 | 63 | #include "atmel_nand_nfc.h" /* Nand Flash Controller definition */ |
77f5492c RG |
64 | |
65 | /* oob layout for large page size | |
66 | * bad block info is on bytes 0 and 1 | |
67 | * the bytes have to be consecutives to avoid | |
68 | * several NAND_CMD_RNDOUT during read | |
69 | */ | |
3c3796cc | 70 | static struct nand_ecclayout atmel_oobinfo_large = { |
77f5492c RG |
71 | .eccbytes = 4, |
72 | .eccpos = {60, 61, 62, 63}, | |
73 | .oobfree = { | |
74 | {2, 58} | |
75 | }, | |
76 | }; | |
77 | ||
78 | /* oob layout for small page size | |
79 | * bad block info is on bytes 4 and 5 | |
80 | * the bytes have to be consecutives to avoid | |
81 | * several NAND_CMD_RNDOUT during read | |
82 | */ | |
3c3796cc | 83 | static struct nand_ecclayout atmel_oobinfo_small = { |
77f5492c RG |
84 | .eccbytes = 4, |
85 | .eccpos = {0, 1, 2, 3}, | |
86 | .oobfree = { | |
87 | {6, 10} | |
88 | }, | |
89 | }; | |
90 | ||
7dc37de7 JW |
91 | struct atmel_nfc { |
92 | void __iomem *base_cmd_regs; | |
93 | void __iomem *hsmc_regs; | |
94 | void __iomem *sram_bank0; | |
95 | dma_addr_t sram_bank0_phys; | |
1ae9c092 | 96 | bool use_nfc_sram; |
6054d4d5 | 97 | bool write_by_sram; |
7dc37de7 JW |
98 | |
99 | bool is_initialized; | |
100 | struct completion comp_nfc; | |
1ae9c092 JW |
101 | |
102 | /* Point to the sram bank which include readed data via NFC */ | |
103 | void __iomem *data_in_sram; | |
6054d4d5 | 104 | bool will_write_sram; |
7dc37de7 JW |
105 | }; |
106 | static struct atmel_nfc nand_nfc; | |
107 | ||
3c3796cc | 108 | struct atmel_nand_host { |
42cb1403 AV |
109 | struct nand_chip nand_chip; |
110 | struct mtd_info mtd; | |
111 | void __iomem *io_base; | |
cbc6c5e7 | 112 | dma_addr_t io_phys; |
d6a01661 | 113 | struct atmel_nand_data board; |
77f5492c RG |
114 | struct device *dev; |
115 | void __iomem *ecc; | |
cbc6c5e7 HX |
116 | |
117 | struct completion comp; | |
118 | struct dma_chan *dma_chan; | |
a41b51a1 | 119 | |
7dc37de7 JW |
120 | struct atmel_nfc *nfc; |
121 | ||
a41b51a1 JW |
122 | bool has_pmecc; |
123 | u8 pmecc_corr_cap; | |
124 | u16 pmecc_sector_size; | |
125 | u32 pmecc_lookup_table_offset; | |
e66b4318 JW |
126 | u32 pmecc_lookup_table_offset_512; |
127 | u32 pmecc_lookup_table_offset_1024; | |
1c7b874d JW |
128 | |
129 | int pmecc_bytes_per_sector; | |
130 | int pmecc_sector_number; | |
131 | int pmecc_degree; /* Degree of remainders */ | |
132 | int pmecc_cw_len; /* Length of codeword */ | |
133 | ||
134 | void __iomem *pmerrloc_base; | |
135 | void __iomem *pmecc_rom_base; | |
136 | ||
137 | /* lookup table for alpha_to and index_of */ | |
138 | void __iomem *pmecc_alpha_to; | |
139 | void __iomem *pmecc_index_of; | |
140 | ||
141 | /* data for pmecc computation */ | |
142 | int16_t *pmecc_partial_syn; | |
143 | int16_t *pmecc_si; | |
144 | int16_t *pmecc_smu; /* Sigma table */ | |
145 | int16_t *pmecc_lmu; /* polynomal order */ | |
146 | int *pmecc_mu; | |
147 | int *pmecc_dmu; | |
148 | int *pmecc_delta; | |
42cb1403 AV |
149 | }; |
150 | ||
1c7b874d JW |
151 | static struct nand_ecclayout atmel_pmecc_oobinfo; |
152 | ||
8136508c AN |
153 | /* |
154 | * Enable NAND. | |
155 | */ | |
3c3796cc | 156 | static void atmel_nand_enable(struct atmel_nand_host *host) |
8136508c | 157 | { |
d6a01661 JCPV |
158 | if (gpio_is_valid(host->board.enable_pin)) |
159 | gpio_set_value(host->board.enable_pin, 0); | |
8136508c AN |
160 | } |
161 | ||
162 | /* | |
163 | * Disable NAND. | |
164 | */ | |
3c3796cc | 165 | static void atmel_nand_disable(struct atmel_nand_host *host) |
8136508c | 166 | { |
d6a01661 JCPV |
167 | if (gpio_is_valid(host->board.enable_pin)) |
168 | gpio_set_value(host->board.enable_pin, 1); | |
8136508c AN |
169 | } |
170 | ||
42cb1403 AV |
171 | /* |
172 | * Hardware specific access to control-lines | |
173 | */ | |
3c3796cc | 174 | static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
42cb1403 AV |
175 | { |
176 | struct nand_chip *nand_chip = mtd->priv; | |
3c3796cc | 177 | struct atmel_nand_host *host = nand_chip->priv; |
42cb1403 | 178 | |
8136508c | 179 | if (ctrl & NAND_CTRL_CHANGE) { |
2314488e | 180 | if (ctrl & NAND_NCE) |
3c3796cc | 181 | atmel_nand_enable(host); |
2314488e | 182 | else |
3c3796cc | 183 | atmel_nand_disable(host); |
2314488e | 184 | } |
42cb1403 AV |
185 | if (cmd == NAND_CMD_NONE) |
186 | return; | |
187 | ||
188 | if (ctrl & NAND_CLE) | |
d6a01661 | 189 | writeb(cmd, host->io_base + (1 << host->board.cle)); |
42cb1403 | 190 | else |
d6a01661 | 191 | writeb(cmd, host->io_base + (1 << host->board.ale)); |
42cb1403 AV |
192 | } |
193 | ||
194 | /* | |
195 | * Read the Device Ready pin. | |
196 | */ | |
3c3796cc | 197 | static int atmel_nand_device_ready(struct mtd_info *mtd) |
42cb1403 AV |
198 | { |
199 | struct nand_chip *nand_chip = mtd->priv; | |
3c3796cc | 200 | struct atmel_nand_host *host = nand_chip->priv; |
42cb1403 | 201 | |
d6a01661 JCPV |
202 | return gpio_get_value(host->board.rdy_pin) ^ |
203 | !!host->board.rdy_pin_active_low; | |
42cb1403 AV |
204 | } |
205 | ||
7dc37de7 JW |
206 | /* Set up for hardware ready pin and enable pin. */ |
207 | static int atmel_nand_set_enable_ready_pins(struct mtd_info *mtd) | |
208 | { | |
209 | struct nand_chip *chip = mtd->priv; | |
210 | struct atmel_nand_host *host = chip->priv; | |
211 | int res = 0; | |
212 | ||
213 | if (gpio_is_valid(host->board.rdy_pin)) { | |
214 | res = devm_gpio_request(host->dev, | |
215 | host->board.rdy_pin, "nand_rdy"); | |
216 | if (res < 0) { | |
217 | dev_err(host->dev, | |
218 | "can't request rdy gpio %d\n", | |
219 | host->board.rdy_pin); | |
220 | return res; | |
221 | } | |
222 | ||
223 | res = gpio_direction_input(host->board.rdy_pin); | |
224 | if (res < 0) { | |
225 | dev_err(host->dev, | |
226 | "can't request input direction rdy gpio %d\n", | |
227 | host->board.rdy_pin); | |
228 | return res; | |
229 | } | |
230 | ||
231 | chip->dev_ready = atmel_nand_device_ready; | |
232 | } | |
233 | ||
234 | if (gpio_is_valid(host->board.enable_pin)) { | |
235 | res = devm_gpio_request(host->dev, | |
236 | host->board.enable_pin, "nand_enable"); | |
237 | if (res < 0) { | |
238 | dev_err(host->dev, | |
239 | "can't request enable gpio %d\n", | |
240 | host->board.enable_pin); | |
241 | return res; | |
242 | } | |
243 | ||
244 | res = gpio_direction_output(host->board.enable_pin, 1); | |
245 | if (res < 0) { | |
246 | dev_err(host->dev, | |
247 | "can't request output direction enable gpio %d\n", | |
248 | host->board.enable_pin); | |
249 | return res; | |
250 | } | |
251 | } | |
252 | ||
253 | return res; | |
254 | } | |
255 | ||
1ae9c092 JW |
256 | static void memcpy32_fromio(void *trg, const void __iomem *src, size_t size) |
257 | { | |
258 | int i; | |
259 | u32 *t = trg; | |
260 | const __iomem u32 *s = src; | |
261 | ||
262 | for (i = 0; i < (size >> 2); i++) | |
263 | *t++ = readl_relaxed(s++); | |
264 | } | |
265 | ||
6054d4d5 JW |
266 | static void memcpy32_toio(void __iomem *trg, const void *src, int size) |
267 | { | |
268 | int i; | |
269 | u32 __iomem *t = trg; | |
270 | const u32 *s = src; | |
271 | ||
272 | for (i = 0; i < (size >> 2); i++) | |
273 | writel_relaxed(*s++, t++); | |
274 | } | |
275 | ||
50082319 AB |
276 | /* |
277 | * Minimal-overhead PIO for data access. | |
278 | */ | |
279 | static void atmel_read_buf8(struct mtd_info *mtd, u8 *buf, int len) | |
280 | { | |
281 | struct nand_chip *nand_chip = mtd->priv; | |
1ae9c092 | 282 | struct atmel_nand_host *host = nand_chip->priv; |
50082319 | 283 | |
1ae9c092 JW |
284 | if (host->nfc && host->nfc->use_nfc_sram && host->nfc->data_in_sram) { |
285 | memcpy32_fromio(buf, host->nfc->data_in_sram, len); | |
286 | host->nfc->data_in_sram += len; | |
287 | } else { | |
288 | __raw_readsb(nand_chip->IO_ADDR_R, buf, len); | |
289 | } | |
50082319 AB |
290 | } |
291 | ||
292 | static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len) | |
293 | { | |
294 | struct nand_chip *nand_chip = mtd->priv; | |
1ae9c092 | 295 | struct atmel_nand_host *host = nand_chip->priv; |
50082319 | 296 | |
1ae9c092 JW |
297 | if (host->nfc && host->nfc->use_nfc_sram && host->nfc->data_in_sram) { |
298 | memcpy32_fromio(buf, host->nfc->data_in_sram, len); | |
299 | host->nfc->data_in_sram += len; | |
300 | } else { | |
301 | __raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2); | |
302 | } | |
50082319 AB |
303 | } |
304 | ||
305 | static void atmel_write_buf8(struct mtd_info *mtd, const u8 *buf, int len) | |
306 | { | |
307 | struct nand_chip *nand_chip = mtd->priv; | |
308 | ||
309 | __raw_writesb(nand_chip->IO_ADDR_W, buf, len); | |
310 | } | |
311 | ||
312 | static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len) | |
313 | { | |
314 | struct nand_chip *nand_chip = mtd->priv; | |
315 | ||
316 | __raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2); | |
317 | } | |
318 | ||
cbc6c5e7 HX |
319 | static void dma_complete_func(void *completion) |
320 | { | |
321 | complete(completion); | |
322 | } | |
323 | ||
1ae9c092 JW |
324 | static int nfc_set_sram_bank(struct atmel_nand_host *host, unsigned int bank) |
325 | { | |
326 | /* NFC only has two banks. Must be 0 or 1 */ | |
327 | if (bank > 1) | |
328 | return -EINVAL; | |
329 | ||
330 | if (bank) { | |
331 | /* Only for a 2k-page or lower flash, NFC can handle 2 banks */ | |
332 | if (host->mtd.writesize > 2048) | |
333 | return -EINVAL; | |
334 | nfc_writel(host->nfc->hsmc_regs, BANK, ATMEL_HSMC_NFC_BANK1); | |
335 | } else { | |
336 | nfc_writel(host->nfc->hsmc_regs, BANK, ATMEL_HSMC_NFC_BANK0); | |
337 | } | |
338 | ||
339 | return 0; | |
340 | } | |
341 | ||
342 | static uint nfc_get_sram_off(struct atmel_nand_host *host) | |
343 | { | |
344 | if (nfc_readl(host->nfc->hsmc_regs, BANK) & ATMEL_HSMC_NFC_BANK1) | |
345 | return NFC_SRAM_BANK1_OFFSET; | |
346 | else | |
347 | return 0; | |
348 | } | |
349 | ||
350 | static dma_addr_t nfc_sram_phys(struct atmel_nand_host *host) | |
351 | { | |
352 | if (nfc_readl(host->nfc->hsmc_regs, BANK) & ATMEL_HSMC_NFC_BANK1) | |
353 | return host->nfc->sram_bank0_phys + NFC_SRAM_BANK1_OFFSET; | |
354 | else | |
355 | return host->nfc->sram_bank0_phys; | |
356 | } | |
357 | ||
cbc6c5e7 HX |
358 | static int atmel_nand_dma_op(struct mtd_info *mtd, void *buf, int len, |
359 | int is_read) | |
360 | { | |
361 | struct dma_device *dma_dev; | |
362 | enum dma_ctrl_flags flags; | |
363 | dma_addr_t dma_src_addr, dma_dst_addr, phys_addr; | |
364 | struct dma_async_tx_descriptor *tx = NULL; | |
365 | dma_cookie_t cookie; | |
366 | struct nand_chip *chip = mtd->priv; | |
367 | struct atmel_nand_host *host = chip->priv; | |
368 | void *p = buf; | |
369 | int err = -EIO; | |
370 | enum dma_data_direction dir = is_read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; | |
1ae9c092 | 371 | struct atmel_nfc *nfc = host->nfc; |
cbc6c5e7 | 372 | |
80b4f81a HX |
373 | if (buf >= high_memory) |
374 | goto err_buf; | |
cbc6c5e7 HX |
375 | |
376 | dma_dev = host->dma_chan->device; | |
377 | ||
378 | flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT | DMA_COMPL_SKIP_SRC_UNMAP | | |
379 | DMA_COMPL_SKIP_DEST_UNMAP; | |
380 | ||
381 | phys_addr = dma_map_single(dma_dev->dev, p, len, dir); | |
382 | if (dma_mapping_error(dma_dev->dev, phys_addr)) { | |
383 | dev_err(host->dev, "Failed to dma_map_single\n"); | |
384 | goto err_buf; | |
385 | } | |
386 | ||
387 | if (is_read) { | |
1ae9c092 JW |
388 | if (nfc && nfc->data_in_sram) |
389 | dma_src_addr = nfc_sram_phys(host) + (nfc->data_in_sram | |
390 | - (nfc->sram_bank0 + nfc_get_sram_off(host))); | |
391 | else | |
392 | dma_src_addr = host->io_phys; | |
393 | ||
cbc6c5e7 HX |
394 | dma_dst_addr = phys_addr; |
395 | } else { | |
396 | dma_src_addr = phys_addr; | |
6054d4d5 JW |
397 | |
398 | if (nfc && nfc->write_by_sram) | |
399 | dma_dst_addr = nfc_sram_phys(host); | |
400 | else | |
401 | dma_dst_addr = host->io_phys; | |
cbc6c5e7 HX |
402 | } |
403 | ||
404 | tx = dma_dev->device_prep_dma_memcpy(host->dma_chan, dma_dst_addr, | |
405 | dma_src_addr, len, flags); | |
406 | if (!tx) { | |
407 | dev_err(host->dev, "Failed to prepare DMA memcpy\n"); | |
408 | goto err_dma; | |
409 | } | |
410 | ||
411 | init_completion(&host->comp); | |
412 | tx->callback = dma_complete_func; | |
413 | tx->callback_param = &host->comp; | |
414 | ||
415 | cookie = tx->tx_submit(tx); | |
416 | if (dma_submit_error(cookie)) { | |
417 | dev_err(host->dev, "Failed to do DMA tx_submit\n"); | |
418 | goto err_dma; | |
419 | } | |
420 | ||
421 | dma_async_issue_pending(host->dma_chan); | |
422 | wait_for_completion(&host->comp); | |
423 | ||
1ae9c092 JW |
424 | if (is_read && nfc && nfc->data_in_sram) |
425 | /* After read data from SRAM, need to increase the position */ | |
426 | nfc->data_in_sram += len; | |
427 | ||
cbc6c5e7 HX |
428 | err = 0; |
429 | ||
430 | err_dma: | |
431 | dma_unmap_single(dma_dev->dev, phys_addr, len, dir); | |
432 | err_buf: | |
433 | if (err != 0) | |
434 | dev_warn(host->dev, "Fall back to CPU I/O\n"); | |
435 | return err; | |
436 | } | |
437 | ||
438 | static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len) | |
439 | { | |
440 | struct nand_chip *chip = mtd->priv; | |
50082319 | 441 | struct atmel_nand_host *host = chip->priv; |
cbc6c5e7 | 442 | |
9d51567e NF |
443 | if (use_dma && len > mtd->oobsize) |
444 | /* only use DMA for bigger than oob size: better performances */ | |
cbc6c5e7 HX |
445 | if (atmel_nand_dma_op(mtd, buf, len, 1) == 0) |
446 | return; | |
447 | ||
d6a01661 | 448 | if (host->board.bus_width_16) |
50082319 AB |
449 | atmel_read_buf16(mtd, buf, len); |
450 | else | |
451 | atmel_read_buf8(mtd, buf, len); | |
cbc6c5e7 HX |
452 | } |
453 | ||
454 | static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len) | |
455 | { | |
456 | struct nand_chip *chip = mtd->priv; | |
50082319 | 457 | struct atmel_nand_host *host = chip->priv; |
cbc6c5e7 | 458 | |
9d51567e NF |
459 | if (use_dma && len > mtd->oobsize) |
460 | /* only use DMA for bigger than oob size: better performances */ | |
cbc6c5e7 HX |
461 | if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) == 0) |
462 | return; | |
463 | ||
d6a01661 | 464 | if (host->board.bus_width_16) |
50082319 AB |
465 | atmel_write_buf16(mtd, buf, len); |
466 | else | |
467 | atmel_write_buf8(mtd, buf, len); | |
cbc6c5e7 HX |
468 | } |
469 | ||
1c7b874d JW |
470 | /* |
471 | * Return number of ecc bytes per sector according to sector size and | |
472 | * correction capability | |
473 | * | |
474 | * Following table shows what at91 PMECC supported: | |
475 | * Correction Capability Sector_512_bytes Sector_1024_bytes | |
476 | * ===================== ================ ================= | |
477 | * 2-bits 4-bytes 4-bytes | |
478 | * 4-bits 7-bytes 7-bytes | |
479 | * 8-bits 13-bytes 14-bytes | |
480 | * 12-bits 20-bytes 21-bytes | |
481 | * 24-bits 39-bytes 42-bytes | |
482 | */ | |
06f25510 | 483 | static int pmecc_get_ecc_bytes(int cap, int sector_size) |
1c7b874d JW |
484 | { |
485 | int m = 12 + sector_size / 512; | |
486 | return (m * cap + 7) / 8; | |
487 | } | |
488 | ||
06f25510 | 489 | static void pmecc_config_ecc_layout(struct nand_ecclayout *layout, |
d8929942 | 490 | int oobsize, int ecc_len) |
1c7b874d JW |
491 | { |
492 | int i; | |
493 | ||
494 | layout->eccbytes = ecc_len; | |
495 | ||
496 | /* ECC will occupy the last ecc_len bytes continuously */ | |
497 | for (i = 0; i < ecc_len; i++) | |
498 | layout->eccpos[i] = oobsize - ecc_len + i; | |
499 | ||
500 | layout->oobfree[0].offset = 2; | |
501 | layout->oobfree[0].length = | |
502 | oobsize - ecc_len - layout->oobfree[0].offset; | |
503 | } | |
504 | ||
06f25510 | 505 | static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host) |
1c7b874d JW |
506 | { |
507 | int table_size; | |
508 | ||
509 | table_size = host->pmecc_sector_size == 512 ? | |
510 | PMECC_LOOKUP_TABLE_SIZE_512 : PMECC_LOOKUP_TABLE_SIZE_1024; | |
511 | ||
512 | return host->pmecc_rom_base + host->pmecc_lookup_table_offset + | |
513 | table_size * sizeof(int16_t); | |
514 | } | |
515 | ||
06f25510 | 516 | static int pmecc_data_alloc(struct atmel_nand_host *host) |
1c7b874d JW |
517 | { |
518 | const int cap = host->pmecc_corr_cap; | |
0d63748d JCPV |
519 | int size; |
520 | ||
521 | size = (2 * cap + 1) * sizeof(int16_t); | |
522 | host->pmecc_partial_syn = devm_kzalloc(host->dev, size, GFP_KERNEL); | |
523 | host->pmecc_si = devm_kzalloc(host->dev, size, GFP_KERNEL); | |
524 | host->pmecc_lmu = devm_kzalloc(host->dev, | |
525 | (cap + 1) * sizeof(int16_t), GFP_KERNEL); | |
526 | host->pmecc_smu = devm_kzalloc(host->dev, | |
527 | (cap + 2) * size, GFP_KERNEL); | |
528 | ||
529 | size = (cap + 1) * sizeof(int); | |
530 | host->pmecc_mu = devm_kzalloc(host->dev, size, GFP_KERNEL); | |
531 | host->pmecc_dmu = devm_kzalloc(host->dev, size, GFP_KERNEL); | |
532 | host->pmecc_delta = devm_kzalloc(host->dev, size, GFP_KERNEL); | |
533 | ||
534 | if (!host->pmecc_partial_syn || | |
535 | !host->pmecc_si || | |
536 | !host->pmecc_lmu || | |
537 | !host->pmecc_smu || | |
538 | !host->pmecc_mu || | |
539 | !host->pmecc_dmu || | |
540 | !host->pmecc_delta) | |
541 | return -ENOMEM; | |
1c7b874d | 542 | |
0d63748d | 543 | return 0; |
1c7b874d JW |
544 | } |
545 | ||
546 | static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector) | |
547 | { | |
548 | struct nand_chip *nand_chip = mtd->priv; | |
549 | struct atmel_nand_host *host = nand_chip->priv; | |
550 | int i; | |
551 | uint32_t value; | |
552 | ||
553 | /* Fill odd syndromes */ | |
554 | for (i = 0; i < host->pmecc_corr_cap; i++) { | |
555 | value = pmecc_readl_rem_relaxed(host->ecc, sector, i / 2); | |
556 | if (i & 1) | |
557 | value >>= 16; | |
558 | value &= 0xffff; | |
559 | host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value; | |
560 | } | |
561 | } | |
562 | ||
563 | static void pmecc_substitute(struct mtd_info *mtd) | |
564 | { | |
565 | struct nand_chip *nand_chip = mtd->priv; | |
566 | struct atmel_nand_host *host = nand_chip->priv; | |
567 | int16_t __iomem *alpha_to = host->pmecc_alpha_to; | |
568 | int16_t __iomem *index_of = host->pmecc_index_of; | |
569 | int16_t *partial_syn = host->pmecc_partial_syn; | |
570 | const int cap = host->pmecc_corr_cap; | |
571 | int16_t *si; | |
572 | int i, j; | |
573 | ||
574 | /* si[] is a table that holds the current syndrome value, | |
575 | * an element of that table belongs to the field | |
576 | */ | |
577 | si = host->pmecc_si; | |
578 | ||
579 | memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1)); | |
580 | ||
581 | /* Computation 2t syndromes based on S(x) */ | |
582 | /* Odd syndromes */ | |
583 | for (i = 1; i < 2 * cap; i += 2) { | |
584 | for (j = 0; j < host->pmecc_degree; j++) { | |
585 | if (partial_syn[i] & ((unsigned short)0x1 << j)) | |
586 | si[i] = readw_relaxed(alpha_to + i * j) ^ si[i]; | |
587 | } | |
588 | } | |
589 | /* Even syndrome = (Odd syndrome) ** 2 */ | |
590 | for (i = 2, j = 1; j <= cap; i = ++j << 1) { | |
591 | if (si[j] == 0) { | |
592 | si[i] = 0; | |
593 | } else { | |
594 | int16_t tmp; | |
595 | ||
596 | tmp = readw_relaxed(index_of + si[j]); | |
597 | tmp = (tmp * 2) % host->pmecc_cw_len; | |
598 | si[i] = readw_relaxed(alpha_to + tmp); | |
599 | } | |
600 | } | |
601 | ||
602 | return; | |
603 | } | |
604 | ||
605 | static void pmecc_get_sigma(struct mtd_info *mtd) | |
606 | { | |
607 | struct nand_chip *nand_chip = mtd->priv; | |
608 | struct atmel_nand_host *host = nand_chip->priv; | |
609 | ||
610 | int16_t *lmu = host->pmecc_lmu; | |
611 | int16_t *si = host->pmecc_si; | |
612 | int *mu = host->pmecc_mu; | |
613 | int *dmu = host->pmecc_dmu; /* Discrepancy */ | |
614 | int *delta = host->pmecc_delta; /* Delta order */ | |
615 | int cw_len = host->pmecc_cw_len; | |
616 | const int16_t cap = host->pmecc_corr_cap; | |
617 | const int num = 2 * cap + 1; | |
618 | int16_t __iomem *index_of = host->pmecc_index_of; | |
619 | int16_t __iomem *alpha_to = host->pmecc_alpha_to; | |
620 | int i, j, k; | |
621 | uint32_t dmu_0_count, tmp; | |
622 | int16_t *smu = host->pmecc_smu; | |
623 | ||
624 | /* index of largest delta */ | |
625 | int ro; | |
626 | int largest; | |
627 | int diff; | |
628 | ||
629 | dmu_0_count = 0; | |
630 | ||
631 | /* First Row */ | |
632 | ||
633 | /* Mu */ | |
634 | mu[0] = -1; | |
635 | ||
636 | memset(smu, 0, sizeof(int16_t) * num); | |
637 | smu[0] = 1; | |
638 | ||
639 | /* discrepancy set to 1 */ | |
640 | dmu[0] = 1; | |
641 | /* polynom order set to 0 */ | |
642 | lmu[0] = 0; | |
643 | delta[0] = (mu[0] * 2 - lmu[0]) >> 1; | |
644 | ||
645 | /* Second Row */ | |
646 | ||
647 | /* Mu */ | |
648 | mu[1] = 0; | |
649 | /* Sigma(x) set to 1 */ | |
650 | memset(&smu[num], 0, sizeof(int16_t) * num); | |
651 | smu[num] = 1; | |
652 | ||
653 | /* discrepancy set to S1 */ | |
654 | dmu[1] = si[1]; | |
655 | ||
656 | /* polynom order set to 0 */ | |
657 | lmu[1] = 0; | |
658 | ||
659 | delta[1] = (mu[1] * 2 - lmu[1]) >> 1; | |
660 | ||
661 | /* Init the Sigma(x) last row */ | |
662 | memset(&smu[(cap + 1) * num], 0, sizeof(int16_t) * num); | |
663 | ||
664 | for (i = 1; i <= cap; i++) { | |
665 | mu[i + 1] = i << 1; | |
666 | /* Begin Computing Sigma (Mu+1) and L(mu) */ | |
667 | /* check if discrepancy is set to 0 */ | |
668 | if (dmu[i] == 0) { | |
669 | dmu_0_count++; | |
670 | ||
671 | tmp = ((cap - (lmu[i] >> 1) - 1) / 2); | |
672 | if ((cap - (lmu[i] >> 1) - 1) & 0x1) | |
673 | tmp += 2; | |
674 | else | |
675 | tmp += 1; | |
676 | ||
677 | if (dmu_0_count == tmp) { | |
678 | for (j = 0; j <= (lmu[i] >> 1) + 1; j++) | |
679 | smu[(cap + 1) * num + j] = | |
680 | smu[i * num + j]; | |
681 | ||
682 | lmu[cap + 1] = lmu[i]; | |
683 | return; | |
684 | } | |
685 | ||
686 | /* copy polynom */ | |
687 | for (j = 0; j <= lmu[i] >> 1; j++) | |
688 | smu[(i + 1) * num + j] = smu[i * num + j]; | |
689 | ||
690 | /* copy previous polynom order to the next */ | |
691 | lmu[i + 1] = lmu[i]; | |
692 | } else { | |
693 | ro = 0; | |
694 | largest = -1; | |
695 | /* find largest delta with dmu != 0 */ | |
696 | for (j = 0; j < i; j++) { | |
697 | if ((dmu[j]) && (delta[j] > largest)) { | |
698 | largest = delta[j]; | |
699 | ro = j; | |
700 | } | |
701 | } | |
702 | ||
703 | /* compute difference */ | |
704 | diff = (mu[i] - mu[ro]); | |
705 | ||
706 | /* Compute degree of the new smu polynomial */ | |
707 | if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff)) | |
708 | lmu[i + 1] = lmu[i]; | |
709 | else | |
710 | lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2; | |
711 | ||
712 | /* Init smu[i+1] with 0 */ | |
713 | for (k = 0; k < num; k++) | |
714 | smu[(i + 1) * num + k] = 0; | |
715 | ||
716 | /* Compute smu[i+1] */ | |
717 | for (k = 0; k <= lmu[ro] >> 1; k++) { | |
718 | int16_t a, b, c; | |
719 | ||
720 | if (!(smu[ro * num + k] && dmu[i])) | |
721 | continue; | |
722 | a = readw_relaxed(index_of + dmu[i]); | |
723 | b = readw_relaxed(index_of + dmu[ro]); | |
724 | c = readw_relaxed(index_of + smu[ro * num + k]); | |
725 | tmp = a + (cw_len - b) + c; | |
726 | a = readw_relaxed(alpha_to + tmp % cw_len); | |
727 | smu[(i + 1) * num + (k + diff)] = a; | |
728 | } | |
729 | ||
730 | for (k = 0; k <= lmu[i] >> 1; k++) | |
731 | smu[(i + 1) * num + k] ^= smu[i * num + k]; | |
732 | } | |
733 | ||
734 | /* End Computing Sigma (Mu+1) and L(mu) */ | |
735 | /* In either case compute delta */ | |
736 | delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1; | |
737 | ||
738 | /* Do not compute discrepancy for the last iteration */ | |
739 | if (i >= cap) | |
740 | continue; | |
741 | ||
742 | for (k = 0; k <= (lmu[i + 1] >> 1); k++) { | |
743 | tmp = 2 * (i - 1); | |
744 | if (k == 0) { | |
745 | dmu[i + 1] = si[tmp + 3]; | |
746 | } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) { | |
747 | int16_t a, b, c; | |
748 | a = readw_relaxed(index_of + | |
749 | smu[(i + 1) * num + k]); | |
750 | b = si[2 * (i - 1) + 3 - k]; | |
751 | c = readw_relaxed(index_of + b); | |
752 | tmp = a + c; | |
753 | tmp %= cw_len; | |
754 | dmu[i + 1] = readw_relaxed(alpha_to + tmp) ^ | |
755 | dmu[i + 1]; | |
756 | } | |
757 | } | |
758 | } | |
759 | ||
760 | return; | |
761 | } | |
762 | ||
763 | static int pmecc_err_location(struct mtd_info *mtd) | |
764 | { | |
765 | struct nand_chip *nand_chip = mtd->priv; | |
766 | struct atmel_nand_host *host = nand_chip->priv; | |
767 | unsigned long end_time; | |
768 | const int cap = host->pmecc_corr_cap; | |
769 | const int num = 2 * cap + 1; | |
770 | int sector_size = host->pmecc_sector_size; | |
771 | int err_nbr = 0; /* number of error */ | |
772 | int roots_nbr; /* number of roots */ | |
773 | int i; | |
774 | uint32_t val; | |
775 | int16_t *smu = host->pmecc_smu; | |
776 | ||
777 | pmerrloc_writel(host->pmerrloc_base, ELDIS, PMERRLOC_DISABLE); | |
778 | ||
779 | for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) { | |
780 | pmerrloc_writel_sigma_relaxed(host->pmerrloc_base, i, | |
781 | smu[(cap + 1) * num + i]); | |
782 | err_nbr++; | |
783 | } | |
784 | ||
785 | val = (err_nbr - 1) << 16; | |
786 | if (sector_size == 1024) | |
787 | val |= 1; | |
788 | ||
789 | pmerrloc_writel(host->pmerrloc_base, ELCFG, val); | |
790 | pmerrloc_writel(host->pmerrloc_base, ELEN, | |
791 | sector_size * 8 + host->pmecc_degree * cap); | |
792 | ||
793 | end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS); | |
794 | while (!(pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR) | |
795 | & PMERRLOC_CALC_DONE)) { | |
796 | if (unlikely(time_after(jiffies, end_time))) { | |
797 | dev_err(host->dev, "PMECC: Timeout to calculate error location.\n"); | |
798 | return -1; | |
799 | } | |
800 | cpu_relax(); | |
801 | } | |
802 | ||
803 | roots_nbr = (pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR) | |
804 | & PMERRLOC_ERR_NUM_MASK) >> 8; | |
805 | /* Number of roots == degree of smu hence <= cap */ | |
806 | if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1) | |
807 | return err_nbr - 1; | |
808 | ||
809 | /* Number of roots does not match the degree of smu | |
810 | * unable to correct error */ | |
811 | return -1; | |
812 | } | |
813 | ||
814 | static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc, | |
815 | int sector_num, int extra_bytes, int err_nbr) | |
816 | { | |
817 | struct nand_chip *nand_chip = mtd->priv; | |
818 | struct atmel_nand_host *host = nand_chip->priv; | |
819 | int i = 0; | |
820 | int byte_pos, bit_pos, sector_size, pos; | |
821 | uint32_t tmp; | |
822 | uint8_t err_byte; | |
823 | ||
824 | sector_size = host->pmecc_sector_size; | |
825 | ||
826 | while (err_nbr) { | |
827 | tmp = pmerrloc_readl_el_relaxed(host->pmerrloc_base, i) - 1; | |
828 | byte_pos = tmp / 8; | |
829 | bit_pos = tmp % 8; | |
830 | ||
831 | if (byte_pos >= (sector_size + extra_bytes)) | |
832 | BUG(); /* should never happen */ | |
833 | ||
834 | if (byte_pos < sector_size) { | |
835 | err_byte = *(buf + byte_pos); | |
836 | *(buf + byte_pos) ^= (1 << bit_pos); | |
837 | ||
838 | pos = sector_num * host->pmecc_sector_size + byte_pos; | |
839 | dev_info(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n", | |
840 | pos, bit_pos, err_byte, *(buf + byte_pos)); | |
841 | } else { | |
842 | /* Bit flip in OOB area */ | |
843 | tmp = sector_num * host->pmecc_bytes_per_sector | |
844 | + (byte_pos - sector_size); | |
845 | err_byte = ecc[tmp]; | |
846 | ecc[tmp] ^= (1 << bit_pos); | |
847 | ||
848 | pos = tmp + nand_chip->ecc.layout->eccpos[0]; | |
849 | dev_info(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n", | |
850 | pos, bit_pos, err_byte, ecc[tmp]); | |
851 | } | |
852 | ||
853 | i++; | |
854 | err_nbr--; | |
855 | } | |
856 | ||
857 | return; | |
858 | } | |
859 | ||
860 | static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf, | |
861 | u8 *ecc) | |
862 | { | |
863 | struct nand_chip *nand_chip = mtd->priv; | |
864 | struct atmel_nand_host *host = nand_chip->priv; | |
865 | int i, err_nbr, eccbytes; | |
866 | uint8_t *buf_pos; | |
c0c70d9e | 867 | int total_err = 0; |
1c7b874d JW |
868 | |
869 | eccbytes = nand_chip->ecc.bytes; | |
870 | for (i = 0; i < eccbytes; i++) | |
871 | if (ecc[i] != 0xff) | |
872 | goto normal_check; | |
873 | /* Erased page, return OK */ | |
874 | return 0; | |
875 | ||
876 | normal_check: | |
877 | for (i = 0; i < host->pmecc_sector_number; i++) { | |
878 | err_nbr = 0; | |
879 | if (pmecc_stat & 0x1) { | |
880 | buf_pos = buf + i * host->pmecc_sector_size; | |
881 | ||
882 | pmecc_gen_syndrome(mtd, i); | |
883 | pmecc_substitute(mtd); | |
884 | pmecc_get_sigma(mtd); | |
885 | ||
886 | err_nbr = pmecc_err_location(mtd); | |
887 | if (err_nbr == -1) { | |
888 | dev_err(host->dev, "PMECC: Too many errors\n"); | |
889 | mtd->ecc_stats.failed++; | |
890 | return -EIO; | |
891 | } else { | |
892 | pmecc_correct_data(mtd, buf_pos, ecc, i, | |
893 | host->pmecc_bytes_per_sector, err_nbr); | |
894 | mtd->ecc_stats.corrected += err_nbr; | |
c0c70d9e | 895 | total_err += err_nbr; |
1c7b874d JW |
896 | } |
897 | } | |
898 | pmecc_stat >>= 1; | |
899 | } | |
900 | ||
c0c70d9e | 901 | return total_err; |
1c7b874d JW |
902 | } |
903 | ||
5ee3d9da JW |
904 | static void pmecc_enable(struct atmel_nand_host *host, int ecc_op) |
905 | { | |
906 | u32 val; | |
907 | ||
5ee3d9da JW |
908 | if (ecc_op != NAND_ECC_READ && ecc_op != NAND_ECC_WRITE) { |
909 | dev_err(host->dev, "atmel_nand: wrong pmecc operation type!"); | |
910 | return; | |
911 | } | |
912 | ||
1fad0e8b JW |
913 | pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST); |
914 | pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE); | |
915 | val = pmecc_readl_relaxed(host->ecc, CFG); | |
916 | ||
5ee3d9da JW |
917 | if (ecc_op == NAND_ECC_READ) |
918 | pmecc_writel(host->ecc, CFG, (val & ~PMECC_CFG_WRITE_OP) | |
919 | | PMECC_CFG_AUTO_ENABLE); | |
920 | else | |
921 | pmecc_writel(host->ecc, CFG, (val | PMECC_CFG_WRITE_OP) | |
922 | & ~PMECC_CFG_AUTO_ENABLE); | |
923 | ||
924 | pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE); | |
925 | pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA); | |
926 | } | |
927 | ||
1c7b874d JW |
928 | static int atmel_nand_pmecc_read_page(struct mtd_info *mtd, |
929 | struct nand_chip *chip, uint8_t *buf, int oob_required, int page) | |
930 | { | |
931 | struct atmel_nand_host *host = chip->priv; | |
932 | int eccsize = chip->ecc.size; | |
933 | uint8_t *oob = chip->oob_poi; | |
934 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
935 | uint32_t stat; | |
936 | unsigned long end_time; | |
c0c70d9e | 937 | int bitflips = 0; |
1c7b874d | 938 | |
1ae9c092 JW |
939 | if (!host->nfc || !host->nfc->use_nfc_sram) |
940 | pmecc_enable(host, NAND_ECC_READ); | |
1c7b874d JW |
941 | |
942 | chip->read_buf(mtd, buf, eccsize); | |
943 | chip->read_buf(mtd, oob, mtd->oobsize); | |
944 | ||
945 | end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS); | |
946 | while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) { | |
947 | if (unlikely(time_after(jiffies, end_time))) { | |
948 | dev_err(host->dev, "PMECC: Timeout to get error status.\n"); | |
949 | return -EIO; | |
950 | } | |
951 | cpu_relax(); | |
952 | } | |
953 | ||
954 | stat = pmecc_readl_relaxed(host->ecc, ISR); | |
c0c70d9e JW |
955 | if (stat != 0) { |
956 | bitflips = pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]); | |
957 | if (bitflips < 0) | |
958 | /* uncorrectable errors */ | |
959 | return 0; | |
960 | } | |
1c7b874d | 961 | |
c0c70d9e | 962 | return bitflips; |
1c7b874d JW |
963 | } |
964 | ||
965 | static int atmel_nand_pmecc_write_page(struct mtd_info *mtd, | |
966 | struct nand_chip *chip, const uint8_t *buf, int oob_required) | |
967 | { | |
968 | struct atmel_nand_host *host = chip->priv; | |
969 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
970 | int i, j; | |
971 | unsigned long end_time; | |
972 | ||
6054d4d5 JW |
973 | if (!host->nfc || !host->nfc->write_by_sram) { |
974 | pmecc_enable(host, NAND_ECC_WRITE); | |
975 | chip->write_buf(mtd, (u8 *)buf, mtd->writesize); | |
976 | } | |
1c7b874d JW |
977 | |
978 | end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS); | |
979 | while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) { | |
980 | if (unlikely(time_after(jiffies, end_time))) { | |
981 | dev_err(host->dev, "PMECC: Timeout to get ECC value.\n"); | |
982 | return -EIO; | |
983 | } | |
984 | cpu_relax(); | |
985 | } | |
986 | ||
987 | for (i = 0; i < host->pmecc_sector_number; i++) { | |
988 | for (j = 0; j < host->pmecc_bytes_per_sector; j++) { | |
989 | int pos; | |
990 | ||
991 | pos = i * host->pmecc_bytes_per_sector + j; | |
992 | chip->oob_poi[eccpos[pos]] = | |
993 | pmecc_readb_ecc_relaxed(host->ecc, i, j); | |
994 | } | |
995 | } | |
996 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
997 | ||
998 | return 0; | |
999 | } | |
1000 | ||
1001 | static void atmel_pmecc_core_init(struct mtd_info *mtd) | |
1002 | { | |
1003 | struct nand_chip *nand_chip = mtd->priv; | |
1004 | struct atmel_nand_host *host = nand_chip->priv; | |
1005 | uint32_t val = 0; | |
1006 | struct nand_ecclayout *ecc_layout; | |
1007 | ||
1008 | pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST); | |
1009 | pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE); | |
1010 | ||
1011 | switch (host->pmecc_corr_cap) { | |
1012 | case 2: | |
1013 | val = PMECC_CFG_BCH_ERR2; | |
1014 | break; | |
1015 | case 4: | |
1016 | val = PMECC_CFG_BCH_ERR4; | |
1017 | break; | |
1018 | case 8: | |
1019 | val = PMECC_CFG_BCH_ERR8; | |
1020 | break; | |
1021 | case 12: | |
1022 | val = PMECC_CFG_BCH_ERR12; | |
1023 | break; | |
1024 | case 24: | |
1025 | val = PMECC_CFG_BCH_ERR24; | |
1026 | break; | |
1027 | } | |
1028 | ||
1029 | if (host->pmecc_sector_size == 512) | |
1030 | val |= PMECC_CFG_SECTOR512; | |
1031 | else if (host->pmecc_sector_size == 1024) | |
1032 | val |= PMECC_CFG_SECTOR1024; | |
1033 | ||
1034 | switch (host->pmecc_sector_number) { | |
1035 | case 1: | |
1036 | val |= PMECC_CFG_PAGE_1SECTOR; | |
1037 | break; | |
1038 | case 2: | |
1039 | val |= PMECC_CFG_PAGE_2SECTORS; | |
1040 | break; | |
1041 | case 4: | |
1042 | val |= PMECC_CFG_PAGE_4SECTORS; | |
1043 | break; | |
1044 | case 8: | |
1045 | val |= PMECC_CFG_PAGE_8SECTORS; | |
1046 | break; | |
1047 | } | |
1048 | ||
1049 | val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE | |
1050 | | PMECC_CFG_AUTO_DISABLE); | |
1051 | pmecc_writel(host->ecc, CFG, val); | |
1052 | ||
1053 | ecc_layout = nand_chip->ecc.layout; | |
1054 | pmecc_writel(host->ecc, SAREA, mtd->oobsize - 1); | |
1055 | pmecc_writel(host->ecc, SADDR, ecc_layout->eccpos[0]); | |
1056 | pmecc_writel(host->ecc, EADDR, | |
1057 | ecc_layout->eccpos[ecc_layout->eccbytes - 1]); | |
1058 | /* See datasheet about PMECC Clock Control Register */ | |
1059 | pmecc_writel(host->ecc, CLK, 2); | |
1060 | pmecc_writel(host->ecc, IDR, 0xff); | |
1061 | pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE); | |
1062 | } | |
1063 | ||
84cfbbb8 JW |
1064 | /* |
1065 | * Get ECC requirement in ONFI parameters, returns -1 if ONFI | |
1066 | * parameters is not supported. | |
1067 | * return 0 if success to get the ECC requirement. | |
1068 | */ | |
1069 | static int get_onfi_ecc_param(struct nand_chip *chip, | |
1070 | int *ecc_bits, int *sector_size) | |
1071 | { | |
1072 | *ecc_bits = *sector_size = 0; | |
1073 | ||
1074 | if (chip->onfi_params.ecc_bits == 0xff) | |
1075 | /* TODO: the sector_size and ecc_bits need to be find in | |
1076 | * extended ecc parameter, currently we don't support it. | |
1077 | */ | |
1078 | return -1; | |
1079 | ||
1080 | *ecc_bits = chip->onfi_params.ecc_bits; | |
1081 | ||
1082 | /* The default sector size (ecc codeword size) is 512 */ | |
1083 | *sector_size = 512; | |
1084 | ||
1085 | return 0; | |
1086 | } | |
1087 | ||
1088 | /* | |
1089 | * Get ecc requirement from ONFI parameters ecc requirement. | |
1090 | * If pmecc-cap, pmecc-sector-size in DTS are not specified, this function | |
1091 | * will set them according to ONFI ecc requirement. Otherwise, use the | |
1092 | * value in DTS file. | |
1093 | * return 0 if success. otherwise return error code. | |
1094 | */ | |
1095 | static int pmecc_choose_ecc(struct atmel_nand_host *host, | |
1096 | int *cap, int *sector_size) | |
1097 | { | |
1098 | /* Get ECC requirement from ONFI parameters */ | |
1099 | *cap = *sector_size = 0; | |
1100 | if (host->nand_chip.onfi_version) { | |
1101 | if (!get_onfi_ecc_param(&host->nand_chip, cap, sector_size)) | |
1102 | dev_info(host->dev, "ONFI params, minimum required ECC: %d bits in %d bytes\n", | |
1103 | *cap, *sector_size); | |
1104 | else | |
1105 | dev_info(host->dev, "NAND chip ECC reqirement is in Extended ONFI parameter, we don't support yet.\n"); | |
1106 | } else { | |
1107 | dev_info(host->dev, "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes"); | |
1108 | } | |
1109 | if (*cap == 0 && *sector_size == 0) { | |
1110 | *cap = 2; | |
1111 | *sector_size = 512; | |
1112 | } | |
1113 | ||
1114 | /* If dts file doesn't specify then use the one in ONFI parameters */ | |
1115 | if (host->pmecc_corr_cap == 0) { | |
1116 | /* use the most fitable ecc bits (the near bigger one ) */ | |
1117 | if (*cap <= 2) | |
1118 | host->pmecc_corr_cap = 2; | |
1119 | else if (*cap <= 4) | |
1120 | host->pmecc_corr_cap = 4; | |
edc9cba4 | 1121 | else if (*cap <= 8) |
84cfbbb8 | 1122 | host->pmecc_corr_cap = 8; |
edc9cba4 | 1123 | else if (*cap <= 12) |
84cfbbb8 | 1124 | host->pmecc_corr_cap = 12; |
edc9cba4 | 1125 | else if (*cap <= 24) |
84cfbbb8 JW |
1126 | host->pmecc_corr_cap = 24; |
1127 | else | |
1128 | return -EINVAL; | |
1129 | } | |
1130 | if (host->pmecc_sector_size == 0) { | |
1131 | /* use the most fitable sector size (the near smaller one ) */ | |
1132 | if (*sector_size >= 1024) | |
1133 | host->pmecc_sector_size = 1024; | |
1134 | else if (*sector_size >= 512) | |
1135 | host->pmecc_sector_size = 512; | |
1136 | else | |
1137 | return -EINVAL; | |
1138 | } | |
1139 | return 0; | |
1140 | } | |
1141 | ||
1c7b874d JW |
1142 | static int __init atmel_pmecc_nand_init_params(struct platform_device *pdev, |
1143 | struct atmel_nand_host *host) | |
1144 | { | |
1145 | struct mtd_info *mtd = &host->mtd; | |
1146 | struct nand_chip *nand_chip = &host->nand_chip; | |
1147 | struct resource *regs, *regs_pmerr, *regs_rom; | |
1148 | int cap, sector_size, err_no; | |
1149 | ||
84cfbbb8 JW |
1150 | err_no = pmecc_choose_ecc(host, &cap, §or_size); |
1151 | if (err_no) { | |
1152 | dev_err(host->dev, "The NAND flash's ECC requirement are not support!"); | |
1153 | return err_no; | |
1154 | } | |
1155 | ||
f666d649 | 1156 | if (cap > host->pmecc_corr_cap || |
84cfbbb8 JW |
1157 | sector_size != host->pmecc_sector_size) |
1158 | dev_info(host->dev, "WARNING: Be Caution! Using different PMECC parameters from Nand ONFI ECC reqirement.\n"); | |
e66b4318 | 1159 | |
1c7b874d JW |
1160 | cap = host->pmecc_corr_cap; |
1161 | sector_size = host->pmecc_sector_size; | |
e66b4318 JW |
1162 | host->pmecc_lookup_table_offset = (sector_size == 512) ? |
1163 | host->pmecc_lookup_table_offset_512 : | |
1164 | host->pmecc_lookup_table_offset_1024; | |
1165 | ||
1c7b874d JW |
1166 | dev_info(host->dev, "Initialize PMECC params, cap: %d, sector: %d\n", |
1167 | cap, sector_size); | |
1168 | ||
1169 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1170 | if (!regs) { | |
1171 | dev_warn(host->dev, | |
1172 | "Can't get I/O resource regs for PMECC controller, rolling back on software ECC\n"); | |
1173 | nand_chip->ecc.mode = NAND_ECC_SOFT; | |
1174 | return 0; | |
1175 | } | |
1176 | ||
0d63748d JCPV |
1177 | host->ecc = devm_ioremap_resource(&pdev->dev, regs); |
1178 | if (IS_ERR(host->ecc)) { | |
1c7b874d | 1179 | dev_err(host->dev, "ioremap failed\n"); |
0d63748d JCPV |
1180 | err_no = PTR_ERR(host->ecc); |
1181 | goto err; | |
1c7b874d JW |
1182 | } |
1183 | ||
1184 | regs_pmerr = platform_get_resource(pdev, IORESOURCE_MEM, 2); | |
0d63748d JCPV |
1185 | host->pmerrloc_base = devm_ioremap_resource(&pdev->dev, regs_pmerr); |
1186 | if (IS_ERR(host->pmerrloc_base)) { | |
1187 | dev_err(host->dev, | |
1188 | "Can not get I/O resource for PMECC ERRLOC controller!\n"); | |
1189 | err_no = PTR_ERR(host->pmerrloc_base); | |
1190 | goto err; | |
1c7b874d JW |
1191 | } |
1192 | ||
0d63748d JCPV |
1193 | regs_rom = platform_get_resource(pdev, IORESOURCE_MEM, 3); |
1194 | host->pmecc_rom_base = devm_ioremap_resource(&pdev->dev, regs_rom); | |
1195 | if (IS_ERR(host->pmecc_rom_base)) { | |
1196 | dev_err(host->dev, "Can not get I/O resource for ROM!\n"); | |
1197 | err_no = PTR_ERR(host->pmecc_rom_base); | |
1198 | goto err; | |
1c7b874d JW |
1199 | } |
1200 | ||
1201 | /* ECC is calculated for the whole page (1 step) */ | |
1202 | nand_chip->ecc.size = mtd->writesize; | |
1203 | ||
1204 | /* set ECC page size and oob layout */ | |
1205 | switch (mtd->writesize) { | |
1206 | case 2048: | |
2fa831f9 JW |
1207 | host->pmecc_degree = (sector_size == 512) ? |
1208 | PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14; | |
1c7b874d JW |
1209 | host->pmecc_cw_len = (1 << host->pmecc_degree) - 1; |
1210 | host->pmecc_sector_number = mtd->writesize / sector_size; | |
1211 | host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes( | |
1212 | cap, sector_size); | |
1213 | host->pmecc_alpha_to = pmecc_get_alpha_to(host); | |
1214 | host->pmecc_index_of = host->pmecc_rom_base + | |
1215 | host->pmecc_lookup_table_offset; | |
1216 | ||
1217 | nand_chip->ecc.steps = 1; | |
1218 | nand_chip->ecc.strength = cap; | |
1219 | nand_chip->ecc.bytes = host->pmecc_bytes_per_sector * | |
1220 | host->pmecc_sector_number; | |
1221 | if (nand_chip->ecc.bytes > mtd->oobsize - 2) { | |
1222 | dev_err(host->dev, "No room for ECC bytes\n"); | |
1223 | err_no = -EINVAL; | |
0d63748d | 1224 | goto err; |
1c7b874d JW |
1225 | } |
1226 | pmecc_config_ecc_layout(&atmel_pmecc_oobinfo, | |
1227 | mtd->oobsize, | |
1228 | nand_chip->ecc.bytes); | |
1229 | nand_chip->ecc.layout = &atmel_pmecc_oobinfo; | |
1230 | break; | |
1231 | case 512: | |
1232 | case 1024: | |
1233 | case 4096: | |
1234 | /* TODO */ | |
1235 | dev_warn(host->dev, | |
1236 | "Unsupported page size for PMECC, use Software ECC\n"); | |
1237 | default: | |
1238 | /* page size not handled by HW ECC */ | |
1239 | /* switching back to soft ECC */ | |
1240 | nand_chip->ecc.mode = NAND_ECC_SOFT; | |
1241 | return 0; | |
1242 | } | |
1243 | ||
1244 | /* Allocate data for PMECC computation */ | |
1245 | err_no = pmecc_data_alloc(host); | |
1246 | if (err_no) { | |
1247 | dev_err(host->dev, | |
1248 | "Cannot allocate memory for PMECC computation!\n"); | |
0d63748d | 1249 | goto err; |
1c7b874d JW |
1250 | } |
1251 | ||
1252 | nand_chip->ecc.read_page = atmel_nand_pmecc_read_page; | |
1253 | nand_chip->ecc.write_page = atmel_nand_pmecc_write_page; | |
1254 | ||
1255 | atmel_pmecc_core_init(mtd); | |
1256 | ||
1257 | return 0; | |
1258 | ||
0d63748d | 1259 | err: |
1c7b874d JW |
1260 | return err_no; |
1261 | } | |
1262 | ||
77f5492c RG |
1263 | /* |
1264 | * Calculate HW ECC | |
1265 | * | |
1266 | * function called after a write | |
1267 | * | |
1268 | * mtd: MTD block structure | |
1269 | * dat: raw data (unused) | |
1270 | * ecc_code: buffer for ECC | |
1271 | */ | |
3c3796cc | 1272 | static int atmel_nand_calculate(struct mtd_info *mtd, |
77f5492c RG |
1273 | const u_char *dat, unsigned char *ecc_code) |
1274 | { | |
1275 | struct nand_chip *nand_chip = mtd->priv; | |
3c3796cc | 1276 | struct atmel_nand_host *host = nand_chip->priv; |
77f5492c RG |
1277 | unsigned int ecc_value; |
1278 | ||
1279 | /* get the first 2 ECC bytes */ | |
d43fa149 | 1280 | ecc_value = ecc_readl(host->ecc, PR); |
77f5492c | 1281 | |
3fc23898 RG |
1282 | ecc_code[0] = ecc_value & 0xFF; |
1283 | ecc_code[1] = (ecc_value >> 8) & 0xFF; | |
77f5492c RG |
1284 | |
1285 | /* get the last 2 ECC bytes */ | |
3c3796cc | 1286 | ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY; |
77f5492c | 1287 | |
3fc23898 RG |
1288 | ecc_code[2] = ecc_value & 0xFF; |
1289 | ecc_code[3] = (ecc_value >> 8) & 0xFF; | |
77f5492c RG |
1290 | |
1291 | return 0; | |
1292 | } | |
1293 | ||
1294 | /* | |
1295 | * HW ECC read page function | |
1296 | * | |
1297 | * mtd: mtd info structure | |
1298 | * chip: nand chip info structure | |
1299 | * buf: buffer to store read data | |
1fbb938d | 1300 | * oob_required: caller expects OOB data read to chip->oob_poi |
77f5492c | 1301 | */ |
1fbb938d BN |
1302 | static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip, |
1303 | uint8_t *buf, int oob_required, int page) | |
77f5492c RG |
1304 | { |
1305 | int eccsize = chip->ecc.size; | |
1306 | int eccbytes = chip->ecc.bytes; | |
1307 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1308 | uint8_t *p = buf; | |
1309 | uint8_t *oob = chip->oob_poi; | |
1310 | uint8_t *ecc_pos; | |
1311 | int stat; | |
3f91e94f | 1312 | unsigned int max_bitflips = 0; |
77f5492c | 1313 | |
d6248fdd HS |
1314 | /* |
1315 | * Errata: ALE is incorrectly wired up to the ECC controller | |
1316 | * on the AP7000, so it will include the address cycles in the | |
1317 | * ECC calculation. | |
1318 | * | |
1319 | * Workaround: Reset the parity registers before reading the | |
1320 | * actual data. | |
1321 | */ | |
71b94e2e JW |
1322 | struct atmel_nand_host *host = chip->priv; |
1323 | if (host->board.need_reset_workaround) | |
d6248fdd | 1324 | ecc_writel(host->ecc, CR, ATMEL_ECC_RST); |
d6248fdd | 1325 | |
77f5492c RG |
1326 | /* read the page */ |
1327 | chip->read_buf(mtd, p, eccsize); | |
1328 | ||
1329 | /* move to ECC position if needed */ | |
1330 | if (eccpos[0] != 0) { | |
1331 | /* This only works on large pages | |
1332 | * because the ECC controller waits for | |
1333 | * NAND_CMD_RNDOUTSTART after the | |
1334 | * NAND_CMD_RNDOUT. | |
1335 | * anyway, for small pages, the eccpos[0] == 0 | |
1336 | */ | |
1337 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, | |
1338 | mtd->writesize + eccpos[0], -1); | |
1339 | } | |
1340 | ||
1341 | /* the ECC controller needs to read the ECC just after the data */ | |
1342 | ecc_pos = oob + eccpos[0]; | |
1343 | chip->read_buf(mtd, ecc_pos, eccbytes); | |
1344 | ||
1345 | /* check if there's an error */ | |
1346 | stat = chip->ecc.correct(mtd, p, oob, NULL); | |
1347 | ||
3f91e94f | 1348 | if (stat < 0) { |
77f5492c | 1349 | mtd->ecc_stats.failed++; |
3f91e94f | 1350 | } else { |
77f5492c | 1351 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1352 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1353 | } | |
77f5492c RG |
1354 | |
1355 | /* get back to oob start (end of page) */ | |
1356 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1); | |
1357 | ||
1358 | /* read the oob */ | |
1359 | chip->read_buf(mtd, oob, mtd->oobsize); | |
1360 | ||
3f91e94f | 1361 | return max_bitflips; |
77f5492c RG |
1362 | } |
1363 | ||
1364 | /* | |
1365 | * HW ECC Correction | |
1366 | * | |
1367 | * function called after a read | |
1368 | * | |
1369 | * mtd: MTD block structure | |
1370 | * dat: raw data read from the chip | |
1371 | * read_ecc: ECC from the chip (unused) | |
1372 | * isnull: unused | |
1373 | * | |
1374 | * Detect and correct a 1 bit error for a page | |
1375 | */ | |
3c3796cc | 1376 | static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat, |
77f5492c RG |
1377 | u_char *read_ecc, u_char *isnull) |
1378 | { | |
1379 | struct nand_chip *nand_chip = mtd->priv; | |
3c3796cc | 1380 | struct atmel_nand_host *host = nand_chip->priv; |
77f5492c RG |
1381 | unsigned int ecc_status; |
1382 | unsigned int ecc_word, ecc_bit; | |
1383 | ||
1384 | /* get the status from the Status Register */ | |
1385 | ecc_status = ecc_readl(host->ecc, SR); | |
1386 | ||
1387 | /* if there's no error */ | |
3c3796cc | 1388 | if (likely(!(ecc_status & ATMEL_ECC_RECERR))) |
77f5492c RG |
1389 | return 0; |
1390 | ||
1391 | /* get error bit offset (4 bits) */ | |
3c3796cc | 1392 | ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR; |
77f5492c | 1393 | /* get word address (12 bits) */ |
3c3796cc | 1394 | ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR; |
77f5492c RG |
1395 | ecc_word >>= 4; |
1396 | ||
1397 | /* if there are multiple errors */ | |
3c3796cc | 1398 | if (ecc_status & ATMEL_ECC_MULERR) { |
77f5492c RG |
1399 | /* check if it is a freshly erased block |
1400 | * (filled with 0xff) */ | |
3c3796cc HS |
1401 | if ((ecc_bit == ATMEL_ECC_BITADDR) |
1402 | && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) { | |
77f5492c RG |
1403 | /* the block has just been erased, return OK */ |
1404 | return 0; | |
1405 | } | |
1406 | /* it doesn't seems to be a freshly | |
1407 | * erased block. | |
1408 | * We can't correct so many errors */ | |
3c3796cc | 1409 | dev_dbg(host->dev, "atmel_nand : multiple errors detected." |
77f5492c RG |
1410 | " Unable to correct.\n"); |
1411 | return -EIO; | |
1412 | } | |
1413 | ||
1414 | /* if there's a single bit error : we can correct it */ | |
3c3796cc | 1415 | if (ecc_status & ATMEL_ECC_ECCERR) { |
77f5492c RG |
1416 | /* there's nothing much to do here. |
1417 | * the bit error is on the ECC itself. | |
1418 | */ | |
3c3796cc | 1419 | dev_dbg(host->dev, "atmel_nand : one bit error on ECC code." |
77f5492c RG |
1420 | " Nothing to correct\n"); |
1421 | return 0; | |
1422 | } | |
1423 | ||
3c3796cc | 1424 | dev_dbg(host->dev, "atmel_nand : one bit error on data." |
77f5492c RG |
1425 | " (word offset in the page :" |
1426 | " 0x%x bit offset : 0x%x)\n", | |
1427 | ecc_word, ecc_bit); | |
1428 | /* correct the error */ | |
1429 | if (nand_chip->options & NAND_BUSWIDTH_16) { | |
1430 | /* 16 bits words */ | |
1431 | ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit); | |
1432 | } else { | |
1433 | /* 8 bits words */ | |
1434 | dat[ecc_word] ^= (1 << ecc_bit); | |
1435 | } | |
3c3796cc | 1436 | dev_dbg(host->dev, "atmel_nand : error corrected\n"); |
77f5492c RG |
1437 | return 1; |
1438 | } | |
1439 | ||
1440 | /* | |
d6248fdd | 1441 | * Enable HW ECC : unused on most chips |
77f5492c | 1442 | */ |
d6248fdd HS |
1443 | static void atmel_nand_hwctl(struct mtd_info *mtd, int mode) |
1444 | { | |
71b94e2e JW |
1445 | struct nand_chip *nand_chip = mtd->priv; |
1446 | struct atmel_nand_host *host = nand_chip->priv; | |
1447 | ||
1448 | if (host->board.need_reset_workaround) | |
d6248fdd | 1449 | ecc_writel(host->ecc, CR, ATMEL_ECC_RST); |
d6248fdd | 1450 | } |
77f5492c | 1451 | |
d6a01661 | 1452 | #if defined(CONFIG_OF) |
06f25510 | 1453 | static int atmel_of_init_port(struct atmel_nand_host *host, |
d8929942 | 1454 | struct device_node *np) |
d6a01661 | 1455 | { |
c0cf787f | 1456 | u32 val; |
a41b51a1 | 1457 | u32 offset[2]; |
d6a01661 JCPV |
1458 | int ecc_mode; |
1459 | struct atmel_nand_data *board = &host->board; | |
1460 | enum of_gpio_flags flags; | |
1461 | ||
1462 | if (of_property_read_u32(np, "atmel,nand-addr-offset", &val) == 0) { | |
1463 | if (val >= 32) { | |
1464 | dev_err(host->dev, "invalid addr-offset %u\n", val); | |
1465 | return -EINVAL; | |
1466 | } | |
1467 | board->ale = val; | |
1468 | } | |
1469 | ||
1470 | if (of_property_read_u32(np, "atmel,nand-cmd-offset", &val) == 0) { | |
1471 | if (val >= 32) { | |
1472 | dev_err(host->dev, "invalid cmd-offset %u\n", val); | |
1473 | return -EINVAL; | |
1474 | } | |
1475 | board->cle = val; | |
1476 | } | |
1477 | ||
1478 | ecc_mode = of_get_nand_ecc_mode(np); | |
1479 | ||
1480 | board->ecc_mode = ecc_mode < 0 ? NAND_ECC_SOFT : ecc_mode; | |
1481 | ||
1482 | board->on_flash_bbt = of_get_nand_on_flash_bbt(np); | |
1483 | ||
1b719265 JW |
1484 | board->has_dma = of_property_read_bool(np, "atmel,nand-has-dma"); |
1485 | ||
d6a01661 JCPV |
1486 | if (of_get_nand_bus_width(np) == 16) |
1487 | board->bus_width_16 = 1; | |
1488 | ||
1489 | board->rdy_pin = of_get_gpio_flags(np, 0, &flags); | |
1490 | board->rdy_pin_active_low = (flags == OF_GPIO_ACTIVE_LOW); | |
1491 | ||
1492 | board->enable_pin = of_get_gpio(np, 1); | |
1493 | board->det_pin = of_get_gpio(np, 2); | |
1494 | ||
a41b51a1 JW |
1495 | host->has_pmecc = of_property_read_bool(np, "atmel,has-pmecc"); |
1496 | ||
7dc37de7 JW |
1497 | /* load the nfc driver if there is */ |
1498 | of_platform_populate(np, NULL, NULL, host->dev); | |
1499 | ||
a41b51a1 JW |
1500 | if (!(board->ecc_mode == NAND_ECC_HW) || !host->has_pmecc) |
1501 | return 0; /* Not using PMECC */ | |
1502 | ||
1503 | /* use PMECC, get correction capability, sector size and lookup | |
1504 | * table offset. | |
e66b4318 JW |
1505 | * If correction bits and sector size are not specified, then find |
1506 | * them from NAND ONFI parameters. | |
a41b51a1 | 1507 | */ |
e66b4318 JW |
1508 | if (of_property_read_u32(np, "atmel,pmecc-cap", &val) == 0) { |
1509 | if ((val != 2) && (val != 4) && (val != 8) && (val != 12) && | |
1510 | (val != 24)) { | |
1511 | dev_err(host->dev, | |
1512 | "Unsupported PMECC correction capability: %d; should be 2, 4, 8, 12 or 24\n", | |
1513 | val); | |
1514 | return -EINVAL; | |
1515 | } | |
1516 | host->pmecc_corr_cap = (u8)val; | |
a41b51a1 | 1517 | } |
a41b51a1 | 1518 | |
e66b4318 JW |
1519 | if (of_property_read_u32(np, "atmel,pmecc-sector-size", &val) == 0) { |
1520 | if ((val != 512) && (val != 1024)) { | |
1521 | dev_err(host->dev, | |
1522 | "Unsupported PMECC sector size: %d; should be 512 or 1024 bytes\n", | |
1523 | val); | |
1524 | return -EINVAL; | |
1525 | } | |
1526 | host->pmecc_sector_size = (u16)val; | |
a41b51a1 | 1527 | } |
a41b51a1 JW |
1528 | |
1529 | if (of_property_read_u32_array(np, "atmel,pmecc-lookup-table-offset", | |
1530 | offset, 2) != 0) { | |
1531 | dev_err(host->dev, "Cannot get PMECC lookup table offset\n"); | |
1532 | return -EINVAL; | |
1533 | } | |
c0cf787f | 1534 | if (!offset[0] && !offset[1]) { |
a41b51a1 JW |
1535 | dev_err(host->dev, "Invalid PMECC lookup table offset\n"); |
1536 | return -EINVAL; | |
1537 | } | |
e66b4318 JW |
1538 | host->pmecc_lookup_table_offset_512 = offset[0]; |
1539 | host->pmecc_lookup_table_offset_1024 = offset[1]; | |
a41b51a1 | 1540 | |
d6a01661 JCPV |
1541 | return 0; |
1542 | } | |
1543 | #else | |
06f25510 | 1544 | static int atmel_of_init_port(struct atmel_nand_host *host, |
d8929942 | 1545 | struct device_node *np) |
d6a01661 JCPV |
1546 | { |
1547 | return -EINVAL; | |
1548 | } | |
1549 | #endif | |
1550 | ||
3dfe41a4 JW |
1551 | static int __init atmel_hw_nand_init_params(struct platform_device *pdev, |
1552 | struct atmel_nand_host *host) | |
1553 | { | |
1554 | struct mtd_info *mtd = &host->mtd; | |
1555 | struct nand_chip *nand_chip = &host->nand_chip; | |
1556 | struct resource *regs; | |
1557 | ||
1558 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1559 | if (!regs) { | |
1560 | dev_err(host->dev, | |
1561 | "Can't get I/O resource regs, use software ECC\n"); | |
1562 | nand_chip->ecc.mode = NAND_ECC_SOFT; | |
1563 | return 0; | |
1564 | } | |
1565 | ||
0d63748d JCPV |
1566 | host->ecc = devm_ioremap_resource(&pdev->dev, regs); |
1567 | if (IS_ERR(host->ecc)) { | |
3dfe41a4 | 1568 | dev_err(host->dev, "ioremap failed\n"); |
0d63748d | 1569 | return PTR_ERR(host->ecc); |
3dfe41a4 JW |
1570 | } |
1571 | ||
1572 | /* ECC is calculated for the whole page (1 step) */ | |
1573 | nand_chip->ecc.size = mtd->writesize; | |
1574 | ||
1575 | /* set ECC page size and oob layout */ | |
1576 | switch (mtd->writesize) { | |
1577 | case 512: | |
1578 | nand_chip->ecc.layout = &atmel_oobinfo_small; | |
1579 | ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528); | |
1580 | break; | |
1581 | case 1024: | |
1582 | nand_chip->ecc.layout = &atmel_oobinfo_large; | |
1583 | ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056); | |
1584 | break; | |
1585 | case 2048: | |
1586 | nand_chip->ecc.layout = &atmel_oobinfo_large; | |
1587 | ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112); | |
1588 | break; | |
1589 | case 4096: | |
1590 | nand_chip->ecc.layout = &atmel_oobinfo_large; | |
1591 | ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224); | |
1592 | break; | |
1593 | default: | |
1594 | /* page size not handled by HW ECC */ | |
1595 | /* switching back to soft ECC */ | |
1596 | nand_chip->ecc.mode = NAND_ECC_SOFT; | |
1597 | return 0; | |
1598 | } | |
1599 | ||
1600 | /* set up for HW ECC */ | |
1601 | nand_chip->ecc.calculate = atmel_nand_calculate; | |
1602 | nand_chip->ecc.correct = atmel_nand_correct; | |
1603 | nand_chip->ecc.hwctl = atmel_nand_hwctl; | |
1604 | nand_chip->ecc.read_page = atmel_nand_read_page; | |
1605 | nand_chip->ecc.bytes = 4; | |
1606 | nand_chip->ecc.strength = 1; | |
1607 | ||
1608 | return 0; | |
1609 | } | |
1610 | ||
7dc37de7 JW |
1611 | /* SMC interrupt service routine */ |
1612 | static irqreturn_t hsmc_interrupt(int irq, void *dev_id) | |
1613 | { | |
1614 | struct atmel_nand_host *host = dev_id; | |
1615 | u32 status, mask, pending; | |
1616 | irqreturn_t ret = IRQ_HANDLED; | |
1617 | ||
1618 | status = nfc_readl(host->nfc->hsmc_regs, SR); | |
1619 | mask = nfc_readl(host->nfc->hsmc_regs, IMR); | |
1620 | pending = status & mask; | |
1621 | ||
1622 | if (pending & NFC_SR_XFR_DONE) { | |
1623 | complete(&host->nfc->comp_nfc); | |
1624 | nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_XFR_DONE); | |
1625 | } else if (pending & NFC_SR_RB_EDGE) { | |
1626 | complete(&host->nfc->comp_nfc); | |
1627 | nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_RB_EDGE); | |
1628 | } else if (pending & NFC_SR_CMD_DONE) { | |
1629 | complete(&host->nfc->comp_nfc); | |
1630 | nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_CMD_DONE); | |
1631 | } else { | |
1632 | ret = IRQ_NONE; | |
1633 | } | |
1634 | ||
1635 | return ret; | |
1636 | } | |
1637 | ||
1638 | /* NFC(Nand Flash Controller) related functions */ | |
1639 | static int nfc_wait_interrupt(struct atmel_nand_host *host, u32 flag) | |
1640 | { | |
1641 | unsigned long timeout; | |
1642 | init_completion(&host->nfc->comp_nfc); | |
1643 | ||
1644 | /* Enable interrupt that need to wait for */ | |
1645 | nfc_writel(host->nfc->hsmc_regs, IER, flag); | |
1646 | ||
1647 | timeout = wait_for_completion_timeout(&host->nfc->comp_nfc, | |
1648 | msecs_to_jiffies(NFC_TIME_OUT_MS)); | |
1649 | if (timeout) | |
1650 | return 0; | |
1651 | ||
1652 | /* Time out to wait for the interrupt */ | |
1653 | dev_err(host->dev, "Time out to wait for interrupt: 0x%08x\n", flag); | |
1654 | return -ETIMEDOUT; | |
1655 | } | |
1656 | ||
1657 | static int nfc_send_command(struct atmel_nand_host *host, | |
1658 | unsigned int cmd, unsigned int addr, unsigned char cycle0) | |
1659 | { | |
1660 | unsigned long timeout; | |
1661 | dev_dbg(host->dev, | |
1662 | "nfc_cmd: 0x%08x, addr1234: 0x%08x, cycle0: 0x%02x\n", | |
1663 | cmd, addr, cycle0); | |
1664 | ||
1665 | timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS); | |
1666 | while (nfc_cmd_readl(NFCADDR_CMD_NFCBUSY, host->nfc->base_cmd_regs) | |
1667 | & NFCADDR_CMD_NFCBUSY) { | |
1668 | if (time_after(jiffies, timeout)) { | |
1669 | dev_err(host->dev, | |
1670 | "Time out to wait CMD_NFCBUSY ready!\n"); | |
1671 | return -ETIMEDOUT; | |
1672 | } | |
1673 | } | |
1674 | nfc_writel(host->nfc->hsmc_regs, CYCLE0, cycle0); | |
1675 | nfc_cmd_addr1234_writel(cmd, addr, host->nfc->base_cmd_regs); | |
1676 | return nfc_wait_interrupt(host, NFC_SR_CMD_DONE); | |
1677 | } | |
1678 | ||
1679 | static int nfc_device_ready(struct mtd_info *mtd) | |
1680 | { | |
1681 | struct nand_chip *nand_chip = mtd->priv; | |
1682 | struct atmel_nand_host *host = nand_chip->priv; | |
1683 | if (!nfc_wait_interrupt(host, NFC_SR_RB_EDGE)) | |
1684 | return 1; | |
1685 | return 0; | |
1686 | } | |
1687 | ||
1688 | static void nfc_select_chip(struct mtd_info *mtd, int chip) | |
1689 | { | |
1690 | struct nand_chip *nand_chip = mtd->priv; | |
1691 | struct atmel_nand_host *host = nand_chip->priv; | |
1692 | ||
1693 | if (chip == -1) | |
1694 | nfc_writel(host->nfc->hsmc_regs, CTRL, NFC_CTRL_DISABLE); | |
1695 | else | |
1696 | nfc_writel(host->nfc->hsmc_regs, CTRL, NFC_CTRL_ENABLE); | |
1697 | } | |
1698 | ||
1699 | static int nfc_make_addr(struct mtd_info *mtd, int column, int page_addr, | |
1700 | unsigned int *addr1234, unsigned int *cycle0) | |
1701 | { | |
1702 | struct nand_chip *chip = mtd->priv; | |
1703 | ||
1704 | int acycle = 0; | |
1705 | unsigned char addr_bytes[8]; | |
1706 | int index = 0, bit_shift; | |
1707 | ||
1708 | BUG_ON(addr1234 == NULL || cycle0 == NULL); | |
1709 | ||
1710 | *cycle0 = 0; | |
1711 | *addr1234 = 0; | |
1712 | ||
1713 | if (column != -1) { | |
1714 | if (chip->options & NAND_BUSWIDTH_16) | |
1715 | column >>= 1; | |
1716 | addr_bytes[acycle++] = column & 0xff; | |
1717 | if (mtd->writesize > 512) | |
1718 | addr_bytes[acycle++] = (column >> 8) & 0xff; | |
1719 | } | |
1720 | ||
1721 | if (page_addr != -1) { | |
1722 | addr_bytes[acycle++] = page_addr & 0xff; | |
1723 | addr_bytes[acycle++] = (page_addr >> 8) & 0xff; | |
1724 | if (chip->chipsize > (128 << 20)) | |
1725 | addr_bytes[acycle++] = (page_addr >> 16) & 0xff; | |
1726 | } | |
1727 | ||
1728 | if (acycle > 4) | |
1729 | *cycle0 = addr_bytes[index++]; | |
1730 | ||
1731 | for (bit_shift = 0; index < acycle; bit_shift += 8) | |
1732 | *addr1234 += addr_bytes[index++] << bit_shift; | |
1733 | ||
1734 | /* return acycle in cmd register */ | |
1735 | return acycle << NFCADDR_CMD_ACYCLE_BIT_POS; | |
1736 | } | |
1737 | ||
1738 | static void nfc_nand_command(struct mtd_info *mtd, unsigned int command, | |
1739 | int column, int page_addr) | |
1740 | { | |
1741 | struct nand_chip *chip = mtd->priv; | |
1742 | struct atmel_nand_host *host = chip->priv; | |
1743 | unsigned long timeout; | |
1744 | unsigned int nfc_addr_cmd = 0; | |
1745 | ||
1746 | unsigned int cmd1 = command << NFCADDR_CMD_CMD1_BIT_POS; | |
1747 | ||
1748 | /* Set default settings: no cmd2, no addr cycle. read from nand */ | |
1749 | unsigned int cmd2 = 0; | |
1750 | unsigned int vcmd2 = 0; | |
1751 | int acycle = NFCADDR_CMD_ACYCLE_NONE; | |
1752 | int csid = NFCADDR_CMD_CSID_3; | |
1753 | int dataen = NFCADDR_CMD_DATADIS; | |
1754 | int nfcwr = NFCADDR_CMD_NFCRD; | |
1755 | unsigned int addr1234 = 0; | |
1756 | unsigned int cycle0 = 0; | |
1757 | bool do_addr = true; | |
1ae9c092 | 1758 | host->nfc->data_in_sram = NULL; |
7dc37de7 JW |
1759 | |
1760 | dev_dbg(host->dev, "%s: cmd = 0x%02x, col = 0x%08x, page = 0x%08x\n", | |
1761 | __func__, command, column, page_addr); | |
1762 | ||
1763 | switch (command) { | |
1764 | case NAND_CMD_RESET: | |
1765 | nfc_addr_cmd = cmd1 | acycle | csid | dataen | nfcwr; | |
1766 | nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0); | |
1767 | udelay(chip->chip_delay); | |
1768 | ||
1769 | nfc_nand_command(mtd, NAND_CMD_STATUS, -1, -1); | |
1770 | timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS); | |
1771 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) { | |
1772 | if (time_after(jiffies, timeout)) { | |
1773 | dev_err(host->dev, | |
1774 | "Time out to wait status ready!\n"); | |
1775 | break; | |
1776 | } | |
1777 | } | |
1778 | return; | |
1779 | case NAND_CMD_STATUS: | |
1780 | do_addr = false; | |
1781 | break; | |
1782 | case NAND_CMD_PARAM: | |
1783 | case NAND_CMD_READID: | |
1784 | do_addr = false; | |
1785 | acycle = NFCADDR_CMD_ACYCLE_1; | |
1786 | if (column != -1) | |
1787 | addr1234 = column; | |
1788 | break; | |
1789 | case NAND_CMD_RNDOUT: | |
1790 | cmd2 = NAND_CMD_RNDOUTSTART << NFCADDR_CMD_CMD2_BIT_POS; | |
1791 | vcmd2 = NFCADDR_CMD_VCMD2; | |
1792 | break; | |
1793 | case NAND_CMD_READ0: | |
1794 | case NAND_CMD_READOOB: | |
1795 | if (command == NAND_CMD_READOOB) { | |
1796 | column += mtd->writesize; | |
1797 | command = NAND_CMD_READ0; /* only READ0 is valid */ | |
1798 | cmd1 = command << NFCADDR_CMD_CMD1_BIT_POS; | |
1799 | } | |
1ae9c092 JW |
1800 | if (host->nfc->use_nfc_sram) { |
1801 | /* Enable Data transfer to sram */ | |
1802 | dataen = NFCADDR_CMD_DATAEN; | |
1803 | ||
1804 | /* Need enable PMECC now, since NFC will transfer | |
1805 | * data in bus after sending nfc read command. | |
1806 | */ | |
1807 | if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc) | |
1808 | pmecc_enable(host, NAND_ECC_READ); | |
1809 | } | |
7dc37de7 JW |
1810 | |
1811 | cmd2 = NAND_CMD_READSTART << NFCADDR_CMD_CMD2_BIT_POS; | |
1812 | vcmd2 = NFCADDR_CMD_VCMD2; | |
1813 | break; | |
1814 | /* For prgramming command, the cmd need set to write enable */ | |
1815 | case NAND_CMD_PAGEPROG: | |
1816 | case NAND_CMD_SEQIN: | |
1817 | case NAND_CMD_RNDIN: | |
1818 | nfcwr = NFCADDR_CMD_NFCWR; | |
6054d4d5 JW |
1819 | if (host->nfc->will_write_sram && command == NAND_CMD_SEQIN) |
1820 | dataen = NFCADDR_CMD_DATAEN; | |
7dc37de7 JW |
1821 | break; |
1822 | default: | |
1823 | break; | |
1824 | } | |
1825 | ||
1826 | if (do_addr) | |
1827 | acycle = nfc_make_addr(mtd, column, page_addr, &addr1234, | |
1828 | &cycle0); | |
1829 | ||
1830 | nfc_addr_cmd = cmd1 | cmd2 | vcmd2 | acycle | csid | dataen | nfcwr; | |
1831 | nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0); | |
1832 | ||
1ae9c092 JW |
1833 | if (dataen == NFCADDR_CMD_DATAEN) |
1834 | if (nfc_wait_interrupt(host, NFC_SR_XFR_DONE)) | |
1835 | dev_err(host->dev, "something wrong, No XFR_DONE interrupt comes.\n"); | |
1836 | ||
7dc37de7 JW |
1837 | /* |
1838 | * Program and erase have their own busy handlers status, sequential | |
1839 | * in, and deplete1 need no delay. | |
1840 | */ | |
1841 | switch (command) { | |
1842 | case NAND_CMD_CACHEDPROG: | |
1843 | case NAND_CMD_PAGEPROG: | |
1844 | case NAND_CMD_ERASE1: | |
1845 | case NAND_CMD_ERASE2: | |
1846 | case NAND_CMD_RNDIN: | |
1847 | case NAND_CMD_STATUS: | |
1848 | case NAND_CMD_RNDOUT: | |
1849 | case NAND_CMD_SEQIN: | |
1850 | case NAND_CMD_READID: | |
1851 | return; | |
1852 | ||
1853 | case NAND_CMD_READ0: | |
1ae9c092 JW |
1854 | if (dataen == NFCADDR_CMD_DATAEN) { |
1855 | host->nfc->data_in_sram = host->nfc->sram_bank0 + | |
1856 | nfc_get_sram_off(host); | |
1857 | return; | |
1858 | } | |
7dc37de7 JW |
1859 | /* fall through */ |
1860 | default: | |
1861 | nfc_wait_interrupt(host, NFC_SR_RB_EDGE); | |
1862 | } | |
1863 | } | |
1864 | ||
6054d4d5 JW |
1865 | static int nfc_sram_write_page(struct mtd_info *mtd, struct nand_chip *chip, |
1866 | uint32_t offset, int data_len, const uint8_t *buf, | |
1867 | int oob_required, int page, int cached, int raw) | |
1868 | { | |
1869 | int cfg, len; | |
1870 | int status = 0; | |
1871 | struct atmel_nand_host *host = chip->priv; | |
1872 | void __iomem *sram = host->nfc->sram_bank0 + nfc_get_sram_off(host); | |
1873 | ||
1874 | /* Subpage write is not supported */ | |
1875 | if (offset || (data_len < mtd->writesize)) | |
1876 | return -EINVAL; | |
1877 | ||
1878 | cfg = nfc_readl(host->nfc->hsmc_regs, CFG); | |
1879 | len = mtd->writesize; | |
1880 | ||
1881 | if (unlikely(raw)) { | |
1882 | len += mtd->oobsize; | |
1883 | nfc_writel(host->nfc->hsmc_regs, CFG, cfg | NFC_CFG_WSPARE); | |
1884 | } else | |
1885 | nfc_writel(host->nfc->hsmc_regs, CFG, cfg & ~NFC_CFG_WSPARE); | |
1886 | ||
1887 | /* Copy page data to sram that will write to nand via NFC */ | |
1888 | if (use_dma) { | |
1889 | if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) != 0) | |
1890 | /* Fall back to use cpu copy */ | |
1891 | memcpy32_toio(sram, buf, len); | |
1892 | } else { | |
1893 | memcpy32_toio(sram, buf, len); | |
1894 | } | |
1895 | ||
1896 | if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc) | |
1897 | /* | |
1898 | * When use NFC sram, need set up PMECC before send | |
1899 | * NAND_CMD_SEQIN command. Since when the nand command | |
1900 | * is sent, nfc will do transfer from sram and nand. | |
1901 | */ | |
1902 | pmecc_enable(host, NAND_ECC_WRITE); | |
1903 | ||
1904 | host->nfc->will_write_sram = true; | |
1905 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); | |
1906 | host->nfc->will_write_sram = false; | |
1907 | ||
1908 | if (likely(!raw)) | |
1909 | /* Need to write ecc into oob */ | |
1910 | status = chip->ecc.write_page(mtd, chip, buf, oob_required); | |
1911 | ||
1912 | if (status < 0) | |
1913 | return status; | |
1914 | ||
1915 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1916 | status = chip->waitfunc(mtd, chip); | |
1917 | ||
1918 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
1919 | status = chip->errstat(mtd, chip, FL_WRITING, status, page); | |
1920 | ||
1921 | if (status & NAND_STATUS_FAIL) | |
1922 | return -EIO; | |
1923 | ||
1924 | return 0; | |
1925 | } | |
1926 | ||
1ae9c092 JW |
1927 | static int nfc_sram_init(struct mtd_info *mtd) |
1928 | { | |
1929 | struct nand_chip *chip = mtd->priv; | |
1930 | struct atmel_nand_host *host = chip->priv; | |
1931 | int res = 0; | |
1932 | ||
1933 | /* Initialize the NFC CFG register */ | |
1934 | unsigned int cfg_nfc = 0; | |
1935 | ||
1936 | /* set page size and oob layout */ | |
1937 | switch (mtd->writesize) { | |
1938 | case 512: | |
1939 | cfg_nfc = NFC_CFG_PAGESIZE_512; | |
1940 | break; | |
1941 | case 1024: | |
1942 | cfg_nfc = NFC_CFG_PAGESIZE_1024; | |
1943 | break; | |
1944 | case 2048: | |
1945 | cfg_nfc = NFC_CFG_PAGESIZE_2048; | |
1946 | break; | |
1947 | case 4096: | |
1948 | cfg_nfc = NFC_CFG_PAGESIZE_4096; | |
1949 | break; | |
1950 | case 8192: | |
1951 | cfg_nfc = NFC_CFG_PAGESIZE_8192; | |
1952 | break; | |
1953 | default: | |
1954 | dev_err(host->dev, "Unsupported page size for NFC.\n"); | |
1955 | res = -ENXIO; | |
1956 | return res; | |
1957 | } | |
1958 | ||
1959 | /* oob bytes size = (NFCSPARESIZE + 1) * 4 | |
1960 | * Max support spare size is 512 bytes. */ | |
1961 | cfg_nfc |= (((mtd->oobsize / 4) - 1) << NFC_CFG_NFC_SPARESIZE_BIT_POS | |
1962 | & NFC_CFG_NFC_SPARESIZE); | |
1963 | /* default set a max timeout */ | |
1964 | cfg_nfc |= NFC_CFG_RSPARE | | |
1965 | NFC_CFG_NFC_DTOCYC | NFC_CFG_NFC_DTOMUL; | |
1966 | ||
1967 | nfc_writel(host->nfc->hsmc_regs, CFG, cfg_nfc); | |
1968 | ||
6054d4d5 | 1969 | host->nfc->will_write_sram = false; |
1ae9c092 JW |
1970 | nfc_set_sram_bank(host, 0); |
1971 | ||
6054d4d5 JW |
1972 | /* Use Write page with NFC SRAM only for PMECC or ECC NONE. */ |
1973 | if (host->nfc->write_by_sram) { | |
1974 | if ((chip->ecc.mode == NAND_ECC_HW && host->has_pmecc) || | |
1975 | chip->ecc.mode == NAND_ECC_NONE) | |
1976 | chip->write_page = nfc_sram_write_page; | |
1977 | else | |
1978 | host->nfc->write_by_sram = false; | |
1979 | } | |
1ae9c092 | 1980 | |
6054d4d5 JW |
1981 | dev_info(host->dev, "Using NFC Sram read %s\n", |
1982 | host->nfc->write_by_sram ? "and write" : ""); | |
1ae9c092 JW |
1983 | return 0; |
1984 | } | |
1985 | ||
7dc37de7 | 1986 | static struct platform_driver atmel_nand_nfc_driver; |
42cb1403 AV |
1987 | /* |
1988 | * Probe for the NAND device. | |
1989 | */ | |
3c3796cc | 1990 | static int __init atmel_nand_probe(struct platform_device *pdev) |
42cb1403 | 1991 | { |
3c3796cc | 1992 | struct atmel_nand_host *host; |
42cb1403 AV |
1993 | struct mtd_info *mtd; |
1994 | struct nand_chip *nand_chip; | |
77f5492c | 1995 | struct resource *mem; |
d6a01661 | 1996 | struct mtd_part_parser_data ppdata = {}; |
7dc37de7 | 1997 | int res, irq; |
42cb1403 AV |
1998 | |
1999 | /* Allocate memory for the device structure (and zero it) */ | |
0d63748d | 2000 | host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); |
42cb1403 | 2001 | if (!host) { |
3c3796cc | 2002 | printk(KERN_ERR "atmel_nand: failed to allocate device structure.\n"); |
42cb1403 AV |
2003 | return -ENOMEM; |
2004 | } | |
2005 | ||
7dc37de7 JW |
2006 | res = platform_driver_register(&atmel_nand_nfc_driver); |
2007 | if (res) | |
2008 | dev_err(&pdev->dev, "atmel_nand: can't register NFC driver\n"); | |
2009 | ||
0d63748d JCPV |
2010 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
2011 | host->io_base = devm_ioremap_resource(&pdev->dev, mem); | |
2012 | if (IS_ERR(host->io_base)) { | |
2013 | dev_err(&pdev->dev, "atmel_nand: ioremap resource failed\n"); | |
2014 | res = PTR_ERR(host->io_base); | |
cc0c72e1 | 2015 | goto err_nand_ioremap; |
42cb1403 | 2016 | } |
0d63748d | 2017 | host->io_phys = (dma_addr_t)mem->start; |
42cb1403 AV |
2018 | |
2019 | mtd = &host->mtd; | |
2020 | nand_chip = &host->nand_chip; | |
77f5492c | 2021 | host->dev = &pdev->dev; |
d6a01661 JCPV |
2022 | if (pdev->dev.of_node) { |
2023 | res = atmel_of_init_port(host, pdev->dev.of_node); | |
2024 | if (res) | |
0d63748d | 2025 | goto err_nand_ioremap; |
d6a01661 | 2026 | } else { |
453810b7 | 2027 | memcpy(&host->board, dev_get_platdata(&pdev->dev), |
d6a01661 JCPV |
2028 | sizeof(struct atmel_nand_data)); |
2029 | } | |
42cb1403 AV |
2030 | |
2031 | nand_chip->priv = host; /* link the private data structures */ | |
2032 | mtd->priv = nand_chip; | |
2033 | mtd->owner = THIS_MODULE; | |
2034 | ||
2035 | /* Set address of NAND IO lines */ | |
2036 | nand_chip->IO_ADDR_R = host->io_base; | |
2037 | nand_chip->IO_ADDR_W = host->io_base; | |
28446acb | 2038 | |
7dc37de7 JW |
2039 | if (nand_nfc.is_initialized) { |
2040 | /* NFC driver is probed and initialized */ | |
2041 | host->nfc = &nand_nfc; | |
28446acb | 2042 | |
7dc37de7 JW |
2043 | nand_chip->select_chip = nfc_select_chip; |
2044 | nand_chip->dev_ready = nfc_device_ready; | |
2045 | nand_chip->cmdfunc = nfc_nand_command; | |
28446acb | 2046 | |
7dc37de7 JW |
2047 | /* Initialize the interrupt for NFC */ |
2048 | irq = platform_get_irq(pdev, 0); | |
2049 | if (irq < 0) { | |
2050 | dev_err(host->dev, "Cannot get HSMC irq!\n"); | |
ff52c67a | 2051 | res = irq; |
0d63748d | 2052 | goto err_nand_ioremap; |
28446acb JCPV |
2053 | } |
2054 | ||
7dc37de7 JW |
2055 | res = devm_request_irq(&pdev->dev, irq, hsmc_interrupt, |
2056 | 0, "hsmc", host); | |
2057 | if (res) { | |
2058 | dev_err(&pdev->dev, "Unable to request HSMC irq %d\n", | |
2059 | irq); | |
0d63748d | 2060 | goto err_nand_ioremap; |
28446acb | 2061 | } |
7dc37de7 JW |
2062 | } else { |
2063 | res = atmel_nand_set_enable_ready_pins(mtd); | |
2064 | if (res) | |
2065 | goto err_nand_ioremap; | |
2066 | ||
2067 | nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl; | |
28446acb | 2068 | } |
a4265f8d | 2069 | |
d6a01661 | 2070 | nand_chip->ecc.mode = host->board.ecc_mode; |
42cb1403 AV |
2071 | nand_chip->chip_delay = 20; /* 20us command delay time */ |
2072 | ||
d6a01661 | 2073 | if (host->board.bus_width_16) /* 16-bit bus width */ |
dd11b8cd | 2074 | nand_chip->options |= NAND_BUSWIDTH_16; |
cbc6c5e7 HX |
2075 | |
2076 | nand_chip->read_buf = atmel_read_buf; | |
2077 | nand_chip->write_buf = atmel_write_buf; | |
dd11b8cd | 2078 | |
42cb1403 | 2079 | platform_set_drvdata(pdev, host); |
3c3796cc | 2080 | atmel_nand_enable(host); |
42cb1403 | 2081 | |
d6a01661 | 2082 | if (gpio_is_valid(host->board.det_pin)) { |
0d63748d JCPV |
2083 | res = devm_gpio_request(&pdev->dev, |
2084 | host->board.det_pin, "nand_det"); | |
28446acb JCPV |
2085 | if (res < 0) { |
2086 | dev_err(&pdev->dev, | |
2087 | "can't request det gpio %d\n", | |
2088 | host->board.det_pin); | |
2089 | goto err_no_card; | |
2090 | } | |
2091 | ||
2092 | res = gpio_direction_input(host->board.det_pin); | |
2093 | if (res < 0) { | |
2094 | dev_err(&pdev->dev, | |
2095 | "can't request input direction det gpio %d\n", | |
2096 | host->board.det_pin); | |
2097 | goto err_no_card; | |
2098 | } | |
2099 | ||
d6a01661 | 2100 | if (gpio_get_value(host->board.det_pin)) { |
f4fa697c | 2101 | printk(KERN_INFO "No SmartMedia card inserted.\n"); |
895fb494 | 2102 | res = -ENXIO; |
cc0c72e1 | 2103 | goto err_no_card; |
42cb1403 AV |
2104 | } |
2105 | } | |
2106 | ||
d6a01661 | 2107 | if (host->board.on_flash_bbt || on_flash_bbt) { |
f4fa697c | 2108 | printk(KERN_INFO "atmel_nand: Use On Flash BBT\n"); |
bb9ebd4e | 2109 | nand_chip->bbt_options |= NAND_BBT_USE_FLASH; |
f4fa697c SP |
2110 | } |
2111 | ||
1b719265 | 2112 | if (!host->board.has_dma) |
cb457a4d HX |
2113 | use_dma = 0; |
2114 | ||
2115 | if (use_dma) { | |
cbc6c5e7 HX |
2116 | dma_cap_mask_t mask; |
2117 | ||
2118 | dma_cap_zero(mask); | |
2119 | dma_cap_set(DMA_MEMCPY, mask); | |
201ab536 | 2120 | host->dma_chan = dma_request_channel(mask, NULL, NULL); |
cbc6c5e7 HX |
2121 | if (!host->dma_chan) { |
2122 | dev_err(host->dev, "Failed to request DMA channel\n"); | |
2123 | use_dma = 0; | |
2124 | } | |
2125 | } | |
2126 | if (use_dma) | |
042bc9c0 NF |
2127 | dev_info(host->dev, "Using %s for DMA transfers.\n", |
2128 | dma_chan_name(host->dma_chan)); | |
cbc6c5e7 HX |
2129 | else |
2130 | dev_info(host->dev, "No DMA support for NAND access.\n"); | |
2131 | ||
77f5492c | 2132 | /* first scan to find the device and get the page size */ |
5e81e88a | 2133 | if (nand_scan_ident(mtd, 1, NULL)) { |
77f5492c | 2134 | res = -ENXIO; |
cc0c72e1 | 2135 | goto err_scan_ident; |
77f5492c RG |
2136 | } |
2137 | ||
3fc23898 | 2138 | if (nand_chip->ecc.mode == NAND_ECC_HW) { |
1c7b874d JW |
2139 | if (host->has_pmecc) |
2140 | res = atmel_pmecc_nand_init_params(pdev, host); | |
2141 | else | |
2142 | res = atmel_hw_nand_init_params(pdev, host); | |
2143 | ||
3dfe41a4 JW |
2144 | if (res != 0) |
2145 | goto err_hw_ecc; | |
77f5492c RG |
2146 | } |
2147 | ||
1ae9c092 JW |
2148 | /* initialize the nfc configuration register */ |
2149 | if (host->nfc && host->nfc->use_nfc_sram) { | |
2150 | res = nfc_sram_init(mtd); | |
2151 | if (res) { | |
2152 | host->nfc->use_nfc_sram = false; | |
2153 | dev_err(host->dev, "Disable use nfc sram for data transfer.\n"); | |
2154 | } | |
2155 | } | |
2156 | ||
77f5492c RG |
2157 | /* second phase scan */ |
2158 | if (nand_scan_tail(mtd)) { | |
42cb1403 | 2159 | res = -ENXIO; |
cc0c72e1 | 2160 | goto err_scan_tail; |
42cb1403 AV |
2161 | } |
2162 | ||
3c3796cc | 2163 | mtd->name = "atmel_nand"; |
d6a01661 JCPV |
2164 | ppdata.of_node = pdev->dev.of_node; |
2165 | res = mtd_device_parse_register(mtd, NULL, &ppdata, | |
2166 | host->board.parts, host->board.num_parts); | |
42cb1403 AV |
2167 | if (!res) |
2168 | return res; | |
2169 | ||
cc0c72e1 | 2170 | err_scan_tail: |
0d63748d | 2171 | if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW) |
1c7b874d | 2172 | pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE); |
3dfe41a4 | 2173 | err_hw_ecc: |
cc0c72e1 HS |
2174 | err_scan_ident: |
2175 | err_no_card: | |
3c3796cc | 2176 | atmel_nand_disable(host); |
cbc6c5e7 HX |
2177 | if (host->dma_chan) |
2178 | dma_release_channel(host->dma_chan); | |
cc0c72e1 | 2179 | err_nand_ioremap: |
7dc37de7 | 2180 | platform_driver_unregister(&atmel_nand_nfc_driver); |
42cb1403 AV |
2181 | return res; |
2182 | } | |
2183 | ||
2184 | /* | |
2185 | * Remove a NAND device. | |
2186 | */ | |
23a346ca | 2187 | static int __exit atmel_nand_remove(struct platform_device *pdev) |
42cb1403 | 2188 | { |
3c3796cc | 2189 | struct atmel_nand_host *host = platform_get_drvdata(pdev); |
42cb1403 AV |
2190 | struct mtd_info *mtd = &host->mtd; |
2191 | ||
2192 | nand_release(mtd); | |
2193 | ||
3c3796cc | 2194 | atmel_nand_disable(host); |
42cb1403 | 2195 | |
1c7b874d JW |
2196 | if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW) { |
2197 | pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE); | |
2198 | pmerrloc_writel(host->pmerrloc_base, ELDIS, | |
2199 | PMERRLOC_DISABLE); | |
1c7b874d JW |
2200 | } |
2201 | ||
cbc6c5e7 HX |
2202 | if (host->dma_chan) |
2203 | dma_release_channel(host->dma_chan); | |
2204 | ||
7dc37de7 JW |
2205 | platform_driver_unregister(&atmel_nand_nfc_driver); |
2206 | ||
42cb1403 AV |
2207 | return 0; |
2208 | } | |
2209 | ||
d6a01661 JCPV |
2210 | #if defined(CONFIG_OF) |
2211 | static const struct of_device_id atmel_nand_dt_ids[] = { | |
2212 | { .compatible = "atmel,at91rm9200-nand" }, | |
2213 | { /* sentinel */ } | |
2214 | }; | |
2215 | ||
2216 | MODULE_DEVICE_TABLE(of, atmel_nand_dt_ids); | |
2217 | #endif | |
2218 | ||
7dc37de7 JW |
2219 | static int atmel_nand_nfc_probe(struct platform_device *pdev) |
2220 | { | |
2221 | struct atmel_nfc *nfc = &nand_nfc; | |
2222 | struct resource *nfc_cmd_regs, *nfc_hsmc_regs, *nfc_sram; | |
2223 | ||
2224 | nfc_cmd_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2225 | nfc->base_cmd_regs = devm_ioremap_resource(&pdev->dev, nfc_cmd_regs); | |
2226 | if (IS_ERR(nfc->base_cmd_regs)) | |
2227 | return PTR_ERR(nfc->base_cmd_regs); | |
2228 | ||
2229 | nfc_hsmc_regs = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
2230 | nfc->hsmc_regs = devm_ioremap_resource(&pdev->dev, nfc_hsmc_regs); | |
2231 | if (IS_ERR(nfc->hsmc_regs)) | |
2232 | return PTR_ERR(nfc->hsmc_regs); | |
2233 | ||
2234 | nfc_sram = platform_get_resource(pdev, IORESOURCE_MEM, 2); | |
2235 | if (nfc_sram) { | |
2236 | nfc->sram_bank0 = devm_ioremap_resource(&pdev->dev, nfc_sram); | |
1ae9c092 | 2237 | if (IS_ERR(nfc->sram_bank0)) { |
7dc37de7 JW |
2238 | dev_warn(&pdev->dev, "Fail to ioremap the NFC sram with error: %ld. So disable NFC sram.\n", |
2239 | PTR_ERR(nfc->sram_bank0)); | |
1ae9c092 JW |
2240 | } else { |
2241 | nfc->use_nfc_sram = true; | |
7dc37de7 | 2242 | nfc->sram_bank0_phys = (dma_addr_t)nfc_sram->start; |
6054d4d5 JW |
2243 | |
2244 | if (pdev->dev.of_node) | |
2245 | nfc->write_by_sram = of_property_read_bool( | |
2246 | pdev->dev.of_node, | |
2247 | "atmel,write-by-sram"); | |
1ae9c092 | 2248 | } |
7dc37de7 JW |
2249 | } |
2250 | ||
2251 | nfc->is_initialized = true; | |
2252 | dev_info(&pdev->dev, "NFC is probed.\n"); | |
2253 | return 0; | |
2254 | } | |
2255 | ||
9fe5f52c | 2256 | #if defined(CONFIG_OF) |
7dc37de7 JW |
2257 | static struct of_device_id atmel_nand_nfc_match[] = { |
2258 | { .compatible = "atmel,sama5d3-nfc" }, | |
2259 | { /* sentinel */ } | |
2260 | }; | |
9fe5f52c | 2261 | #endif |
7dc37de7 JW |
2262 | |
2263 | static struct platform_driver atmel_nand_nfc_driver = { | |
2264 | .driver = { | |
2265 | .name = "atmel_nand_nfc", | |
2266 | .owner = THIS_MODULE, | |
2267 | .of_match_table = of_match_ptr(atmel_nand_nfc_match), | |
2268 | }, | |
2269 | .probe = atmel_nand_nfc_probe, | |
2270 | }; | |
2271 | ||
3c3796cc | 2272 | static struct platform_driver atmel_nand_driver = { |
23a346ca | 2273 | .remove = __exit_p(atmel_nand_remove), |
42cb1403 | 2274 | .driver = { |
3c3796cc | 2275 | .name = "atmel_nand", |
42cb1403 | 2276 | .owner = THIS_MODULE, |
d6a01661 | 2277 | .of_match_table = of_match_ptr(atmel_nand_dt_ids), |
42cb1403 AV |
2278 | }, |
2279 | }; | |
2280 | ||
c5345edf | 2281 | module_platform_driver_probe(atmel_nand_driver, atmel_nand_probe); |
42cb1403 AV |
2282 | |
2283 | MODULE_LICENSE("GPL"); | |
2284 | MODULE_AUTHOR("Rick Bronson"); | |
d4f4c0aa | 2285 | MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32"); |
3c3796cc | 2286 | MODULE_ALIAS("platform:atmel_nand"); |