[deliverable/linux.git] / drivers / mtd / nand / atmel_nand.c

/*
 *  Copyright (C) 2003 Rick Bronson
 *
 *  Derived from drivers/mtd/nand/autcpu12.c
 *	 Copyright (c) 2001 Thomas Gleixner (gleixner@autronix.de)
 *
 *  Derived from drivers/mtd/spia.c
 *	 Copyright (C) 2000 Steven J. Hill (sjhill@cotw.com)
 *
 *
 *  Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
 *     Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright (C) 2007
 *
 *     Derived from Das U-Boot source code
 *     		(u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
 *     (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
 *
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <linux/slab.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>

#include <linux/gpio.h>
#include <linux/io.h>

#include <mach/board.h>
#include <mach/cpu.h>

#ifdef CONFIG_MTD_NAND_ATMEL_ECC_HW
#define hard_ecc	1
#else
#define hard_ecc	0
#endif

#ifdef CONFIG_MTD_NAND_ATMEL_ECC_NONE
#define no_ecc		1
#else
#define no_ecc		0
#endif

/* Register access macros */
#define ecc_readl(add, reg)				\
	__raw_readl(add + ATMEL_ECC_##reg)
#define ecc_writel(add, reg, value)			\
	__raw_writel((value), add + ATMEL_ECC_##reg)

#include "atmel_nand_ecc.h"	/* Hardware ECC registers */

/* oob layout for large page size
 * bad block info is on bytes 0 and 1
 * the bytes have to be consecutives to avoid
 * several NAND_CMD_RNDOUT during read
 */
static struct nand_ecclayout atmel_oobinfo_large = {
	.eccbytes = 4,
	.eccpos = {60, 61, 62, 63},
	.oobfree = {
		{2, 58}
	},
};

/* oob layout for small page size
 * bad block info is on bytes 4 and 5
 * the bytes have to be consecutives to avoid
 * several NAND_CMD_RNDOUT during read
 */
static struct nand_ecclayout atmel_oobinfo_small = {
	.eccbytes = 4,
	.eccpos = {0, 1, 2, 3},
	.oobfree = {
		{6, 10}
	},
};

struct atmel_nand_host {
	struct nand_chip	nand_chip;
	struct mtd_info		mtd;
	void __iomem		*io_base;
	struct atmel_nand_data	*board;
	struct device		*dev;
	void __iomem		*ecc;
};

/*
 * Enable NAND.
 */
static void atmel_nand_enable(struct atmel_nand_host *host)
{
	if (host->board->enable_pin)
		gpio_set_value(host->board->enable_pin, 0);
}

/*
 * Disable NAND.
 */
static void atmel_nand_disable(struct atmel_nand_host *host)
{
	if (host->board->enable_pin)
		gpio_set_value(host->board->enable_pin, 1);
}

/*
 * Hardware specific access to control-lines
 */
static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
	struct nand_chip *nand_chip = mtd->priv;
	struct atmel_nand_host *host = nand_chip->priv;

	if (ctrl & NAND_CTRL_CHANGE) {
		if (ctrl & NAND_NCE)
			atmel_nand_enable(host);
		else
			atmel_nand_disable(host);
	}
	if (cmd == NAND_CMD_NONE)
		return;

	if (ctrl & NAND_CLE)
		writeb(cmd, host->io_base + (1 << host->board->cle));
	else
		writeb(cmd, host->io_base + (1 << host->board->ale));
}

/*
 * Read the Device Ready pin.
 */
static int atmel_nand_device_ready(struct mtd_info *mtd)
{
	struct nand_chip *nand_chip = mtd->priv;
	struct atmel_nand_host *host = nand_chip->priv;

	return gpio_get_value(host->board->rdy_pin);
}

/*
 * Minimal-overhead PIO for data access.
 */
static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
{
	struct nand_chip	*nand_chip = mtd->priv;

	__raw_readsb(nand_chip->IO_ADDR_R, buf, len);
}

static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
{
	struct nand_chip	*nand_chip = mtd->priv;

	__raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
}

static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
{
	struct nand_chip	*nand_chip = mtd->priv;

	__raw_writesb(nand_chip->IO_ADDR_W, buf, len);
}

static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
{
	struct nand_chip	*nand_chip = mtd->priv;

	__raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
}

/*
 * Calculate HW ECC
 *
 * function called after a write
 *
 * mtd:        MTD block structure
 * dat:        raw data (unused)
 * ecc_code:   buffer for ECC
 */
static int atmel_nand_calculate(struct mtd_info *mtd,
		const u_char *dat, unsigned char *ecc_code)
{
	struct nand_chip *nand_chip = mtd->priv;
	struct atmel_nand_host *host = nand_chip->priv;
	uint32_t *eccpos = nand_chip->ecc.layout->eccpos;
	unsigned int ecc_value;

	/* get the first 2 ECC bytes */
	ecc_value = ecc_readl(host->ecc, PR);

	ecc_code[0] = ecc_value & 0xFF;
	ecc_code[1] = (ecc_value >> 8) & 0xFF;

	/* get the last 2 ECC bytes */
	ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY;

	ecc_code[2] = ecc_value & 0xFF;
	ecc_code[3] = (ecc_value >> 8) & 0xFF;

	return 0;
}

/*
 * HW ECC read page function
 *
 * mtd:        mtd info structure
 * chip:       nand chip info structure
 * buf:        buffer to store read data
 */
static int atmel_nand_read_page(struct mtd_info *mtd,
		struct nand_chip *chip, uint8_t *buf)
{
	int eccsize = chip->ecc.size;
	int eccbytes = chip->ecc.bytes;
	uint32_t *eccpos = chip->ecc.layout->eccpos;
	uint8_t *p = buf;
	uint8_t *oob = chip->oob_poi;
	uint8_t *ecc_pos;
	int stat;

	/*
	 * Errata: ALE is incorrectly wired up to the ECC controller
	 * on the AP7000, so it will include the address cycles in the
	 * ECC calculation.
	 *
	 * Workaround: Reset the parity registers before reading the
	 * actual data.
	 */
	if (cpu_is_at32ap7000()) {
		struct atmel_nand_host *host = chip->priv;
		ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
	}

	/* read the page */
	chip->read_buf(mtd, p, eccsize);

	/* move to ECC position if needed */
	if (eccpos[0] != 0) {
		/* This only works on large pages
		 * because the ECC controller waits for
		 * NAND_CMD_RNDOUTSTART after the
		 * NAND_CMD_RNDOUT.
		 * anyway, for small pages, the eccpos[0] == 0
		 */
		chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
				mtd->writesize + eccpos[0], -1);
	}

	/* the ECC controller needs to read the ECC just after the data */
	ecc_pos = oob + eccpos[0];
	chip->read_buf(mtd, ecc_pos, eccbytes);

	/* check if there's an error */
	stat = chip->ecc.correct(mtd, p, oob, NULL);

	if (stat < 0)
		mtd->ecc_stats.failed++;
	else
		mtd->ecc_stats.corrected += stat;

	/* get back to oob start (end of page) */
	chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);

	/* read the oob */
	chip->read_buf(mtd, oob, mtd->oobsize);

	return 0;
}

/*
 * HW ECC Correction
 *
 * function called after a read
 *
 * mtd:        MTD block structure
 * dat:        raw data read from the chip
 * read_ecc:   ECC from the chip (unused)
 * isnull:     unused
 *
 * Detect and correct a 1 bit error for a page
 */
static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
		u_char *read_ecc, u_char *isnull)
{
	struct nand_chip *nand_chip = mtd->priv;
	struct atmel_nand_host *host = nand_chip->priv;
	unsigned int ecc_status;
	unsigned int ecc_word, ecc_bit;

	/* get the status from the Status Register */
	ecc_status = ecc_readl(host->ecc, SR);

	/* if there's no error */
	if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
		return 0;

	/* get error bit offset (4 bits) */
	ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR;
	/* get word address (12 bits) */
	ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR;
	ecc_word >>= 4;

	/* if there are multiple errors */
	if (ecc_status & ATMEL_ECC_MULERR) {
		/* check if it is a freshly erased block
		 * (filled with 0xff) */
		if ((ecc_bit == ATMEL_ECC_BITADDR)
				&& (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
			/* the block has just been erased, return OK */
			return 0;
		}
		/* it doesn't seems to be a freshly
		 * erased block.
		 * We can't correct so many errors */
		dev_dbg(host->dev, "atmel_nand : multiple errors detected."
				" Unable to correct.\n");
		return -EIO;
	}

	/* if there's a single bit error : we can correct it */
	if (ecc_status & ATMEL_ECC_ECCERR) {
		/* there's nothing much to do here.
		 * the bit error is on the ECC itself.
		 */
		dev_dbg(host->dev, "atmel_nand : one bit error on ECC code."
				" Nothing to correct\n");
		return 0;
	}

	dev_dbg(host->dev, "atmel_nand : one bit error on data."
			" (word offset in the page :"
			" 0x%x bit offset : 0x%x)\n",
			ecc_word, ecc_bit);
	/* correct the error */
	if (nand_chip->options & NAND_BUSWIDTH_16) {
		/* 16 bits words */
		((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
	} else {
		/* 8 bits words */
		dat[ecc_word] ^= (1 << ecc_bit);
	}
	dev_dbg(host->dev, "atmel_nand : error corrected\n");
	return 1;
}

/*
 * Enable HW ECC : unused on most chips
 */
static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
{
	if (cpu_is_at32ap7000()) {
		struct nand_chip *nand_chip = mtd->priv;
		struct atmel_nand_host *host = nand_chip->priv;
		ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
	}
}

#ifdef CONFIG_MTD_PARTITIONS
static const char *part_probes[] = { "cmdlinepart", NULL };
#endif

/*
 * Probe for the NAND device.
 */
static int __init atmel_nand_probe(struct platform_device *pdev)
{
	struct atmel_nand_host *host;
	struct mtd_info *mtd;
	struct nand_chip *nand_chip;
	struct resource *regs;
	struct resource *mem;
	int res;

#ifdef CONFIG_MTD_PARTITIONS
	struct mtd_partition *partitions = NULL;
	int num_partitions = 0;
#endif

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!mem) {
		printk(KERN_ERR "atmel_nand: can't get I/O resource mem\n");
		return -ENXIO;
	}

	/* Allocate memory for the device structure (and zero it) */
	host = kzalloc(sizeof(struct atmel_nand_host), GFP_KERNEL);
	if (!host) {
		printk(KERN_ERR "atmel_nand: failed to allocate device structure.\n");
		return -ENOMEM;
	}

	host->io_base = ioremap(mem->start, mem->end - mem->start + 1);
	if (host->io_base == NULL) {
		printk(KERN_ERR "atmel_nand: ioremap failed\n");
		res = -EIO;
		goto err_nand_ioremap;
	}

	mtd = &host->mtd;
	nand_chip = &host->nand_chip;
	host->board = pdev->dev.platform_data;
	host->dev = &pdev->dev;

	nand_chip->priv = host;		/* link the private data structures */
	mtd->priv = nand_chip;
	mtd->owner = THIS_MODULE;

	/* Set address of NAND IO lines */
	nand_chip->IO_ADDR_R = host->io_base;
	nand_chip->IO_ADDR_W = host->io_base;
	nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;

	if (host->board->rdy_pin)
		nand_chip->dev_ready = atmel_nand_device_ready;

	regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	if (!regs && hard_ecc) {
		printk(KERN_ERR "atmel_nand: can't get I/O resource "
				"regs\nFalling back on software ECC\n");
	}

	nand_chip->ecc.mode = NAND_ECC_SOFT;	/* enable ECC */
	if (no_ecc)
		nand_chip->ecc.mode = NAND_ECC_NONE;
	if (hard_ecc && regs) {
		host->ecc = ioremap(regs->start, regs->end - regs->start + 1);
		if (host->ecc == NULL) {
			printk(KERN_ERR "atmel_nand: ioremap failed\n");
			res = -EIO;
			goto err_ecc_ioremap;
		}
		nand_chip->ecc.mode = NAND_ECC_HW;
		nand_chip->ecc.calculate = atmel_nand_calculate;
		nand_chip->ecc.correct = atmel_nand_correct;
		nand_chip->ecc.hwctl = atmel_nand_hwctl;
		nand_chip->ecc.read_page = atmel_nand_read_page;
		nand_chip->ecc.bytes = 4;
	}

	nand_chip->chip_delay = 20;		/* 20us command delay time */

	if (host->board->bus_width_16) {	/* 16-bit bus width */
		nand_chip->options |= NAND_BUSWIDTH_16;
		nand_chip->read_buf = atmel_read_buf16;
		nand_chip->write_buf = atmel_write_buf16;
	} else {
		nand_chip->read_buf = atmel_read_buf;
		nand_chip->write_buf = atmel_write_buf;
	}

	platform_set_drvdata(pdev, host);
	atmel_nand_enable(host);

	if (host->board->det_pin) {
		if (gpio_get_value(host->board->det_pin)) {
			printk("No SmartMedia card inserted.\n");
			res = ENXIO;
			goto err_no_card;
		}
	}

	/* first scan to find the device and get the page size */
	if (nand_scan_ident(mtd, 1)) {
		res = -ENXIO;
		goto err_scan_ident;
	}

	if (nand_chip->ecc.mode == NAND_ECC_HW) {
		/* ECC is calculated for the whole page (1 step) */
		nand_chip->ecc.size = mtd->writesize;

		/* set ECC page size and oob layout */
		switch (mtd->writesize) {
		case 512:
			nand_chip->ecc.layout = &atmel_oobinfo_small;
			ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
			break;
		case 1024:
			nand_chip->ecc.layout = &atmel_oobinfo_large;
			ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
			break;
		case 2048:
			nand_chip->ecc.layout = &atmel_oobinfo_large;
			ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
			break;
		case 4096:
			nand_chip->ecc.layout = &atmel_oobinfo_large;
			ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
			break;
		default:
			/* page size not handled by HW ECC */
			/* switching back to soft ECC */
			nand_chip->ecc.mode = NAND_ECC_SOFT;
			nand_chip->ecc.calculate = NULL;
			nand_chip->ecc.correct = NULL;
			nand_chip->ecc.hwctl = NULL;
			nand_chip->ecc.read_page = NULL;
			nand_chip->ecc.postpad = 0;
			nand_chip->ecc.prepad = 0;
			nand_chip->ecc.bytes = 0;
			break;
		}
	}

	/* second phase scan */
	if (nand_scan_tail(mtd)) {
		res = -ENXIO;
		goto err_scan_tail;
	}

#ifdef CONFIG_MTD_PARTITIONS
#ifdef CONFIG_MTD_CMDLINE_PARTS
	mtd->name = "atmel_nand";
	num_partitions = parse_mtd_partitions(mtd, part_probes,
					      &partitions, 0);
#endif
	if (num_partitions <= 0 && host->board->partition_info)
		partitions = host->board->partition_info(mtd->size,
							 &num_partitions);

	if ((!partitions) || (num_partitions == 0)) {
		printk(KERN_ERR "atmel_nand: No parititions defined, or unsupported device.\n");
		res = ENXIO;
		goto err_no_partitions;
	}

	res = add_mtd_partitions(mtd, partitions, num_partitions);
#else
	res = add_mtd_device(mtd);
#endif

	if (!res)
		return res;

#ifdef CONFIG_MTD_PARTITIONS
err_no_partitions:
#endif
	nand_release(mtd);
err_scan_tail:
err_scan_ident:
err_no_card:
	atmel_nand_disable(host);
	platform_set_drvdata(pdev, NULL);
	if (host->ecc)
		iounmap(host->ecc);
err_ecc_ioremap:
	iounmap(host->io_base);
err_nand_ioremap:
	kfree(host);
	return res;
}

/*
 * Remove a NAND device.
 */
static int __exit atmel_nand_remove(struct platform_device *pdev)
{
	struct atmel_nand_host *host = platform_get_drvdata(pdev);
	struct mtd_info *mtd = &host->mtd;

	nand_release(mtd);

	atmel_nand_disable(host);

	if (host->ecc)
		iounmap(host->ecc);
	iounmap(host->io_base);
	kfree(host);

	return 0;
}

static struct platform_driver atmel_nand_driver = {
	.remove		= __exit_p(atmel_nand_remove),
	.driver		= {
		.name	= "atmel_nand",
		.owner	= THIS_MODULE,
	},
};

static int __init atmel_nand_init(void)
{
	return platform_driver_probe(&atmel_nand_driver, atmel_nand_probe);
}


static void __exit atmel_nand_exit(void)
{
	platform_driver_unregister(&atmel_nand_driver);
}


module_init(atmel_nand_init);
module_exit(atmel_nand_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Rick Bronson");
MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
MODULE_ALIAS("platform:atmel_nand");
Commit	Line	Data
42cb1403	1	/*
42cb1403 AV	2	* Copyright (C) 2003 Rick Bronson
	3	*
	4	* Derived from drivers/mtd/nand/autcpu12.c
	5	* Copyright (c) 2001 Thomas Gleixner (gleixner@autronix.de)
	6	*
	7	* Derived from drivers/mtd/spia.c
	8	* Copyright (C) 2000 Steven J. Hill (sjhill@cotw.com)
	9	*
77f5492c RG	10	*
	11	* Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
	12	* Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright (C) 2007
	13	*
	14	* Derived from Das U-Boot source code
	15	* (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
	16	* (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
	17	*
	18	*
42cb1403 AV	19	* This program is free software; you can redistribute it and/or modify
	20	* it under the terms of the GNU General Public License version 2 as
	21	* published by the Free Software Foundation.
	22	*
	23	*/
	24
	25	#include <linux/slab.h>
	26	#include <linux/module.h>
	27	#include <linux/platform_device.h>
	28	#include <linux/mtd/mtd.h>
	29	#include <linux/mtd/nand.h>
	30	#include <linux/mtd/partitions.h>
	31
90574d0a DW	32	#include <linux/gpio.h>
90574d0a DW	33	#include <linux/io.h>
42cb1403	34
a09e64fb RK	35	#include <mach/board.h>
a09e64fb RK	36	#include <mach/cpu.h>
42cb1403	37
d4f4c0aa	38	#ifdef CONFIG_MTD_NAND_ATMEL_ECC_HW
77f5492c RG	39	#define hard_ecc 1
	40	#else
	41	#define hard_ecc 0
	42	#endif
	43
d4f4c0aa	44	#ifdef CONFIG_MTD_NAND_ATMEL_ECC_NONE
77f5492c RG	45	#define no_ecc 1
	46	#else
	47	#define no_ecc 0
	48	#endif
	49
	50	/* Register access macros */
	51	#define ecc_readl(add, reg) \
3c3796cc	52	__raw_readl(add + ATMEL_ECC_##reg)
77f5492c	53	#define ecc_writel(add, reg, value) \
3c3796cc	54	__raw_writel((value), add + ATMEL_ECC_##reg)
77f5492c	55
d4f4c0aa	56	#include "atmel_nand_ecc.h" /* Hardware ECC registers */
77f5492c RG	57
	58	/* oob layout for large page size
	59	* bad block info is on bytes 0 and 1
	60	* the bytes have to be consecutives to avoid
	61	* several NAND_CMD_RNDOUT during read
	62	*/
3c3796cc	63	static struct nand_ecclayout atmel_oobinfo_large = {
77f5492c RG	64	.eccbytes = 4,
	65	.eccpos = {60, 61, 62, 63},
	66	.oobfree = {
	67	{2, 58}
	68	},
	69	};
	70
	71	/* oob layout for small page size
	72	* bad block info is on bytes 4 and 5
	73	* the bytes have to be consecutives to avoid
	74	* several NAND_CMD_RNDOUT during read
	75	*/
3c3796cc	76	static struct nand_ecclayout atmel_oobinfo_small = {
77f5492c RG	77	.eccbytes = 4,
	78	.eccpos = {0, 1, 2, 3},
	79	.oobfree = {
	80	{6, 10}
	81	},
	82	};
	83
3c3796cc	84	struct atmel_nand_host {
42cb1403 AV	85	struct nand_chip nand_chip;
	86	struct mtd_info mtd;
	87	void __iomem *io_base;
3c3796cc	88	struct atmel_nand_data *board;
77f5492c RG	89	struct device *dev;
77f5492c RG	90	void __iomem *ecc;
42cb1403 AV	91	};
42cb1403 AV	92
8136508c AN	93	/*
	94	* Enable NAND.
	95	*/
3c3796cc	96	static void atmel_nand_enable(struct atmel_nand_host *host)
8136508c AN	97	{
8136508c AN	98	if (host->board->enable_pin)
62fd71fe	99	gpio_set_value(host->board->enable_pin, 0);
8136508c AN	100	}
	101
	102	/*
	103	* Disable NAND.
	104	*/
3c3796cc	105	static void atmel_nand_disable(struct atmel_nand_host *host)
8136508c AN	106	{
8136508c AN	107	if (host->board->enable_pin)
62fd71fe	108	gpio_set_value(host->board->enable_pin, 1);
8136508c AN	109	}
8136508c AN	110
42cb1403 AV	111	/*
	112	* Hardware specific access to control-lines
	113	*/
3c3796cc	114	static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
42cb1403 AV	115	{
42cb1403 AV	116	struct nand_chip *nand_chip = mtd->priv;
3c3796cc	117	struct atmel_nand_host *host = nand_chip->priv;
42cb1403	118
8136508c	119	if (ctrl & NAND_CTRL_CHANGE) {
2314488e	120	if (ctrl & NAND_NCE)
3c3796cc	121	atmel_nand_enable(host);
2314488e	122	else
3c3796cc	123	atmel_nand_disable(host);
2314488e	124	}
42cb1403 AV	125	if (cmd == NAND_CMD_NONE)
	126	return;
	127
	128	if (ctrl & NAND_CLE)
	129	writeb(cmd, host->io_base + (1 << host->board->cle));
	130	else
	131	writeb(cmd, host->io_base + (1 << host->board->ale));
	132	}
	133
	134	/*
	135	* Read the Device Ready pin.
	136	*/
3c3796cc	137	static int atmel_nand_device_ready(struct mtd_info *mtd)
42cb1403 AV	138	{
42cb1403 AV	139	struct nand_chip *nand_chip = mtd->priv;
3c3796cc	140	struct atmel_nand_host *host = nand_chip->priv;
42cb1403	141
62fd71fe	142	return gpio_get_value(host->board->rdy_pin);
42cb1403 AV	143	}
42cb1403 AV	144
23a346ca DB	145	/*
	146	* Minimal-overhead PIO for data access.
	147	*/
	148	static void atmel_read_buf(struct mtd_info mtd, u8 buf, int len)
	149	{
	150	struct nand_chip *nand_chip = mtd->priv;
	151
	152	__raw_readsb(nand_chip->IO_ADDR_R, buf, len);
	153	}
	154
	155	static void atmel_read_buf16(struct mtd_info mtd, u8 buf, int len)
	156	{
	157	struct nand_chip *nand_chip = mtd->priv;
	158
	159	__raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
	160	}
	161
	162	static void atmel_write_buf(struct mtd_info mtd, const u8 buf, int len)
	163	{
	164	struct nand_chip *nand_chip = mtd->priv;
	165
	166	__raw_writesb(nand_chip->IO_ADDR_W, buf, len);
	167	}
	168
	169	static void atmel_write_buf16(struct mtd_info mtd, const u8 buf, int len)
	170	{
	171	struct nand_chip *nand_chip = mtd->priv;
	172
	173	__raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
	174	}
	175
77f5492c RG	176	/*
	177	* Calculate HW ECC
	178	*
	179	* function called after a write
	180	*
	181	* mtd: MTD block structure
	182	* dat: raw data (unused)
	183	* ecc_code: buffer for ECC
	184	*/
3c3796cc	185	static int atmel_nand_calculate(struct mtd_info *mtd,
77f5492c RG	186	const u_char dat, unsigned char ecc_code)
	187	{
	188	struct nand_chip *nand_chip = mtd->priv;
3c3796cc	189	struct atmel_nand_host *host = nand_chip->priv;
77f5492c RG	190	uint32_t *eccpos = nand_chip->ecc.layout->eccpos;
	191	unsigned int ecc_value;
	192
	193	/* get the first 2 ECC bytes */
d43fa149	194	ecc_value = ecc_readl(host->ecc, PR);
77f5492c	195
3fc23898 RG	196	ecc_code[0] = ecc_value & 0xFF;
3fc23898 RG	197	ecc_code[1] = (ecc_value >> 8) & 0xFF;
77f5492c RG	198
77f5492c RG	199	/* get the last 2 ECC bytes */
3c3796cc	200	ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY;
77f5492c	201
3fc23898 RG	202	ecc_code[2] = ecc_value & 0xFF;
3fc23898 RG	203	ecc_code[3] = (ecc_value >> 8) & 0xFF;
77f5492c RG	204
	205	return 0;
	206	}
	207
	208	/*
	209	* HW ECC read page function
	210	*
	211	* mtd: mtd info structure
	212	* chip: nand chip info structure
	213	* buf: buffer to store read data
	214	*/
3c3796cc	215	static int atmel_nand_read_page(struct mtd_info *mtd,
77f5492c RG	216	struct nand_chip chip, uint8_t buf)
	217	{
	218	int eccsize = chip->ecc.size;
	219	int eccbytes = chip->ecc.bytes;
	220	uint32_t *eccpos = chip->ecc.layout->eccpos;
	221	uint8_t *p = buf;
	222	uint8_t *oob = chip->oob_poi;
	223	uint8_t *ecc_pos;
	224	int stat;
	225
d6248fdd HS	226	/*
	227	* Errata: ALE is incorrectly wired up to the ECC controller
	228	* on the AP7000, so it will include the address cycles in the
	229	* ECC calculation.
	230	*
	231	* Workaround: Reset the parity registers before reading the
	232	* actual data.
	233	*/
	234	if (cpu_is_at32ap7000()) {
	235	struct atmel_nand_host *host = chip->priv;
	236	ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
	237	}
	238
77f5492c RG	239	/* read the page */
	240	chip->read_buf(mtd, p, eccsize);
	241
	242	/* move to ECC position if needed */
	243	if (eccpos[0] != 0) {
	244	/* This only works on large pages
	245	* because the ECC controller waits for
	246	* NAND_CMD_RNDOUTSTART after the
	247	* NAND_CMD_RNDOUT.
	248	* anyway, for small pages, the eccpos[0] == 0
	249	*/
	250	chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
	251	mtd->writesize + eccpos[0], -1);
	252	}
	253
	254	/* the ECC controller needs to read the ECC just after the data */
	255	ecc_pos = oob + eccpos[0];
	256	chip->read_buf(mtd, ecc_pos, eccbytes);
	257
	258	/* check if there's an error */
	259	stat = chip->ecc.correct(mtd, p, oob, NULL);
	260
	261	if (stat < 0)
	262	mtd->ecc_stats.failed++;
	263	else
	264	mtd->ecc_stats.corrected += stat;
	265
	266	/* get back to oob start (end of page) */
	267	chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
	268
	269	/* read the oob */
	270	chip->read_buf(mtd, oob, mtd->oobsize);
	271
	272	return 0;
	273	}
	274
	275	/*
	276	* HW ECC Correction
	277	*
	278	* function called after a read
	279	*
	280	* mtd: MTD block structure
	281	* dat: raw data read from the chip
	282	* read_ecc: ECC from the chip (unused)
	283	* isnull: unused
	284	*
	285	* Detect and correct a 1 bit error for a page
	286	*/
3c3796cc	287	static int atmel_nand_correct(struct mtd_info mtd, u_char dat,
77f5492c RG	288	u_char read_ecc, u_char isnull)
	289	{
	290	struct nand_chip *nand_chip = mtd->priv;
3c3796cc	291	struct atmel_nand_host *host = nand_chip->priv;
77f5492c RG	292	unsigned int ecc_status;
	293	unsigned int ecc_word, ecc_bit;
	294
	295	/* get the status from the Status Register */
	296	ecc_status = ecc_readl(host->ecc, SR);
	297
	298	/* if there's no error */
3c3796cc	299	if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
77f5492c RG	300	return 0;
	301
	302	/* get error bit offset (4 bits) */
3c3796cc	303	ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR;
77f5492c	304	/* get word address (12 bits) */
3c3796cc	305	ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR;
77f5492c RG	306	ecc_word >>= 4;
	307
	308	/* if there are multiple errors */
3c3796cc	309	if (ecc_status & ATMEL_ECC_MULERR) {
77f5492c RG	310	/* check if it is a freshly erased block
77f5492c RG	311	* (filled with 0xff) */
3c3796cc HS	312	if ((ecc_bit == ATMEL_ECC_BITADDR)
3c3796cc HS	313	&& (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
77f5492c RG	314	/* the block has just been erased, return OK */
	315	return 0;
	316	}
	317	/* it doesn't seems to be a freshly
	318	* erased block.
	319	* We can't correct so many errors */
3c3796cc	320	dev_dbg(host->dev, "atmel_nand : multiple errors detected."
77f5492c RG	321	" Unable to correct.\n");
	322	return -EIO;
	323	}
	324
	325	/* if there's a single bit error : we can correct it */
3c3796cc	326	if (ecc_status & ATMEL_ECC_ECCERR) {
77f5492c RG	327	/* there's nothing much to do here.
	328	* the bit error is on the ECC itself.
	329	*/
3c3796cc	330	dev_dbg(host->dev, "atmel_nand : one bit error on ECC code."
77f5492c RG	331	" Nothing to correct\n");
	332	return 0;
	333	}
	334
3c3796cc	335	dev_dbg(host->dev, "atmel_nand : one bit error on data."
77f5492c RG	336	" (word offset in the page :"
	337	" 0x%x bit offset : 0x%x)\n",
	338	ecc_word, ecc_bit);
	339	/* correct the error */
	340	if (nand_chip->options & NAND_BUSWIDTH_16) {
	341	/* 16 bits words */
	342	((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
	343	} else {
	344	/* 8 bits words */
	345	dat[ecc_word] ^= (1 << ecc_bit);
	346	}
3c3796cc	347	dev_dbg(host->dev, "atmel_nand : error corrected\n");
77f5492c RG	348	return 1;
	349	}
	350
	351	/*
d6248fdd	352	* Enable HW ECC : unused on most chips
77f5492c	353	*/
d6248fdd HS	354	static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
	355	{
	356	if (cpu_is_at32ap7000()) {
	357	struct nand_chip *nand_chip = mtd->priv;
	358	struct atmel_nand_host *host = nand_chip->priv;
	359	ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
	360	}
	361	}
77f5492c	362
693ef66d	363	#ifdef CONFIG_MTD_PARTITIONS
52f83014	364	static const char *part_probes[] = { "cmdlinepart", NULL };
693ef66d AV	365	#endif
693ef66d AV	366
42cb1403 AV	367	/*
	368	* Probe for the NAND device.
	369	*/
3c3796cc	370	static int __init atmel_nand_probe(struct platform_device *pdev)
42cb1403	371	{
3c3796cc	372	struct atmel_nand_host *host;
42cb1403 AV	373	struct mtd_info *mtd;
42cb1403 AV	374	struct nand_chip *nand_chip;
77f5492c RG	375	struct resource *regs;
77f5492c RG	376	struct resource *mem;
42cb1403 AV	377	int res;
	378
	379	#ifdef CONFIG_MTD_PARTITIONS
	380	struct mtd_partition *partitions = NULL;
	381	int num_partitions = 0;
	382	#endif
	383
cc0c72e1 HS	384	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	385	if (!mem) {
	386	printk(KERN_ERR "atmel_nand: can't get I/O resource mem\n");
	387	return -ENXIO;
	388	}
	389
42cb1403	390	/* Allocate memory for the device structure (and zero it) */
3c3796cc	391	host = kzalloc(sizeof(struct atmel_nand_host), GFP_KERNEL);
42cb1403	392	if (!host) {
3c3796cc	393	printk(KERN_ERR "atmel_nand: failed to allocate device structure.\n");
42cb1403 AV	394	return -ENOMEM;
	395	}
	396
77f5492c	397	host->io_base = ioremap(mem->start, mem->end - mem->start + 1);
42cb1403	398	if (host->io_base == NULL) {
3c3796cc	399	printk(KERN_ERR "atmel_nand: ioremap failed\n");
cc0c72e1 HS	400	res = -EIO;
cc0c72e1 HS	401	goto err_nand_ioremap;
42cb1403 AV	402	}
	403
	404	mtd = &host->mtd;
	405	nand_chip = &host->nand_chip;
	406	host->board = pdev->dev.platform_data;
77f5492c	407	host->dev = &pdev->dev;
42cb1403 AV	408
	409	nand_chip->priv = host; /* link the private data structures */
	410	mtd->priv = nand_chip;
	411	mtd->owner = THIS_MODULE;
	412
	413	/* Set address of NAND IO lines */
	414	nand_chip->IO_ADDR_R = host->io_base;
	415	nand_chip->IO_ADDR_W = host->io_base;
3c3796cc	416	nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
a4265f8d IK	417
a4265f8d IK	418	if (host->board->rdy_pin)
3c3796cc	419	nand_chip->dev_ready = atmel_nand_device_ready;
a4265f8d	420
77f5492c RG	421	regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
77f5492c RG	422	if (!regs && hard_ecc) {
3c3796cc	423	printk(KERN_ERR "atmel_nand: can't get I/O resource "
77f5492c RG	424	"regs\nFalling back on software ECC\n");
	425	}
	426
42cb1403	427	nand_chip->ecc.mode = NAND_ECC_SOFT; /* enable ECC */
77f5492c RG	428	if (no_ecc)
	429	nand_chip->ecc.mode = NAND_ECC_NONE;
	430	if (hard_ecc && regs) {
	431	host->ecc = ioremap(regs->start, regs->end - regs->start + 1);
	432	if (host->ecc == NULL) {
3c3796cc	433	printk(KERN_ERR "atmel_nand: ioremap failed\n");
77f5492c RG	434	res = -EIO;
	435	goto err_ecc_ioremap;
	436	}
3fc23898	437	nand_chip->ecc.mode = NAND_ECC_HW;
3c3796cc HS	438	nand_chip->ecc.calculate = atmel_nand_calculate;
	439	nand_chip->ecc.correct = atmel_nand_correct;
	440	nand_chip->ecc.hwctl = atmel_nand_hwctl;
	441	nand_chip->ecc.read_page = atmel_nand_read_page;
77f5492c	442	nand_chip->ecc.bytes = 4;
77f5492c RG	443	}
77f5492c RG	444
42cb1403 AV	445	nand_chip->chip_delay = 20; /* 20us command delay time */
42cb1403 AV	446
23a346ca	447	if (host->board->bus_width_16) { /* 16-bit bus width */
dd11b8cd	448	nand_chip->options \|= NAND_BUSWIDTH_16;
23a346ca DB	449	nand_chip->read_buf = atmel_read_buf16;
	450	nand_chip->write_buf = atmel_write_buf16;
	451	} else {
	452	nand_chip->read_buf = atmel_read_buf;
	453	nand_chip->write_buf = atmel_write_buf;
	454	}
dd11b8cd	455
42cb1403	456	platform_set_drvdata(pdev, host);
3c3796cc	457	atmel_nand_enable(host);
42cb1403 AV	458
42cb1403 AV	459	if (host->board->det_pin) {
62fd71fe	460	if (gpio_get_value(host->board->det_pin)) {
90574d0a	461	printk("No SmartMedia card inserted.\n");
42cb1403	462	res = ENXIO;
cc0c72e1	463	goto err_no_card;
42cb1403 AV	464	}
	465	}
	466
77f5492c RG	467	/* first scan to find the device and get the page size */
	468	if (nand_scan_ident(mtd, 1)) {
	469	res = -ENXIO;
cc0c72e1	470	goto err_scan_ident;
77f5492c RG	471	}
77f5492c RG	472
3fc23898	473	if (nand_chip->ecc.mode == NAND_ECC_HW) {
77f5492c RG	474	/* ECC is calculated for the whole page (1 step) */
	475	nand_chip->ecc.size = mtd->writesize;
	476
	477	/* set ECC page size and oob layout */
	478	switch (mtd->writesize) {
	479	case 512:
3c3796cc	480	nand_chip->ecc.layout = &atmel_oobinfo_small;
3c3796cc	481	ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
77f5492c RG	482	break;
77f5492c RG	483	case 1024:
3c3796cc HS	484	nand_chip->ecc.layout = &atmel_oobinfo_large;
3c3796cc HS	485	ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
77f5492c RG	486	break;
77f5492c RG	487	case 2048:
3c3796cc HS	488	nand_chip->ecc.layout = &atmel_oobinfo_large;
3c3796cc HS	489	ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
77f5492c RG	490	break;
77f5492c RG	491	case 4096:
3c3796cc HS	492	nand_chip->ecc.layout = &atmel_oobinfo_large;
3c3796cc HS	493	ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
77f5492c RG	494	break;
	495	default:
	496	/* page size not handled by HW ECC */
	497	/* switching back to soft ECC */
	498	nand_chip->ecc.mode = NAND_ECC_SOFT;
	499	nand_chip->ecc.calculate = NULL;
	500	nand_chip->ecc.correct = NULL;
	501	nand_chip->ecc.hwctl = NULL;
	502	nand_chip->ecc.read_page = NULL;
	503	nand_chip->ecc.postpad = 0;
	504	nand_chip->ecc.prepad = 0;
	505	nand_chip->ecc.bytes = 0;
	506	break;
	507	}
	508	}
	509
	510	/* second phase scan */
	511	if (nand_scan_tail(mtd)) {
42cb1403	512	res = -ENXIO;
cc0c72e1	513	goto err_scan_tail;
42cb1403 AV	514	}
	515
	516	#ifdef CONFIG_MTD_PARTITIONS
693ef66d	517	#ifdef CONFIG_MTD_CMDLINE_PARTS
3c3796cc	518	mtd->name = "atmel_nand";
842b1a10 AN	519	num_partitions = parse_mtd_partitions(mtd, part_probes,
842b1a10 AN	520	&partitions, 0);
693ef66d	521	#endif
842b1a10 AN	522	if (num_partitions <= 0 && host->board->partition_info)
	523	partitions = host->board->partition_info(mtd->size,
	524	&num_partitions);
42cb1403 AV	525
42cb1403 AV	526	if ((!partitions) \|\| (num_partitions == 0)) {
3c3796cc	527	printk(KERN_ERR "atmel_nand: No parititions defined, or unsupported device.\n");
42cb1403	528	res = ENXIO;
cc0c72e1	529	goto err_no_partitions;
42cb1403 AV	530	}
	531
	532	res = add_mtd_partitions(mtd, partitions, num_partitions);
	533	#else
	534	res = add_mtd_device(mtd);
	535	#endif
	536
	537	if (!res)
	538	return res;
	539
77f5492c	540	#ifdef CONFIG_MTD_PARTITIONS
cc0c72e1	541	err_no_partitions:
77f5492c	542	#endif
42cb1403	543	nand_release(mtd);
cc0c72e1 HS	544	err_scan_tail:
	545	err_scan_ident:
	546	err_no_card:
3c3796cc	547	atmel_nand_disable(host);
42cb1403	548	platform_set_drvdata(pdev, NULL);
cc0c72e1 HS	549	if (host->ecc)
	550	iounmap(host->ecc);
	551	err_ecc_ioremap:
42cb1403	552	iounmap(host->io_base);
cc0c72e1	553	err_nand_ioremap:
42cb1403 AV	554	kfree(host);
	555	return res;
	556	}
	557
	558	/*
	559	* Remove a NAND device.
	560	*/
23a346ca	561	static int __exit atmel_nand_remove(struct platform_device *pdev)
42cb1403	562	{
3c3796cc	563	struct atmel_nand_host *host = platform_get_drvdata(pdev);
42cb1403 AV	564	struct mtd_info *mtd = &host->mtd;
	565
	566	nand_release(mtd);
	567
3c3796cc	568	atmel_nand_disable(host);
42cb1403	569
cc0c72e1 HS	570	if (host->ecc)
cc0c72e1 HS	571	iounmap(host->ecc);
42cb1403 AV	572	iounmap(host->io_base);
	573	kfree(host);
	574
	575	return 0;
	576	}
	577
3c3796cc	578	static struct platform_driver atmel_nand_driver = {
23a346ca	579	.remove = __exit_p(atmel_nand_remove),
42cb1403	580	.driver = {
3c3796cc	581	.name = "atmel_nand",
42cb1403 AV	582	.owner = THIS_MODULE,
	583	},
	584	};
	585
3c3796cc	586	static int __init atmel_nand_init(void)
42cb1403	587	{
23a346ca	588	return platform_driver_probe(&atmel_nand_driver, atmel_nand_probe);
42cb1403 AV	589	}
	590
	591
3c3796cc	592	static void __exit atmel_nand_exit(void)
42cb1403	593	{
3c3796cc	594	platform_driver_unregister(&atmel_nand_driver);
42cb1403 AV	595	}
	596
	597
3c3796cc HS	598	module_init(atmel_nand_init);
3c3796cc HS	599	module_exit(atmel_nand_exit);
42cb1403 AV	600
	601	MODULE_LICENSE("GPL");
	602	MODULE_AUTHOR("Rick Bronson");
d4f4c0aa	603	MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
3c3796cc	604	MODULE_ALIAS("platform:atmel_nand");