[deliverable/linux.git] / drivers / mtd / nand / atmel_nand.c

/*
 *  Copyright (C) 2003 Rick Bronson
 *
 *  Derived from drivers/mtd/nand/autcpu12.c
 *	 Copyright (c) 2001 Thomas Gleixner (gleixner@autronix.de)
 *
 *  Derived from drivers/mtd/spia.c
 *	 Copyright (C) 2000 Steven J. Hill (sjhill@cotw.com)
 *
 *
 *  Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
 *     Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright (C) 2007
 *
 *     Derived from Das U-Boot source code
 *     		(u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
 *     (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
 *
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <linux/slab.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>

#include <linux/gpio.h>
#include <linux/io.h>

#include <mach/board.h>
#include <mach/cpu.h>

#ifdef CONFIG_MTD_NAND_ATMEL_ECC_HW
#define hard_ecc	1
#else
#define hard_ecc	0
#endif

#ifdef CONFIG_MTD_NAND_ATMEL_ECC_NONE
#define no_ecc		1
#else
#define no_ecc		0
#endif

static int on_flash_bbt = 0;
module_param(on_flash_bbt, int, 0);

/* Register access macros */
#define ecc_readl(add, reg)				\
	__raw_readl(add + ATMEL_ECC_##reg)
#define ecc_writel(add, reg, value)			\
	__raw_writel((value), add + ATMEL_ECC_##reg)

#include "atmel_nand_ecc.h"	/* Hardware ECC registers */

/* oob layout for large page size
 * bad block info is on bytes 0 and 1
 * the bytes have to be consecutives to avoid
 * several NAND_CMD_RNDOUT during read
 */
static struct nand_ecclayout atmel_oobinfo_large = {
	.eccbytes = 4,
	.eccpos = {60, 61, 62, 63},
	.oobfree = {
		{2, 58}
	},
};

/* oob layout for small page size
 * bad block info is on bytes 4 and 5
 * the bytes have to be consecutives to avoid
 * several NAND_CMD_RNDOUT during read
 */
static struct nand_ecclayout atmel_oobinfo_small = {
	.eccbytes = 4,
	.eccpos = {0, 1, 2, 3},
	.oobfree = {
		{6, 10}
	},
};

struct atmel_nand_host {
	struct nand_chip	nand_chip;
	struct mtd_info		mtd;
	void __iomem		*io_base;
	struct atmel_nand_data	*board;
	struct device		*dev;
	void __iomem		*ecc;
};

/*
 * Enable NAND.
 */
static void atmel_nand_enable(struct atmel_nand_host *host)
{
	if (host->board->enable_pin)
		gpio_set_value(host->board->enable_pin, 0);
}

/*
 * Disable NAND.
 */
static void atmel_nand_disable(struct atmel_nand_host *host)
{
	if (host->board->enable_pin)
		gpio_set_value(host->board->enable_pin, 1);
}

/*
 * Hardware specific access to control-lines
 */
static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
	struct nand_chip *nand_chip = mtd->priv;
	struct atmel_nand_host *host = nand_chip->priv;

	if (ctrl & NAND_CTRL_CHANGE) {
		if (ctrl & NAND_NCE)
			atmel_nand_enable(host);
		else
			atmel_nand_disable(host);
	}
	if (cmd == NAND_CMD_NONE)
		return;

	if (ctrl & NAND_CLE)
		writeb(cmd, host->io_base + (1 << host->board->cle));
	else
		writeb(cmd, host->io_base + (1 << host->board->ale));
}

/*
 * Read the Device Ready pin.
 */
static int atmel_nand_device_ready(struct mtd_info *mtd)
{
	struct nand_chip *nand_chip = mtd->priv;
	struct atmel_nand_host *host = nand_chip->priv;

	return gpio_get_value(host->board->rdy_pin) ^
                !!host->board->rdy_pin_active_low;
}

/*
 * Minimal-overhead PIO for data access.
 */
static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
{
	struct nand_chip	*nand_chip = mtd->priv;

	__raw_readsb(nand_chip->IO_ADDR_R, buf, len);
}

static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
{
	struct nand_chip	*nand_chip = mtd->priv;

	__raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
}

static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
{
	struct nand_chip	*nand_chip = mtd->priv;

	__raw_writesb(nand_chip->IO_ADDR_W, buf, len);
}

static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
{
	struct nand_chip	*nand_chip = mtd->priv;

	__raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
}

/*
 * Calculate HW ECC
 *
 * function called after a write
 *
 * mtd:        MTD block structure
 * dat:        raw data (unused)
 * ecc_code:   buffer for ECC
 */
static int atmel_nand_calculate(struct mtd_info *mtd,
		const u_char *dat, unsigned char *ecc_code)
{
	struct nand_chip *nand_chip = mtd->priv;
	struct atmel_nand_host *host = nand_chip->priv;
	unsigned int ecc_value;

	/* get the first 2 ECC bytes */
	ecc_value = ecc_readl(host->ecc, PR);

	ecc_code[0] = ecc_value & 0xFF;
	ecc_code[1] = (ecc_value >> 8) & 0xFF;

	/* get the last 2 ECC bytes */
	ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY;

	ecc_code[2] = ecc_value & 0xFF;
	ecc_code[3] = (ecc_value >> 8) & 0xFF;

	return 0;
}

/*
 * HW ECC read page function
 *
 * mtd:        mtd info structure
 * chip:       nand chip info structure
 * buf:        buffer to store read data
 */
static int atmel_nand_read_page(struct mtd_info *mtd,
		struct nand_chip *chip, uint8_t *buf, int page)
{
	int eccsize = chip->ecc.size;
	int eccbytes = chip->ecc.bytes;
	uint32_t *eccpos = chip->ecc.layout->eccpos;
	uint8_t *p = buf;
	uint8_t *oob = chip->oob_poi;
	uint8_t *ecc_pos;
	int stat;

	/*
	 * Errata: ALE is incorrectly wired up to the ECC controller
	 * on the AP7000, so it will include the address cycles in the
	 * ECC calculation.
	 *
	 * Workaround: Reset the parity registers before reading the
	 * actual data.
	 */
	if (cpu_is_at32ap7000()) {
		struct atmel_nand_host *host = chip->priv;
		ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
	}

	/* read the page */
	chip->read_buf(mtd, p, eccsize);

	/* move to ECC position if needed */
	if (eccpos[0] != 0) {
		/* This only works on large pages
		 * because the ECC controller waits for
		 * NAND_CMD_RNDOUTSTART after the
		 * NAND_CMD_RNDOUT.
		 * anyway, for small pages, the eccpos[0] == 0
		 */
		chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
				mtd->writesize + eccpos[0], -1);
	}

	/* the ECC controller needs to read the ECC just after the data */
	ecc_pos = oob + eccpos[0];
	chip->read_buf(mtd, ecc_pos, eccbytes);

	/* check if there's an error */
	stat = chip->ecc.correct(mtd, p, oob, NULL);

	if (stat < 0)
		mtd->ecc_stats.failed++;
	else
		mtd->ecc_stats.corrected += stat;

	/* get back to oob start (end of page) */
	chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);

	/* read the oob */
	chip->read_buf(mtd, oob, mtd->oobsize);

	return 0;
}

/*
 * HW ECC Correction
 *
 * function called after a read
 *
 * mtd:        MTD block structure
 * dat:        raw data read from the chip
 * read_ecc:   ECC from the chip (unused)
 * isnull:     unused
 *
 * Detect and correct a 1 bit error for a page
 */
static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
		u_char *read_ecc, u_char *isnull)
{
	struct nand_chip *nand_chip = mtd->priv;
	struct atmel_nand_host *host = nand_chip->priv;
	unsigned int ecc_status;
	unsigned int ecc_word, ecc_bit;

	/* get the status from the Status Register */
	ecc_status = ecc_readl(host->ecc, SR);

	/* if there's no error */
	if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
		return 0;

	/* get error bit offset (4 bits) */
	ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR;
	/* get word address (12 bits) */
	ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR;
	ecc_word >>= 4;

	/* if there are multiple errors */
	if (ecc_status & ATMEL_ECC_MULERR) {
		/* check if it is a freshly erased block
		 * (filled with 0xff) */
		if ((ecc_bit == ATMEL_ECC_BITADDR)
				&& (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
			/* the block has just been erased, return OK */
			return 0;
		}
		/* it doesn't seems to be a freshly
		 * erased block.
		 * We can't correct so many errors */
		dev_dbg(host->dev, "atmel_nand : multiple errors detected."
				" Unable to correct.\n");
		return -EIO;
	}

	/* if there's a single bit error : we can correct it */
	if (ecc_status & ATMEL_ECC_ECCERR) {
		/* there's nothing much to do here.
		 * the bit error is on the ECC itself.
		 */
		dev_dbg(host->dev, "atmel_nand : one bit error on ECC code."
				" Nothing to correct\n");
		return 0;
	}

	dev_dbg(host->dev, "atmel_nand : one bit error on data."
			" (word offset in the page :"
			" 0x%x bit offset : 0x%x)\n",
			ecc_word, ecc_bit);
	/* correct the error */
	if (nand_chip->options & NAND_BUSWIDTH_16) {
		/* 16 bits words */
		((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
	} else {
		/* 8 bits words */
		dat[ecc_word] ^= (1 << ecc_bit);
	}
	dev_dbg(host->dev, "atmel_nand : error corrected\n");
	return 1;
}

/*
 * Enable HW ECC : unused on most chips
 */
static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
{
	if (cpu_is_at32ap7000()) {
		struct nand_chip *nand_chip = mtd->priv;
		struct atmel_nand_host *host = nand_chip->priv;
		ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
	}
}

#ifdef CONFIG_MTD_PARTITIONS
static const char *part_probes[] = { "cmdlinepart", NULL };
#endif

/*
 * Probe for the NAND device.
 */
static int __init atmel_nand_probe(struct platform_device *pdev)
{
	struct atmel_nand_host *host;
	struct mtd_info *mtd;
	struct nand_chip *nand_chip;
	struct resource *regs;
	struct resource *mem;
	int res;

#ifdef CONFIG_MTD_PARTITIONS
	struct mtd_partition *partitions = NULL;
	int num_partitions = 0;
#endif

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!mem) {
		printk(KERN_ERR "atmel_nand: can't get I/O resource mem\n");
		return -ENXIO;
	}

	/* Allocate memory for the device structure (and zero it) */
	host = kzalloc(sizeof(struct atmel_nand_host), GFP_KERNEL);
	if (!host) {
		printk(KERN_ERR "atmel_nand: failed to allocate device structure.\n");
		return -ENOMEM;
	}

	host->io_base = ioremap(mem->start, mem->end - mem->start + 1);
	if (host->io_base == NULL) {
		printk(KERN_ERR "atmel_nand: ioremap failed\n");
		res = -EIO;
		goto err_nand_ioremap;
	}

	mtd = &host->mtd;
	nand_chip = &host->nand_chip;
	host->board = pdev->dev.platform_data;
	host->dev = &pdev->dev;

	nand_chip->priv = host;		/* link the private data structures */
	mtd->priv = nand_chip;
	mtd->owner = THIS_MODULE;

	/* Set address of NAND IO lines */
	nand_chip->IO_ADDR_R = host->io_base;
	nand_chip->IO_ADDR_W = host->io_base;
	nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;

	if (host->board->rdy_pin)
		nand_chip->dev_ready = atmel_nand_device_ready;

	regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	if (!regs && hard_ecc) {
		printk(KERN_ERR "atmel_nand: can't get I/O resource "
				"regs\nFalling back on software ECC\n");
	}

	nand_chip->ecc.mode = NAND_ECC_SOFT;	/* enable ECC */
	if (no_ecc)
		nand_chip->ecc.mode = NAND_ECC_NONE;
	if (hard_ecc && regs) {
		host->ecc = ioremap(regs->start, regs->end - regs->start + 1);
		if (host->ecc == NULL) {
			printk(KERN_ERR "atmel_nand: ioremap failed\n");
			res = -EIO;
			goto err_ecc_ioremap;
		}
		nand_chip->ecc.mode = NAND_ECC_HW;
		nand_chip->ecc.calculate = atmel_nand_calculate;
		nand_chip->ecc.correct = atmel_nand_correct;
		nand_chip->ecc.hwctl = atmel_nand_hwctl;
		nand_chip->ecc.read_page = atmel_nand_read_page;
		nand_chip->ecc.bytes = 4;
	}

	nand_chip->chip_delay = 20;		/* 20us command delay time */

	if (host->board->bus_width_16) {	/* 16-bit bus width */
		nand_chip->options |= NAND_BUSWIDTH_16;
		nand_chip->read_buf = atmel_read_buf16;
		nand_chip->write_buf = atmel_write_buf16;
	} else {
		nand_chip->read_buf = atmel_read_buf;
		nand_chip->write_buf = atmel_write_buf;
	}

	platform_set_drvdata(pdev, host);
	atmel_nand_enable(host);

	if (host->board->det_pin) {
		if (gpio_get_value(host->board->det_pin)) {
			printk(KERN_INFO "No SmartMedia card inserted.\n");
			res = -ENXIO;
			goto err_no_card;
		}
	}

	if (on_flash_bbt) {
		printk(KERN_INFO "atmel_nand: Use On Flash BBT\n");
		nand_chip->options |= NAND_USE_FLASH_BBT;
	}

	/* first scan to find the device and get the page size */
	if (nand_scan_ident(mtd, 1, NULL)) {
		res = -ENXIO;
		goto err_scan_ident;
	}

	if (nand_chip->ecc.mode == NAND_ECC_HW) {
		/* ECC is calculated for the whole page (1 step) */
		nand_chip->ecc.size = mtd->writesize;

		/* set ECC page size and oob layout */
		switch (mtd->writesize) {
		case 512:
			nand_chip->ecc.layout = &atmel_oobinfo_small;
			ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
			break;
		case 1024:
			nand_chip->ecc.layout = &atmel_oobinfo_large;
			ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
			break;
		case 2048:
			nand_chip->ecc.layout = &atmel_oobinfo_large;
			ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
			break;
		case 4096:
			nand_chip->ecc.layout = &atmel_oobinfo_large;
			ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
			break;
		default:
			/* page size not handled by HW ECC */
			/* switching back to soft ECC */
			nand_chip->ecc.mode = NAND_ECC_SOFT;
			nand_chip->ecc.calculate = NULL;
			nand_chip->ecc.correct = NULL;
			nand_chip->ecc.hwctl = NULL;
			nand_chip->ecc.read_page = NULL;
			nand_chip->ecc.postpad = 0;
			nand_chip->ecc.prepad = 0;
			nand_chip->ecc.bytes = 0;
			break;
		}
	}

	/* second phase scan */
	if (nand_scan_tail(mtd)) {
		res = -ENXIO;
		goto err_scan_tail;
	}

#ifdef CONFIG_MTD_PARTITIONS
#ifdef CONFIG_MTD_CMDLINE_PARTS
	mtd->name = "atmel_nand";
	num_partitions = parse_mtd_partitions(mtd, part_probes,
					      &partitions, 0);
#endif
	if (num_partitions <= 0 && host->board->partition_info)
		partitions = host->board->partition_info(mtd->size,
							 &num_partitions);

	if ((!partitions) || (num_partitions == 0)) {
		printk(KERN_ERR "atmel_nand: No partitions defined, or unsupported device.\n");
		res = -ENXIO;
		goto err_no_partitions;
	}

	res = add_mtd_partitions(mtd, partitions, num_partitions);
#else
	res = add_mtd_device(mtd);
#endif

	if (!res)
		return res;

#ifdef CONFIG_MTD_PARTITIONS
err_no_partitions:
#endif
	nand_release(mtd);
err_scan_tail:
err_scan_ident:
err_no_card:
	atmel_nand_disable(host);
	platform_set_drvdata(pdev, NULL);
	if (host->ecc)
		iounmap(host->ecc);
err_ecc_ioremap:
	iounmap(host->io_base);
err_nand_ioremap:
	kfree(host);
	return res;
}

/*
 * Remove a NAND device.
 */
static int __exit atmel_nand_remove(struct platform_device *pdev)
{
	struct atmel_nand_host *host = platform_get_drvdata(pdev);
	struct mtd_info *mtd = &host->mtd;

	nand_release(mtd);

	atmel_nand_disable(host);

	if (host->ecc)
		iounmap(host->ecc);
	iounmap(host->io_base);
	kfree(host);

	return 0;
}

static struct platform_driver atmel_nand_driver = {
	.remove		= __exit_p(atmel_nand_remove),
	.driver		= {
		.name	= "atmel_nand",
		.owner	= THIS_MODULE,
	},
};

static int __init atmel_nand_init(void)
{
	return platform_driver_probe(&atmel_nand_driver, atmel_nand_probe);
}


static void __exit atmel_nand_exit(void)
{
	platform_driver_unregister(&atmel_nand_driver);
}


module_init(atmel_nand_init);
module_exit(atmel_nand_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Rick Bronson");
MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
MODULE_ALIAS("platform:atmel_nand");
Commit	Line	Data
42cb1403	1	/*
42cb1403 AV	2	* Copyright (C) 2003 Rick Bronson
	3	*
	4	* Derived from drivers/mtd/nand/autcpu12.c
	5	* Copyright (c) 2001 Thomas Gleixner (gleixner@autronix.de)
	6	*
	7	* Derived from drivers/mtd/spia.c
	8	* Copyright (C) 2000 Steven J. Hill (sjhill@cotw.com)
	9	*
77f5492c RG	10	*
	11	* Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
	12	* Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright (C) 2007
	13	*
	14	* Derived from Das U-Boot source code
	15	* (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
	16	* (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
	17	*
	18	*
42cb1403 AV	19	* This program is free software; you can redistribute it and/or modify
	20	* it under the terms of the GNU General Public License version 2 as
	21	* published by the Free Software Foundation.
	22	*
	23	*/
	24
	25	#include <linux/slab.h>
	26	#include <linux/module.h>
f4fa697c	27	#include <linux/moduleparam.h>
42cb1403 AV	28	#include <linux/platform_device.h>
	29	#include <linux/mtd/mtd.h>
	30	#include <linux/mtd/nand.h>
	31	#include <linux/mtd/partitions.h>
	32
90574d0a DW	33	#include <linux/gpio.h>
90574d0a DW	34	#include <linux/io.h>
42cb1403	35
a09e64fb RK	36	#include <mach/board.h>
a09e64fb RK	37	#include <mach/cpu.h>
42cb1403	38
d4f4c0aa	39	#ifdef CONFIG_MTD_NAND_ATMEL_ECC_HW
77f5492c RG	40	#define hard_ecc 1
	41	#else
	42	#define hard_ecc 0
	43	#endif
	44
d4f4c0aa	45	#ifdef CONFIG_MTD_NAND_ATMEL_ECC_NONE
77f5492c RG	46	#define no_ecc 1
	47	#else
	48	#define no_ecc 0
	49	#endif
	50
f4fa697c SP	51	static int on_flash_bbt = 0;
	52	module_param(on_flash_bbt, int, 0);
	53
77f5492c RG	54	/* Register access macros */
77f5492c RG	55	#define ecc_readl(add, reg) \
3c3796cc	56	__raw_readl(add + ATMEL_ECC_##reg)
77f5492c	57	#define ecc_writel(add, reg, value) \
3c3796cc	58	__raw_writel((value), add + ATMEL_ECC_##reg)
77f5492c	59
d4f4c0aa	60	#include "atmel_nand_ecc.h" /* Hardware ECC registers */
77f5492c RG	61
	62	/* oob layout for large page size
	63	* bad block info is on bytes 0 and 1
	64	* the bytes have to be consecutives to avoid
	65	* several NAND_CMD_RNDOUT during read
	66	*/
3c3796cc	67	static struct nand_ecclayout atmel_oobinfo_large = {
77f5492c RG	68	.eccbytes = 4,
	69	.eccpos = {60, 61, 62, 63},
	70	.oobfree = {
	71	{2, 58}
	72	},
	73	};
	74
	75	/* oob layout for small page size
	76	* bad block info is on bytes 4 and 5
	77	* the bytes have to be consecutives to avoid
	78	* several NAND_CMD_RNDOUT during read
	79	*/
3c3796cc	80	static struct nand_ecclayout atmel_oobinfo_small = {
77f5492c RG	81	.eccbytes = 4,
	82	.eccpos = {0, 1, 2, 3},
	83	.oobfree = {
	84	{6, 10}
	85	},
	86	};
	87
3c3796cc	88	struct atmel_nand_host {
42cb1403 AV	89	struct nand_chip nand_chip;
	90	struct mtd_info mtd;
	91	void __iomem *io_base;
3c3796cc	92	struct atmel_nand_data *board;
77f5492c RG	93	struct device *dev;
77f5492c RG	94	void __iomem *ecc;
42cb1403 AV	95	};
42cb1403 AV	96
8136508c AN	97	/*
	98	* Enable NAND.
	99	*/
3c3796cc	100	static void atmel_nand_enable(struct atmel_nand_host *host)
8136508c AN	101	{
8136508c AN	102	if (host->board->enable_pin)
62fd71fe	103	gpio_set_value(host->board->enable_pin, 0);
8136508c AN	104	}
	105
	106	/*
	107	* Disable NAND.
	108	*/
3c3796cc	109	static void atmel_nand_disable(struct atmel_nand_host *host)
8136508c AN	110	{
8136508c AN	111	if (host->board->enable_pin)
62fd71fe	112	gpio_set_value(host->board->enable_pin, 1);
8136508c AN	113	}
8136508c AN	114
42cb1403 AV	115	/*
	116	* Hardware specific access to control-lines
	117	*/
3c3796cc	118	static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
42cb1403 AV	119	{
42cb1403 AV	120	struct nand_chip *nand_chip = mtd->priv;
3c3796cc	121	struct atmel_nand_host *host = nand_chip->priv;
42cb1403	122
8136508c	123	if (ctrl & NAND_CTRL_CHANGE) {
2314488e	124	if (ctrl & NAND_NCE)
3c3796cc	125	atmel_nand_enable(host);
2314488e	126	else
3c3796cc	127	atmel_nand_disable(host);
2314488e	128	}
42cb1403 AV	129	if (cmd == NAND_CMD_NONE)
	130	return;
	131
	132	if (ctrl & NAND_CLE)
	133	writeb(cmd, host->io_base + (1 << host->board->cle));
	134	else
	135	writeb(cmd, host->io_base + (1 << host->board->ale));
	136	}
	137
	138	/*
	139	* Read the Device Ready pin.
	140	*/
3c3796cc	141	static int atmel_nand_device_ready(struct mtd_info *mtd)
42cb1403 AV	142	{
42cb1403 AV	143	struct nand_chip *nand_chip = mtd->priv;
3c3796cc	144	struct atmel_nand_host *host = nand_chip->priv;
42cb1403	145
744f6592 GC	146	return gpio_get_value(host->board->rdy_pin) ^
744f6592 GC	147	!!host->board->rdy_pin_active_low;
42cb1403 AV	148	}
42cb1403 AV	149
23a346ca DB	150	/*
	151	* Minimal-overhead PIO for data access.
	152	*/
	153	static void atmel_read_buf(struct mtd_info mtd, u8 buf, int len)
	154	{
	155	struct nand_chip *nand_chip = mtd->priv;
	156
	157	__raw_readsb(nand_chip->IO_ADDR_R, buf, len);
	158	}
	159
	160	static void atmel_read_buf16(struct mtd_info mtd, u8 buf, int len)
	161	{
	162	struct nand_chip *nand_chip = mtd->priv;
	163
	164	__raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
	165	}
	166
	167	static void atmel_write_buf(struct mtd_info mtd, const u8 buf, int len)
	168	{
	169	struct nand_chip *nand_chip = mtd->priv;
	170
	171	__raw_writesb(nand_chip->IO_ADDR_W, buf, len);
	172	}
	173
	174	static void atmel_write_buf16(struct mtd_info mtd, const u8 buf, int len)
	175	{
	176	struct nand_chip *nand_chip = mtd->priv;
	177
	178	__raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
	179	}
	180
77f5492c RG	181	/*
	182	* Calculate HW ECC
	183	*
	184	* function called after a write
	185	*
	186	* mtd: MTD block structure
	187	* dat: raw data (unused)
	188	* ecc_code: buffer for ECC
	189	*/
3c3796cc	190	static int atmel_nand_calculate(struct mtd_info *mtd,
77f5492c RG	191	const u_char dat, unsigned char ecc_code)
	192	{
	193	struct nand_chip *nand_chip = mtd->priv;
3c3796cc	194	struct atmel_nand_host *host = nand_chip->priv;
77f5492c RG	195	unsigned int ecc_value;
	196
	197	/* get the first 2 ECC bytes */
d43fa149	198	ecc_value = ecc_readl(host->ecc, PR);
77f5492c	199
3fc23898 RG	200	ecc_code[0] = ecc_value & 0xFF;
3fc23898 RG	201	ecc_code[1] = (ecc_value >> 8) & 0xFF;
77f5492c RG	202
77f5492c RG	203	/* get the last 2 ECC bytes */
3c3796cc	204	ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY;
77f5492c	205
3fc23898 RG	206	ecc_code[2] = ecc_value & 0xFF;
3fc23898 RG	207	ecc_code[3] = (ecc_value >> 8) & 0xFF;
77f5492c RG	208
	209	return 0;
	210	}
	211
	212	/*
	213	* HW ECC read page function
	214	*
	215	* mtd: mtd info structure
	216	* chip: nand chip info structure
	217	* buf: buffer to store read data
	218	*/
3c3796cc	219	static int atmel_nand_read_page(struct mtd_info *mtd,
46a8cf2d	220	struct nand_chip chip, uint8_t buf, int page)
77f5492c RG	221	{
	222	int eccsize = chip->ecc.size;
	223	int eccbytes = chip->ecc.bytes;
	224	uint32_t *eccpos = chip->ecc.layout->eccpos;
	225	uint8_t *p = buf;
	226	uint8_t *oob = chip->oob_poi;
	227	uint8_t *ecc_pos;
	228	int stat;
	229
d6248fdd HS	230	/*
	231	* Errata: ALE is incorrectly wired up to the ECC controller
	232	* on the AP7000, so it will include the address cycles in the
	233	* ECC calculation.
	234	*
	235	* Workaround: Reset the parity registers before reading the
	236	* actual data.
	237	*/
	238	if (cpu_is_at32ap7000()) {
	239	struct atmel_nand_host *host = chip->priv;
	240	ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
	241	}
	242
77f5492c RG	243	/* read the page */
	244	chip->read_buf(mtd, p, eccsize);
	245
	246	/* move to ECC position if needed */
	247	if (eccpos[0] != 0) {
	248	/* This only works on large pages
	249	* because the ECC controller waits for
	250	* NAND_CMD_RNDOUTSTART after the
	251	* NAND_CMD_RNDOUT.
	252	* anyway, for small pages, the eccpos[0] == 0
	253	*/
	254	chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
	255	mtd->writesize + eccpos[0], -1);
	256	}
	257
	258	/* the ECC controller needs to read the ECC just after the data */
	259	ecc_pos = oob + eccpos[0];
	260	chip->read_buf(mtd, ecc_pos, eccbytes);
	261
	262	/* check if there's an error */
	263	stat = chip->ecc.correct(mtd, p, oob, NULL);
	264
	265	if (stat < 0)
	266	mtd->ecc_stats.failed++;
	267	else
	268	mtd->ecc_stats.corrected += stat;
	269
	270	/* get back to oob start (end of page) */
	271	chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
	272
	273	/* read the oob */
	274	chip->read_buf(mtd, oob, mtd->oobsize);
	275
	276	return 0;
	277	}
	278
	279	/*
	280	* HW ECC Correction
	281	*
	282	* function called after a read
	283	*
	284	* mtd: MTD block structure
	285	* dat: raw data read from the chip
	286	* read_ecc: ECC from the chip (unused)
	287	* isnull: unused
	288	*
	289	* Detect and correct a 1 bit error for a page
	290	*/
3c3796cc	291	static int atmel_nand_correct(struct mtd_info mtd, u_char dat,
77f5492c RG	292	u_char read_ecc, u_char isnull)
	293	{
	294	struct nand_chip *nand_chip = mtd->priv;
3c3796cc	295	struct atmel_nand_host *host = nand_chip->priv;
77f5492c RG	296	unsigned int ecc_status;
	297	unsigned int ecc_word, ecc_bit;
	298
	299	/* get the status from the Status Register */
	300	ecc_status = ecc_readl(host->ecc, SR);
	301
	302	/* if there's no error */
3c3796cc	303	if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
77f5492c RG	304	return 0;
	305
	306	/* get error bit offset (4 bits) */
3c3796cc	307	ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR;
77f5492c	308	/* get word address (12 bits) */
3c3796cc	309	ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR;
77f5492c RG	310	ecc_word >>= 4;
	311
	312	/* if there are multiple errors */
3c3796cc	313	if (ecc_status & ATMEL_ECC_MULERR) {
77f5492c RG	314	/* check if it is a freshly erased block
77f5492c RG	315	* (filled with 0xff) */
3c3796cc HS	316	if ((ecc_bit == ATMEL_ECC_BITADDR)
3c3796cc HS	317	&& (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
77f5492c RG	318	/* the block has just been erased, return OK */
	319	return 0;
	320	}
	321	/* it doesn't seems to be a freshly
	322	* erased block.
	323	* We can't correct so many errors */
3c3796cc	324	dev_dbg(host->dev, "atmel_nand : multiple errors detected."
77f5492c RG	325	" Unable to correct.\n");
	326	return -EIO;
	327	}
	328
	329	/* if there's a single bit error : we can correct it */
3c3796cc	330	if (ecc_status & ATMEL_ECC_ECCERR) {
77f5492c RG	331	/* there's nothing much to do here.
	332	* the bit error is on the ECC itself.
	333	*/
3c3796cc	334	dev_dbg(host->dev, "atmel_nand : one bit error on ECC code."
77f5492c RG	335	" Nothing to correct\n");
	336	return 0;
	337	}
	338
3c3796cc	339	dev_dbg(host->dev, "atmel_nand : one bit error on data."
77f5492c RG	340	" (word offset in the page :"
	341	" 0x%x bit offset : 0x%x)\n",
	342	ecc_word, ecc_bit);
	343	/* correct the error */
	344	if (nand_chip->options & NAND_BUSWIDTH_16) {
	345	/* 16 bits words */
	346	((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
	347	} else {
	348	/* 8 bits words */
	349	dat[ecc_word] ^= (1 << ecc_bit);
	350	}
3c3796cc	351	dev_dbg(host->dev, "atmel_nand : error corrected\n");
77f5492c RG	352	return 1;
	353	}
	354
	355	/*
d6248fdd	356	* Enable HW ECC : unused on most chips
77f5492c	357	*/
d6248fdd HS	358	static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
	359	{
	360	if (cpu_is_at32ap7000()) {
	361	struct nand_chip *nand_chip = mtd->priv;
	362	struct atmel_nand_host *host = nand_chip->priv;
	363	ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
	364	}
	365	}
77f5492c	366
693ef66d	367	#ifdef CONFIG_MTD_PARTITIONS
52f83014	368	static const char *part_probes[] = { "cmdlinepart", NULL };
693ef66d AV	369	#endif
693ef66d AV	370
42cb1403 AV	371	/*
	372	* Probe for the NAND device.
	373	*/
3c3796cc	374	static int __init atmel_nand_probe(struct platform_device *pdev)
42cb1403	375	{
3c3796cc	376	struct atmel_nand_host *host;
42cb1403 AV	377	struct mtd_info *mtd;
42cb1403 AV	378	struct nand_chip *nand_chip;
77f5492c RG	379	struct resource *regs;
77f5492c RG	380	struct resource *mem;
42cb1403 AV	381	int res;
	382
	383	#ifdef CONFIG_MTD_PARTITIONS
	384	struct mtd_partition *partitions = NULL;
	385	int num_partitions = 0;
	386	#endif
	387
cc0c72e1 HS	388	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	389	if (!mem) {
	390	printk(KERN_ERR "atmel_nand: can't get I/O resource mem\n");
	391	return -ENXIO;
	392	}
	393
42cb1403	394	/* Allocate memory for the device structure (and zero it) */
3c3796cc	395	host = kzalloc(sizeof(struct atmel_nand_host), GFP_KERNEL);
42cb1403	396	if (!host) {
3c3796cc	397	printk(KERN_ERR "atmel_nand: failed to allocate device structure.\n");
42cb1403 AV	398	return -ENOMEM;
	399	}
	400
77f5492c	401	host->io_base = ioremap(mem->start, mem->end - mem->start + 1);
42cb1403	402	if (host->io_base == NULL) {
3c3796cc	403	printk(KERN_ERR "atmel_nand: ioremap failed\n");
cc0c72e1 HS	404	res = -EIO;
cc0c72e1 HS	405	goto err_nand_ioremap;
42cb1403 AV	406	}
	407
	408	mtd = &host->mtd;
	409	nand_chip = &host->nand_chip;
	410	host->board = pdev->dev.platform_data;
77f5492c	411	host->dev = &pdev->dev;
42cb1403 AV	412
	413	nand_chip->priv = host; /* link the private data structures */
	414	mtd->priv = nand_chip;
	415	mtd->owner = THIS_MODULE;
	416
	417	/* Set address of NAND IO lines */
	418	nand_chip->IO_ADDR_R = host->io_base;
	419	nand_chip->IO_ADDR_W = host->io_base;
3c3796cc	420	nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
a4265f8d IK	421
a4265f8d IK	422	if (host->board->rdy_pin)
3c3796cc	423	nand_chip->dev_ready = atmel_nand_device_ready;
a4265f8d	424
77f5492c RG	425	regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
77f5492c RG	426	if (!regs && hard_ecc) {
3c3796cc	427	printk(KERN_ERR "atmel_nand: can't get I/O resource "
77f5492c RG	428	"regs\nFalling back on software ECC\n");
	429	}
	430
42cb1403	431	nand_chip->ecc.mode = NAND_ECC_SOFT; /* enable ECC */
77f5492c RG	432	if (no_ecc)
	433	nand_chip->ecc.mode = NAND_ECC_NONE;
	434	if (hard_ecc && regs) {
	435	host->ecc = ioremap(regs->start, regs->end - regs->start + 1);
	436	if (host->ecc == NULL) {
3c3796cc	437	printk(KERN_ERR "atmel_nand: ioremap failed\n");
77f5492c RG	438	res = -EIO;
	439	goto err_ecc_ioremap;
	440	}
3fc23898	441	nand_chip->ecc.mode = NAND_ECC_HW;
3c3796cc HS	442	nand_chip->ecc.calculate = atmel_nand_calculate;
	443	nand_chip->ecc.correct = atmel_nand_correct;
	444	nand_chip->ecc.hwctl = atmel_nand_hwctl;
	445	nand_chip->ecc.read_page = atmel_nand_read_page;
77f5492c	446	nand_chip->ecc.bytes = 4;
77f5492c RG	447	}
77f5492c RG	448
42cb1403 AV	449	nand_chip->chip_delay = 20; /* 20us command delay time */
42cb1403 AV	450
23a346ca	451	if (host->board->bus_width_16) { /* 16-bit bus width */
dd11b8cd	452	nand_chip->options \|= NAND_BUSWIDTH_16;
23a346ca DB	453	nand_chip->read_buf = atmel_read_buf16;
	454	nand_chip->write_buf = atmel_write_buf16;
	455	} else {
	456	nand_chip->read_buf = atmel_read_buf;
	457	nand_chip->write_buf = atmel_write_buf;
	458	}
dd11b8cd	459
42cb1403	460	platform_set_drvdata(pdev, host);
3c3796cc	461	atmel_nand_enable(host);
42cb1403 AV	462
42cb1403 AV	463	if (host->board->det_pin) {
62fd71fe	464	if (gpio_get_value(host->board->det_pin)) {
f4fa697c	465	printk(KERN_INFO "No SmartMedia card inserted.\n");
895fb494	466	res = -ENXIO;
cc0c72e1	467	goto err_no_card;
42cb1403 AV	468	}
	469	}
	470
f4fa697c SP	471	if (on_flash_bbt) {
	472	printk(KERN_INFO "atmel_nand: Use On Flash BBT\n");
	473	nand_chip->options \|= NAND_USE_FLASH_BBT;
	474	}
	475
77f5492c	476	/* first scan to find the device and get the page size */
5e81e88a	477	if (nand_scan_ident(mtd, 1, NULL)) {
77f5492c	478	res = -ENXIO;
cc0c72e1	479	goto err_scan_ident;
77f5492c RG	480	}
77f5492c RG	481
3fc23898	482	if (nand_chip->ecc.mode == NAND_ECC_HW) {
77f5492c RG	483	/* ECC is calculated for the whole page (1 step) */
	484	nand_chip->ecc.size = mtd->writesize;
	485
	486	/* set ECC page size and oob layout */
	487	switch (mtd->writesize) {
	488	case 512:
3c3796cc	489	nand_chip->ecc.layout = &atmel_oobinfo_small;
3c3796cc	490	ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
77f5492c RG	491	break;
77f5492c RG	492	case 1024:
3c3796cc HS	493	nand_chip->ecc.layout = &atmel_oobinfo_large;
3c3796cc HS	494	ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
77f5492c RG	495	break;
77f5492c RG	496	case 2048:
3c3796cc HS	497	nand_chip->ecc.layout = &atmel_oobinfo_large;
3c3796cc HS	498	ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
77f5492c RG	499	break;
77f5492c RG	500	case 4096:
3c3796cc HS	501	nand_chip->ecc.layout = &atmel_oobinfo_large;
3c3796cc HS	502	ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
77f5492c RG	503	break;
	504	default:
	505	/* page size not handled by HW ECC */
	506	/* switching back to soft ECC */
	507	nand_chip->ecc.mode = NAND_ECC_SOFT;
	508	nand_chip->ecc.calculate = NULL;
	509	nand_chip->ecc.correct = NULL;
	510	nand_chip->ecc.hwctl = NULL;
	511	nand_chip->ecc.read_page = NULL;
	512	nand_chip->ecc.postpad = 0;
	513	nand_chip->ecc.prepad = 0;
	514	nand_chip->ecc.bytes = 0;
	515	break;
	516	}
	517	}
	518
	519	/* second phase scan */
	520	if (nand_scan_tail(mtd)) {
42cb1403	521	res = -ENXIO;
cc0c72e1	522	goto err_scan_tail;
42cb1403 AV	523	}
	524
	525	#ifdef CONFIG_MTD_PARTITIONS
693ef66d	526	#ifdef CONFIG_MTD_CMDLINE_PARTS
3c3796cc	527	mtd->name = "atmel_nand";
842b1a10 AN	528	num_partitions = parse_mtd_partitions(mtd, part_probes,
842b1a10 AN	529	&partitions, 0);
693ef66d	530	#endif
842b1a10 AN	531	if (num_partitions <= 0 && host->board->partition_info)
	532	partitions = host->board->partition_info(mtd->size,
	533	&num_partitions);
42cb1403 AV	534
42cb1403 AV	535	if ((!partitions) \|\| (num_partitions == 0)) {
ae27a7ab	536	printk(KERN_ERR "atmel_nand: No partitions defined, or unsupported device.\n");
895fb494	537	res = -ENXIO;
cc0c72e1	538	goto err_no_partitions;
42cb1403 AV	539	}
	540
	541	res = add_mtd_partitions(mtd, partitions, num_partitions);
	542	#else
	543	res = add_mtd_device(mtd);
	544	#endif
	545
	546	if (!res)
	547	return res;
	548
77f5492c	549	#ifdef CONFIG_MTD_PARTITIONS
cc0c72e1	550	err_no_partitions:
77f5492c	551	#endif
42cb1403	552	nand_release(mtd);
cc0c72e1 HS	553	err_scan_tail:
	554	err_scan_ident:
	555	err_no_card:
3c3796cc	556	atmel_nand_disable(host);
42cb1403	557	platform_set_drvdata(pdev, NULL);
cc0c72e1 HS	558	if (host->ecc)
	559	iounmap(host->ecc);
	560	err_ecc_ioremap:
42cb1403	561	iounmap(host->io_base);
cc0c72e1	562	err_nand_ioremap:
42cb1403 AV	563	kfree(host);
	564	return res;
	565	}
	566
	567	/*
	568	* Remove a NAND device.
	569	*/
23a346ca	570	static int __exit atmel_nand_remove(struct platform_device *pdev)
42cb1403	571	{
3c3796cc	572	struct atmel_nand_host *host = platform_get_drvdata(pdev);
42cb1403 AV	573	struct mtd_info *mtd = &host->mtd;
	574
	575	nand_release(mtd);
	576
3c3796cc	577	atmel_nand_disable(host);
42cb1403	578
cc0c72e1 HS	579	if (host->ecc)
cc0c72e1 HS	580	iounmap(host->ecc);
42cb1403 AV	581	iounmap(host->io_base);
	582	kfree(host);
	583
	584	return 0;
	585	}
	586
3c3796cc	587	static struct platform_driver atmel_nand_driver = {
23a346ca	588	.remove = __exit_p(atmel_nand_remove),
42cb1403	589	.driver = {
3c3796cc	590	.name = "atmel_nand",
42cb1403 AV	591	.owner = THIS_MODULE,
	592	},
	593	};
	594
3c3796cc	595	static int __init atmel_nand_init(void)
42cb1403	596	{
23a346ca	597	return platform_driver_probe(&atmel_nand_driver, atmel_nand_probe);
42cb1403 AV	598	}
	599
	600
3c3796cc	601	static void __exit atmel_nand_exit(void)
42cb1403	602	{
3c3796cc	603	platform_driver_unregister(&atmel_nand_driver);
42cb1403 AV	604	}
	605
	606
3c3796cc HS	607	module_init(atmel_nand_init);
3c3796cc HS	608	module_exit(atmel_nand_exit);
42cb1403 AV	609
	610	MODULE_LICENSE("GPL");
	611	MODULE_AUTHOR("Rick Bronson");
d4f4c0aa	612	MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
3c3796cc	613	MODULE_ALIAS("platform:atmel_nand");