Commit | Line | Data |
---|---|---|
42cb1403 | 1 | /* |
42cb1403 AV |
2 | * Copyright (C) 2003 Rick Bronson |
3 | * | |
4 | * Derived from drivers/mtd/nand/autcpu12.c | |
5 | * Copyright (c) 2001 Thomas Gleixner (gleixner@autronix.de) | |
6 | * | |
7 | * Derived from drivers/mtd/spia.c | |
8 | * Copyright (C) 2000 Steven J. Hill (sjhill@cotw.com) | |
9 | * | |
77f5492c RG |
10 | * |
11 | * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263 | |
12 | * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright (C) 2007 | |
13 | * | |
14 | * Derived from Das U-Boot source code | |
15 | * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c) | |
16 | * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas | |
17 | * | |
18 | * | |
42cb1403 AV |
19 | * This program is free software; you can redistribute it and/or modify |
20 | * it under the terms of the GNU General Public License version 2 as | |
21 | * published by the Free Software Foundation. | |
22 | * | |
23 | */ | |
24 | ||
b7f080cf | 25 | #include <linux/dma-mapping.h> |
42cb1403 AV |
26 | #include <linux/slab.h> |
27 | #include <linux/module.h> | |
f4fa697c | 28 | #include <linux/moduleparam.h> |
42cb1403 AV |
29 | #include <linux/platform_device.h> |
30 | #include <linux/mtd/mtd.h> | |
31 | #include <linux/mtd/nand.h> | |
32 | #include <linux/mtd/partitions.h> | |
33 | ||
5c39c4c5 | 34 | #include <linux/dmaengine.h> |
90574d0a DW |
35 | #include <linux/gpio.h> |
36 | #include <linux/io.h> | |
42cb1403 | 37 | |
a09e64fb RK |
38 | #include <mach/board.h> |
39 | #include <mach/cpu.h> | |
42cb1403 | 40 | |
d4f4c0aa | 41 | #ifdef CONFIG_MTD_NAND_ATMEL_ECC_HW |
77f5492c RG |
42 | #define hard_ecc 1 |
43 | #else | |
44 | #define hard_ecc 0 | |
45 | #endif | |
46 | ||
d4f4c0aa | 47 | #ifdef CONFIG_MTD_NAND_ATMEL_ECC_NONE |
77f5492c RG |
48 | #define no_ecc 1 |
49 | #else | |
50 | #define no_ecc 0 | |
51 | #endif | |
52 | ||
cbc6c5e7 HX |
53 | static int use_dma = 1; |
54 | module_param(use_dma, int, 0); | |
55 | ||
f4fa697c SP |
56 | static int on_flash_bbt = 0; |
57 | module_param(on_flash_bbt, int, 0); | |
58 | ||
77f5492c RG |
59 | /* Register access macros */ |
60 | #define ecc_readl(add, reg) \ | |
3c3796cc | 61 | __raw_readl(add + ATMEL_ECC_##reg) |
77f5492c | 62 | #define ecc_writel(add, reg, value) \ |
3c3796cc | 63 | __raw_writel((value), add + ATMEL_ECC_##reg) |
77f5492c | 64 | |
d4f4c0aa | 65 | #include "atmel_nand_ecc.h" /* Hardware ECC registers */ |
77f5492c RG |
66 | |
67 | /* oob layout for large page size | |
68 | * bad block info is on bytes 0 and 1 | |
69 | * the bytes have to be consecutives to avoid | |
70 | * several NAND_CMD_RNDOUT during read | |
71 | */ | |
3c3796cc | 72 | static struct nand_ecclayout atmel_oobinfo_large = { |
77f5492c RG |
73 | .eccbytes = 4, |
74 | .eccpos = {60, 61, 62, 63}, | |
75 | .oobfree = { | |
76 | {2, 58} | |
77 | }, | |
78 | }; | |
79 | ||
80 | /* oob layout for small page size | |
81 | * bad block info is on bytes 4 and 5 | |
82 | * the bytes have to be consecutives to avoid | |
83 | * several NAND_CMD_RNDOUT during read | |
84 | */ | |
3c3796cc | 85 | static struct nand_ecclayout atmel_oobinfo_small = { |
77f5492c RG |
86 | .eccbytes = 4, |
87 | .eccpos = {0, 1, 2, 3}, | |
88 | .oobfree = { | |
89 | {6, 10} | |
90 | }, | |
91 | }; | |
92 | ||
3c3796cc | 93 | struct atmel_nand_host { |
42cb1403 AV |
94 | struct nand_chip nand_chip; |
95 | struct mtd_info mtd; | |
96 | void __iomem *io_base; | |
cbc6c5e7 | 97 | dma_addr_t io_phys; |
3c3796cc | 98 | struct atmel_nand_data *board; |
77f5492c RG |
99 | struct device *dev; |
100 | void __iomem *ecc; | |
cbc6c5e7 HX |
101 | |
102 | struct completion comp; | |
103 | struct dma_chan *dma_chan; | |
42cb1403 AV |
104 | }; |
105 | ||
cbc6c5e7 HX |
106 | static int cpu_has_dma(void) |
107 | { | |
108 | return cpu_is_at91sam9rl() || cpu_is_at91sam9g45(); | |
109 | } | |
110 | ||
8136508c AN |
111 | /* |
112 | * Enable NAND. | |
113 | */ | |
3c3796cc | 114 | static void atmel_nand_enable(struct atmel_nand_host *host) |
8136508c AN |
115 | { |
116 | if (host->board->enable_pin) | |
62fd71fe | 117 | gpio_set_value(host->board->enable_pin, 0); |
8136508c AN |
118 | } |
119 | ||
120 | /* | |
121 | * Disable NAND. | |
122 | */ | |
3c3796cc | 123 | static void atmel_nand_disable(struct atmel_nand_host *host) |
8136508c AN |
124 | { |
125 | if (host->board->enable_pin) | |
62fd71fe | 126 | gpio_set_value(host->board->enable_pin, 1); |
8136508c AN |
127 | } |
128 | ||
42cb1403 AV |
129 | /* |
130 | * Hardware specific access to control-lines | |
131 | */ | |
3c3796cc | 132 | static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
42cb1403 AV |
133 | { |
134 | struct nand_chip *nand_chip = mtd->priv; | |
3c3796cc | 135 | struct atmel_nand_host *host = nand_chip->priv; |
42cb1403 | 136 | |
8136508c | 137 | if (ctrl & NAND_CTRL_CHANGE) { |
2314488e | 138 | if (ctrl & NAND_NCE) |
3c3796cc | 139 | atmel_nand_enable(host); |
2314488e | 140 | else |
3c3796cc | 141 | atmel_nand_disable(host); |
2314488e | 142 | } |
42cb1403 AV |
143 | if (cmd == NAND_CMD_NONE) |
144 | return; | |
145 | ||
146 | if (ctrl & NAND_CLE) | |
147 | writeb(cmd, host->io_base + (1 << host->board->cle)); | |
148 | else | |
149 | writeb(cmd, host->io_base + (1 << host->board->ale)); | |
150 | } | |
151 | ||
152 | /* | |
153 | * Read the Device Ready pin. | |
154 | */ | |
3c3796cc | 155 | static int atmel_nand_device_ready(struct mtd_info *mtd) |
42cb1403 AV |
156 | { |
157 | struct nand_chip *nand_chip = mtd->priv; | |
3c3796cc | 158 | struct atmel_nand_host *host = nand_chip->priv; |
42cb1403 | 159 | |
744f6592 GC |
160 | return gpio_get_value(host->board->rdy_pin) ^ |
161 | !!host->board->rdy_pin_active_low; | |
42cb1403 AV |
162 | } |
163 | ||
23a346ca DB |
164 | /* |
165 | * Minimal-overhead PIO for data access. | |
166 | */ | |
cbc6c5e7 | 167 | static void atmel_read_buf8(struct mtd_info *mtd, u8 *buf, int len) |
23a346ca DB |
168 | { |
169 | struct nand_chip *nand_chip = mtd->priv; | |
170 | ||
171 | __raw_readsb(nand_chip->IO_ADDR_R, buf, len); | |
172 | } | |
173 | ||
174 | static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len) | |
175 | { | |
176 | struct nand_chip *nand_chip = mtd->priv; | |
177 | ||
178 | __raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2); | |
179 | } | |
180 | ||
cbc6c5e7 | 181 | static void atmel_write_buf8(struct mtd_info *mtd, const u8 *buf, int len) |
23a346ca DB |
182 | { |
183 | struct nand_chip *nand_chip = mtd->priv; | |
184 | ||
185 | __raw_writesb(nand_chip->IO_ADDR_W, buf, len); | |
186 | } | |
187 | ||
188 | static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len) | |
189 | { | |
190 | struct nand_chip *nand_chip = mtd->priv; | |
191 | ||
192 | __raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2); | |
193 | } | |
194 | ||
cbc6c5e7 HX |
195 | static void dma_complete_func(void *completion) |
196 | { | |
197 | complete(completion); | |
198 | } | |
199 | ||
200 | static int atmel_nand_dma_op(struct mtd_info *mtd, void *buf, int len, | |
201 | int is_read) | |
202 | { | |
203 | struct dma_device *dma_dev; | |
204 | enum dma_ctrl_flags flags; | |
205 | dma_addr_t dma_src_addr, dma_dst_addr, phys_addr; | |
206 | struct dma_async_tx_descriptor *tx = NULL; | |
207 | dma_cookie_t cookie; | |
208 | struct nand_chip *chip = mtd->priv; | |
209 | struct atmel_nand_host *host = chip->priv; | |
210 | void *p = buf; | |
211 | int err = -EIO; | |
212 | enum dma_data_direction dir = is_read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; | |
213 | ||
80b4f81a HX |
214 | if (buf >= high_memory) |
215 | goto err_buf; | |
cbc6c5e7 HX |
216 | |
217 | dma_dev = host->dma_chan->device; | |
218 | ||
219 | flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT | DMA_COMPL_SKIP_SRC_UNMAP | | |
220 | DMA_COMPL_SKIP_DEST_UNMAP; | |
221 | ||
222 | phys_addr = dma_map_single(dma_dev->dev, p, len, dir); | |
223 | if (dma_mapping_error(dma_dev->dev, phys_addr)) { | |
224 | dev_err(host->dev, "Failed to dma_map_single\n"); | |
225 | goto err_buf; | |
226 | } | |
227 | ||
228 | if (is_read) { | |
229 | dma_src_addr = host->io_phys; | |
230 | dma_dst_addr = phys_addr; | |
231 | } else { | |
232 | dma_src_addr = phys_addr; | |
233 | dma_dst_addr = host->io_phys; | |
234 | } | |
235 | ||
236 | tx = dma_dev->device_prep_dma_memcpy(host->dma_chan, dma_dst_addr, | |
237 | dma_src_addr, len, flags); | |
238 | if (!tx) { | |
239 | dev_err(host->dev, "Failed to prepare DMA memcpy\n"); | |
240 | goto err_dma; | |
241 | } | |
242 | ||
243 | init_completion(&host->comp); | |
244 | tx->callback = dma_complete_func; | |
245 | tx->callback_param = &host->comp; | |
246 | ||
247 | cookie = tx->tx_submit(tx); | |
248 | if (dma_submit_error(cookie)) { | |
249 | dev_err(host->dev, "Failed to do DMA tx_submit\n"); | |
250 | goto err_dma; | |
251 | } | |
252 | ||
253 | dma_async_issue_pending(host->dma_chan); | |
254 | wait_for_completion(&host->comp); | |
255 | ||
256 | err = 0; | |
257 | ||
258 | err_dma: | |
259 | dma_unmap_single(dma_dev->dev, phys_addr, len, dir); | |
260 | err_buf: | |
261 | if (err != 0) | |
262 | dev_warn(host->dev, "Fall back to CPU I/O\n"); | |
263 | return err; | |
264 | } | |
265 | ||
266 | static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len) | |
267 | { | |
268 | struct nand_chip *chip = mtd->priv; | |
269 | struct atmel_nand_host *host = chip->priv; | |
270 | ||
9d51567e NF |
271 | if (use_dma && len > mtd->oobsize) |
272 | /* only use DMA for bigger than oob size: better performances */ | |
cbc6c5e7 HX |
273 | if (atmel_nand_dma_op(mtd, buf, len, 1) == 0) |
274 | return; | |
275 | ||
276 | if (host->board->bus_width_16) | |
277 | atmel_read_buf16(mtd, buf, len); | |
278 | else | |
279 | atmel_read_buf8(mtd, buf, len); | |
280 | } | |
281 | ||
282 | static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len) | |
283 | { | |
284 | struct nand_chip *chip = mtd->priv; | |
285 | struct atmel_nand_host *host = chip->priv; | |
286 | ||
9d51567e NF |
287 | if (use_dma && len > mtd->oobsize) |
288 | /* only use DMA for bigger than oob size: better performances */ | |
cbc6c5e7 HX |
289 | if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) == 0) |
290 | return; | |
291 | ||
292 | if (host->board->bus_width_16) | |
293 | atmel_write_buf16(mtd, buf, len); | |
294 | else | |
295 | atmel_write_buf8(mtd, buf, len); | |
296 | } | |
297 | ||
77f5492c RG |
298 | /* |
299 | * Calculate HW ECC | |
300 | * | |
301 | * function called after a write | |
302 | * | |
303 | * mtd: MTD block structure | |
304 | * dat: raw data (unused) | |
305 | * ecc_code: buffer for ECC | |
306 | */ | |
3c3796cc | 307 | static int atmel_nand_calculate(struct mtd_info *mtd, |
77f5492c RG |
308 | const u_char *dat, unsigned char *ecc_code) |
309 | { | |
310 | struct nand_chip *nand_chip = mtd->priv; | |
3c3796cc | 311 | struct atmel_nand_host *host = nand_chip->priv; |
77f5492c RG |
312 | unsigned int ecc_value; |
313 | ||
314 | /* get the first 2 ECC bytes */ | |
d43fa149 | 315 | ecc_value = ecc_readl(host->ecc, PR); |
77f5492c | 316 | |
3fc23898 RG |
317 | ecc_code[0] = ecc_value & 0xFF; |
318 | ecc_code[1] = (ecc_value >> 8) & 0xFF; | |
77f5492c RG |
319 | |
320 | /* get the last 2 ECC bytes */ | |
3c3796cc | 321 | ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY; |
77f5492c | 322 | |
3fc23898 RG |
323 | ecc_code[2] = ecc_value & 0xFF; |
324 | ecc_code[3] = (ecc_value >> 8) & 0xFF; | |
77f5492c RG |
325 | |
326 | return 0; | |
327 | } | |
328 | ||
329 | /* | |
330 | * HW ECC read page function | |
331 | * | |
332 | * mtd: mtd info structure | |
333 | * chip: nand chip info structure | |
334 | * buf: buffer to store read data | |
335 | */ | |
3c3796cc | 336 | static int atmel_nand_read_page(struct mtd_info *mtd, |
46a8cf2d | 337 | struct nand_chip *chip, uint8_t *buf, int page) |
77f5492c RG |
338 | { |
339 | int eccsize = chip->ecc.size; | |
340 | int eccbytes = chip->ecc.bytes; | |
341 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
342 | uint8_t *p = buf; | |
343 | uint8_t *oob = chip->oob_poi; | |
344 | uint8_t *ecc_pos; | |
345 | int stat; | |
346 | ||
d6248fdd HS |
347 | /* |
348 | * Errata: ALE is incorrectly wired up to the ECC controller | |
349 | * on the AP7000, so it will include the address cycles in the | |
350 | * ECC calculation. | |
351 | * | |
352 | * Workaround: Reset the parity registers before reading the | |
353 | * actual data. | |
354 | */ | |
355 | if (cpu_is_at32ap7000()) { | |
356 | struct atmel_nand_host *host = chip->priv; | |
357 | ecc_writel(host->ecc, CR, ATMEL_ECC_RST); | |
358 | } | |
359 | ||
77f5492c RG |
360 | /* read the page */ |
361 | chip->read_buf(mtd, p, eccsize); | |
362 | ||
363 | /* move to ECC position if needed */ | |
364 | if (eccpos[0] != 0) { | |
365 | /* This only works on large pages | |
366 | * because the ECC controller waits for | |
367 | * NAND_CMD_RNDOUTSTART after the | |
368 | * NAND_CMD_RNDOUT. | |
369 | * anyway, for small pages, the eccpos[0] == 0 | |
370 | */ | |
371 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, | |
372 | mtd->writesize + eccpos[0], -1); | |
373 | } | |
374 | ||
375 | /* the ECC controller needs to read the ECC just after the data */ | |
376 | ecc_pos = oob + eccpos[0]; | |
377 | chip->read_buf(mtd, ecc_pos, eccbytes); | |
378 | ||
379 | /* check if there's an error */ | |
380 | stat = chip->ecc.correct(mtd, p, oob, NULL); | |
381 | ||
382 | if (stat < 0) | |
383 | mtd->ecc_stats.failed++; | |
384 | else | |
385 | mtd->ecc_stats.corrected += stat; | |
386 | ||
387 | /* get back to oob start (end of page) */ | |
388 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1); | |
389 | ||
390 | /* read the oob */ | |
391 | chip->read_buf(mtd, oob, mtd->oobsize); | |
392 | ||
393 | return 0; | |
394 | } | |
395 | ||
396 | /* | |
397 | * HW ECC Correction | |
398 | * | |
399 | * function called after a read | |
400 | * | |
401 | * mtd: MTD block structure | |
402 | * dat: raw data read from the chip | |
403 | * read_ecc: ECC from the chip (unused) | |
404 | * isnull: unused | |
405 | * | |
406 | * Detect and correct a 1 bit error for a page | |
407 | */ | |
3c3796cc | 408 | static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat, |
77f5492c RG |
409 | u_char *read_ecc, u_char *isnull) |
410 | { | |
411 | struct nand_chip *nand_chip = mtd->priv; | |
3c3796cc | 412 | struct atmel_nand_host *host = nand_chip->priv; |
77f5492c RG |
413 | unsigned int ecc_status; |
414 | unsigned int ecc_word, ecc_bit; | |
415 | ||
416 | /* get the status from the Status Register */ | |
417 | ecc_status = ecc_readl(host->ecc, SR); | |
418 | ||
419 | /* if there's no error */ | |
3c3796cc | 420 | if (likely(!(ecc_status & ATMEL_ECC_RECERR))) |
77f5492c RG |
421 | return 0; |
422 | ||
423 | /* get error bit offset (4 bits) */ | |
3c3796cc | 424 | ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR; |
77f5492c | 425 | /* get word address (12 bits) */ |
3c3796cc | 426 | ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR; |
77f5492c RG |
427 | ecc_word >>= 4; |
428 | ||
429 | /* if there are multiple errors */ | |
3c3796cc | 430 | if (ecc_status & ATMEL_ECC_MULERR) { |
77f5492c RG |
431 | /* check if it is a freshly erased block |
432 | * (filled with 0xff) */ | |
3c3796cc HS |
433 | if ((ecc_bit == ATMEL_ECC_BITADDR) |
434 | && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) { | |
77f5492c RG |
435 | /* the block has just been erased, return OK */ |
436 | return 0; | |
437 | } | |
438 | /* it doesn't seems to be a freshly | |
439 | * erased block. | |
440 | * We can't correct so many errors */ | |
3c3796cc | 441 | dev_dbg(host->dev, "atmel_nand : multiple errors detected." |
77f5492c RG |
442 | " Unable to correct.\n"); |
443 | return -EIO; | |
444 | } | |
445 | ||
446 | /* if there's a single bit error : we can correct it */ | |
3c3796cc | 447 | if (ecc_status & ATMEL_ECC_ECCERR) { |
77f5492c RG |
448 | /* there's nothing much to do here. |
449 | * the bit error is on the ECC itself. | |
450 | */ | |
3c3796cc | 451 | dev_dbg(host->dev, "atmel_nand : one bit error on ECC code." |
77f5492c RG |
452 | " Nothing to correct\n"); |
453 | return 0; | |
454 | } | |
455 | ||
3c3796cc | 456 | dev_dbg(host->dev, "atmel_nand : one bit error on data." |
77f5492c RG |
457 | " (word offset in the page :" |
458 | " 0x%x bit offset : 0x%x)\n", | |
459 | ecc_word, ecc_bit); | |
460 | /* correct the error */ | |
461 | if (nand_chip->options & NAND_BUSWIDTH_16) { | |
462 | /* 16 bits words */ | |
463 | ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit); | |
464 | } else { | |
465 | /* 8 bits words */ | |
466 | dat[ecc_word] ^= (1 << ecc_bit); | |
467 | } | |
3c3796cc | 468 | dev_dbg(host->dev, "atmel_nand : error corrected\n"); |
77f5492c RG |
469 | return 1; |
470 | } | |
471 | ||
472 | /* | |
d6248fdd | 473 | * Enable HW ECC : unused on most chips |
77f5492c | 474 | */ |
d6248fdd HS |
475 | static void atmel_nand_hwctl(struct mtd_info *mtd, int mode) |
476 | { | |
477 | if (cpu_is_at32ap7000()) { | |
478 | struct nand_chip *nand_chip = mtd->priv; | |
479 | struct atmel_nand_host *host = nand_chip->priv; | |
480 | ecc_writel(host->ecc, CR, ATMEL_ECC_RST); | |
481 | } | |
482 | } | |
77f5492c | 483 | |
9a9745c3 | 484 | #ifdef CONFIG_MTD_CMDLINE_PARTS |
52f83014 | 485 | static const char *part_probes[] = { "cmdlinepart", NULL }; |
693ef66d AV |
486 | #endif |
487 | ||
42cb1403 AV |
488 | /* |
489 | * Probe for the NAND device. | |
490 | */ | |
3c3796cc | 491 | static int __init atmel_nand_probe(struct platform_device *pdev) |
42cb1403 | 492 | { |
3c3796cc | 493 | struct atmel_nand_host *host; |
42cb1403 AV |
494 | struct mtd_info *mtd; |
495 | struct nand_chip *nand_chip; | |
77f5492c RG |
496 | struct resource *regs; |
497 | struct resource *mem; | |
42cb1403 | 498 | int res; |
42cb1403 AV |
499 | struct mtd_partition *partitions = NULL; |
500 | int num_partitions = 0; | |
42cb1403 | 501 | |
cc0c72e1 HS |
502 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
503 | if (!mem) { | |
504 | printk(KERN_ERR "atmel_nand: can't get I/O resource mem\n"); | |
505 | return -ENXIO; | |
506 | } | |
507 | ||
42cb1403 | 508 | /* Allocate memory for the device structure (and zero it) */ |
3c3796cc | 509 | host = kzalloc(sizeof(struct atmel_nand_host), GFP_KERNEL); |
42cb1403 | 510 | if (!host) { |
3c3796cc | 511 | printk(KERN_ERR "atmel_nand: failed to allocate device structure.\n"); |
42cb1403 AV |
512 | return -ENOMEM; |
513 | } | |
514 | ||
cbc6c5e7 HX |
515 | host->io_phys = (dma_addr_t)mem->start; |
516 | ||
28f65c11 | 517 | host->io_base = ioremap(mem->start, resource_size(mem)); |
42cb1403 | 518 | if (host->io_base == NULL) { |
3c3796cc | 519 | printk(KERN_ERR "atmel_nand: ioremap failed\n"); |
cc0c72e1 HS |
520 | res = -EIO; |
521 | goto err_nand_ioremap; | |
42cb1403 AV |
522 | } |
523 | ||
524 | mtd = &host->mtd; | |
525 | nand_chip = &host->nand_chip; | |
526 | host->board = pdev->dev.platform_data; | |
77f5492c | 527 | host->dev = &pdev->dev; |
42cb1403 AV |
528 | |
529 | nand_chip->priv = host; /* link the private data structures */ | |
530 | mtd->priv = nand_chip; | |
531 | mtd->owner = THIS_MODULE; | |
532 | ||
533 | /* Set address of NAND IO lines */ | |
534 | nand_chip->IO_ADDR_R = host->io_base; | |
535 | nand_chip->IO_ADDR_W = host->io_base; | |
3c3796cc | 536 | nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl; |
a4265f8d IK |
537 | |
538 | if (host->board->rdy_pin) | |
3c3796cc | 539 | nand_chip->dev_ready = atmel_nand_device_ready; |
a4265f8d | 540 | |
77f5492c RG |
541 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
542 | if (!regs && hard_ecc) { | |
3c3796cc | 543 | printk(KERN_ERR "atmel_nand: can't get I/O resource " |
77f5492c RG |
544 | "regs\nFalling back on software ECC\n"); |
545 | } | |
546 | ||
42cb1403 | 547 | nand_chip->ecc.mode = NAND_ECC_SOFT; /* enable ECC */ |
77f5492c RG |
548 | if (no_ecc) |
549 | nand_chip->ecc.mode = NAND_ECC_NONE; | |
550 | if (hard_ecc && regs) { | |
28f65c11 | 551 | host->ecc = ioremap(regs->start, resource_size(regs)); |
77f5492c | 552 | if (host->ecc == NULL) { |
3c3796cc | 553 | printk(KERN_ERR "atmel_nand: ioremap failed\n"); |
77f5492c RG |
554 | res = -EIO; |
555 | goto err_ecc_ioremap; | |
556 | } | |
3fc23898 | 557 | nand_chip->ecc.mode = NAND_ECC_HW; |
3c3796cc HS |
558 | nand_chip->ecc.calculate = atmel_nand_calculate; |
559 | nand_chip->ecc.correct = atmel_nand_correct; | |
560 | nand_chip->ecc.hwctl = atmel_nand_hwctl; | |
561 | nand_chip->ecc.read_page = atmel_nand_read_page; | |
77f5492c | 562 | nand_chip->ecc.bytes = 4; |
77f5492c RG |
563 | } |
564 | ||
42cb1403 AV |
565 | nand_chip->chip_delay = 20; /* 20us command delay time */ |
566 | ||
cbc6c5e7 | 567 | if (host->board->bus_width_16) /* 16-bit bus width */ |
dd11b8cd | 568 | nand_chip->options |= NAND_BUSWIDTH_16; |
cbc6c5e7 HX |
569 | |
570 | nand_chip->read_buf = atmel_read_buf; | |
571 | nand_chip->write_buf = atmel_write_buf; | |
dd11b8cd | 572 | |
42cb1403 | 573 | platform_set_drvdata(pdev, host); |
3c3796cc | 574 | atmel_nand_enable(host); |
42cb1403 AV |
575 | |
576 | if (host->board->det_pin) { | |
62fd71fe | 577 | if (gpio_get_value(host->board->det_pin)) { |
f4fa697c | 578 | printk(KERN_INFO "No SmartMedia card inserted.\n"); |
895fb494 | 579 | res = -ENXIO; |
cc0c72e1 | 580 | goto err_no_card; |
42cb1403 AV |
581 | } |
582 | } | |
583 | ||
f4fa697c SP |
584 | if (on_flash_bbt) { |
585 | printk(KERN_INFO "atmel_nand: Use On Flash BBT\n"); | |
a40f7341 | 586 | nand_chip->bbt_options |= NAND_USE_FLASH_BBT; |
f4fa697c SP |
587 | } |
588 | ||
cb457a4d HX |
589 | if (!cpu_has_dma()) |
590 | use_dma = 0; | |
591 | ||
592 | if (use_dma) { | |
cbc6c5e7 HX |
593 | dma_cap_mask_t mask; |
594 | ||
595 | dma_cap_zero(mask); | |
596 | dma_cap_set(DMA_MEMCPY, mask); | |
597 | host->dma_chan = dma_request_channel(mask, 0, NULL); | |
598 | if (!host->dma_chan) { | |
599 | dev_err(host->dev, "Failed to request DMA channel\n"); | |
600 | use_dma = 0; | |
601 | } | |
602 | } | |
603 | if (use_dma) | |
042bc9c0 NF |
604 | dev_info(host->dev, "Using %s for DMA transfers.\n", |
605 | dma_chan_name(host->dma_chan)); | |
cbc6c5e7 HX |
606 | else |
607 | dev_info(host->dev, "No DMA support for NAND access.\n"); | |
608 | ||
77f5492c | 609 | /* first scan to find the device and get the page size */ |
5e81e88a | 610 | if (nand_scan_ident(mtd, 1, NULL)) { |
77f5492c | 611 | res = -ENXIO; |
cc0c72e1 | 612 | goto err_scan_ident; |
77f5492c RG |
613 | } |
614 | ||
3fc23898 | 615 | if (nand_chip->ecc.mode == NAND_ECC_HW) { |
77f5492c RG |
616 | /* ECC is calculated for the whole page (1 step) */ |
617 | nand_chip->ecc.size = mtd->writesize; | |
618 | ||
619 | /* set ECC page size and oob layout */ | |
620 | switch (mtd->writesize) { | |
621 | case 512: | |
3c3796cc | 622 | nand_chip->ecc.layout = &atmel_oobinfo_small; |
3c3796cc | 623 | ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528); |
77f5492c RG |
624 | break; |
625 | case 1024: | |
3c3796cc HS |
626 | nand_chip->ecc.layout = &atmel_oobinfo_large; |
627 | ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056); | |
77f5492c RG |
628 | break; |
629 | case 2048: | |
3c3796cc HS |
630 | nand_chip->ecc.layout = &atmel_oobinfo_large; |
631 | ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112); | |
77f5492c RG |
632 | break; |
633 | case 4096: | |
3c3796cc HS |
634 | nand_chip->ecc.layout = &atmel_oobinfo_large; |
635 | ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224); | |
77f5492c RG |
636 | break; |
637 | default: | |
638 | /* page size not handled by HW ECC */ | |
639 | /* switching back to soft ECC */ | |
640 | nand_chip->ecc.mode = NAND_ECC_SOFT; | |
641 | nand_chip->ecc.calculate = NULL; | |
642 | nand_chip->ecc.correct = NULL; | |
643 | nand_chip->ecc.hwctl = NULL; | |
644 | nand_chip->ecc.read_page = NULL; | |
645 | nand_chip->ecc.postpad = 0; | |
646 | nand_chip->ecc.prepad = 0; | |
647 | nand_chip->ecc.bytes = 0; | |
648 | break; | |
649 | } | |
650 | } | |
651 | ||
652 | /* second phase scan */ | |
653 | if (nand_scan_tail(mtd)) { | |
42cb1403 | 654 | res = -ENXIO; |
cc0c72e1 | 655 | goto err_scan_tail; |
42cb1403 AV |
656 | } |
657 | ||
693ef66d | 658 | #ifdef CONFIG_MTD_CMDLINE_PARTS |
3c3796cc | 659 | mtd->name = "atmel_nand"; |
842b1a10 AN |
660 | num_partitions = parse_mtd_partitions(mtd, part_probes, |
661 | &partitions, 0); | |
693ef66d | 662 | #endif |
842b1a10 AN |
663 | if (num_partitions <= 0 && host->board->partition_info) |
664 | partitions = host->board->partition_info(mtd->size, | |
665 | &num_partitions); | |
42cb1403 AV |
666 | |
667 | if ((!partitions) || (num_partitions == 0)) { | |
ae27a7ab | 668 | printk(KERN_ERR "atmel_nand: No partitions defined, or unsupported device.\n"); |
895fb494 | 669 | res = -ENXIO; |
cc0c72e1 | 670 | goto err_no_partitions; |
42cb1403 AV |
671 | } |
672 | ||
e6232b42 | 673 | res = mtd_device_register(mtd, partitions, num_partitions); |
42cb1403 AV |
674 | if (!res) |
675 | return res; | |
676 | ||
cc0c72e1 | 677 | err_no_partitions: |
42cb1403 | 678 | nand_release(mtd); |
cc0c72e1 HS |
679 | err_scan_tail: |
680 | err_scan_ident: | |
681 | err_no_card: | |
3c3796cc | 682 | atmel_nand_disable(host); |
42cb1403 | 683 | platform_set_drvdata(pdev, NULL); |
cbc6c5e7 HX |
684 | if (host->dma_chan) |
685 | dma_release_channel(host->dma_chan); | |
cc0c72e1 HS |
686 | if (host->ecc) |
687 | iounmap(host->ecc); | |
688 | err_ecc_ioremap: | |
42cb1403 | 689 | iounmap(host->io_base); |
cc0c72e1 | 690 | err_nand_ioremap: |
42cb1403 AV |
691 | kfree(host); |
692 | return res; | |
693 | } | |
694 | ||
695 | /* | |
696 | * Remove a NAND device. | |
697 | */ | |
23a346ca | 698 | static int __exit atmel_nand_remove(struct platform_device *pdev) |
42cb1403 | 699 | { |
3c3796cc | 700 | struct atmel_nand_host *host = platform_get_drvdata(pdev); |
42cb1403 AV |
701 | struct mtd_info *mtd = &host->mtd; |
702 | ||
703 | nand_release(mtd); | |
704 | ||
3c3796cc | 705 | atmel_nand_disable(host); |
42cb1403 | 706 | |
cc0c72e1 HS |
707 | if (host->ecc) |
708 | iounmap(host->ecc); | |
cbc6c5e7 HX |
709 | |
710 | if (host->dma_chan) | |
711 | dma_release_channel(host->dma_chan); | |
712 | ||
42cb1403 AV |
713 | iounmap(host->io_base); |
714 | kfree(host); | |
715 | ||
716 | return 0; | |
717 | } | |
718 | ||
3c3796cc | 719 | static struct platform_driver atmel_nand_driver = { |
23a346ca | 720 | .remove = __exit_p(atmel_nand_remove), |
42cb1403 | 721 | .driver = { |
3c3796cc | 722 | .name = "atmel_nand", |
42cb1403 AV |
723 | .owner = THIS_MODULE, |
724 | }, | |
725 | }; | |
726 | ||
3c3796cc | 727 | static int __init atmel_nand_init(void) |
42cb1403 | 728 | { |
23a346ca | 729 | return platform_driver_probe(&atmel_nand_driver, atmel_nand_probe); |
42cb1403 AV |
730 | } |
731 | ||
732 | ||
3c3796cc | 733 | static void __exit atmel_nand_exit(void) |
42cb1403 | 734 | { |
3c3796cc | 735 | platform_driver_unregister(&atmel_nand_driver); |
42cb1403 AV |
736 | } |
737 | ||
738 | ||
3c3796cc HS |
739 | module_init(atmel_nand_init); |
740 | module_exit(atmel_nand_exit); | |
42cb1403 AV |
741 | |
742 | MODULE_LICENSE("GPL"); | |
743 | MODULE_AUTHOR("Rick Bronson"); | |
d4f4c0aa | 744 | MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32"); |
3c3796cc | 745 | MODULE_ALIAS("platform:atmel_nand"); |