Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * drivers/mtd/nand/au1550nd.c | |
3 | * | |
4 | * Copyright (C) 2004 Embedded Edge, LLC | |
5 | * | |
1da177e4 LT |
6 | * This program is free software; you can redistribute it and/or modify |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | */ | |
11 | ||
12 | #include <linux/slab.h> | |
b7f720d6 | 13 | #include <linux/gpio.h> |
1da177e4 LT |
14 | #include <linux/init.h> |
15 | #include <linux/module.h> | |
35af68b5 | 16 | #include <linux/interrupt.h> |
1da177e4 LT |
17 | #include <linux/mtd/mtd.h> |
18 | #include <linux/mtd/nand.h> | |
19 | #include <linux/mtd/partitions.h> | |
20 | #include <asm/io.h> | |
21 | ||
50d5676e ML |
22 | #ifdef CONFIG_MIPS_PB1550 |
23 | #include <asm/mach-pb1x00/pb1550.h> | |
24 | #elif defined(CONFIG_MIPS_DB1550) | |
25 | #include <asm/mach-db1x00/db1x00.h> | |
26 | #endif | |
9bdcf336 | 27 | #include <asm/mach-db1x00/bcsr.h> |
1da177e4 LT |
28 | |
29 | /* | |
30 | * MTD structure for NAND controller | |
31 | */ | |
32 | static struct mtd_info *au1550_mtd = NULL; | |
33 | static void __iomem *p_nand; | |
e0c7d767 | 34 | static int nand_width = 1; /* default x8 */ |
cad74f2c | 35 | static void (*au1550_write_byte)(struct mtd_info *, u_char); |
1da177e4 | 36 | |
1da177e4 LT |
37 | /* |
38 | * Define partitions for flash device | |
39 | */ | |
3c6bee1d | 40 | static const struct mtd_partition partition_info[] = { |
61b03bd7 | 41 | { |
e0c7d767 DW |
42 | .name = "NAND FS 0", |
43 | .offset = 0, | |
44 | .size = 8 * 1024 * 1024}, | |
61b03bd7 | 45 | { |
e0c7d767 DW |
46 | .name = "NAND FS 1", |
47 | .offset = MTDPART_OFS_APPEND, | |
48 | .size = MTDPART_SIZ_FULL} | |
1da177e4 | 49 | }; |
1da177e4 LT |
50 | |
51 | /** | |
52 | * au_read_byte - read one byte from the chip | |
53 | * @mtd: MTD device structure | |
54 | * | |
7854d3f7 | 55 | * read function for 8bit buswidth |
1da177e4 LT |
56 | */ |
57 | static u_char au_read_byte(struct mtd_info *mtd) | |
58 | { | |
59 | struct nand_chip *this = mtd->priv; | |
60 | u_char ret = readb(this->IO_ADDR_R); | |
61 | au_sync(); | |
62 | return ret; | |
63 | } | |
64 | ||
65 | /** | |
66 | * au_write_byte - write one byte to the chip | |
67 | * @mtd: MTD device structure | |
68 | * @byte: pointer to data byte to write | |
69 | * | |
7854d3f7 | 70 | * write function for 8it buswidth |
1da177e4 LT |
71 | */ |
72 | static void au_write_byte(struct mtd_info *mtd, u_char byte) | |
73 | { | |
74 | struct nand_chip *this = mtd->priv; | |
75 | writeb(byte, this->IO_ADDR_W); | |
76 | au_sync(); | |
77 | } | |
78 | ||
79 | /** | |
7854d3f7 | 80 | * au_read_byte16 - read one byte endianness aware from the chip |
1da177e4 LT |
81 | * @mtd: MTD device structure |
82 | * | |
7854d3f7 | 83 | * read function for 16bit buswidth with endianness conversion |
1da177e4 LT |
84 | */ |
85 | static u_char au_read_byte16(struct mtd_info *mtd) | |
86 | { | |
87 | struct nand_chip *this = mtd->priv; | |
88 | u_char ret = (u_char) cpu_to_le16(readw(this->IO_ADDR_R)); | |
89 | au_sync(); | |
90 | return ret; | |
91 | } | |
92 | ||
93 | /** | |
7854d3f7 | 94 | * au_write_byte16 - write one byte endianness aware to the chip |
1da177e4 LT |
95 | * @mtd: MTD device structure |
96 | * @byte: pointer to data byte to write | |
97 | * | |
7854d3f7 | 98 | * write function for 16bit buswidth with endianness conversion |
1da177e4 LT |
99 | */ |
100 | static void au_write_byte16(struct mtd_info *mtd, u_char byte) | |
101 | { | |
102 | struct nand_chip *this = mtd->priv; | |
103 | writew(le16_to_cpu((u16) byte), this->IO_ADDR_W); | |
104 | au_sync(); | |
105 | } | |
106 | ||
107 | /** | |
108 | * au_read_word - read one word from the chip | |
109 | * @mtd: MTD device structure | |
110 | * | |
7854d3f7 | 111 | * read function for 16bit buswidth without endianness conversion |
1da177e4 LT |
112 | */ |
113 | static u16 au_read_word(struct mtd_info *mtd) | |
114 | { | |
115 | struct nand_chip *this = mtd->priv; | |
116 | u16 ret = readw(this->IO_ADDR_R); | |
117 | au_sync(); | |
118 | return ret; | |
119 | } | |
120 | ||
1da177e4 LT |
121 | /** |
122 | * au_write_buf - write buffer to chip | |
123 | * @mtd: MTD device structure | |
124 | * @buf: data buffer | |
125 | * @len: number of bytes to write | |
126 | * | |
7854d3f7 | 127 | * write function for 8bit buswidth |
1da177e4 LT |
128 | */ |
129 | static void au_write_buf(struct mtd_info *mtd, const u_char *buf, int len) | |
130 | { | |
131 | int i; | |
132 | struct nand_chip *this = mtd->priv; | |
133 | ||
e0c7d767 | 134 | for (i = 0; i < len; i++) { |
1da177e4 LT |
135 | writeb(buf[i], this->IO_ADDR_W); |
136 | au_sync(); | |
137 | } | |
138 | } | |
139 | ||
140 | /** | |
61b03bd7 | 141 | * au_read_buf - read chip data into buffer |
1da177e4 LT |
142 | * @mtd: MTD device structure |
143 | * @buf: buffer to store date | |
144 | * @len: number of bytes to read | |
145 | * | |
7854d3f7 | 146 | * read function for 8bit buswidth |
1da177e4 LT |
147 | */ |
148 | static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len) | |
149 | { | |
150 | int i; | |
151 | struct nand_chip *this = mtd->priv; | |
152 | ||
e0c7d767 | 153 | for (i = 0; i < len; i++) { |
1da177e4 | 154 | buf[i] = readb(this->IO_ADDR_R); |
61b03bd7 | 155 | au_sync(); |
1da177e4 LT |
156 | } |
157 | } | |
158 | ||
159 | /** | |
61b03bd7 | 160 | * au_verify_buf - Verify chip data against buffer |
1da177e4 LT |
161 | * @mtd: MTD device structure |
162 | * @buf: buffer containing the data to compare | |
163 | * @len: number of bytes to compare | |
164 | * | |
7854d3f7 | 165 | * verify function for 8bit buswidth |
1da177e4 LT |
166 | */ |
167 | static int au_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) | |
168 | { | |
169 | int i; | |
170 | struct nand_chip *this = mtd->priv; | |
171 | ||
e0c7d767 | 172 | for (i = 0; i < len; i++) { |
1da177e4 LT |
173 | if (buf[i] != readb(this->IO_ADDR_R)) |
174 | return -EFAULT; | |
175 | au_sync(); | |
176 | } | |
177 | ||
178 | return 0; | |
179 | } | |
180 | ||
181 | /** | |
182 | * au_write_buf16 - write buffer to chip | |
183 | * @mtd: MTD device structure | |
184 | * @buf: data buffer | |
185 | * @len: number of bytes to write | |
186 | * | |
7854d3f7 | 187 | * write function for 16bit buswidth |
1da177e4 LT |
188 | */ |
189 | static void au_write_buf16(struct mtd_info *mtd, const u_char *buf, int len) | |
190 | { | |
191 | int i; | |
192 | struct nand_chip *this = mtd->priv; | |
193 | u16 *p = (u16 *) buf; | |
194 | len >>= 1; | |
61b03bd7 | 195 | |
e0c7d767 | 196 | for (i = 0; i < len; i++) { |
1da177e4 LT |
197 | writew(p[i], this->IO_ADDR_W); |
198 | au_sync(); | |
199 | } | |
61b03bd7 | 200 | |
1da177e4 LT |
201 | } |
202 | ||
203 | /** | |
61b03bd7 | 204 | * au_read_buf16 - read chip data into buffer |
1da177e4 LT |
205 | * @mtd: MTD device structure |
206 | * @buf: buffer to store date | |
207 | * @len: number of bytes to read | |
208 | * | |
7854d3f7 | 209 | * read function for 16bit buswidth |
1da177e4 LT |
210 | */ |
211 | static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len) | |
212 | { | |
213 | int i; | |
214 | struct nand_chip *this = mtd->priv; | |
215 | u16 *p = (u16 *) buf; | |
216 | len >>= 1; | |
217 | ||
e0c7d767 | 218 | for (i = 0; i < len; i++) { |
1da177e4 LT |
219 | p[i] = readw(this->IO_ADDR_R); |
220 | au_sync(); | |
221 | } | |
222 | } | |
223 | ||
224 | /** | |
61b03bd7 | 225 | * au_verify_buf16 - Verify chip data against buffer |
1da177e4 LT |
226 | * @mtd: MTD device structure |
227 | * @buf: buffer containing the data to compare | |
228 | * @len: number of bytes to compare | |
229 | * | |
7854d3f7 | 230 | * verify function for 16bit buswidth |
1da177e4 LT |
231 | */ |
232 | static int au_verify_buf16(struct mtd_info *mtd, const u_char *buf, int len) | |
233 | { | |
234 | int i; | |
235 | struct nand_chip *this = mtd->priv; | |
236 | u16 *p = (u16 *) buf; | |
237 | len >>= 1; | |
238 | ||
e0c7d767 | 239 | for (i = 0; i < len; i++) { |
1da177e4 LT |
240 | if (p[i] != readw(this->IO_ADDR_R)) |
241 | return -EFAULT; | |
242 | au_sync(); | |
243 | } | |
244 | return 0; | |
245 | } | |
246 | ||
7abd3ef9 TG |
247 | /* Select the chip by setting nCE to low */ |
248 | #define NAND_CTL_SETNCE 1 | |
249 | /* Deselect the chip by setting nCE to high */ | |
250 | #define NAND_CTL_CLRNCE 2 | |
251 | /* Select the command latch by setting CLE to high */ | |
252 | #define NAND_CTL_SETCLE 3 | |
253 | /* Deselect the command latch by setting CLE to low */ | |
254 | #define NAND_CTL_CLRCLE 4 | |
255 | /* Select the address latch by setting ALE to high */ | |
256 | #define NAND_CTL_SETALE 5 | |
257 | /* Deselect the address latch by setting ALE to low */ | |
258 | #define NAND_CTL_CLRALE 6 | |
1da177e4 LT |
259 | |
260 | static void au1550_hwcontrol(struct mtd_info *mtd, int cmd) | |
261 | { | |
262 | register struct nand_chip *this = mtd->priv; | |
263 | ||
e0c7d767 DW |
264 | switch (cmd) { |
265 | ||
266 | case NAND_CTL_SETCLE: | |
267 | this->IO_ADDR_W = p_nand + MEM_STNAND_CMD; | |
268 | break; | |
269 | ||
270 | case NAND_CTL_CLRCLE: | |
271 | this->IO_ADDR_W = p_nand + MEM_STNAND_DATA; | |
272 | break; | |
1da177e4 | 273 | |
e0c7d767 DW |
274 | case NAND_CTL_SETALE: |
275 | this->IO_ADDR_W = p_nand + MEM_STNAND_ADDR; | |
276 | break; | |
1da177e4 | 277 | |
61b03bd7 TG |
278 | case NAND_CTL_CLRALE: |
279 | this->IO_ADDR_W = p_nand + MEM_STNAND_DATA; | |
e0c7d767 | 280 | /* FIXME: Nobody knows why this is necessary, |
1da177e4 | 281 | * but it works only that way */ |
61b03bd7 | 282 | udelay(1); |
1da177e4 LT |
283 | break; |
284 | ||
61b03bd7 | 285 | case NAND_CTL_SETNCE: |
1da177e4 | 286 | /* assert (force assert) chip enable */ |
e0c7d767 | 287 | au_writel((1 << (4 + NAND_CS)), MEM_STNDCTL); |
1da177e4 LT |
288 | break; |
289 | ||
61b03bd7 | 290 | case NAND_CTL_CLRNCE: |
e0c7d767 DW |
291 | /* deassert chip enable */ |
292 | au_writel(0, MEM_STNDCTL); | |
1da177e4 LT |
293 | break; |
294 | } | |
295 | ||
296 | this->IO_ADDR_R = this->IO_ADDR_W; | |
61b03bd7 | 297 | |
1da177e4 LT |
298 | /* Drain the writebuffer */ |
299 | au_sync(); | |
300 | } | |
301 | ||
302 | int au1550_device_ready(struct mtd_info *mtd) | |
303 | { | |
304 | int ret = (au_readl(MEM_STSTAT) & 0x1) ? 1 : 0; | |
305 | au_sync(); | |
306 | return ret; | |
307 | } | |
308 | ||
35af68b5 SS |
309 | /** |
310 | * au1550_select_chip - control -CE line | |
311 | * Forbid driving -CE manually permitting the NAND controller to do this. | |
312 | * Keeping -CE asserted during the whole sector reads interferes with the | |
313 | * NOR flash and PCMCIA drivers as it causes contention on the static bus. | |
314 | * We only have to hold -CE low for the NAND read commands since the flash | |
315 | * chip needs it to be asserted during chip not ready time but the NAND | |
316 | * controller keeps it released. | |
317 | * | |
318 | * @mtd: MTD device structure | |
319 | * @chip: chipnumber to select, -1 for deselect | |
320 | */ | |
321 | static void au1550_select_chip(struct mtd_info *mtd, int chip) | |
322 | { | |
323 | } | |
324 | ||
325 | /** | |
326 | * au1550_command - Send command to NAND device | |
327 | * @mtd: MTD device structure | |
328 | * @command: the command to be sent | |
329 | * @column: the column address for this command, -1 if none | |
330 | * @page_addr: the page address for this command, -1 if none | |
331 | */ | |
332 | static void au1550_command(struct mtd_info *mtd, unsigned command, int column, int page_addr) | |
333 | { | |
334 | register struct nand_chip *this = mtd->priv; | |
335 | int ce_override = 0, i; | |
336 | ulong flags; | |
337 | ||
338 | /* Begin command latch cycle */ | |
7abd3ef9 | 339 | au1550_hwcontrol(mtd, NAND_CTL_SETCLE); |
35af68b5 SS |
340 | /* |
341 | * Write out the command to the device. | |
342 | */ | |
343 | if (command == NAND_CMD_SEQIN) { | |
344 | int readcmd; | |
345 | ||
28318776 | 346 | if (column >= mtd->writesize) { |
35af68b5 | 347 | /* OOB area */ |
28318776 | 348 | column -= mtd->writesize; |
35af68b5 SS |
349 | readcmd = NAND_CMD_READOOB; |
350 | } else if (column < 256) { | |
351 | /* First 256 bytes --> READ0 */ | |
352 | readcmd = NAND_CMD_READ0; | |
353 | } else { | |
354 | column -= 256; | |
355 | readcmd = NAND_CMD_READ1; | |
356 | } | |
cad74f2c | 357 | au1550_write_byte(mtd, readcmd); |
35af68b5 | 358 | } |
cad74f2c | 359 | au1550_write_byte(mtd, command); |
35af68b5 SS |
360 | |
361 | /* Set ALE and clear CLE to start address cycle */ | |
7abd3ef9 | 362 | au1550_hwcontrol(mtd, NAND_CTL_CLRCLE); |
35af68b5 SS |
363 | |
364 | if (column != -1 || page_addr != -1) { | |
7abd3ef9 | 365 | au1550_hwcontrol(mtd, NAND_CTL_SETALE); |
35af68b5 SS |
366 | |
367 | /* Serially input address */ | |
368 | if (column != -1) { | |
369 | /* Adjust columns for 16 bit buswidth */ | |
370 | if (this->options & NAND_BUSWIDTH_16) | |
371 | column >>= 1; | |
cad74f2c | 372 | au1550_write_byte(mtd, column); |
35af68b5 SS |
373 | } |
374 | if (page_addr != -1) { | |
cad74f2c | 375 | au1550_write_byte(mtd, (u8)(page_addr & 0xff)); |
35af68b5 SS |
376 | |
377 | if (command == NAND_CMD_READ0 || | |
378 | command == NAND_CMD_READ1 || | |
379 | command == NAND_CMD_READOOB) { | |
380 | /* | |
381 | * NAND controller will release -CE after | |
382 | * the last address byte is written, so we'll | |
383 | * have to forcibly assert it. No interrupts | |
384 | * are allowed while we do this as we don't | |
385 | * want the NOR flash or PCMCIA drivers to | |
386 | * steal our precious bytes of data... | |
387 | */ | |
388 | ce_override = 1; | |
389 | local_irq_save(flags); | |
7abd3ef9 | 390 | au1550_hwcontrol(mtd, NAND_CTL_SETNCE); |
35af68b5 SS |
391 | } |
392 | ||
cad74f2c | 393 | au1550_write_byte(mtd, (u8)(page_addr >> 8)); |
35af68b5 SS |
394 | |
395 | /* One more address cycle for devices > 32MiB */ | |
396 | if (this->chipsize > (32 << 20)) | |
cad74f2c | 397 | au1550_write_byte(mtd, (u8)((page_addr >> 16) & 0x0f)); |
35af68b5 SS |
398 | } |
399 | /* Latch in address */ | |
7abd3ef9 | 400 | au1550_hwcontrol(mtd, NAND_CTL_CLRALE); |
35af68b5 SS |
401 | } |
402 | ||
403 | /* | |
404 | * Program and erase have their own busy handlers. | |
405 | * Status and sequential in need no delay. | |
406 | */ | |
407 | switch (command) { | |
408 | ||
409 | case NAND_CMD_PAGEPROG: | |
410 | case NAND_CMD_ERASE1: | |
411 | case NAND_CMD_ERASE2: | |
412 | case NAND_CMD_SEQIN: | |
413 | case NAND_CMD_STATUS: | |
414 | return; | |
415 | ||
416 | case NAND_CMD_RESET: | |
417 | break; | |
418 | ||
419 | case NAND_CMD_READ0: | |
420 | case NAND_CMD_READ1: | |
421 | case NAND_CMD_READOOB: | |
422 | /* Check if we're really driving -CE low (just in case) */ | |
423 | if (unlikely(!ce_override)) | |
424 | break; | |
425 | ||
426 | /* Apply a short delay always to ensure that we do wait tWB. */ | |
427 | ndelay(100); | |
428 | /* Wait for a chip to become ready... */ | |
429 | for (i = this->chip_delay; !this->dev_ready(mtd) && i > 0; --i) | |
430 | udelay(1); | |
431 | ||
432 | /* Release -CE and re-enable interrupts. */ | |
7abd3ef9 | 433 | au1550_hwcontrol(mtd, NAND_CTL_CLRNCE); |
35af68b5 SS |
434 | local_irq_restore(flags); |
435 | return; | |
436 | } | |
437 | /* Apply this short delay always to ensure that we do wait tWB. */ | |
438 | ndelay(100); | |
439 | ||
440 | while(!this->dev_ready(mtd)); | |
441 | } | |
442 | ||
443 | ||
1da177e4 LT |
444 | /* |
445 | * Main initialization routine | |
446 | */ | |
cead4dbc | 447 | static int __init au1xxx_nand_init(void) |
1da177e4 LT |
448 | { |
449 | struct nand_chip *this; | |
e0c7d767 | 450 | u16 boot_swapboot = 0; /* default value */ |
1da177e4 | 451 | int retval; |
ef6f0d1f PP |
452 | u32 mem_staddr; |
453 | u32 nand_phys; | |
1da177e4 LT |
454 | |
455 | /* Allocate memory for MTD device structure and private data */ | |
34970a7d | 456 | au1550_mtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL); |
1da177e4 | 457 | if (!au1550_mtd) { |
e0c7d767 | 458 | printk("Unable to allocate NAND MTD dev structure.\n"); |
1da177e4 LT |
459 | return -ENOMEM; |
460 | } | |
461 | ||
462 | /* Get pointer to private data */ | |
e0c7d767 | 463 | this = (struct nand_chip *)(&au1550_mtd[1]); |
1da177e4 | 464 | |
1da177e4 LT |
465 | /* Link the private data with the MTD structure */ |
466 | au1550_mtd->priv = this; | |
552d9205 | 467 | au1550_mtd->owner = THIS_MODULE; |
1da177e4 | 468 | |
61b03bd7 | 469 | |
155285c4 SS |
470 | /* MEM_STNDCTL: disable ints, disable nand boot */ |
471 | au_writel(0, MEM_STNDCTL); | |
1da177e4 LT |
472 | |
473 | #ifdef CONFIG_MIPS_PB1550 | |
474 | /* set gpio206 high */ | |
b7f720d6 | 475 | gpio_direction_input(206); |
1da177e4 | 476 | |
9bdcf336 ML |
477 | boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) | ((bcsr_read(BCSR_STATUS) >> 6) & 0x1); |
478 | ||
1da177e4 | 479 | switch (boot_swapboot) { |
e0c7d767 DW |
480 | case 0: |
481 | case 2: | |
482 | case 8: | |
483 | case 0xC: | |
484 | case 0xD: | |
485 | /* x16 NAND Flash */ | |
486 | nand_width = 0; | |
487 | break; | |
488 | case 1: | |
489 | case 9: | |
490 | case 3: | |
491 | case 0xE: | |
492 | case 0xF: | |
493 | /* x8 NAND Flash */ | |
494 | nand_width = 1; | |
495 | break; | |
496 | default: | |
497 | printk("Pb1550 NAND: bad boot:swap\n"); | |
498 | retval = -EINVAL; | |
499 | goto outmem; | |
1da177e4 LT |
500 | } |
501 | #endif | |
502 | ||
ef6f0d1f PP |
503 | /* Configure chip-select; normally done by boot code, e.g. YAMON */ |
504 | #ifdef NAND_STCFG | |
505 | if (NAND_CS == 0) { | |
506 | au_writel(NAND_STCFG, MEM_STCFG0); | |
507 | au_writel(NAND_STTIME, MEM_STTIME0); | |
508 | au_writel(NAND_STADDR, MEM_STADDR0); | |
509 | } | |
510 | if (NAND_CS == 1) { | |
511 | au_writel(NAND_STCFG, MEM_STCFG1); | |
512 | au_writel(NAND_STTIME, MEM_STTIME1); | |
513 | au_writel(NAND_STADDR, MEM_STADDR1); | |
514 | } | |
515 | if (NAND_CS == 2) { | |
516 | au_writel(NAND_STCFG, MEM_STCFG2); | |
517 | au_writel(NAND_STTIME, MEM_STTIME2); | |
518 | au_writel(NAND_STADDR, MEM_STADDR2); | |
519 | } | |
520 | if (NAND_CS == 3) { | |
521 | au_writel(NAND_STCFG, MEM_STCFG3); | |
522 | au_writel(NAND_STTIME, MEM_STTIME3); | |
523 | au_writel(NAND_STADDR, MEM_STADDR3); | |
524 | } | |
525 | #endif | |
61b03bd7 | 526 | |
ef6f0d1f PP |
527 | /* Locate NAND chip-select in order to determine NAND phys address */ |
528 | mem_staddr = 0x00000000; | |
529 | if (((au_readl(MEM_STCFG0) & 0x7) == 0x5) && (NAND_CS == 0)) | |
530 | mem_staddr = au_readl(MEM_STADDR0); | |
531 | else if (((au_readl(MEM_STCFG1) & 0x7) == 0x5) && (NAND_CS == 1)) | |
532 | mem_staddr = au_readl(MEM_STADDR1); | |
533 | else if (((au_readl(MEM_STCFG2) & 0x7) == 0x5) && (NAND_CS == 2)) | |
534 | mem_staddr = au_readl(MEM_STADDR2); | |
535 | else if (((au_readl(MEM_STCFG3) & 0x7) == 0x5) && (NAND_CS == 3)) | |
536 | mem_staddr = au_readl(MEM_STADDR3); | |
537 | ||
538 | if (mem_staddr == 0x00000000) { | |
539 | printk("Au1xxx NAND: ERROR WITH NAND CHIP-SELECT\n"); | |
540 | kfree(au1550_mtd); | |
541 | return 1; | |
542 | } | |
543 | nand_phys = (mem_staddr << 4) & 0xFFFC0000; | |
1da177e4 | 544 | |
440d4f9f | 545 | p_nand = ioremap(nand_phys, 0x1000); |
ef6f0d1f PP |
546 | |
547 | /* make controller and MTD agree */ | |
548 | if (NAND_CS == 0) | |
e0c7d767 | 549 | nand_width = au_readl(MEM_STCFG0) & (1 << 22); |
ef6f0d1f | 550 | if (NAND_CS == 1) |
e0c7d767 | 551 | nand_width = au_readl(MEM_STCFG1) & (1 << 22); |
ef6f0d1f | 552 | if (NAND_CS == 2) |
e0c7d767 | 553 | nand_width = au_readl(MEM_STCFG2) & (1 << 22); |
ef6f0d1f | 554 | if (NAND_CS == 3) |
e0c7d767 | 555 | nand_width = au_readl(MEM_STCFG3) & (1 << 22); |
1da177e4 LT |
556 | |
557 | /* Set address of hardware control function */ | |
1da177e4 | 558 | this->dev_ready = au1550_device_ready; |
35af68b5 SS |
559 | this->select_chip = au1550_select_chip; |
560 | this->cmdfunc = au1550_command; | |
561 | ||
1da177e4 | 562 | /* 30 us command delay time */ |
61b03bd7 | 563 | this->chip_delay = 30; |
6dfc6d25 | 564 | this->ecc.mode = NAND_ECC_SOFT; |
1da177e4 LT |
565 | |
566 | this->options = NAND_NO_AUTOINCR; | |
567 | ||
568 | if (!nand_width) | |
569 | this->options |= NAND_BUSWIDTH_16; | |
570 | ||
571 | this->read_byte = (!nand_width) ? au_read_byte16 : au_read_byte; | |
cad74f2c | 572 | au1550_write_byte = (!nand_width) ? au_write_byte16 : au_write_byte; |
1da177e4 LT |
573 | this->read_word = au_read_word; |
574 | this->write_buf = (!nand_width) ? au_write_buf16 : au_write_buf; | |
575 | this->read_buf = (!nand_width) ? au_read_buf16 : au_read_buf; | |
576 | this->verify_buf = (!nand_width) ? au_verify_buf16 : au_verify_buf; | |
577 | ||
578 | /* Scan to find existence of the device */ | |
e0c7d767 | 579 | if (nand_scan(au1550_mtd, 1)) { |
1da177e4 LT |
580 | retval = -ENXIO; |
581 | goto outio; | |
582 | } | |
583 | ||
584 | /* Register the partitions */ | |
ee0e87b1 JI |
585 | mtd_device_register(au1550_mtd, partition_info, |
586 | ARRAY_SIZE(partition_info)); | |
1da177e4 LT |
587 | |
588 | return 0; | |
589 | ||
590 | outio: | |
440d4f9f | 591 | iounmap(p_nand); |
61b03bd7 | 592 | |
1da177e4 | 593 | outmem: |
e0c7d767 | 594 | kfree(au1550_mtd); |
1da177e4 LT |
595 | return retval; |
596 | } | |
597 | ||
ef6f0d1f | 598 | module_init(au1xxx_nand_init); |
1da177e4 LT |
599 | |
600 | /* | |
601 | * Clean up routine | |
602 | */ | |
e0c7d767 | 603 | static void __exit au1550_cleanup(void) |
1da177e4 | 604 | { |
1da177e4 | 605 | /* Release resources, unregister device */ |
e0c7d767 | 606 | nand_release(au1550_mtd); |
1da177e4 LT |
607 | |
608 | /* Free the MTD device structure */ | |
e0c7d767 | 609 | kfree(au1550_mtd); |
1da177e4 LT |
610 | |
611 | /* Unmap */ | |
440d4f9f | 612 | iounmap(p_nand); |
1da177e4 | 613 | } |
e0c7d767 | 614 | |
1da177e4 | 615 | module_exit(au1550_cleanup); |
1da177e4 LT |
616 | |
617 | MODULE_LICENSE("GPL"); | |
618 | MODULE_AUTHOR("Embedded Edge, LLC"); | |
619 | MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board"); |