Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * drivers/mtd/nand/au1550nd.c | |
3 | * | |
4 | * Copyright (C) 2004 Embedded Edge, LLC | |
5 | * | |
1da177e4 LT |
6 | * This program is free software; you can redistribute it and/or modify |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | */ | |
11 | ||
12 | #include <linux/slab.h> | |
b7f720d6 | 13 | #include <linux/gpio.h> |
1da177e4 | 14 | #include <linux/module.h> |
35af68b5 | 15 | #include <linux/interrupt.h> |
1da177e4 LT |
16 | #include <linux/mtd/mtd.h> |
17 | #include <linux/mtd/nand.h> | |
18 | #include <linux/mtd/partitions.h> | |
b67a1a02 | 19 | #include <linux/platform_device.h> |
1da177e4 | 20 | #include <asm/io.h> |
b67a1a02 ML |
21 | #include <asm/mach-au1x00/au1000.h> |
22 | #include <asm/mach-au1x00/au1550nd.h> | |
1da177e4 | 23 | |
1da177e4 | 24 | |
b67a1a02 ML |
25 | struct au1550nd_ctx { |
26 | struct mtd_info info; | |
27 | struct nand_chip chip; | |
1da177e4 | 28 | |
b67a1a02 ML |
29 | int cs; |
30 | void __iomem *base; | |
31 | void (*write_byte)(struct mtd_info *, u_char); | |
1da177e4 | 32 | }; |
1da177e4 LT |
33 | |
34 | /** | |
35 | * au_read_byte - read one byte from the chip | |
36 | * @mtd: MTD device structure | |
37 | * | |
7854d3f7 | 38 | * read function for 8bit buswidth |
1da177e4 LT |
39 | */ |
40 | static u_char au_read_byte(struct mtd_info *mtd) | |
41 | { | |
42 | struct nand_chip *this = mtd->priv; | |
43 | u_char ret = readb(this->IO_ADDR_R); | |
44 | au_sync(); | |
45 | return ret; | |
46 | } | |
47 | ||
48 | /** | |
49 | * au_write_byte - write one byte to the chip | |
50 | * @mtd: MTD device structure | |
51 | * @byte: pointer to data byte to write | |
52 | * | |
7854d3f7 | 53 | * write function for 8it buswidth |
1da177e4 LT |
54 | */ |
55 | static void au_write_byte(struct mtd_info *mtd, u_char byte) | |
56 | { | |
57 | struct nand_chip *this = mtd->priv; | |
58 | writeb(byte, this->IO_ADDR_W); | |
59 | au_sync(); | |
60 | } | |
61 | ||
62 | /** | |
7854d3f7 | 63 | * au_read_byte16 - read one byte endianness aware from the chip |
1da177e4 LT |
64 | * @mtd: MTD device structure |
65 | * | |
7854d3f7 | 66 | * read function for 16bit buswidth with endianness conversion |
1da177e4 LT |
67 | */ |
68 | static u_char au_read_byte16(struct mtd_info *mtd) | |
69 | { | |
70 | struct nand_chip *this = mtd->priv; | |
71 | u_char ret = (u_char) cpu_to_le16(readw(this->IO_ADDR_R)); | |
72 | au_sync(); | |
73 | return ret; | |
74 | } | |
75 | ||
76 | /** | |
7854d3f7 | 77 | * au_write_byte16 - write one byte endianness aware to the chip |
1da177e4 LT |
78 | * @mtd: MTD device structure |
79 | * @byte: pointer to data byte to write | |
80 | * | |
7854d3f7 | 81 | * write function for 16bit buswidth with endianness conversion |
1da177e4 LT |
82 | */ |
83 | static void au_write_byte16(struct mtd_info *mtd, u_char byte) | |
84 | { | |
85 | struct nand_chip *this = mtd->priv; | |
86 | writew(le16_to_cpu((u16) byte), this->IO_ADDR_W); | |
87 | au_sync(); | |
88 | } | |
89 | ||
90 | /** | |
91 | * au_read_word - read one word from the chip | |
92 | * @mtd: MTD device structure | |
93 | * | |
7854d3f7 | 94 | * read function for 16bit buswidth without endianness conversion |
1da177e4 LT |
95 | */ |
96 | static u16 au_read_word(struct mtd_info *mtd) | |
97 | { | |
98 | struct nand_chip *this = mtd->priv; | |
99 | u16 ret = readw(this->IO_ADDR_R); | |
100 | au_sync(); | |
101 | return ret; | |
102 | } | |
103 | ||
1da177e4 LT |
104 | /** |
105 | * au_write_buf - write buffer to chip | |
106 | * @mtd: MTD device structure | |
107 | * @buf: data buffer | |
108 | * @len: number of bytes to write | |
109 | * | |
7854d3f7 | 110 | * write function for 8bit buswidth |
1da177e4 LT |
111 | */ |
112 | static void au_write_buf(struct mtd_info *mtd, const u_char *buf, int len) | |
113 | { | |
114 | int i; | |
115 | struct nand_chip *this = mtd->priv; | |
116 | ||
e0c7d767 | 117 | for (i = 0; i < len; i++) { |
1da177e4 LT |
118 | writeb(buf[i], this->IO_ADDR_W); |
119 | au_sync(); | |
120 | } | |
121 | } | |
122 | ||
123 | /** | |
61b03bd7 | 124 | * au_read_buf - read chip data into buffer |
1da177e4 LT |
125 | * @mtd: MTD device structure |
126 | * @buf: buffer to store date | |
127 | * @len: number of bytes to read | |
128 | * | |
7854d3f7 | 129 | * read function for 8bit buswidth |
1da177e4 LT |
130 | */ |
131 | static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len) | |
132 | { | |
133 | int i; | |
134 | struct nand_chip *this = mtd->priv; | |
135 | ||
e0c7d767 | 136 | for (i = 0; i < len; i++) { |
1da177e4 | 137 | buf[i] = readb(this->IO_ADDR_R); |
61b03bd7 | 138 | au_sync(); |
1da177e4 LT |
139 | } |
140 | } | |
141 | ||
1da177e4 LT |
142 | /** |
143 | * au_write_buf16 - write buffer to chip | |
144 | * @mtd: MTD device structure | |
145 | * @buf: data buffer | |
146 | * @len: number of bytes to write | |
147 | * | |
7854d3f7 | 148 | * write function for 16bit buswidth |
1da177e4 LT |
149 | */ |
150 | static void au_write_buf16(struct mtd_info *mtd, const u_char *buf, int len) | |
151 | { | |
152 | int i; | |
153 | struct nand_chip *this = mtd->priv; | |
154 | u16 *p = (u16 *) buf; | |
155 | len >>= 1; | |
61b03bd7 | 156 | |
e0c7d767 | 157 | for (i = 0; i < len; i++) { |
1da177e4 LT |
158 | writew(p[i], this->IO_ADDR_W); |
159 | au_sync(); | |
160 | } | |
61b03bd7 | 161 | |
1da177e4 LT |
162 | } |
163 | ||
164 | /** | |
61b03bd7 | 165 | * au_read_buf16 - read chip data into buffer |
1da177e4 LT |
166 | * @mtd: MTD device structure |
167 | * @buf: buffer to store date | |
168 | * @len: number of bytes to read | |
169 | * | |
7854d3f7 | 170 | * read function for 16bit buswidth |
1da177e4 LT |
171 | */ |
172 | static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len) | |
173 | { | |
174 | int i; | |
175 | struct nand_chip *this = mtd->priv; | |
176 | u16 *p = (u16 *) buf; | |
177 | len >>= 1; | |
178 | ||
e0c7d767 | 179 | for (i = 0; i < len; i++) { |
1da177e4 LT |
180 | p[i] = readw(this->IO_ADDR_R); |
181 | au_sync(); | |
182 | } | |
183 | } | |
184 | ||
7abd3ef9 TG |
185 | /* Select the chip by setting nCE to low */ |
186 | #define NAND_CTL_SETNCE 1 | |
187 | /* Deselect the chip by setting nCE to high */ | |
188 | #define NAND_CTL_CLRNCE 2 | |
189 | /* Select the command latch by setting CLE to high */ | |
190 | #define NAND_CTL_SETCLE 3 | |
191 | /* Deselect the command latch by setting CLE to low */ | |
192 | #define NAND_CTL_CLRCLE 4 | |
193 | /* Select the address latch by setting ALE to high */ | |
194 | #define NAND_CTL_SETALE 5 | |
195 | /* Deselect the address latch by setting ALE to low */ | |
196 | #define NAND_CTL_CLRALE 6 | |
1da177e4 LT |
197 | |
198 | static void au1550_hwcontrol(struct mtd_info *mtd, int cmd) | |
199 | { | |
b67a1a02 ML |
200 | struct au1550nd_ctx *ctx = container_of(mtd, struct au1550nd_ctx, info); |
201 | struct nand_chip *this = mtd->priv; | |
1da177e4 | 202 | |
e0c7d767 DW |
203 | switch (cmd) { |
204 | ||
205 | case NAND_CTL_SETCLE: | |
b67a1a02 | 206 | this->IO_ADDR_W = ctx->base + MEM_STNAND_CMD; |
e0c7d767 DW |
207 | break; |
208 | ||
209 | case NAND_CTL_CLRCLE: | |
b67a1a02 | 210 | this->IO_ADDR_W = ctx->base + MEM_STNAND_DATA; |
e0c7d767 | 211 | break; |
1da177e4 | 212 | |
e0c7d767 | 213 | case NAND_CTL_SETALE: |
b67a1a02 | 214 | this->IO_ADDR_W = ctx->base + MEM_STNAND_ADDR; |
e0c7d767 | 215 | break; |
1da177e4 | 216 | |
61b03bd7 | 217 | case NAND_CTL_CLRALE: |
b67a1a02 | 218 | this->IO_ADDR_W = ctx->base + MEM_STNAND_DATA; |
e0c7d767 | 219 | /* FIXME: Nobody knows why this is necessary, |
1da177e4 | 220 | * but it works only that way */ |
61b03bd7 | 221 | udelay(1); |
1da177e4 LT |
222 | break; |
223 | ||
61b03bd7 | 224 | case NAND_CTL_SETNCE: |
1da177e4 | 225 | /* assert (force assert) chip enable */ |
b67a1a02 | 226 | au_writel((1 << (4 + ctx->cs)), MEM_STNDCTL); |
1da177e4 LT |
227 | break; |
228 | ||
61b03bd7 | 229 | case NAND_CTL_CLRNCE: |
e0c7d767 DW |
230 | /* deassert chip enable */ |
231 | au_writel(0, MEM_STNDCTL); | |
1da177e4 LT |
232 | break; |
233 | } | |
234 | ||
235 | this->IO_ADDR_R = this->IO_ADDR_W; | |
61b03bd7 | 236 | |
1da177e4 LT |
237 | /* Drain the writebuffer */ |
238 | au_sync(); | |
239 | } | |
240 | ||
241 | int au1550_device_ready(struct mtd_info *mtd) | |
242 | { | |
243 | int ret = (au_readl(MEM_STSTAT) & 0x1) ? 1 : 0; | |
244 | au_sync(); | |
245 | return ret; | |
246 | } | |
247 | ||
35af68b5 SS |
248 | /** |
249 | * au1550_select_chip - control -CE line | |
250 | * Forbid driving -CE manually permitting the NAND controller to do this. | |
251 | * Keeping -CE asserted during the whole sector reads interferes with the | |
252 | * NOR flash and PCMCIA drivers as it causes contention on the static bus. | |
253 | * We only have to hold -CE low for the NAND read commands since the flash | |
254 | * chip needs it to be asserted during chip not ready time but the NAND | |
255 | * controller keeps it released. | |
256 | * | |
257 | * @mtd: MTD device structure | |
258 | * @chip: chipnumber to select, -1 for deselect | |
259 | */ | |
260 | static void au1550_select_chip(struct mtd_info *mtd, int chip) | |
261 | { | |
262 | } | |
263 | ||
264 | /** | |
265 | * au1550_command - Send command to NAND device | |
266 | * @mtd: MTD device structure | |
267 | * @command: the command to be sent | |
268 | * @column: the column address for this command, -1 if none | |
269 | * @page_addr: the page address for this command, -1 if none | |
270 | */ | |
271 | static void au1550_command(struct mtd_info *mtd, unsigned command, int column, int page_addr) | |
272 | { | |
b67a1a02 ML |
273 | struct au1550nd_ctx *ctx = container_of(mtd, struct au1550nd_ctx, info); |
274 | struct nand_chip *this = mtd->priv; | |
35af68b5 | 275 | int ce_override = 0, i; |
b67a1a02 | 276 | unsigned long flags = 0; |
35af68b5 SS |
277 | |
278 | /* Begin command latch cycle */ | |
7abd3ef9 | 279 | au1550_hwcontrol(mtd, NAND_CTL_SETCLE); |
35af68b5 SS |
280 | /* |
281 | * Write out the command to the device. | |
282 | */ | |
283 | if (command == NAND_CMD_SEQIN) { | |
284 | int readcmd; | |
285 | ||
28318776 | 286 | if (column >= mtd->writesize) { |
35af68b5 | 287 | /* OOB area */ |
28318776 | 288 | column -= mtd->writesize; |
35af68b5 SS |
289 | readcmd = NAND_CMD_READOOB; |
290 | } else if (column < 256) { | |
291 | /* First 256 bytes --> READ0 */ | |
292 | readcmd = NAND_CMD_READ0; | |
293 | } else { | |
294 | column -= 256; | |
295 | readcmd = NAND_CMD_READ1; | |
296 | } | |
b67a1a02 | 297 | ctx->write_byte(mtd, readcmd); |
35af68b5 | 298 | } |
b67a1a02 | 299 | ctx->write_byte(mtd, command); |
35af68b5 SS |
300 | |
301 | /* Set ALE and clear CLE to start address cycle */ | |
7abd3ef9 | 302 | au1550_hwcontrol(mtd, NAND_CTL_CLRCLE); |
35af68b5 SS |
303 | |
304 | if (column != -1 || page_addr != -1) { | |
7abd3ef9 | 305 | au1550_hwcontrol(mtd, NAND_CTL_SETALE); |
35af68b5 SS |
306 | |
307 | /* Serially input address */ | |
308 | if (column != -1) { | |
309 | /* Adjust columns for 16 bit buswidth */ | |
310 | if (this->options & NAND_BUSWIDTH_16) | |
311 | column >>= 1; | |
b67a1a02 | 312 | ctx->write_byte(mtd, column); |
35af68b5 SS |
313 | } |
314 | if (page_addr != -1) { | |
b67a1a02 | 315 | ctx->write_byte(mtd, (u8)(page_addr & 0xff)); |
35af68b5 SS |
316 | |
317 | if (command == NAND_CMD_READ0 || | |
318 | command == NAND_CMD_READ1 || | |
319 | command == NAND_CMD_READOOB) { | |
320 | /* | |
321 | * NAND controller will release -CE after | |
322 | * the last address byte is written, so we'll | |
323 | * have to forcibly assert it. No interrupts | |
324 | * are allowed while we do this as we don't | |
325 | * want the NOR flash or PCMCIA drivers to | |
326 | * steal our precious bytes of data... | |
327 | */ | |
328 | ce_override = 1; | |
329 | local_irq_save(flags); | |
7abd3ef9 | 330 | au1550_hwcontrol(mtd, NAND_CTL_SETNCE); |
35af68b5 SS |
331 | } |
332 | ||
b67a1a02 | 333 | ctx->write_byte(mtd, (u8)(page_addr >> 8)); |
35af68b5 SS |
334 | |
335 | /* One more address cycle for devices > 32MiB */ | |
336 | if (this->chipsize > (32 << 20)) | |
b67a1a02 ML |
337 | ctx->write_byte(mtd, |
338 | ((page_addr >> 16) & 0x0f)); | |
35af68b5 SS |
339 | } |
340 | /* Latch in address */ | |
7abd3ef9 | 341 | au1550_hwcontrol(mtd, NAND_CTL_CLRALE); |
35af68b5 SS |
342 | } |
343 | ||
344 | /* | |
345 | * Program and erase have their own busy handlers. | |
346 | * Status and sequential in need no delay. | |
347 | */ | |
348 | switch (command) { | |
349 | ||
350 | case NAND_CMD_PAGEPROG: | |
351 | case NAND_CMD_ERASE1: | |
352 | case NAND_CMD_ERASE2: | |
353 | case NAND_CMD_SEQIN: | |
354 | case NAND_CMD_STATUS: | |
355 | return; | |
356 | ||
357 | case NAND_CMD_RESET: | |
358 | break; | |
359 | ||
360 | case NAND_CMD_READ0: | |
361 | case NAND_CMD_READ1: | |
362 | case NAND_CMD_READOOB: | |
363 | /* Check if we're really driving -CE low (just in case) */ | |
364 | if (unlikely(!ce_override)) | |
365 | break; | |
366 | ||
367 | /* Apply a short delay always to ensure that we do wait tWB. */ | |
368 | ndelay(100); | |
369 | /* Wait for a chip to become ready... */ | |
370 | for (i = this->chip_delay; !this->dev_ready(mtd) && i > 0; --i) | |
371 | udelay(1); | |
372 | ||
373 | /* Release -CE and re-enable interrupts. */ | |
7abd3ef9 | 374 | au1550_hwcontrol(mtd, NAND_CTL_CLRNCE); |
35af68b5 SS |
375 | local_irq_restore(flags); |
376 | return; | |
377 | } | |
378 | /* Apply this short delay always to ensure that we do wait tWB. */ | |
379 | ndelay(100); | |
380 | ||
381 | while(!this->dev_ready(mtd)); | |
382 | } | |
383 | ||
06f25510 | 384 | static int find_nand_cs(unsigned long nand_base) |
1da177e4 | 385 | { |
b67a1a02 ML |
386 | void __iomem *base = |
387 | (void __iomem *)KSEG1ADDR(AU1000_STATIC_MEM_PHYS_ADDR); | |
388 | unsigned long addr, staddr, start, mask, end; | |
389 | int i; | |
61b03bd7 | 390 | |
b67a1a02 ML |
391 | for (i = 0; i < 4; i++) { |
392 | addr = 0x1000 + (i * 0x10); /* CSx */ | |
393 | staddr = __raw_readl(base + addr + 0x08); /* STADDRx */ | |
394 | /* figure out the decoded range of this CS */ | |
395 | start = (staddr << 4) & 0xfffc0000; | |
396 | mask = (staddr << 18) & 0xfffc0000; | |
397 | end = (start | (start - 1)) & ~(start ^ mask); | |
398 | if ((nand_base >= start) && (nand_base < end)) | |
399 | return i; | |
400 | } | |
1da177e4 | 401 | |
b67a1a02 ML |
402 | return -ENODEV; |
403 | } | |
1da177e4 | 404 | |
06f25510 | 405 | static int au1550nd_probe(struct platform_device *pdev) |
b67a1a02 ML |
406 | { |
407 | struct au1550nd_platdata *pd; | |
408 | struct au1550nd_ctx *ctx; | |
409 | struct nand_chip *this; | |
410 | struct resource *r; | |
411 | int ret, cs; | |
9bdcf336 | 412 | |
453810b7 | 413 | pd = dev_get_platdata(&pdev->dev); |
b67a1a02 ML |
414 | if (!pd) { |
415 | dev_err(&pdev->dev, "missing platform data\n"); | |
416 | return -ENODEV; | |
1da177e4 | 417 | } |
b67a1a02 ML |
418 | |
419 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); | |
ce3737f0 | 420 | if (!ctx) |
b67a1a02 | 421 | return -ENOMEM; |
b67a1a02 ML |
422 | |
423 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
424 | if (!r) { | |
425 | dev_err(&pdev->dev, "no NAND memory resource\n"); | |
426 | ret = -ENODEV; | |
427 | goto out1; | |
ef6f0d1f | 428 | } |
b67a1a02 ML |
429 | if (request_mem_region(r->start, resource_size(r), "au1550-nand")) { |
430 | dev_err(&pdev->dev, "cannot claim NAND memory area\n"); | |
431 | ret = -ENOMEM; | |
432 | goto out1; | |
ef6f0d1f | 433 | } |
b67a1a02 ML |
434 | |
435 | ctx->base = ioremap_nocache(r->start, 0x1000); | |
436 | if (!ctx->base) { | |
437 | dev_err(&pdev->dev, "cannot remap NAND memory area\n"); | |
438 | ret = -ENODEV; | |
439 | goto out2; | |
ef6f0d1f | 440 | } |
1da177e4 | 441 | |
b67a1a02 ML |
442 | this = &ctx->chip; |
443 | ctx->info.priv = this; | |
444 | ctx->info.owner = THIS_MODULE; | |
ef6f0d1f | 445 | |
b67a1a02 ML |
446 | /* figure out which CS# r->start belongs to */ |
447 | cs = find_nand_cs(r->start); | |
448 | if (cs < 0) { | |
449 | dev_err(&pdev->dev, "cannot detect NAND chipselect\n"); | |
450 | ret = -ENODEV; | |
451 | goto out3; | |
452 | } | |
453 | ctx->cs = cs; | |
1da177e4 | 454 | |
1da177e4 | 455 | this->dev_ready = au1550_device_ready; |
35af68b5 SS |
456 | this->select_chip = au1550_select_chip; |
457 | this->cmdfunc = au1550_command; | |
458 | ||
1da177e4 | 459 | /* 30 us command delay time */ |
61b03bd7 | 460 | this->chip_delay = 30; |
6dfc6d25 | 461 | this->ecc.mode = NAND_ECC_SOFT; |
1da177e4 | 462 | |
b67a1a02 | 463 | if (pd->devwidth) |
1da177e4 LT |
464 | this->options |= NAND_BUSWIDTH_16; |
465 | ||
b67a1a02 ML |
466 | this->read_byte = (pd->devwidth) ? au_read_byte16 : au_read_byte; |
467 | ctx->write_byte = (pd->devwidth) ? au_write_byte16 : au_write_byte; | |
1da177e4 | 468 | this->read_word = au_read_word; |
b67a1a02 ML |
469 | this->write_buf = (pd->devwidth) ? au_write_buf16 : au_write_buf; |
470 | this->read_buf = (pd->devwidth) ? au_read_buf16 : au_read_buf; | |
b67a1a02 ML |
471 | |
472 | ret = nand_scan(&ctx->info, 1); | |
473 | if (ret) { | |
474 | dev_err(&pdev->dev, "NAND scan failed with %d\n", ret); | |
475 | goto out3; | |
1da177e4 LT |
476 | } |
477 | ||
b67a1a02 | 478 | mtd_device_register(&ctx->info, pd->parts, pd->num_parts); |
1da177e4 | 479 | |
a1d7994e WY |
480 | platform_set_drvdata(pdev, ctx); |
481 | ||
1da177e4 LT |
482 | return 0; |
483 | ||
b67a1a02 ML |
484 | out3: |
485 | iounmap(ctx->base); | |
486 | out2: | |
487 | release_mem_region(r->start, resource_size(r)); | |
488 | out1: | |
489 | kfree(ctx); | |
490 | return ret; | |
1da177e4 LT |
491 | } |
492 | ||
810b7e06 | 493 | static int au1550nd_remove(struct platform_device *pdev) |
1da177e4 | 494 | { |
b67a1a02 ML |
495 | struct au1550nd_ctx *ctx = platform_get_drvdata(pdev); |
496 | struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1da177e4 | 497 | |
b67a1a02 ML |
498 | nand_release(&ctx->info); |
499 | iounmap(ctx->base); | |
500 | release_mem_region(r->start, 0x1000); | |
501 | kfree(ctx); | |
502 | return 0; | |
1da177e4 | 503 | } |
e0c7d767 | 504 | |
b67a1a02 ML |
505 | static struct platform_driver au1550nd_driver = { |
506 | .driver = { | |
507 | .name = "au1550-nand", | |
508 | .owner = THIS_MODULE, | |
509 | }, | |
510 | .probe = au1550nd_probe, | |
5153b88c | 511 | .remove = au1550nd_remove, |
b67a1a02 ML |
512 | }; |
513 | ||
514 | module_platform_driver(au1550nd_driver); | |
1da177e4 LT |
515 | |
516 | MODULE_LICENSE("GPL"); | |
517 | MODULE_AUTHOR("Embedded Edge, LLC"); | |
518 | MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board"); |