Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * drivers/mtd/nand/au1550nd.c | |
3 | * | |
4 | * Copyright (C) 2004 Embedded Edge, LLC | |
5 | * | |
1da177e4 LT |
6 | * This program is free software; you can redistribute it and/or modify |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | */ | |
11 | ||
12 | #include <linux/slab.h> | |
b7f720d6 | 13 | #include <linux/gpio.h> |
1da177e4 LT |
14 | #include <linux/init.h> |
15 | #include <linux/module.h> | |
35af68b5 | 16 | #include <linux/interrupt.h> |
1da177e4 LT |
17 | #include <linux/mtd/mtd.h> |
18 | #include <linux/mtd/nand.h> | |
19 | #include <linux/mtd/partitions.h> | |
20 | #include <asm/io.h> | |
21 | ||
ef6f0d1f | 22 | #include <asm/mach-au1x00/au1xxx.h> |
9bdcf336 | 23 | #include <asm/mach-db1x00/bcsr.h> |
1da177e4 LT |
24 | |
25 | /* | |
26 | * MTD structure for NAND controller | |
27 | */ | |
28 | static struct mtd_info *au1550_mtd = NULL; | |
29 | static void __iomem *p_nand; | |
e0c7d767 | 30 | static int nand_width = 1; /* default x8 */ |
cad74f2c | 31 | static void (*au1550_write_byte)(struct mtd_info *, u_char); |
1da177e4 | 32 | |
1da177e4 LT |
33 | /* |
34 | * Define partitions for flash device | |
35 | */ | |
3c6bee1d | 36 | static const struct mtd_partition partition_info[] = { |
61b03bd7 | 37 | { |
e0c7d767 DW |
38 | .name = "NAND FS 0", |
39 | .offset = 0, | |
40 | .size = 8 * 1024 * 1024}, | |
61b03bd7 | 41 | { |
e0c7d767 DW |
42 | .name = "NAND FS 1", |
43 | .offset = MTDPART_OFS_APPEND, | |
44 | .size = MTDPART_SIZ_FULL} | |
1da177e4 | 45 | }; |
1da177e4 LT |
46 | |
47 | /** | |
48 | * au_read_byte - read one byte from the chip | |
49 | * @mtd: MTD device structure | |
50 | * | |
7854d3f7 | 51 | * read function for 8bit buswidth |
1da177e4 LT |
52 | */ |
53 | static u_char au_read_byte(struct mtd_info *mtd) | |
54 | { | |
55 | struct nand_chip *this = mtd->priv; | |
56 | u_char ret = readb(this->IO_ADDR_R); | |
57 | au_sync(); | |
58 | return ret; | |
59 | } | |
60 | ||
61 | /** | |
62 | * au_write_byte - write one byte to the chip | |
63 | * @mtd: MTD device structure | |
64 | * @byte: pointer to data byte to write | |
65 | * | |
7854d3f7 | 66 | * write function for 8it buswidth |
1da177e4 LT |
67 | */ |
68 | static void au_write_byte(struct mtd_info *mtd, u_char byte) | |
69 | { | |
70 | struct nand_chip *this = mtd->priv; | |
71 | writeb(byte, this->IO_ADDR_W); | |
72 | au_sync(); | |
73 | } | |
74 | ||
75 | /** | |
7854d3f7 | 76 | * au_read_byte16 - read one byte endianness aware from the chip |
1da177e4 LT |
77 | * @mtd: MTD device structure |
78 | * | |
7854d3f7 | 79 | * read function for 16bit buswidth with endianness conversion |
1da177e4 LT |
80 | */ |
81 | static u_char au_read_byte16(struct mtd_info *mtd) | |
82 | { | |
83 | struct nand_chip *this = mtd->priv; | |
84 | u_char ret = (u_char) cpu_to_le16(readw(this->IO_ADDR_R)); | |
85 | au_sync(); | |
86 | return ret; | |
87 | } | |
88 | ||
89 | /** | |
7854d3f7 | 90 | * au_write_byte16 - write one byte endianness aware to the chip |
1da177e4 LT |
91 | * @mtd: MTD device structure |
92 | * @byte: pointer to data byte to write | |
93 | * | |
7854d3f7 | 94 | * write function for 16bit buswidth with endianness conversion |
1da177e4 LT |
95 | */ |
96 | static void au_write_byte16(struct mtd_info *mtd, u_char byte) | |
97 | { | |
98 | struct nand_chip *this = mtd->priv; | |
99 | writew(le16_to_cpu((u16) byte), this->IO_ADDR_W); | |
100 | au_sync(); | |
101 | } | |
102 | ||
103 | /** | |
104 | * au_read_word - read one word from the chip | |
105 | * @mtd: MTD device structure | |
106 | * | |
7854d3f7 | 107 | * read function for 16bit buswidth without endianness conversion |
1da177e4 LT |
108 | */ |
109 | static u16 au_read_word(struct mtd_info *mtd) | |
110 | { | |
111 | struct nand_chip *this = mtd->priv; | |
112 | u16 ret = readw(this->IO_ADDR_R); | |
113 | au_sync(); | |
114 | return ret; | |
115 | } | |
116 | ||
1da177e4 LT |
117 | /** |
118 | * au_write_buf - write buffer to chip | |
119 | * @mtd: MTD device structure | |
120 | * @buf: data buffer | |
121 | * @len: number of bytes to write | |
122 | * | |
7854d3f7 | 123 | * write function for 8bit buswidth |
1da177e4 LT |
124 | */ |
125 | static void au_write_buf(struct mtd_info *mtd, const u_char *buf, int len) | |
126 | { | |
127 | int i; | |
128 | struct nand_chip *this = mtd->priv; | |
129 | ||
e0c7d767 | 130 | for (i = 0; i < len; i++) { |
1da177e4 LT |
131 | writeb(buf[i], this->IO_ADDR_W); |
132 | au_sync(); | |
133 | } | |
134 | } | |
135 | ||
136 | /** | |
61b03bd7 | 137 | * au_read_buf - read chip data into buffer |
1da177e4 LT |
138 | * @mtd: MTD device structure |
139 | * @buf: buffer to store date | |
140 | * @len: number of bytes to read | |
141 | * | |
7854d3f7 | 142 | * read function for 8bit buswidth |
1da177e4 LT |
143 | */ |
144 | static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len) | |
145 | { | |
146 | int i; | |
147 | struct nand_chip *this = mtd->priv; | |
148 | ||
e0c7d767 | 149 | for (i = 0; i < len; i++) { |
1da177e4 | 150 | buf[i] = readb(this->IO_ADDR_R); |
61b03bd7 | 151 | au_sync(); |
1da177e4 LT |
152 | } |
153 | } | |
154 | ||
155 | /** | |
61b03bd7 | 156 | * au_verify_buf - Verify chip data against buffer |
1da177e4 LT |
157 | * @mtd: MTD device structure |
158 | * @buf: buffer containing the data to compare | |
159 | * @len: number of bytes to compare | |
160 | * | |
7854d3f7 | 161 | * verify function for 8bit buswidth |
1da177e4 LT |
162 | */ |
163 | static int au_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) | |
164 | { | |
165 | int i; | |
166 | struct nand_chip *this = mtd->priv; | |
167 | ||
e0c7d767 | 168 | for (i = 0; i < len; i++) { |
1da177e4 LT |
169 | if (buf[i] != readb(this->IO_ADDR_R)) |
170 | return -EFAULT; | |
171 | au_sync(); | |
172 | } | |
173 | ||
174 | return 0; | |
175 | } | |
176 | ||
177 | /** | |
178 | * au_write_buf16 - write buffer to chip | |
179 | * @mtd: MTD device structure | |
180 | * @buf: data buffer | |
181 | * @len: number of bytes to write | |
182 | * | |
7854d3f7 | 183 | * write function for 16bit buswidth |
1da177e4 LT |
184 | */ |
185 | static void au_write_buf16(struct mtd_info *mtd, const u_char *buf, int len) | |
186 | { | |
187 | int i; | |
188 | struct nand_chip *this = mtd->priv; | |
189 | u16 *p = (u16 *) buf; | |
190 | len >>= 1; | |
61b03bd7 | 191 | |
e0c7d767 | 192 | for (i = 0; i < len; i++) { |
1da177e4 LT |
193 | writew(p[i], this->IO_ADDR_W); |
194 | au_sync(); | |
195 | } | |
61b03bd7 | 196 | |
1da177e4 LT |
197 | } |
198 | ||
199 | /** | |
61b03bd7 | 200 | * au_read_buf16 - read chip data into buffer |
1da177e4 LT |
201 | * @mtd: MTD device structure |
202 | * @buf: buffer to store date | |
203 | * @len: number of bytes to read | |
204 | * | |
7854d3f7 | 205 | * read function for 16bit buswidth |
1da177e4 LT |
206 | */ |
207 | static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len) | |
208 | { | |
209 | int i; | |
210 | struct nand_chip *this = mtd->priv; | |
211 | u16 *p = (u16 *) buf; | |
212 | len >>= 1; | |
213 | ||
e0c7d767 | 214 | for (i = 0; i < len; i++) { |
1da177e4 LT |
215 | p[i] = readw(this->IO_ADDR_R); |
216 | au_sync(); | |
217 | } | |
218 | } | |
219 | ||
220 | /** | |
61b03bd7 | 221 | * au_verify_buf16 - Verify chip data against buffer |
1da177e4 LT |
222 | * @mtd: MTD device structure |
223 | * @buf: buffer containing the data to compare | |
224 | * @len: number of bytes to compare | |
225 | * | |
7854d3f7 | 226 | * verify function for 16bit buswidth |
1da177e4 LT |
227 | */ |
228 | static int au_verify_buf16(struct mtd_info *mtd, const u_char *buf, int len) | |
229 | { | |
230 | int i; | |
231 | struct nand_chip *this = mtd->priv; | |
232 | u16 *p = (u16 *) buf; | |
233 | len >>= 1; | |
234 | ||
e0c7d767 | 235 | for (i = 0; i < len; i++) { |
1da177e4 LT |
236 | if (p[i] != readw(this->IO_ADDR_R)) |
237 | return -EFAULT; | |
238 | au_sync(); | |
239 | } | |
240 | return 0; | |
241 | } | |
242 | ||
7abd3ef9 TG |
243 | /* Select the chip by setting nCE to low */ |
244 | #define NAND_CTL_SETNCE 1 | |
245 | /* Deselect the chip by setting nCE to high */ | |
246 | #define NAND_CTL_CLRNCE 2 | |
247 | /* Select the command latch by setting CLE to high */ | |
248 | #define NAND_CTL_SETCLE 3 | |
249 | /* Deselect the command latch by setting CLE to low */ | |
250 | #define NAND_CTL_CLRCLE 4 | |
251 | /* Select the address latch by setting ALE to high */ | |
252 | #define NAND_CTL_SETALE 5 | |
253 | /* Deselect the address latch by setting ALE to low */ | |
254 | #define NAND_CTL_CLRALE 6 | |
1da177e4 LT |
255 | |
256 | static void au1550_hwcontrol(struct mtd_info *mtd, int cmd) | |
257 | { | |
258 | register struct nand_chip *this = mtd->priv; | |
259 | ||
e0c7d767 DW |
260 | switch (cmd) { |
261 | ||
262 | case NAND_CTL_SETCLE: | |
263 | this->IO_ADDR_W = p_nand + MEM_STNAND_CMD; | |
264 | break; | |
265 | ||
266 | case NAND_CTL_CLRCLE: | |
267 | this->IO_ADDR_W = p_nand + MEM_STNAND_DATA; | |
268 | break; | |
1da177e4 | 269 | |
e0c7d767 DW |
270 | case NAND_CTL_SETALE: |
271 | this->IO_ADDR_W = p_nand + MEM_STNAND_ADDR; | |
272 | break; | |
1da177e4 | 273 | |
61b03bd7 TG |
274 | case NAND_CTL_CLRALE: |
275 | this->IO_ADDR_W = p_nand + MEM_STNAND_DATA; | |
e0c7d767 | 276 | /* FIXME: Nobody knows why this is necessary, |
1da177e4 | 277 | * but it works only that way */ |
61b03bd7 | 278 | udelay(1); |
1da177e4 LT |
279 | break; |
280 | ||
61b03bd7 | 281 | case NAND_CTL_SETNCE: |
1da177e4 | 282 | /* assert (force assert) chip enable */ |
e0c7d767 | 283 | au_writel((1 << (4 + NAND_CS)), MEM_STNDCTL); |
1da177e4 LT |
284 | break; |
285 | ||
61b03bd7 | 286 | case NAND_CTL_CLRNCE: |
e0c7d767 DW |
287 | /* deassert chip enable */ |
288 | au_writel(0, MEM_STNDCTL); | |
1da177e4 LT |
289 | break; |
290 | } | |
291 | ||
292 | this->IO_ADDR_R = this->IO_ADDR_W; | |
61b03bd7 | 293 | |
1da177e4 LT |
294 | /* Drain the writebuffer */ |
295 | au_sync(); | |
296 | } | |
297 | ||
298 | int au1550_device_ready(struct mtd_info *mtd) | |
299 | { | |
300 | int ret = (au_readl(MEM_STSTAT) & 0x1) ? 1 : 0; | |
301 | au_sync(); | |
302 | return ret; | |
303 | } | |
304 | ||
35af68b5 SS |
305 | /** |
306 | * au1550_select_chip - control -CE line | |
307 | * Forbid driving -CE manually permitting the NAND controller to do this. | |
308 | * Keeping -CE asserted during the whole sector reads interferes with the | |
309 | * NOR flash and PCMCIA drivers as it causes contention on the static bus. | |
310 | * We only have to hold -CE low for the NAND read commands since the flash | |
311 | * chip needs it to be asserted during chip not ready time but the NAND | |
312 | * controller keeps it released. | |
313 | * | |
314 | * @mtd: MTD device structure | |
315 | * @chip: chipnumber to select, -1 for deselect | |
316 | */ | |
317 | static void au1550_select_chip(struct mtd_info *mtd, int chip) | |
318 | { | |
319 | } | |
320 | ||
321 | /** | |
322 | * au1550_command - Send command to NAND device | |
323 | * @mtd: MTD device structure | |
324 | * @command: the command to be sent | |
325 | * @column: the column address for this command, -1 if none | |
326 | * @page_addr: the page address for this command, -1 if none | |
327 | */ | |
328 | static void au1550_command(struct mtd_info *mtd, unsigned command, int column, int page_addr) | |
329 | { | |
330 | register struct nand_chip *this = mtd->priv; | |
331 | int ce_override = 0, i; | |
332 | ulong flags; | |
333 | ||
334 | /* Begin command latch cycle */ | |
7abd3ef9 | 335 | au1550_hwcontrol(mtd, NAND_CTL_SETCLE); |
35af68b5 SS |
336 | /* |
337 | * Write out the command to the device. | |
338 | */ | |
339 | if (command == NAND_CMD_SEQIN) { | |
340 | int readcmd; | |
341 | ||
28318776 | 342 | if (column >= mtd->writesize) { |
35af68b5 | 343 | /* OOB area */ |
28318776 | 344 | column -= mtd->writesize; |
35af68b5 SS |
345 | readcmd = NAND_CMD_READOOB; |
346 | } else if (column < 256) { | |
347 | /* First 256 bytes --> READ0 */ | |
348 | readcmd = NAND_CMD_READ0; | |
349 | } else { | |
350 | column -= 256; | |
351 | readcmd = NAND_CMD_READ1; | |
352 | } | |
cad74f2c | 353 | au1550_write_byte(mtd, readcmd); |
35af68b5 | 354 | } |
cad74f2c | 355 | au1550_write_byte(mtd, command); |
35af68b5 SS |
356 | |
357 | /* Set ALE and clear CLE to start address cycle */ | |
7abd3ef9 | 358 | au1550_hwcontrol(mtd, NAND_CTL_CLRCLE); |
35af68b5 SS |
359 | |
360 | if (column != -1 || page_addr != -1) { | |
7abd3ef9 | 361 | au1550_hwcontrol(mtd, NAND_CTL_SETALE); |
35af68b5 SS |
362 | |
363 | /* Serially input address */ | |
364 | if (column != -1) { | |
365 | /* Adjust columns for 16 bit buswidth */ | |
366 | if (this->options & NAND_BUSWIDTH_16) | |
367 | column >>= 1; | |
cad74f2c | 368 | au1550_write_byte(mtd, column); |
35af68b5 SS |
369 | } |
370 | if (page_addr != -1) { | |
cad74f2c | 371 | au1550_write_byte(mtd, (u8)(page_addr & 0xff)); |
35af68b5 SS |
372 | |
373 | if (command == NAND_CMD_READ0 || | |
374 | command == NAND_CMD_READ1 || | |
375 | command == NAND_CMD_READOOB) { | |
376 | /* | |
377 | * NAND controller will release -CE after | |
378 | * the last address byte is written, so we'll | |
379 | * have to forcibly assert it. No interrupts | |
380 | * are allowed while we do this as we don't | |
381 | * want the NOR flash or PCMCIA drivers to | |
382 | * steal our precious bytes of data... | |
383 | */ | |
384 | ce_override = 1; | |
385 | local_irq_save(flags); | |
7abd3ef9 | 386 | au1550_hwcontrol(mtd, NAND_CTL_SETNCE); |
35af68b5 SS |
387 | } |
388 | ||
cad74f2c | 389 | au1550_write_byte(mtd, (u8)(page_addr >> 8)); |
35af68b5 SS |
390 | |
391 | /* One more address cycle for devices > 32MiB */ | |
392 | if (this->chipsize > (32 << 20)) | |
cad74f2c | 393 | au1550_write_byte(mtd, (u8)((page_addr >> 16) & 0x0f)); |
35af68b5 SS |
394 | } |
395 | /* Latch in address */ | |
7abd3ef9 | 396 | au1550_hwcontrol(mtd, NAND_CTL_CLRALE); |
35af68b5 SS |
397 | } |
398 | ||
399 | /* | |
400 | * Program and erase have their own busy handlers. | |
401 | * Status and sequential in need no delay. | |
402 | */ | |
403 | switch (command) { | |
404 | ||
405 | case NAND_CMD_PAGEPROG: | |
406 | case NAND_CMD_ERASE1: | |
407 | case NAND_CMD_ERASE2: | |
408 | case NAND_CMD_SEQIN: | |
409 | case NAND_CMD_STATUS: | |
410 | return; | |
411 | ||
412 | case NAND_CMD_RESET: | |
413 | break; | |
414 | ||
415 | case NAND_CMD_READ0: | |
416 | case NAND_CMD_READ1: | |
417 | case NAND_CMD_READOOB: | |
418 | /* Check if we're really driving -CE low (just in case) */ | |
419 | if (unlikely(!ce_override)) | |
420 | break; | |
421 | ||
422 | /* Apply a short delay always to ensure that we do wait tWB. */ | |
423 | ndelay(100); | |
424 | /* Wait for a chip to become ready... */ | |
425 | for (i = this->chip_delay; !this->dev_ready(mtd) && i > 0; --i) | |
426 | udelay(1); | |
427 | ||
428 | /* Release -CE and re-enable interrupts. */ | |
7abd3ef9 | 429 | au1550_hwcontrol(mtd, NAND_CTL_CLRNCE); |
35af68b5 SS |
430 | local_irq_restore(flags); |
431 | return; | |
432 | } | |
433 | /* Apply this short delay always to ensure that we do wait tWB. */ | |
434 | ndelay(100); | |
435 | ||
436 | while(!this->dev_ready(mtd)); | |
437 | } | |
438 | ||
439 | ||
1da177e4 LT |
440 | /* |
441 | * Main initialization routine | |
442 | */ | |
cead4dbc | 443 | static int __init au1xxx_nand_init(void) |
1da177e4 LT |
444 | { |
445 | struct nand_chip *this; | |
e0c7d767 | 446 | u16 boot_swapboot = 0; /* default value */ |
1da177e4 | 447 | int retval; |
ef6f0d1f PP |
448 | u32 mem_staddr; |
449 | u32 nand_phys; | |
1da177e4 LT |
450 | |
451 | /* Allocate memory for MTD device structure and private data */ | |
34970a7d | 452 | au1550_mtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL); |
1da177e4 | 453 | if (!au1550_mtd) { |
e0c7d767 | 454 | printk("Unable to allocate NAND MTD dev structure.\n"); |
1da177e4 LT |
455 | return -ENOMEM; |
456 | } | |
457 | ||
458 | /* Get pointer to private data */ | |
e0c7d767 | 459 | this = (struct nand_chip *)(&au1550_mtd[1]); |
1da177e4 | 460 | |
1da177e4 LT |
461 | /* Link the private data with the MTD structure */ |
462 | au1550_mtd->priv = this; | |
552d9205 | 463 | au1550_mtd->owner = THIS_MODULE; |
1da177e4 | 464 | |
61b03bd7 | 465 | |
155285c4 SS |
466 | /* MEM_STNDCTL: disable ints, disable nand boot */ |
467 | au_writel(0, MEM_STNDCTL); | |
1da177e4 LT |
468 | |
469 | #ifdef CONFIG_MIPS_PB1550 | |
470 | /* set gpio206 high */ | |
b7f720d6 | 471 | gpio_direction_input(206); |
1da177e4 | 472 | |
9bdcf336 ML |
473 | boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) | ((bcsr_read(BCSR_STATUS) >> 6) & 0x1); |
474 | ||
1da177e4 | 475 | switch (boot_swapboot) { |
e0c7d767 DW |
476 | case 0: |
477 | case 2: | |
478 | case 8: | |
479 | case 0xC: | |
480 | case 0xD: | |
481 | /* x16 NAND Flash */ | |
482 | nand_width = 0; | |
483 | break; | |
484 | case 1: | |
485 | case 9: | |
486 | case 3: | |
487 | case 0xE: | |
488 | case 0xF: | |
489 | /* x8 NAND Flash */ | |
490 | nand_width = 1; | |
491 | break; | |
492 | default: | |
493 | printk("Pb1550 NAND: bad boot:swap\n"); | |
494 | retval = -EINVAL; | |
495 | goto outmem; | |
1da177e4 LT |
496 | } |
497 | #endif | |
498 | ||
ef6f0d1f PP |
499 | /* Configure chip-select; normally done by boot code, e.g. YAMON */ |
500 | #ifdef NAND_STCFG | |
501 | if (NAND_CS == 0) { | |
502 | au_writel(NAND_STCFG, MEM_STCFG0); | |
503 | au_writel(NAND_STTIME, MEM_STTIME0); | |
504 | au_writel(NAND_STADDR, MEM_STADDR0); | |
505 | } | |
506 | if (NAND_CS == 1) { | |
507 | au_writel(NAND_STCFG, MEM_STCFG1); | |
508 | au_writel(NAND_STTIME, MEM_STTIME1); | |
509 | au_writel(NAND_STADDR, MEM_STADDR1); | |
510 | } | |
511 | if (NAND_CS == 2) { | |
512 | au_writel(NAND_STCFG, MEM_STCFG2); | |
513 | au_writel(NAND_STTIME, MEM_STTIME2); | |
514 | au_writel(NAND_STADDR, MEM_STADDR2); | |
515 | } | |
516 | if (NAND_CS == 3) { | |
517 | au_writel(NAND_STCFG, MEM_STCFG3); | |
518 | au_writel(NAND_STTIME, MEM_STTIME3); | |
519 | au_writel(NAND_STADDR, MEM_STADDR3); | |
520 | } | |
521 | #endif | |
61b03bd7 | 522 | |
ef6f0d1f PP |
523 | /* Locate NAND chip-select in order to determine NAND phys address */ |
524 | mem_staddr = 0x00000000; | |
525 | if (((au_readl(MEM_STCFG0) & 0x7) == 0x5) && (NAND_CS == 0)) | |
526 | mem_staddr = au_readl(MEM_STADDR0); | |
527 | else if (((au_readl(MEM_STCFG1) & 0x7) == 0x5) && (NAND_CS == 1)) | |
528 | mem_staddr = au_readl(MEM_STADDR1); | |
529 | else if (((au_readl(MEM_STCFG2) & 0x7) == 0x5) && (NAND_CS == 2)) | |
530 | mem_staddr = au_readl(MEM_STADDR2); | |
531 | else if (((au_readl(MEM_STCFG3) & 0x7) == 0x5) && (NAND_CS == 3)) | |
532 | mem_staddr = au_readl(MEM_STADDR3); | |
533 | ||
534 | if (mem_staddr == 0x00000000) { | |
535 | printk("Au1xxx NAND: ERROR WITH NAND CHIP-SELECT\n"); | |
536 | kfree(au1550_mtd); | |
537 | return 1; | |
538 | } | |
539 | nand_phys = (mem_staddr << 4) & 0xFFFC0000; | |
1da177e4 | 540 | |
440d4f9f | 541 | p_nand = ioremap(nand_phys, 0x1000); |
ef6f0d1f PP |
542 | |
543 | /* make controller and MTD agree */ | |
544 | if (NAND_CS == 0) | |
e0c7d767 | 545 | nand_width = au_readl(MEM_STCFG0) & (1 << 22); |
ef6f0d1f | 546 | if (NAND_CS == 1) |
e0c7d767 | 547 | nand_width = au_readl(MEM_STCFG1) & (1 << 22); |
ef6f0d1f | 548 | if (NAND_CS == 2) |
e0c7d767 | 549 | nand_width = au_readl(MEM_STCFG2) & (1 << 22); |
ef6f0d1f | 550 | if (NAND_CS == 3) |
e0c7d767 | 551 | nand_width = au_readl(MEM_STCFG3) & (1 << 22); |
1da177e4 LT |
552 | |
553 | /* Set address of hardware control function */ | |
1da177e4 | 554 | this->dev_ready = au1550_device_ready; |
35af68b5 SS |
555 | this->select_chip = au1550_select_chip; |
556 | this->cmdfunc = au1550_command; | |
557 | ||
1da177e4 | 558 | /* 30 us command delay time */ |
61b03bd7 | 559 | this->chip_delay = 30; |
6dfc6d25 | 560 | this->ecc.mode = NAND_ECC_SOFT; |
1da177e4 LT |
561 | |
562 | this->options = NAND_NO_AUTOINCR; | |
563 | ||
564 | if (!nand_width) | |
565 | this->options |= NAND_BUSWIDTH_16; | |
566 | ||
567 | this->read_byte = (!nand_width) ? au_read_byte16 : au_read_byte; | |
cad74f2c | 568 | au1550_write_byte = (!nand_width) ? au_write_byte16 : au_write_byte; |
1da177e4 LT |
569 | this->read_word = au_read_word; |
570 | this->write_buf = (!nand_width) ? au_write_buf16 : au_write_buf; | |
571 | this->read_buf = (!nand_width) ? au_read_buf16 : au_read_buf; | |
572 | this->verify_buf = (!nand_width) ? au_verify_buf16 : au_verify_buf; | |
573 | ||
574 | /* Scan to find existence of the device */ | |
e0c7d767 | 575 | if (nand_scan(au1550_mtd, 1)) { |
1da177e4 LT |
576 | retval = -ENXIO; |
577 | goto outio; | |
578 | } | |
579 | ||
580 | /* Register the partitions */ | |
ee0e87b1 JI |
581 | mtd_device_register(au1550_mtd, partition_info, |
582 | ARRAY_SIZE(partition_info)); | |
1da177e4 LT |
583 | |
584 | return 0; | |
585 | ||
586 | outio: | |
440d4f9f | 587 | iounmap(p_nand); |
61b03bd7 | 588 | |
1da177e4 | 589 | outmem: |
e0c7d767 | 590 | kfree(au1550_mtd); |
1da177e4 LT |
591 | return retval; |
592 | } | |
593 | ||
ef6f0d1f | 594 | module_init(au1xxx_nand_init); |
1da177e4 LT |
595 | |
596 | /* | |
597 | * Clean up routine | |
598 | */ | |
e0c7d767 | 599 | static void __exit au1550_cleanup(void) |
1da177e4 | 600 | { |
1da177e4 | 601 | /* Release resources, unregister device */ |
e0c7d767 | 602 | nand_release(au1550_mtd); |
1da177e4 LT |
603 | |
604 | /* Free the MTD device structure */ | |
e0c7d767 | 605 | kfree(au1550_mtd); |
1da177e4 LT |
606 | |
607 | /* Unmap */ | |
440d4f9f | 608 | iounmap(p_nand); |
1da177e4 | 609 | } |
e0c7d767 | 610 | |
1da177e4 | 611 | module_exit(au1550_cleanup); |
1da177e4 LT |
612 | |
613 | MODULE_LICENSE("GPL"); | |
614 | MODULE_AUTHOR("Embedded Edge, LLC"); | |
615 | MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board"); |