[deliverable/linux.git] / drivers / mtd / nand / bcm_umi_nand.c

/*****************************************************************************
* Copyright 2004 - 2009 Broadcom Corporation.  All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/

/* ---- Include Files ---------------------------------------------------- */
#include <linux/module.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/ioport.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>

#include <asm/mach-types.h>

#include <mach/reg_nand.h>
#include <mach/reg_umi.h>

#include "nand_bcm_umi.h"

#include <mach/memory_settings.h>

#define USE_DMA 1
#include <mach/dma.h>
#include <linux/dma-mapping.h>
#include <linux/completion.h>

/* ---- External Variable Declarations ----------------------------------- */
/* ---- External Function Prototypes ------------------------------------- */
/* ---- Public Variables ------------------------------------------------- */
/* ---- Private Constants and Types -------------------------------------- */
static const __devinitconst char gBanner[] = KERN_INFO \
	"BCM UMI MTD NAND Driver: 1.00\n";

#if NAND_ECC_BCH
static uint8_t scan_ff_pattern[] = { 0xff };

static struct nand_bbt_descr largepage_bbt = {
	.options = 0,
	.offs = 0,
	.len = 1,
	.pattern = scan_ff_pattern
};
#endif

/*
** Preallocate a buffer to avoid having to do this every dma operation.
** This is the size of the preallocated coherent DMA buffer.
*/
#if USE_DMA
#define DMA_MIN_BUFLEN	512
#define DMA_MAX_BUFLEN	PAGE_SIZE
#define USE_DIRECT_IO(len)	(((len) < DMA_MIN_BUFLEN) || \
	((len) > DMA_MAX_BUFLEN))

/*
 * The current NAND data space goes from 0x80001900 to 0x80001FFF,
 * which is only 0x700 = 1792 bytes long. This is too small for 2K, 4K page
 * size NAND flash. Need to break the DMA down to multiple 1Ks.
 *
 * Need to make sure REG_NAND_DATA_PADDR + DMA_MAX_LEN < 0x80002000
 */
#define DMA_MAX_LEN             1024

#else /* !USE_DMA */
#define DMA_MIN_BUFLEN          0
#define DMA_MAX_BUFLEN          0
#define USE_DIRECT_IO(len)      1
#endif
/* ---- Private Function Prototypes -------------------------------------- */
static void bcm_umi_nand_read_buf(struct mtd_info *mtd, u_char * buf, int len);
static void bcm_umi_nand_write_buf(struct mtd_info *mtd, const u_char * buf,
				   int len);

/* ---- Private Variables ------------------------------------------------ */
static struct mtd_info *board_mtd;
static void __iomem *bcm_umi_io_base;
static void *virtPtr;
static dma_addr_t physPtr;
static struct completion nand_comp;

/* ---- Private Functions ------------------------------------------------ */
#if NAND_ECC_BCH
#include "bcm_umi_bch.c"
#else
#include "bcm_umi_hamming.c"
#endif

#if USE_DMA

/* Handler called when the DMA finishes. */
static void nand_dma_handler(DMA_Device_t dev, int reason, void *userData)
{
	complete(&nand_comp);
}

static int nand_dma_init(void)
{
	int rc;

	rc = dma_set_device_handler(DMA_DEVICE_NAND_MEM_TO_MEM,
		nand_dma_handler, NULL);
	if (rc != 0) {
		printk(KERN_ERR "dma_set_device_handler failed: %d\n", rc);
		return rc;
	}

	virtPtr =
	    dma_alloc_coherent(NULL, DMA_MAX_BUFLEN, &physPtr, GFP_KERNEL);
	if (virtPtr == NULL) {
		printk(KERN_ERR "NAND - Failed to allocate memory for DMA buffer\n");
		return -ENOMEM;
	}

	return 0;
}

static void nand_dma_term(void)
{
	if (virtPtr != NULL)
		dma_free_coherent(NULL, DMA_MAX_BUFLEN, virtPtr, physPtr);
}

static void nand_dma_read(void *buf, int len)
{
	int offset = 0;
	int tmp_len = 0;
	int len_left = len;
	DMA_Handle_t hndl;

	if (virtPtr == NULL)
		panic("nand_dma_read: virtPtr == NULL\n");

	if ((void *)physPtr == NULL)
		panic("nand_dma_read: physPtr == NULL\n");

	hndl = dma_request_channel(DMA_DEVICE_NAND_MEM_TO_MEM);
	if (hndl < 0) {
		printk(KERN_ERR
		       "nand_dma_read: unable to allocate dma channel: %d\n",
		       (int)hndl);
		panic("\n");
	}

	while (len_left > 0) {
		if (len_left > DMA_MAX_LEN) {
			tmp_len = DMA_MAX_LEN;
			len_left -= DMA_MAX_LEN;
		} else {
			tmp_len = len_left;
			len_left = 0;
		}

		init_completion(&nand_comp);
		dma_transfer_mem_to_mem(hndl, REG_NAND_DATA_PADDR,
					physPtr + offset, tmp_len);
		wait_for_completion(&nand_comp);

		offset += tmp_len;
	}

	dma_free_channel(hndl);

	if (buf != NULL)
		memcpy(buf, virtPtr, len);
}

static void nand_dma_write(const void *buf, int len)
{
	int offset = 0;
	int tmp_len = 0;
	int len_left = len;
	DMA_Handle_t hndl;

	if (buf == NULL)
		panic("nand_dma_write: buf == NULL\n");

	if (virtPtr == NULL)
		panic("nand_dma_write: virtPtr == NULL\n");

	if ((void *)physPtr == NULL)
		panic("nand_dma_write: physPtr == NULL\n");

	memcpy(virtPtr, buf, len);


	hndl = dma_request_channel(DMA_DEVICE_NAND_MEM_TO_MEM);
	if (hndl < 0) {
		printk(KERN_ERR
		       "nand_dma_write: unable to allocate dma channel: %d\n",
		       (int)hndl);
		panic("\n");
	}

	while (len_left > 0) {
		if (len_left > DMA_MAX_LEN) {
			tmp_len = DMA_MAX_LEN;
			len_left -= DMA_MAX_LEN;
		} else {
			tmp_len = len_left;
			len_left = 0;
		}

		init_completion(&nand_comp);
		dma_transfer_mem_to_mem(hndl, physPtr + offset,
					REG_NAND_DATA_PADDR, tmp_len);
		wait_for_completion(&nand_comp);

		offset += tmp_len;
	}

	dma_free_channel(hndl);
}

#endif

static int nand_dev_ready(struct mtd_info *mtd)
{
	return nand_bcm_umi_dev_ready();
}

/****************************************************************************
*
*  bcm_umi_nand_inithw
*
*   This routine does the necessary hardware (board-specific)
*   initializations.  This includes setting up the timings, etc.
*
***************************************************************************/
int bcm_umi_nand_inithw(void)
{
	/* Configure nand timing parameters */
	writel(readl(&REG_UMI_NAND_TCR) & ~0x7ffff, &REG_UMI_NAND_TCR);
	writel(readl(&REG_UMI_NAND_TCR) | HW_CFG_NAND_TCR, &REG_UMI_NAND_TCR);

#if !defined(CONFIG_MTD_NAND_BCM_UMI_HWCS)
	/* enable software control of CS */
	writel(readl(&REG_UMI_NAND_TCR) | REG_UMI_NAND_TCR_CS_SWCTRL, &REG_UMI_NAND_TCR);
#endif

	/* keep NAND chip select asserted */
	writel(readl(&REG_UMI_NAND_RCSR) | REG_UMI_NAND_RCSR_CS_ASSERTED, &REG_UMI_NAND_RCSR);

	writel(readl(&REG_UMI_NAND_TCR) & ~REG_UMI_NAND_TCR_WORD16, &REG_UMI_NAND_TCR);
	/* enable writes to flash */
	writel(readl(&REG_UMI_MMD_ICR) | REG_UMI_MMD_ICR_FLASH_WP, &REG_UMI_MMD_ICR);

	writel(NAND_CMD_RESET, bcm_umi_io_base + REG_NAND_CMD_OFFSET);
	nand_bcm_umi_wait_till_ready();

#if NAND_ECC_BCH
	nand_bcm_umi_bch_config_ecc(NAND_ECC_NUM_BYTES);
#endif

	return 0;
}

/* Used to turn latch the proper register for access. */
static void bcm_umi_nand_hwcontrol(struct mtd_info *mtd, int cmd,
				   unsigned int ctrl)
{
	/* send command to hardware */
	struct nand_chip *chip = mtd->priv;
	if (ctrl & NAND_CTRL_CHANGE) {
		if (ctrl & NAND_CLE) {
			chip->IO_ADDR_W = bcm_umi_io_base + REG_NAND_CMD_OFFSET;
			goto CMD;
		}
		if (ctrl & NAND_ALE) {
			chip->IO_ADDR_W =
			    bcm_umi_io_base + REG_NAND_ADDR_OFFSET;
			goto CMD;
		}
		chip->IO_ADDR_W = bcm_umi_io_base + REG_NAND_DATA8_OFFSET;
	}

CMD:
	/* Send command to chip directly */
	if (cmd != NAND_CMD_NONE)
		writeb(cmd, chip->IO_ADDR_W);
}

static void bcm_umi_nand_write_buf(struct mtd_info *mtd, const u_char * buf,
				   int len)
{
	if (USE_DIRECT_IO(len)) {
		/* Do it the old way if the buffer is small or too large.
		 * Probably quicker than starting and checking dma. */
		int i;
		struct nand_chip *this = mtd->priv;

		for (i = 0; i < len; i++)
			writeb(buf[i], this->IO_ADDR_W);
	}
#if USE_DMA
	else
		nand_dma_write(buf, len);
#endif
}

static void bcm_umi_nand_read_buf(struct mtd_info *mtd, u_char * buf, int len)
{
	if (USE_DIRECT_IO(len)) {
		int i;
		struct nand_chip *this = mtd->priv;

		for (i = 0; i < len; i++)
			buf[i] = readb(this->IO_ADDR_R);
	}
#if USE_DMA
	else
		nand_dma_read(buf, len);
#endif
}

static uint8_t readbackbuf[NAND_MAX_PAGESIZE];
static int bcm_umi_nand_verify_buf(struct mtd_info *mtd, const u_char * buf,
				   int len)
{
	/*
	 * Try to readback page with ECC correction. This is necessary
	 * for MLC parts which may have permanently stuck bits.
	 */
	struct nand_chip *chip = mtd->priv;
	int ret = chip->ecc.read_page(mtd, chip, readbackbuf, 0, 0);
	if (ret < 0)
		return -EFAULT;
	else {
		if (memcmp(readbackbuf, buf, len) == 0)
			return 0;

		return -EFAULT;
	}
	return 0;
}

static int __devinit bcm_umi_nand_probe(struct platform_device *pdev)
{
	struct nand_chip *this;
	struct resource *r;
	int err = 0;

	printk(gBanner);

	/* Allocate memory for MTD device structure and private data */
	board_mtd =
	    kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip),
		    GFP_KERNEL);
	if (!board_mtd) {
		printk(KERN_WARNING
		       "Unable to allocate NAND MTD device structure.\n");
		return -ENOMEM;
	}

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	if (!r) {
		err = -ENXIO;
		goto out_free;
	}

	/* map physical address */
	bcm_umi_io_base = ioremap(r->start, resource_size(r));

	if (!bcm_umi_io_base) {
		printk(KERN_ERR "ioremap to access BCM UMI NAND chip failed\n");
		err = -EIO;
		goto out_free;
	}

	/* Get pointer to private data */
	this = (struct nand_chip *)(&board_mtd[1]);

	/* Initialize structures */
	memset((char *)board_mtd, 0, sizeof(struct mtd_info));
	memset((char *)this, 0, sizeof(struct nand_chip));

	/* Link the private data with the MTD structure */
	board_mtd->priv = this;

	/* Initialize the NAND hardware.  */
	if (bcm_umi_nand_inithw() < 0) {
		printk(KERN_ERR "BCM UMI NAND chip could not be initialized\n");
		err = -EIO;
		goto out_unmap;
	}

	/* Set address of NAND IO lines */
	this->IO_ADDR_W = bcm_umi_io_base + REG_NAND_DATA8_OFFSET;
	this->IO_ADDR_R = bcm_umi_io_base + REG_NAND_DATA8_OFFSET;

	/* Set command delay time, see datasheet for correct value */
	this->chip_delay = 0;
	/* Assign the device ready function, if available */
	this->dev_ready = nand_dev_ready;
	this->options = 0;

	this->write_buf = bcm_umi_nand_write_buf;
	this->read_buf = bcm_umi_nand_read_buf;
	this->verify_buf = bcm_umi_nand_verify_buf;

	this->cmd_ctrl = bcm_umi_nand_hwcontrol;
	this->ecc.mode = NAND_ECC_HW;
	this->ecc.size = 512;
	this->ecc.bytes = NAND_ECC_NUM_BYTES;
#if NAND_ECC_BCH
	this->ecc.read_page = bcm_umi_bch_read_page_hwecc;
	this->ecc.write_page = bcm_umi_bch_write_page_hwecc;
#else
	this->ecc.correct = nand_correct_data512;
	this->ecc.calculate = bcm_umi_hamming_get_hw_ecc;
	this->ecc.hwctl = bcm_umi_hamming_enable_hwecc;
#endif

#if USE_DMA
	err = nand_dma_init();
	if (err != 0)
		goto out_unmap;
#endif

	/* Figure out the size of the device that we have.
	 * We need to do this to figure out which ECC
	 * layout we'll be using.
	 */

	err = nand_scan_ident(board_mtd, 1, NULL);
	if (err) {
		printk(KERN_ERR "nand_scan failed: %d\n", err);
		goto out_unmap;
	}

	/* Now that we know the nand size, we can setup the ECC layout */

	switch (board_mtd->writesize) {	/* writesize is the pagesize */
	case 4096:
		this->ecc.layout = &nand_hw_eccoob_4096;
		break;
	case 2048:
		this->ecc.layout = &nand_hw_eccoob_2048;
		break;
	case 512:
		this->ecc.layout = &nand_hw_eccoob_512;
		break;
	default:
		{
			printk(KERN_ERR "NAND - Unrecognized pagesize: %d\n",
					 board_mtd->writesize);
			err = -EINVAL;
			goto out_unmap;
		}
	}

#if NAND_ECC_BCH
	if (board_mtd->writesize > 512) {
		if (this->bbt_options & NAND_BBT_USE_FLASH)
			largepage_bbt.options = NAND_BBT_SCAN2NDPAGE;
		this->badblock_pattern = &largepage_bbt;
	}

	this->ecc.strength = 8;

#endif

	/* Now finish off the scan, now that ecc.layout has been initialized. */

	err = nand_scan_tail(board_mtd);
	if (err) {
		printk(KERN_ERR "nand_scan failed: %d\n", err);
		goto out_unmap;
	}

	/* Register the partitions */
	board_mtd->name = "bcm_umi-nand";
	mtd_device_parse_register(board_mtd, NULL, NULL, NULL, 0);

	/* Return happy */
	return 0;
out_unmap:
	iounmap(bcm_umi_io_base);
out_free:
	kfree(board_mtd);
	return err;
}

static int bcm_umi_nand_remove(struct platform_device *pdev)
{
#if USE_DMA
	nand_dma_term();
#endif

	/* Release resources, unregister device */
	nand_release(board_mtd);

	/* unmap physical address */
	iounmap(bcm_umi_io_base);

	/* Free the MTD device structure */
	kfree(board_mtd);

	return 0;
}

#ifdef CONFIG_PM
static int bcm_umi_nand_suspend(struct platform_device *pdev,
				pm_message_t state)
{
	printk(KERN_ERR "MTD NAND suspend is being called\n");
	return 0;
}

static int bcm_umi_nand_resume(struct platform_device *pdev)
{
	printk(KERN_ERR "MTD NAND resume is being called\n");
	return 0;
}
#else
#define bcm_umi_nand_suspend   NULL
#define bcm_umi_nand_resume    NULL
#endif

static struct platform_driver nand_driver = {
	.driver = {
		   .name = "bcm-nand",
		   .owner = THIS_MODULE,
		   },
	.probe = bcm_umi_nand_probe,
	.remove = bcm_umi_nand_remove,
	.suspend = bcm_umi_nand_suspend,
	.resume = bcm_umi_nand_resume,
};

module_platform_driver(nand_driver);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Broadcom");
MODULE_DESCRIPTION("BCM UMI MTD NAND driver");
Commit	Line	Data
266dead2 LHC	1	/*****************************************************************************
	2	* Copyright 2004 - 2009 Broadcom Corporation. All rights reserved.
	3	*
	4	* Unless you and Broadcom execute a separate written software license
	5	* agreement governing use of this software, this software is licensed to you
	6	* under the terms of the GNU General Public License version 2, available at
	7	* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
	8	*
	9	* Notwithstanding the above, under no circumstances may you combine this
	10	* software in any way with any other Broadcom software provided under a
	11	* license other than the GPL, without Broadcom's express prior written
	12	* consent.
	13	*****************************************************************************/
	14
	15	/* ---- Include Files ---------------------------------------------------- */
266dead2 LHC	16	#include <linux/module.h>
	17	#include <linux/types.h>
	18	#include <linux/init.h>
	19	#include <linux/kernel.h>
5a0e3ad6	20	#include <linux/slab.h>
266dead2 LHC	21	#include <linux/string.h>
	22	#include <linux/ioport.h>
	23	#include <linux/device.h>
	24	#include <linux/delay.h>
	25	#include <linux/err.h>
	26	#include <linux/io.h>
	27	#include <linux/platform_device.h>
	28	#include <linux/mtd/mtd.h>
	29	#include <linux/mtd/nand.h>
	30	#include <linux/mtd/nand_ecc.h>
	31	#include <linux/mtd/partitions.h>
	32
	33	#include <asm/mach-types.h>
266dead2 LHC	34
	35	#include <mach/reg_nand.h>
	36	#include <mach/reg_umi.h>
	37
	38	#include "nand_bcm_umi.h"
	39
	40	#include <mach/memory_settings.h>
	41
	42	#define USE_DMA 1
	43	#include <mach/dma.h>
	44	#include <linux/dma-mapping.h>
	45	#include <linux/completion.h>
	46
	47	/* ---- External Variable Declarations ----------------------------------- */
	48	/* ---- External Function Prototypes ------------------------------------- */
	49	/* ---- Public Variables ------------------------------------------------- */
	50	/* ---- Private Constants and Types -------------------------------------- */
	51	static const __devinitconst char gBanner[] = KERN_INFO \
	52	"BCM UMI MTD NAND Driver: 1.00\n";
	53
266dead2 LHC	54	#if NAND_ECC_BCH
	55	static uint8_t scan_ff_pattern[] = { 0xff };
	56
	57	static struct nand_bbt_descr largepage_bbt = {
	58	.options = 0,
	59	.offs = 0,
	60	.len = 1,
	61	.pattern = scan_ff_pattern
	62	};
	63	#endif
	64
	65	/*
	66	** Preallocate a buffer to avoid having to do this every dma operation.
	67	** This is the size of the preallocated coherent DMA buffer.
	68	*/
	69	#if USE_DMA
	70	#define DMA_MIN_BUFLEN 512
	71	#define DMA_MAX_BUFLEN PAGE_SIZE
	72	#define USE_DIRECT_IO(len) (((len) < DMA_MIN_BUFLEN) \|\| \
	73	((len) > DMA_MAX_BUFLEN))
	74
	75	/*
	76	* The current NAND data space goes from 0x80001900 to 0x80001FFF,
	77	* which is only 0x700 = 1792 bytes long. This is too small for 2K, 4K page
	78	* size NAND flash. Need to break the DMA down to multiple 1Ks.
	79	*
	80	* Need to make sure REG_NAND_DATA_PADDR + DMA_MAX_LEN < 0x80002000
	81	*/
	82	#define DMA_MAX_LEN 1024
	83
	84	#else /* !USE_DMA */
	85	#define DMA_MIN_BUFLEN 0
	86	#define DMA_MAX_BUFLEN 0
	87	#define USE_DIRECT_IO(len) 1
	88	#endif
	89	/* ---- Private Function Prototypes -------------------------------------- */
	90	static void bcm_umi_nand_read_buf(struct mtd_info mtd, u_char buf, int len);
	91	static void bcm_umi_nand_write_buf(struct mtd_info mtd, const u_char buf,
	92	int len);
	93
	94	/* ---- Private Variables ------------------------------------------------ */
	95	static struct mtd_info *board_mtd;
	96	static void __iomem *bcm_umi_io_base;
	97	static void *virtPtr;
	98	static dma_addr_t physPtr;
	99	static struct completion nand_comp;
	100
	101	/* ---- Private Functions ------------------------------------------------ */
	102	#if NAND_ECC_BCH
	103	#include "bcm_umi_bch.c"
	104	#else
	105	#include "bcm_umi_hamming.c"
	106	#endif
	107
	108	#if USE_DMA
	109
	110	/* Handler called when the DMA finishes. */
	111	static void nand_dma_handler(DMA_Device_t dev, int reason, void *userData)
	112	{
	113	complete(&nand_comp);
	114	}
	115
	116	static int nand_dma_init(void)
	117	{
118	int rc;
119
120	rc = dma_set_device_handler(DMA_DEVICE_NAND_MEM_TO_MEM,
121	nand_dma_handler, NULL);
122	if (rc != 0) {
123	printk(KERN_ERR "dma_set_device_handler failed: %d\n", rc);
124	return rc;
125	}
126
127	virtPtr =
128	dma_alloc_coherent(NULL, DMA_MAX_BUFLEN, &physPtr, GFP_KERNEL);
129	if (virtPtr == NULL) {
130	printk(KERN_ERR "NAND - Failed to allocate memory for DMA buffer\n");
131	return -ENOMEM;
132	}
133
134	return 0;
135	}
136
137	static void nand_dma_term(void)
138	{
139	if (virtPtr != NULL)
140	dma_free_coherent(NULL, DMA_MAX_BUFLEN, virtPtr, physPtr);
141	}
142
143	static void nand_dma_read(void *buf, int len)
144	{
145	int offset = 0;
146	int tmp_len = 0;
147	int len_left = len;
148	DMA_Handle_t hndl;
149
150	if (virtPtr == NULL)
151	panic("nand_dma_read: virtPtr == NULL\n");
152
153	if ((void *)physPtr == NULL)
154	panic("nand_dma_read: physPtr == NULL\n");
155
156	hndl = dma_request_channel(DMA_DEVICE_NAND_MEM_TO_MEM);
157	if (hndl < 0) {
158	printk(KERN_ERR
159	"nand_dma_read: unable to allocate dma channel: %d\n",
160	(int)hndl);
161	panic("\n");
162	}
163
164	while (len_left > 0) {
165	if (len_left > DMA_MAX_LEN) {
166	tmp_len = DMA_MAX_LEN;
167	len_left -= DMA_MAX_LEN;
168	} else {
169	tmp_len = len_left;
170	len_left = 0;
171	}
172
173	init_completion(&nand_comp);
174	dma_transfer_mem_to_mem(hndl, REG_NAND_DATA_PADDR,
175	physPtr + offset, tmp_len);
176	wait_for_completion(&nand_comp);
177
178	offset += tmp_len;
179	}
180
181	dma_free_channel(hndl);
182
183	if (buf != NULL)
184	memcpy(buf, virtPtr, len);
185	}
186
187	static void nand_dma_write(const void *buf, int len)
188	{
189	int offset = 0;
190	int tmp_len = 0;
191	int len_left = len;
192	DMA_Handle_t hndl;
193
194	if (buf == NULL)
195	panic("nand_dma_write: buf == NULL\n");
196
197	if (virtPtr == NULL)
198	panic("nand_dma_write: virtPtr == NULL\n");
199
200	if ((void *)physPtr == NULL)
201	panic("nand_dma_write: physPtr == NULL\n");
202
203	memcpy(virtPtr, buf, len);
204
205
206	hndl = dma_request_channel(DMA_DEVICE_NAND_MEM_TO_MEM);
207	if (hndl < 0) {
208	printk(KERN_ERR
209	"nand_dma_write: unable to allocate dma channel: %d\n",
210	(int)hndl);
211	panic("\n");
212	}
213
214	while (len_left > 0) {
215	if (len_left > DMA_MAX_LEN) {
216	tmp_len = DMA_MAX_LEN;
217	len_left -= DMA_MAX_LEN;
218	} else {
219	tmp_len = len_left;
220	len_left = 0;
221	}
222
223	init_completion(&nand_comp);
224	dma_transfer_mem_to_mem(hndl, physPtr + offset,
225	REG_NAND_DATA_PADDR, tmp_len);
226	wait_for_completion(&nand_comp);
227
228	offset += tmp_len;
229	}
230
231	dma_free_channel(hndl);
232	}
233
234	#endif
235
236	static int nand_dev_ready(struct mtd_info *mtd)
237	{
238	return nand_bcm_umi_dev_ready();
239	}
240
241	/****************************************************************************
242	*
243	* bcm_umi_nand_inithw
244	*
245	* This routine does the necessary hardware (board-specific)
246	* initializations. This includes setting up the timings, etc.
247	*
248	***************************************************************************/
249	int bcm_umi_nand_inithw(void)
250	{
251	/* Configure nand timing parameters */
878040ef AB	252	writel(readl(&REG_UMI_NAND_TCR) & ~0x7ffff, &REG_UMI_NAND_TCR);
878040ef AB	253	writel(readl(&REG_UMI_NAND_TCR) \| HW_CFG_NAND_TCR, &REG_UMI_NAND_TCR);
266dead2 LHC	254
	255	#if !defined(CONFIG_MTD_NAND_BCM_UMI_HWCS)
	256	/* enable software control of CS */
878040ef	257	writel(readl(&REG_UMI_NAND_TCR) \| REG_UMI_NAND_TCR_CS_SWCTRL, &REG_UMI_NAND_TCR);
266dead2 LHC	258	#endif
	259
	260	/* keep NAND chip select asserted */
878040ef	261	writel(readl(&REG_UMI_NAND_RCSR) \| REG_UMI_NAND_RCSR_CS_ASSERTED, &REG_UMI_NAND_RCSR);
266dead2	262
878040ef	263	writel(readl(&REG_UMI_NAND_TCR) & ~REG_UMI_NAND_TCR_WORD16, &REG_UMI_NAND_TCR);
266dead2	264	/* enable writes to flash */
878040ef	265	writel(readl(&REG_UMI_MMD_ICR) \| REG_UMI_MMD_ICR_FLASH_WP, &REG_UMI_MMD_ICR);
266dead2 LHC	266
	267	writel(NAND_CMD_RESET, bcm_umi_io_base + REG_NAND_CMD_OFFSET);
	268	nand_bcm_umi_wait_till_ready();
	269
	270	#if NAND_ECC_BCH
	271	nand_bcm_umi_bch_config_ecc(NAND_ECC_NUM_BYTES);
	272	#endif
	273
	274	return 0;
	275	}
	276
	277	/* Used to turn latch the proper register for access. */
	278	static void bcm_umi_nand_hwcontrol(struct mtd_info *mtd, int cmd,
	279	unsigned int ctrl)
	280	{
	281	/* send command to hardware */
	282	struct nand_chip *chip = mtd->priv;
	283	if (ctrl & NAND_CTRL_CHANGE) {
	284	if (ctrl & NAND_CLE) {
	285	chip->IO_ADDR_W = bcm_umi_io_base + REG_NAND_CMD_OFFSET;
	286	goto CMD;
	287	}
	288	if (ctrl & NAND_ALE) {
	289	chip->IO_ADDR_W =
	290	bcm_umi_io_base + REG_NAND_ADDR_OFFSET;
	291	goto CMD;
	292	}
	293	chip->IO_ADDR_W = bcm_umi_io_base + REG_NAND_DATA8_OFFSET;
	294	}
	295
	296	CMD:
	297	/* Send command to chip directly */
	298	if (cmd != NAND_CMD_NONE)
	299	writeb(cmd, chip->IO_ADDR_W);
	300	}
	301
	302	static void bcm_umi_nand_write_buf(struct mtd_info mtd, const u_char buf,
	303	int len)
	304	{
	305	if (USE_DIRECT_IO(len)) {
	306	/* Do it the old way if the buffer is small or too large.
	307	* Probably quicker than starting and checking dma. */
	308	int i;
	309	struct nand_chip *this = mtd->priv;
	310
	311	for (i = 0; i < len; i++)
	312	writeb(buf[i], this->IO_ADDR_W);
	313	}
	314	#if USE_DMA
	315	else
	316	nand_dma_write(buf, len);
	317	#endif
	318	}
	319
	320	static void bcm_umi_nand_read_buf(struct mtd_info mtd, u_char buf, int len)
	321	{
	322	if (USE_DIRECT_IO(len)) {
	323	int i;
	324	struct nand_chip *this = mtd->priv;
	325
	326	for (i = 0; i < len; i++)
	327	buf[i] = readb(this->IO_ADDR_R);
	328	}
	329	#if USE_DMA
330	else
331	nand_dma_read(buf, len);
332	#endif
333	}
334
335	static uint8_t readbackbuf[NAND_MAX_PAGESIZE];
336	static int bcm_umi_nand_verify_buf(struct mtd_info mtd, const u_char buf,
337	int len)
338	{
339	/*
340	* Try to readback page with ECC correction. This is necessary
341	* for MLC parts which may have permanently stuck bits.
342	*/
343	struct nand_chip *chip = mtd->priv;
1fbb938d	344	int ret = chip->ecc.read_page(mtd, chip, readbackbuf, 0, 0);
266dead2 LHC	345	if (ret < 0)
	346	return -EFAULT;
	347	else {
	348	if (memcmp(readbackbuf, buf, len) == 0)
	349	return 0;
	350
	351	return -EFAULT;
	352	}
	353	return 0;
	354	}
	355
	356	static int __devinit bcm_umi_nand_probe(struct platform_device *pdev)
	357	{
	358	struct nand_chip *this;
	359	struct resource *r;
	360	int err = 0;
	361
	362	printk(gBanner);
	363
	364	/* Allocate memory for MTD device structure and private data */
	365	board_mtd =
	366	kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip),
	367	GFP_KERNEL);
	368	if (!board_mtd) {
	369	printk(KERN_WARNING
	370	"Unable to allocate NAND MTD device structure.\n");
	371	return -ENOMEM;
	372	}
	373
	374	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	375
38ca6ebc JL	376	if (!r) {
	377	err = -ENXIO;
	378	goto out_free;
	379	}
266dead2	380
3ad2f3fb	381	/* map physical address */
28f65c11	382	bcm_umi_io_base = ioremap(r->start, resource_size(r));
266dead2 LHC	383
	384	if (!bcm_umi_io_base) {
	385	printk(KERN_ERR "ioremap to access BCM UMI NAND chip failed\n");
38ca6ebc JL	386	err = -EIO;
38ca6ebc JL	387	goto out_free;
266dead2 LHC	388	}
	389
	390	/* Get pointer to private data */
	391	this = (struct nand_chip *)(&board_mtd[1]);
	392
	393	/* Initialize structures */
	394	memset((char *)board_mtd, 0, sizeof(struct mtd_info));
	395	memset((char *)this, 0, sizeof(struct nand_chip));
	396
	397	/* Link the private data with the MTD structure */
	398	board_mtd->priv = this;
	399
	400	/* Initialize the NAND hardware. */
	401	if (bcm_umi_nand_inithw() < 0) {
	402	printk(KERN_ERR "BCM UMI NAND chip could not be initialized\n");
38ca6ebc JL	403	err = -EIO;
38ca6ebc JL	404	goto out_unmap;
266dead2 LHC	405	}
	406
	407	/* Set address of NAND IO lines */
	408	this->IO_ADDR_W = bcm_umi_io_base + REG_NAND_DATA8_OFFSET;
	409	this->IO_ADDR_R = bcm_umi_io_base + REG_NAND_DATA8_OFFSET;
	410
	411	/* Set command delay time, see datasheet for correct value */
	412	this->chip_delay = 0;
	413	/* Assign the device ready function, if available */
	414	this->dev_ready = nand_dev_ready;
	415	this->options = 0;
	416
	417	this->write_buf = bcm_umi_nand_write_buf;
	418	this->read_buf = bcm_umi_nand_read_buf;
	419	this->verify_buf = bcm_umi_nand_verify_buf;
	420
	421	this->cmd_ctrl = bcm_umi_nand_hwcontrol;
	422	this->ecc.mode = NAND_ECC_HW;
	423	this->ecc.size = 512;
	424	this->ecc.bytes = NAND_ECC_NUM_BYTES;
	425	#if NAND_ECC_BCH
	426	this->ecc.read_page = bcm_umi_bch_read_page_hwecc;
	427	this->ecc.write_page = bcm_umi_bch_write_page_hwecc;
	428	#else
	429	this->ecc.correct = nand_correct_data512;
	430	this->ecc.calculate = bcm_umi_hamming_get_hw_ecc;
	431	this->ecc.hwctl = bcm_umi_hamming_enable_hwecc;
	432	#endif
	433
	434	#if USE_DMA
	435	err = nand_dma_init();
	436	if (err != 0)
38ca6ebc	437	goto out_unmap;
266dead2 LHC	438	#endif
	439
	440	/* Figure out the size of the device that we have.
	441	* We need to do this to figure out which ECC
	442	* layout we'll be using.
	443	*/
	444
5e81e88a	445	err = nand_scan_ident(board_mtd, 1, NULL);
266dead2 LHC	446	if (err) {
266dead2 LHC	447	printk(KERN_ERR "nand_scan failed: %d\n", err);
38ca6ebc	448	goto out_unmap;
266dead2 LHC	449	}
	450
	451	/* Now that we know the nand size, we can setup the ECC layout */
	452
	453	switch (board_mtd->writesize) { /* writesize is the pagesize */
	454	case 4096:
	455	this->ecc.layout = &nand_hw_eccoob_4096;
	456	break;
	457	case 2048:
	458	this->ecc.layout = &nand_hw_eccoob_2048;
	459	break;
	460	case 512:
	461	this->ecc.layout = &nand_hw_eccoob_512;
	462	break;
	463	default:
	464	{
	465	printk(KERN_ERR "NAND - Unrecognized pagesize: %d\n",
	466	board_mtd->writesize);
38ca6ebc JL	467	err = -EINVAL;
38ca6ebc JL	468	goto out_unmap;
266dead2 LHC	469	}
	470	}
	471
	472	#if NAND_ECC_BCH
	473	if (board_mtd->writesize > 512) {
bb9ebd4e	474	if (this->bbt_options & NAND_BBT_USE_FLASH)
266dead2 LHC	475	largepage_bbt.options = NAND_BBT_SCAN2NDPAGE;
	476	this->badblock_pattern = &largepage_bbt;
	477	}
6a918bad	478
44df4d11	479	this->ecc.strength = 8;
6a918bad	480
266dead2 LHC	481	#endif
	482
	483	/* Now finish off the scan, now that ecc.layout has been initialized. */
	484
	485	err = nand_scan_tail(board_mtd);
	486	if (err) {
	487	printk(KERN_ERR "nand_scan failed: %d\n", err);
38ca6ebc	488	goto out_unmap;
266dead2 LHC	489	}
	490
	491	/* Register the partitions */
58171cb1	492	board_mtd->name = "bcm_umi-nand";
42d7fbe2	493	mtd_device_parse_register(board_mtd, NULL, NULL, NULL, 0);
266dead2 LHC	494
	495	/* Return happy */
	496	return 0;
38ca6ebc JL	497	out_unmap:
	498	iounmap(bcm_umi_io_base);
	499	out_free:
	500	kfree(board_mtd);
	501	return err;
266dead2 LHC	502	}
	503
	504	static int bcm_umi_nand_remove(struct platform_device *pdev)
	505	{
	506	#if USE_DMA
	507	nand_dma_term();
	508	#endif
	509
	510	/* Release resources, unregister device */
	511	nand_release(board_mtd);
	512
3ad2f3fb	513	/* unmap physical address */
266dead2 LHC	514	iounmap(bcm_umi_io_base);
	515
	516	/* Free the MTD device structure */
	517	kfree(board_mtd);
	518
	519	return 0;
	520	}
	521
	522	#ifdef CONFIG_PM
	523	static int bcm_umi_nand_suspend(struct platform_device *pdev,
	524	pm_message_t state)
	525	{
	526	printk(KERN_ERR "MTD NAND suspend is being called\n");
	527	return 0;
	528	}
	529
	530	static int bcm_umi_nand_resume(struct platform_device *pdev)
	531	{
	532	printk(KERN_ERR "MTD NAND resume is being called\n");
	533	return 0;
	534	}
	535	#else
	536	#define bcm_umi_nand_suspend NULL
	537	#define bcm_umi_nand_resume NULL
	538	#endif
	539
	540	static struct platform_driver nand_driver = {
	541	.driver = {
	542	.name = "bcm-nand",
	543	.owner = THIS_MODULE,
	544	},
	545	.probe = bcm_umi_nand_probe,
	546	.remove = bcm_umi_nand_remove,
	547	.suspend = bcm_umi_nand_suspend,
	548	.resume = bcm_umi_nand_resume,
	549	};
	550
f99640de	551	module_platform_driver(nand_driver);
266dead2 LHC	552
	553	MODULE_LICENSE("GPL");
	554	MODULE_AUTHOR("Broadcom");
	555	MODULE_DESCRIPTION("BCM UMI MTD NAND driver");