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mtd: nand: pass page number to ecc->write_xxx() methods
[deliverable/linux.git] / drivers / mtd / nand / brcmnand / brcmnand.c
CommitLineData
27c5b17c
BN		 1/*
2 * Copyright © 2010-2015 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/version.h>
15#include <linux/module.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/device.h>
19#include <linux/platform_device.h>
20#include <linux/err.h>
21#include <linux/completion.h>
22#include <linux/interrupt.h>
23#include <linux/spinlock.h>
24#include <linux/dma-mapping.h>
25#include <linux/ioport.h>
26#include <linux/bug.h>
27#include <linux/kernel.h>
28#include <linux/bitops.h>
29#include <linux/mm.h>
30#include <linux/mtd/mtd.h>
31#include <linux/mtd/nand.h>
32#include <linux/mtd/partitions.h>
33#include <linux/of.h>
34#include <linux/of_mtd.h>
35#include <linux/of_platform.h>
36#include <linux/slab.h>
37#include <linux/list.h>
38#include <linux/log2.h>
39
40#include "brcmnand.h"
41
42/*
43 * This flag controls if WP stays on between erase/write commands to mitigate
44 * flash corruption due to power glitches. Values:
45 * 0: NAND_WP is not used or not available
46 * 1: NAND_WP is set by default, cleared for erase/write operations
47 * 2: NAND_WP is always cleared
48 */
49static int wp_on = 1;
50module_param(wp_on, int, 0444);
51
52/***********************************************************************
53 * Definitions
54 ***********************************************************************/
55
56#define DRV_NAME "brcmnand"
57
58#define CMD_NULL 0x00
59#define CMD_PAGE_READ 0x01
60#define CMD_SPARE_AREA_READ 0x02
61#define CMD_STATUS_READ 0x03
62#define CMD_PROGRAM_PAGE 0x04
63#define CMD_PROGRAM_SPARE_AREA 0x05
64#define CMD_COPY_BACK 0x06
65#define CMD_DEVICE_ID_READ 0x07
66#define CMD_BLOCK_ERASE 0x08
67#define CMD_FLASH_RESET 0x09
68#define CMD_BLOCKS_LOCK 0x0a
69#define CMD_BLOCKS_LOCK_DOWN 0x0b
70#define CMD_BLOCKS_UNLOCK 0x0c
71#define CMD_READ_BLOCKS_LOCK_STATUS 0x0d
72#define CMD_PARAMETER_READ 0x0e
73#define CMD_PARAMETER_CHANGE_COL 0x0f
74#define CMD_LOW_LEVEL_OP 0x10
75
76struct brcm_nand_dma_desc {
77 u32 next_desc;
78 u32 next_desc_ext;
79 u32 cmd_irq;
80 u32 dram_addr;
81 u32 dram_addr_ext;
82 u32 tfr_len;
83 u32 total_len;
84 u32 flash_addr;
85 u32 flash_addr_ext;
86 u32 cs;
87 u32 pad2[5];
88 u32 status_valid;
89} __packed;
90
91/* Bitfields for brcm_nand_dma_desc::status_valid */
92#define FLASH_DMA_ECC_ERROR (1 << 8)
93#define FLASH_DMA_CORR_ERROR (1 << 9)
94
95/* 512B flash cache in the NAND controller HW */
96#define FC_SHIFT 9U
97#define FC_BYTES 512U
98#define FC_WORDS (FC_BYTES >> 2)
99
100#define BRCMNAND_MIN_PAGESIZE 512
101#define BRCMNAND_MIN_BLOCKSIZE (8 * 1024)
102#define BRCMNAND_MIN_DEVSIZE (4ULL * 1024 * 1024)
103
104/* Controller feature flags */
105enum {
106 BRCMNAND_HAS_1K_SECTORS = BIT(0),
107 BRCMNAND_HAS_PREFETCH = BIT(1),
108 BRCMNAND_HAS_CACHE_MODE = BIT(2),
109 BRCMNAND_HAS_WP = BIT(3),
110};
111
112struct brcmnand_controller {
113 struct device *dev;
114 struct nand_hw_control controller;
115 void __iomem *nand_base;
116 void __iomem *nand_fc; /* flash cache */
117 void __iomem *flash_dma_base;
118 unsigned int irq;
119 unsigned int dma_irq;
120 int nand_version;
121
c26211d3
BN		 122 /* Some SoCs provide custom interrupt status register(s) */
123 struct brcmnand_soc *soc;
124
27c5b17c
BN		 125 int cmd_pending;
126 bool dma_pending;
127 struct completion done;
128 struct completion dma_done;
129
130 /* List of NAND hosts (one for each chip-select) */
131 struct list_head host_list;
132
133 struct brcm_nand_dma_desc *dma_desc;
134 dma_addr_t dma_pa;
135
136 /* in-memory cache of the FLASH_CACHE, used only for some commands */
137 u32 flash_cache[FC_WORDS];
138
139 /* Controller revision details */
140 const u16 *reg_offsets;
141 unsigned int reg_spacing; /* between CS1, CS2, ... regs */
142 const u8 *cs_offsets; /* within each chip-select */
143 const u8 *cs0_offsets; /* within CS0, if different */
144 unsigned int max_block_size;
145 const unsigned int *block_sizes;
146 unsigned int max_page_size;
147 const unsigned int *page_sizes;
148 unsigned int max_oob;
149 u32 features;
150
151 /* for low-power standby/resume only */
152 u32 nand_cs_nand_select;
153 u32 nand_cs_nand_xor;
154 u32 corr_stat_threshold;
155 u32 flash_dma_mode;
156};
157
158struct brcmnand_cfg {
159 u64 device_size;
160 unsigned int block_size;
161 unsigned int page_size;
162 unsigned int spare_area_size;
163 unsigned int device_width;
164 unsigned int col_adr_bytes;
165 unsigned int blk_adr_bytes;
166 unsigned int ful_adr_bytes;
167 unsigned int sector_size_1k;
168 unsigned int ecc_level;
169 /* use for low-power standby/resume only */
170 u32 acc_control;
171 u32 config;
172 u32 config_ext;
173 u32 timing_1;
174 u32 timing_2;
175};
176
177struct brcmnand_host {
178 struct list_head node;
179 struct device_node *of_node;
180
181 struct nand_chip chip;
182 struct mtd_info mtd;
183 struct platform_device *pdev;
184 int cs;
185
186 unsigned int last_cmd;
187 unsigned int last_byte;
188 u64 last_addr;
189 struct brcmnand_cfg hwcfg;
190 struct brcmnand_controller *ctrl;
191};
192
193enum brcmnand_reg {
194 BRCMNAND_CMD_START = 0,
195 BRCMNAND_CMD_EXT_ADDRESS,
196 BRCMNAND_CMD_ADDRESS,
197 BRCMNAND_INTFC_STATUS,
198 BRCMNAND_CS_SELECT,
199 BRCMNAND_CS_XOR,
200 BRCMNAND_LL_OP,
201 BRCMNAND_CS0_BASE,
202 BRCMNAND_CS1_BASE, /* CS1 regs, if non-contiguous */
203 BRCMNAND_CORR_THRESHOLD,
204 BRCMNAND_CORR_THRESHOLD_EXT,
205 BRCMNAND_UNCORR_COUNT,
206 BRCMNAND_CORR_COUNT,
207 BRCMNAND_CORR_EXT_ADDR,
208 BRCMNAND_CORR_ADDR,
209 BRCMNAND_UNCORR_EXT_ADDR,
210 BRCMNAND_UNCORR_ADDR,
211 BRCMNAND_SEMAPHORE,
212 BRCMNAND_ID,
213 BRCMNAND_ID_EXT,
214 BRCMNAND_LL_RDATA,
215 BRCMNAND_OOB_READ_BASE,
216 BRCMNAND_OOB_READ_10_BASE, /* offset 0x10, if non-contiguous */
217 BRCMNAND_OOB_WRITE_BASE,
218 BRCMNAND_OOB_WRITE_10_BASE, /* offset 0x10, if non-contiguous */
219 BRCMNAND_FC_BASE,
220};
221
222/* BRCMNAND v4.0 */
223static const u16 brcmnand_regs_v40[] = {
224 [BRCMNAND_CMD_START] = 0x04,
225 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
226 [BRCMNAND_CMD_ADDRESS] = 0x0c,
227 [BRCMNAND_INTFC_STATUS] = 0x6c,
228 [BRCMNAND_CS_SELECT] = 0x14,
229 [BRCMNAND_CS_XOR] = 0x18,
230 [BRCMNAND_LL_OP] = 0x178,
231 [BRCMNAND_CS0_BASE] = 0x40,
232 [BRCMNAND_CS1_BASE] = 0xd0,
233 [BRCMNAND_CORR_THRESHOLD] = 0x84,
234 [BRCMNAND_CORR_THRESHOLD_EXT] = 0,
235 [BRCMNAND_UNCORR_COUNT] = 0,
236 [BRCMNAND_CORR_COUNT] = 0,
237 [BRCMNAND_CORR_EXT_ADDR] = 0x70,
238 [BRCMNAND_CORR_ADDR] = 0x74,
239 [BRCMNAND_UNCORR_EXT_ADDR] = 0x78,
240 [BRCMNAND_UNCORR_ADDR] = 0x7c,
241 [BRCMNAND_SEMAPHORE] = 0x58,
242 [BRCMNAND_ID] = 0x60,
243 [BRCMNAND_ID_EXT] = 0x64,
244 [BRCMNAND_LL_RDATA] = 0x17c,
245 [BRCMNAND_OOB_READ_BASE] = 0x20,
246 [BRCMNAND_OOB_READ_10_BASE] = 0x130,
247 [BRCMNAND_OOB_WRITE_BASE] = 0x30,
248 [BRCMNAND_OOB_WRITE_10_BASE] = 0,
249 [BRCMNAND_FC_BASE] = 0x200,
250};
251
252/* BRCMNAND v5.0 */
253static const u16 brcmnand_regs_v50[] = {
254 [BRCMNAND_CMD_START] = 0x04,
255 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
256 [BRCMNAND_CMD_ADDRESS] = 0x0c,
257 [BRCMNAND_INTFC_STATUS] = 0x6c,
258 [BRCMNAND_CS_SELECT] = 0x14,
259 [BRCMNAND_CS_XOR] = 0x18,
260 [BRCMNAND_LL_OP] = 0x178,
261 [BRCMNAND_CS0_BASE] = 0x40,
262 [BRCMNAND_CS1_BASE] = 0xd0,
263 [BRCMNAND_CORR_THRESHOLD] = 0x84,
264 [BRCMNAND_CORR_THRESHOLD_EXT] = 0,
265 [BRCMNAND_UNCORR_COUNT] = 0,
266 [BRCMNAND_CORR_COUNT] = 0,
267 [BRCMNAND_CORR_EXT_ADDR] = 0x70,
268 [BRCMNAND_CORR_ADDR] = 0x74,
269 [BRCMNAND_UNCORR_EXT_ADDR] = 0x78,
270 [BRCMNAND_UNCORR_ADDR] = 0x7c,
271 [BRCMNAND_SEMAPHORE] = 0x58,
272 [BRCMNAND_ID] = 0x60,
273 [BRCMNAND_ID_EXT] = 0x64,
274 [BRCMNAND_LL_RDATA] = 0x17c,
275 [BRCMNAND_OOB_READ_BASE] = 0x20,
276 [BRCMNAND_OOB_READ_10_BASE] = 0x130,
277 [BRCMNAND_OOB_WRITE_BASE] = 0x30,
278 [BRCMNAND_OOB_WRITE_10_BASE] = 0x140,
279 [BRCMNAND_FC_BASE] = 0x200,
280};
281
282/* BRCMNAND v6.0 - v7.1 */
283static const u16 brcmnand_regs_v60[] = {
284 [BRCMNAND_CMD_START] = 0x04,
285 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
286 [BRCMNAND_CMD_ADDRESS] = 0x0c,
287 [BRCMNAND_INTFC_STATUS] = 0x14,
288 [BRCMNAND_CS_SELECT] = 0x18,
289 [BRCMNAND_CS_XOR] = 0x1c,
290 [BRCMNAND_LL_OP] = 0x20,
291 [BRCMNAND_CS0_BASE] = 0x50,
292 [BRCMNAND_CS1_BASE] = 0,
293 [BRCMNAND_CORR_THRESHOLD] = 0xc0,
294 [BRCMNAND_CORR_THRESHOLD_EXT] = 0xc4,
295 [BRCMNAND_UNCORR_COUNT] = 0xfc,
296 [BRCMNAND_CORR_COUNT] = 0x100,
297 [BRCMNAND_CORR_EXT_ADDR] = 0x10c,
298 [BRCMNAND_CORR_ADDR] = 0x110,
299 [BRCMNAND_UNCORR_EXT_ADDR] = 0x114,
300 [BRCMNAND_UNCORR_ADDR] = 0x118,
301 [BRCMNAND_SEMAPHORE] = 0x150,
302 [BRCMNAND_ID] = 0x194,
303 [BRCMNAND_ID_EXT] = 0x198,
304 [BRCMNAND_LL_RDATA] = 0x19c,
305 [BRCMNAND_OOB_READ_BASE] = 0x200,
306 [BRCMNAND_OOB_READ_10_BASE] = 0,
307 [BRCMNAND_OOB_WRITE_BASE] = 0x280,
308 [BRCMNAND_OOB_WRITE_10_BASE] = 0,
309 [BRCMNAND_FC_BASE] = 0x400,
310};
311
312enum brcmnand_cs_reg {
313 BRCMNAND_CS_CFG_EXT = 0,
314 BRCMNAND_CS_CFG,
315 BRCMNAND_CS_ACC_CONTROL,
316 BRCMNAND_CS_TIMING1,
317 BRCMNAND_CS_TIMING2,
318};
319
320/* Per chip-select offsets for v7.1 */
321static const u8 brcmnand_cs_offsets_v71[] = {
322 [BRCMNAND_CS_ACC_CONTROL] = 0x00,
323 [BRCMNAND_CS_CFG_EXT] = 0x04,
324 [BRCMNAND_CS_CFG] = 0x08,
325 [BRCMNAND_CS_TIMING1] = 0x0c,
326 [BRCMNAND_CS_TIMING2] = 0x10,
327};
328
329/* Per chip-select offsets for pre v7.1, except CS0 on <= v5.0 */
330static const u8 brcmnand_cs_offsets[] = {
331 [BRCMNAND_CS_ACC_CONTROL] = 0x00,
332 [BRCMNAND_CS_CFG_EXT] = 0x04,
333 [BRCMNAND_CS_CFG] = 0x04,
334 [BRCMNAND_CS_TIMING1] = 0x08,
335 [BRCMNAND_CS_TIMING2] = 0x0c,
336};
337
338/* Per chip-select offset for <= v5.0 on CS0 only */
339static const u8 brcmnand_cs_offsets_cs0[] = {
340 [BRCMNAND_CS_ACC_CONTROL] = 0x00,
341 [BRCMNAND_CS_CFG_EXT] = 0x08,
342 [BRCMNAND_CS_CFG] = 0x08,
343 [BRCMNAND_CS_TIMING1] = 0x10,
344 [BRCMNAND_CS_TIMING2] = 0x14,
345};
346
347/* BRCMNAND_INTFC_STATUS */
348enum {
349 INTFC_FLASH_STATUS = GENMASK(7, 0),
350
351 INTFC_ERASED = BIT(27),
352 INTFC_OOB_VALID = BIT(28),
353 INTFC_CACHE_VALID = BIT(29),
354 INTFC_FLASH_READY = BIT(30),
355 INTFC_CTLR_READY = BIT(31),
356};
357
358static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs)
359{
360 return brcmnand_readl(ctrl->nand_base + offs);
361}
362
363static inline void nand_writereg(struct brcmnand_controller *ctrl, u32 offs,
364 u32 val)
365{
366 brcmnand_writel(val, ctrl->nand_base + offs);
367}
368
369static int brcmnand_revision_init(struct brcmnand_controller *ctrl)
370{
371 static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 };
372 static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 };
373 static const unsigned int page_sizes[] = { 512, 2048, 4096, 8192, 0 };
374
375 ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff;
376
377 /* Only support v4.0+? */
378 if (ctrl->nand_version < 0x0400) {
379 dev_err(ctrl->dev, "version %#x not supported\n",
380 ctrl->nand_version);
381 return -ENODEV;
382 }
383
384 /* Register offsets */
385 if (ctrl->nand_version >= 0x0600)
386 ctrl->reg_offsets = brcmnand_regs_v60;
387 else if (ctrl->nand_version >= 0x0500)
388 ctrl->reg_offsets = brcmnand_regs_v50;
389 else if (ctrl->nand_version >= 0x0400)
390 ctrl->reg_offsets = brcmnand_regs_v40;
391
392 /* Chip-select stride */
393 if (ctrl->nand_version >= 0x0701)
394 ctrl->reg_spacing = 0x14;
395 else
396 ctrl->reg_spacing = 0x10;
397
398 /* Per chip-select registers */
399 if (ctrl->nand_version >= 0x0701) {
400 ctrl->cs_offsets = brcmnand_cs_offsets_v71;
401 } else {
402 ctrl->cs_offsets = brcmnand_cs_offsets;
403
404 /* v5.0 and earlier has a different CS0 offset layout */
405 if (ctrl->nand_version <= 0x0500)
406 ctrl->cs0_offsets = brcmnand_cs_offsets_cs0;
407 }
408
409 /* Page / block sizes */
410 if (ctrl->nand_version >= 0x0701) {
411 /* >= v7.1 use nice power-of-2 values! */
412 ctrl->max_page_size = 16 * 1024;
413 ctrl->max_block_size = 2 * 1024 * 1024;
414 } else {
415 ctrl->page_sizes = page_sizes;
416 if (ctrl->nand_version >= 0x0600)
417 ctrl->block_sizes = block_sizes_v6;
418 else
419 ctrl->block_sizes = block_sizes_v4;
420
421 if (ctrl->nand_version < 0x0400) {
422 ctrl->max_page_size = 4096;
423 ctrl->max_block_size = 512 * 1024;
424 }
425 }
426
427 /* Maximum spare area sector size (per 512B) */
428 if (ctrl->nand_version >= 0x0600)
429 ctrl->max_oob = 64;
430 else if (ctrl->nand_version >= 0x0500)
431 ctrl->max_oob = 32;
432 else
433 ctrl->max_oob = 16;
434
435 /* v6.0 and newer (except v6.1) have prefetch support */
436 if (ctrl->nand_version >= 0x0600 && ctrl->nand_version != 0x0601)
437 ctrl->features |= BRCMNAND_HAS_PREFETCH;
438
439 /*
440 * v6.x has cache mode, but it's implemented differently. Ignore it for
441 * now.
442 */
443 if (ctrl->nand_version >= 0x0700)
444 ctrl->features |= BRCMNAND_HAS_CACHE_MODE;
445
446 if (ctrl->nand_version >= 0x0500)
447 ctrl->features |= BRCMNAND_HAS_1K_SECTORS;
448
449 if (ctrl->nand_version >= 0x0700)
450 ctrl->features |= BRCMNAND_HAS_WP;
451 else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp"))
452 ctrl->features |= BRCMNAND_HAS_WP;
453
454 return 0;
455}
456
457static inline u32 brcmnand_read_reg(struct brcmnand_controller *ctrl,
458 enum brcmnand_reg reg)
459{
460 u16 offs = ctrl->reg_offsets[reg];
461
462 if (offs)
463 return nand_readreg(ctrl, offs);
464 else
465 return 0;
466}
467
468static inline void brcmnand_write_reg(struct brcmnand_controller *ctrl,
469 enum brcmnand_reg reg, u32 val)
470{
471 u16 offs = ctrl->reg_offsets[reg];
472
473 if (offs)
474 nand_writereg(ctrl, offs, val);
475}
476
477static inline void brcmnand_rmw_reg(struct brcmnand_controller *ctrl,
478 enum brcmnand_reg reg, u32 mask, unsigned
479 int shift, u32 val)
480{
481 u32 tmp = brcmnand_read_reg(ctrl, reg);
482
483 tmp &= ~mask;
484 tmp |= val << shift;
485 brcmnand_write_reg(ctrl, reg, tmp);
486}
487
488static inline u32 brcmnand_read_fc(struct brcmnand_controller *ctrl, int word)
489{
490 return __raw_readl(ctrl->nand_fc + word * 4);
491}
492
493static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl,
494 int word, u32 val)
495{
496 __raw_writel(val, ctrl->nand_fc + word * 4);
497}
498
499static inline u16 brcmnand_cs_offset(struct brcmnand_controller *ctrl, int cs,
500 enum brcmnand_cs_reg reg)
501{
502 u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE];
503 u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE];
504 u8 cs_offs;
505
506 if (cs == 0 && ctrl->cs0_offsets)
507 cs_offs = ctrl->cs0_offsets[reg];
508 else
509 cs_offs = ctrl->cs_offsets[reg];
510
511 if (cs && offs_cs1)
512 return offs_cs1 + (cs - 1) * ctrl->reg_spacing + cs_offs;
513
514 return offs_cs0 + cs * ctrl->reg_spacing + cs_offs;
515}
516
517static inline u32 brcmnand_count_corrected(struct brcmnand_controller *ctrl)
518{
519 if (ctrl->nand_version < 0x0600)
520 return 1;
521 return brcmnand_read_reg(ctrl, BRCMNAND_CORR_COUNT);
522}
523
524static void brcmnand_wr_corr_thresh(struct brcmnand_host *host, u8 val)
525{
526 struct brcmnand_controller *ctrl = host->ctrl;
527 unsigned int shift = 0, bits;
528 enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD;
529 int cs = host->cs;
530
531 if (ctrl->nand_version >= 0x0600)
532 bits = 6;
533 else if (ctrl->nand_version >= 0x0500)
534 bits = 5;
535 else
536 bits = 4;
537
538 if (ctrl->nand_version >= 0x0600) {
539 if (cs >= 5)
540 reg = BRCMNAND_CORR_THRESHOLD_EXT;
541 shift = (cs % 5) * bits;
542 }
543 brcmnand_rmw_reg(ctrl, reg, (bits - 1) << shift, shift, val);
544}
545
546static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl)
547{
548 if (ctrl->nand_version < 0x0700)
549 return 24;
550 return 0;
551}
552
553/***********************************************************************
554 * NAND ACC CONTROL bitfield
555 *
556 * Some bits have remained constant throughout hardware revision, while
557 * others have shifted around.
558 ***********************************************************************/
559
560/* Constant for all versions (where supported) */
561enum {
562 /* See BRCMNAND_HAS_CACHE_MODE */
563 ACC_CONTROL_CACHE_MODE = BIT(22),
564
565 /* See BRCMNAND_HAS_PREFETCH */
566 ACC_CONTROL_PREFETCH = BIT(23),
567
568 ACC_CONTROL_PAGE_HIT = BIT(24),
569 ACC_CONTROL_WR_PREEMPT = BIT(25),
570 ACC_CONTROL_PARTIAL_PAGE = BIT(26),
571 ACC_CONTROL_RD_ERASED = BIT(27),
572 ACC_CONTROL_FAST_PGM_RDIN = BIT(28),
573 ACC_CONTROL_WR_ECC = BIT(30),
574 ACC_CONTROL_RD_ECC = BIT(31),
575};
576
577static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl)
578{
579 if (ctrl->nand_version >= 0x0600)
580 return GENMASK(6, 0);
581 else
582 return GENMASK(5, 0);
583}
584
585#define NAND_ACC_CONTROL_ECC_SHIFT 16
586
587static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl)
588{
589 u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f;
590
591 return mask << NAND_ACC_CONTROL_ECC_SHIFT;
592}
593
594static void brcmnand_set_ecc_enabled(struct brcmnand_host *host, int en)
595{
596 struct brcmnand_controller *ctrl = host->ctrl;
597 u16 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
598 u32 acc_control = nand_readreg(ctrl, offs);
599 u32 ecc_flags = ACC_CONTROL_WR_ECC | ACC_CONTROL_RD_ECC;
600
601 if (en) {
602 acc_control |= ecc_flags; /* enable RD/WR ECC */
603 acc_control |= host->hwcfg.ecc_level
604 << NAND_ACC_CONTROL_ECC_SHIFT;
605 } else {
606 acc_control &= ~ecc_flags; /* disable RD/WR ECC */
607 acc_control &= ~brcmnand_ecc_level_mask(ctrl);
608 }
609
610 nand_writereg(ctrl, offs, acc_control);
611}
612
613static inline int brcmnand_sector_1k_shift(struct brcmnand_controller *ctrl)
614{
615 if (ctrl->nand_version >= 0x0600)
616 return 7;
617 else if (ctrl->nand_version >= 0x0500)
618 return 6;
619 else
620 return -1;
621}
622
623static int brcmnand_get_sector_size_1k(struct brcmnand_host *host)
624{
625 struct brcmnand_controller *ctrl = host->ctrl;
626 int shift = brcmnand_sector_1k_shift(ctrl);
627 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
628 BRCMNAND_CS_ACC_CONTROL);
629
630 if (shift < 0)
631 return 0;
632
633 return (nand_readreg(ctrl, acc_control_offs) >> shift) & 0x1;
634}
635
636static void brcmnand_set_sector_size_1k(struct brcmnand_host *host, int val)
637{
638 struct brcmnand_controller *ctrl = host->ctrl;
639 int shift = brcmnand_sector_1k_shift(ctrl);
640 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
641 BRCMNAND_CS_ACC_CONTROL);
642 u32 tmp;
643
644 if (shift < 0)
645 return;
646
647 tmp = nand_readreg(ctrl, acc_control_offs);
648 tmp &= ~(1 << shift);
649 tmp |= (!!val) << shift;
650 nand_writereg(ctrl, acc_control_offs, tmp);
651}
652
653/***********************************************************************
654 * CS_NAND_SELECT
655 ***********************************************************************/
656
657enum {
658 CS_SELECT_NAND_WP = BIT(29),
659 CS_SELECT_AUTO_DEVICE_ID_CFG = BIT(30),
660};
661
662static inline void brcmnand_set_wp(struct brcmnand_controller *ctrl, bool en)
663{
664 u32 val = en ? CS_SELECT_NAND_WP : 0;
665
666 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, CS_SELECT_NAND_WP, 0, val);
667}
668
669/***********************************************************************
670 * Flash DMA
671 ***********************************************************************/
672
673enum flash_dma_reg {
674 FLASH_DMA_REVISION = 0x00,
675 FLASH_DMA_FIRST_DESC = 0x04,
676 FLASH_DMA_FIRST_DESC_EXT = 0x08,
677 FLASH_DMA_CTRL = 0x0c,
678 FLASH_DMA_MODE = 0x10,
679 FLASH_DMA_STATUS = 0x14,
680 FLASH_DMA_INTERRUPT_DESC = 0x18,
681 FLASH_DMA_INTERRUPT_DESC_EXT = 0x1c,
682 FLASH_DMA_ERROR_STATUS = 0x20,
683 FLASH_DMA_CURRENT_DESC = 0x24,
684 FLASH_DMA_CURRENT_DESC_EXT = 0x28,
685};
686
687static inline bool has_flash_dma(struct brcmnand_controller *ctrl)
688{
689 return ctrl->flash_dma_base;
690}
691
692static inline bool flash_dma_buf_ok(const void *buf)
693{
694 return buf && !is_vmalloc_addr(buf) &&
695 likely(IS_ALIGNED((uintptr_t)buf, 4));
696}
697
698static inline void flash_dma_writel(struct brcmnand_controller *ctrl, u8 offs,
699 u32 val)
700{
701 brcmnand_writel(val, ctrl->flash_dma_base + offs);
702}
703
704static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl, u8 offs)
705{
706 return brcmnand_readl(ctrl->flash_dma_base + offs);
707}
708
709/* Low-level operation types: command, address, write, or read */
710enum brcmnand_llop_type {
711 LL_OP_CMD,
712 LL_OP_ADDR,
713 LL_OP_WR,
714 LL_OP_RD,
715};
716
717/***********************************************************************
718 * Internal support functions
719 ***********************************************************************/
720
721static inline bool is_hamming_ecc(struct brcmnand_cfg *cfg)
722{
723 return cfg->sector_size_1k == 0 && cfg->spare_area_size == 16 &&
724 cfg->ecc_level == 15;
725}
726
727/*
728 * Returns a nand_ecclayout strucutre for the given layout/configuration.
729 * Returns NULL on failure.
730 */
731static struct nand_ecclayout *brcmnand_create_layout(int ecc_level,
732 struct brcmnand_host *host)
733{
734 struct brcmnand_cfg *cfg = &host->hwcfg;
735 int i, j;
736 struct nand_ecclayout *layout;
737 int req;
738 int sectors;
739 int sas;
740 int idx1, idx2;
741
742 layout = devm_kzalloc(&host->pdev->dev, sizeof(*layout), GFP_KERNEL);
743 if (!layout)
744 return NULL;
745
746 sectors = cfg->page_size / (512 << cfg->sector_size_1k);
747 sas = cfg->spare_area_size << cfg->sector_size_1k;
748
749 /* Hamming */
750 if (is_hamming_ecc(cfg)) {
751 for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) {
752 /* First sector of each page may have BBI */
753 if (i == 0) {
754 layout->oobfree[idx2].offset = i * sas + 1;
755 /* Small-page NAND use byte 6 for BBI */
756 if (cfg->page_size == 512)
757 layout->oobfree[idx2].offset--;
758 layout->oobfree[idx2].length = 5;
759 } else {
760 layout->oobfree[idx2].offset = i * sas;
761 layout->oobfree[idx2].length = 6;
762 }
763 idx2++;
764 layout->eccpos[idx1++] = i * sas + 6;
765 layout->eccpos[idx1++] = i * sas + 7;
766 layout->eccpos[idx1++] = i * sas + 8;
767 layout->oobfree[idx2].offset = i * sas + 9;
768 layout->oobfree[idx2].length = 7;
769 idx2++;
770 /* Leave zero-terminated entry for OOBFREE */
771 if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE ||
772 idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1)
773 break;
774 }
775 goto out;
776 }
777
778 /*
779 * CONTROLLER_VERSION:
780 * < v5.0: ECC_REQ = ceil(BCH_T * 13/8)
781 * >= v5.0: ECC_REQ = ceil(BCH_T * 14/8)
782 * But we will just be conservative.
783 */
784 req = DIV_ROUND_UP(ecc_level * 14, 8);
785 if (req >= sas) {
786 dev_err(&host->pdev->dev,
787 "error: ECC too large for OOB (ECC bytes %d, spare sector %d)\n",
788 req, sas);
789 return NULL;
790 }
791
792 layout->eccbytes = req * sectors;
793 for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) {
794 for (j = sas - req; j < sas && idx1 <
795 MTD_MAX_ECCPOS_ENTRIES_LARGE; j++, idx1++)
796 layout->eccpos[idx1] = i * sas + j;
797
798 /* First sector of each page may have BBI */
799 if (i == 0) {
800 if (cfg->page_size == 512 && (sas - req >= 6)) {
801 /* Small-page NAND use byte 6 for BBI */
802 layout->oobfree[idx2].offset = 0;
803 layout->oobfree[idx2].length = 5;
804 idx2++;
805 if (sas - req > 6) {
806 layout->oobfree[idx2].offset = 6;
807 layout->oobfree[idx2].length =
808 sas - req - 6;
809 idx2++;
810 }
811 } else if (sas > req + 1) {
812 layout->oobfree[idx2].offset = i * sas + 1;
813 layout->oobfree[idx2].length = sas - req - 1;
814 idx2++;
815 }
816 } else if (sas > req) {
817 layout->oobfree[idx2].offset = i * sas;
818 layout->oobfree[idx2].length = sas - req;
819 idx2++;
820 }
821 /* Leave zero-terminated entry for OOBFREE */
822 if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE ||
823 idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1)
824 break;
825 }
826out:
827 /* Sum available OOB */
828 for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE; i++)
829 layout->oobavail += layout->oobfree[i].length;
830 return layout;
831}
832
833static struct nand_ecclayout *brcmstb_choose_ecc_layout(
834 struct brcmnand_host *host)
835{
836 struct nand_ecclayout *layout;
837 struct brcmnand_cfg *p = &host->hwcfg;
838 unsigned int ecc_level = p->ecc_level;
839
840 if (p->sector_size_1k)
841 ecc_level <<= 1;
842
843 layout = brcmnand_create_layout(ecc_level, host);
844 if (!layout) {
845 dev_err(&host->pdev->dev,
846 "no proper ecc_layout for this NAND cfg\n");
847 return NULL;
848 }
849
850 return layout;
851}
852
853static void brcmnand_wp(struct mtd_info *mtd, int wp)
854{
855 struct nand_chip *chip = mtd->priv;
856 struct brcmnand_host *host = chip->priv;
857 struct brcmnand_controller *ctrl = host->ctrl;
858
859 if ((ctrl->features & BRCMNAND_HAS_WP) && wp_on == 1) {
860 static int old_wp = -1;
861
862 if (old_wp != wp) {
863 dev_dbg(ctrl->dev, "WP %s\n", wp ? "on" : "off");
864 old_wp = wp;
865 }
866 brcmnand_set_wp(ctrl, wp);
867 }
868}
869
870/* Helper functions for reading and writing OOB registers */
871static inline u8 oob_reg_read(struct brcmnand_controller *ctrl, u32 offs)
872{
873 u16 offset0, offset10, reg_offs;
874
875 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE];
876 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_READ_10_BASE];
877
878 if (offs >= ctrl->max_oob)
879 return 0x77;
880
881 if (offs >= 16 && offset10)
882 reg_offs = offset10 + ((offs - 0x10) & ~0x03);
883 else
884 reg_offs = offset0 + (offs & ~0x03);
885
886 return nand_readreg(ctrl, reg_offs) >> (24 - ((offs & 0x03) << 3));
887}
888
889static inline void oob_reg_write(struct brcmnand_controller *ctrl, u32 offs,
890 u32 data)
891{
892 u16 offset0, offset10, reg_offs;
893
894 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_BASE];
895 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_10_BASE];
896
897 if (offs >= ctrl->max_oob)
898 return;
899
900 if (offs >= 16 && offset10)
901 reg_offs = offset10 + ((offs - 0x10) & ~0x03);
902 else
903 reg_offs = offset0 + (offs & ~0x03);
904
905 nand_writereg(ctrl, reg_offs, data);
906}
907
908/*
909 * read_oob_from_regs - read data from OOB registers
910 * @ctrl: NAND controller
911 * @i: sub-page sector index
912 * @oob: buffer to read to
913 * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
914 * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
915 */
916static int read_oob_from_regs(struct brcmnand_controller *ctrl, int i, u8 *oob,
917 int sas, int sector_1k)
918{
919 int tbytes = sas << sector_1k;
920 int j;
921
922 /* Adjust OOB values for 1K sector size */
923 if (sector_1k && (i & 0x01))
924 tbytes = max(0, tbytes - (int)ctrl->max_oob);
925 tbytes = min_t(int, tbytes, ctrl->max_oob);
926
927 for (j = 0; j < tbytes; j++)
928 oob[j] = oob_reg_read(ctrl, j);
929 return tbytes;
930}
931
932/*
933 * write_oob_to_regs - write data to OOB registers
934 * @i: sub-page sector index
935 * @oob: buffer to write from
936 * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
937 * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
938 */
939static int write_oob_to_regs(struct brcmnand_controller *ctrl, int i,
940 const u8 *oob, int sas, int sector_1k)
941{
942 int tbytes = sas << sector_1k;
943 int j;
944
945 /* Adjust OOB values for 1K sector size */
946 if (sector_1k && (i & 0x01))
947 tbytes = max(0, tbytes - (int)ctrl->max_oob);
948 tbytes = min_t(int, tbytes, ctrl->max_oob);
949
950 for (j = 0; j < tbytes; j += 4)
951 oob_reg_write(ctrl, j,
952 (oob[j + 0] << 24) |
953 (oob[j + 1] << 16) |
954 (oob[j + 2] << 8) |
955 (oob[j + 3] << 0));
956 return tbytes;
957}
958
959static irqreturn_t brcmnand_ctlrdy_irq(int irq, void *data)
960{
961 struct brcmnand_controller *ctrl = data;
962
963 /* Discard all NAND_CTLRDY interrupts during DMA */
964 if (ctrl->dma_pending)
965 return IRQ_HANDLED;
966
967 complete(&ctrl->done);
968 return IRQ_HANDLED;
969}
970
c26211d3
BN		 971/* Handle SoC-specific interrupt hardware */
972static irqreturn_t brcmnand_irq(int irq, void *data)
973{
974 struct brcmnand_controller *ctrl = data;
975
976 if (ctrl->soc->ctlrdy_ack(ctrl->soc))
977 return brcmnand_ctlrdy_irq(irq, data);
978
979 return IRQ_NONE;
980}
981
27c5b17c
BN		 982static irqreturn_t brcmnand_dma_irq(int irq, void *data)
983{
984 struct brcmnand_controller *ctrl = data;
985
986 complete(&ctrl->dma_done);
987
988 return IRQ_HANDLED;
989}
990
991static void brcmnand_send_cmd(struct brcmnand_host *host, int cmd)
992{
993 struct brcmnand_controller *ctrl = host->ctrl;
994 u32 intfc;
995
996 dev_dbg(ctrl->dev, "send native cmd %d addr_lo 0x%x\n", cmd,
997 brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS));
998 BUG_ON(ctrl->cmd_pending != 0);
999 ctrl->cmd_pending = cmd;
1000
1001 intfc = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS);
1002 BUG_ON(!(intfc & INTFC_CTLR_READY));
1003
1004 mb(); /* flush previous writes */
1005 brcmnand_write_reg(ctrl, BRCMNAND_CMD_START,
1006 cmd << brcmnand_cmd_shift(ctrl));
1007}
1008
1009/***********************************************************************
1010 * NAND MTD API: read/program/erase
1011 ***********************************************************************/
1012
1013static void brcmnand_cmd_ctrl(struct mtd_info *mtd, int dat,
1014 unsigned int ctrl)
1015{
1016 /* intentionally left blank */
1017}
1018
1019static int brcmnand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
1020{
1021 struct nand_chip *chip = mtd->priv;
1022 struct brcmnand_host *host = chip->priv;
1023 struct brcmnand_controller *ctrl = host->ctrl;
1024 unsigned long timeo = msecs_to_jiffies(100);
1025
1026 dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending);
1027 if (ctrl->cmd_pending &&
1028 wait_for_completion_timeout(&ctrl->done, timeo) <= 0) {
1029 u32 cmd = brcmnand_read_reg(ctrl, BRCMNAND_CMD_START)
1030 >> brcmnand_cmd_shift(ctrl);
1031
1032 dev_err_ratelimited(ctrl->dev,
1033 "timeout waiting for command %#02x\n", cmd);
1034 dev_err_ratelimited(ctrl->dev, "intfc status %08x\n",
1035 brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS));
1036 }
1037 ctrl->cmd_pending = 0;
1038 return brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
1039 INTFC_FLASH_STATUS;
1040}
1041
1042enum {
1043 LLOP_RE = BIT(16),
1044 LLOP_WE = BIT(17),
1045 LLOP_ALE = BIT(18),
1046 LLOP_CLE = BIT(19),
1047 LLOP_RETURN_IDLE = BIT(31),
1048
1049 LLOP_DATA_MASK = GENMASK(15, 0),
1050};
1051
1052static int brcmnand_low_level_op(struct brcmnand_host *host,
1053 enum brcmnand_llop_type type, u32 data,
1054 bool last_op)
1055{
1056 struct mtd_info *mtd = &host->mtd;
1057 struct nand_chip *chip = &host->chip;
1058 struct brcmnand_controller *ctrl = host->ctrl;
1059 u32 tmp;
1060
1061 tmp = data & LLOP_DATA_MASK;
1062 switch (type) {
1063 case LL_OP_CMD:
1064 tmp |= LLOP_WE | LLOP_CLE;
1065 break;
1066 case LL_OP_ADDR:
1067 /* WE | ALE */
1068 tmp |= LLOP_WE | LLOP_ALE;
1069 break;
1070 case LL_OP_WR:
1071 /* WE */
1072 tmp |= LLOP_WE;
1073 break;
1074 case LL_OP_RD:
1075 /* RE */
1076 tmp |= LLOP_RE;
1077 break;
1078 }
1079 if (last_op)
1080 /* RETURN_IDLE */
1081 tmp |= LLOP_RETURN_IDLE;
1082
1083 dev_dbg(ctrl->dev, "ll_op cmd %#x\n", tmp);
1084
1085 brcmnand_write_reg(ctrl, BRCMNAND_LL_OP, tmp);
1086 (void)brcmnand_read_reg(ctrl, BRCMNAND_LL_OP);
1087
1088 brcmnand_send_cmd(host, CMD_LOW_LEVEL_OP);
1089 return brcmnand_waitfunc(mtd, chip);
1090}
1091
1092static void brcmnand_cmdfunc(struct mtd_info *mtd, unsigned command,
1093 int column, int page_addr)
1094{
1095 struct nand_chip *chip = mtd->priv;
1096 struct brcmnand_host *host = chip->priv;
1097 struct brcmnand_controller *ctrl = host->ctrl;
1098 u64 addr = (u64)page_addr << chip->page_shift;
1099 int native_cmd = 0;
1100
1101 if (command == NAND_CMD_READID || command == NAND_CMD_PARAM ||
1102 command == NAND_CMD_RNDOUT)
1103 addr = (u64)column;
1104 /* Avoid propagating a negative, don't-care address */
1105 else if (page_addr < 0)
1106 addr = 0;
1107
1108 dev_dbg(ctrl->dev, "cmd 0x%x addr 0x%llx\n", command,
1109 (unsigned long long)addr);
1110
1111 host->last_cmd = command;
1112 host->last_byte = 0;
1113 host->last_addr = addr;
1114
1115 switch (command) {
1116 case NAND_CMD_RESET:
1117 native_cmd = CMD_FLASH_RESET;
1118 break;
1119 case NAND_CMD_STATUS:
1120 native_cmd = CMD_STATUS_READ;
1121 break;
1122 case NAND_CMD_READID:
1123 native_cmd = CMD_DEVICE_ID_READ;
1124 break;
1125 case NAND_CMD_READOOB:
1126 native_cmd = CMD_SPARE_AREA_READ;
1127 break;
1128 case NAND_CMD_ERASE1:
1129 native_cmd = CMD_BLOCK_ERASE;
1130 brcmnand_wp(mtd, 0);
1131 break;
1132 case NAND_CMD_PARAM:
1133 native_cmd = CMD_PARAMETER_READ;
1134 break;
1135 case NAND_CMD_SET_FEATURES:
1136 case NAND_CMD_GET_FEATURES:
1137 brcmnand_low_level_op(host, LL_OP_CMD, command, false);
1138 brcmnand_low_level_op(host, LL_OP_ADDR, column, false);
1139 break;
1140 case NAND_CMD_RNDOUT:
1141 native_cmd = CMD_PARAMETER_CHANGE_COL;
1142 addr &= ~((u64)(FC_BYTES - 1));
1143 /*
1144 * HW quirk: PARAMETER_CHANGE_COL requires SECTOR_SIZE_1K=0
1145 * NB: hwcfg.sector_size_1k may not be initialized yet
1146 */
1147 if (brcmnand_get_sector_size_1k(host)) {
1148 host->hwcfg.sector_size_1k =
1149 brcmnand_get_sector_size_1k(host);
1150 brcmnand_set_sector_size_1k(host, 0);
1151 }
1152 break;
1153 }
1154
1155 if (!native_cmd)
1156 return;
1157
1158 brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1159 (host->cs << 16) | ((addr >> 32) & 0xffff));
1160 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1161 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, lower_32_bits(addr));
1162 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1163
1164 brcmnand_send_cmd(host, native_cmd);
1165 brcmnand_waitfunc(mtd, chip);
1166
1167 if (native_cmd == CMD_PARAMETER_READ ||
1168 native_cmd == CMD_PARAMETER_CHANGE_COL) {
1169 int i;
c26211d3
BN		 1170
1171 brcmnand_soc_data_bus_prepare(ctrl->soc);
1172
27c5b17c
BN		 1173 /*
1174 * Must cache the FLASH_CACHE now, since changes in
1175 * SECTOR_SIZE_1K may invalidate it
1176 */
1177 for (i = 0; i < FC_WORDS; i++)
1178 ctrl->flash_cache[i] = brcmnand_read_fc(ctrl, i);
c26211d3
BN		 1179
1180 brcmnand_soc_data_bus_unprepare(ctrl->soc);
1181
27c5b17c
BN		 1182 /* Cleanup from HW quirk: restore SECTOR_SIZE_1K */
1183 if (host->hwcfg.sector_size_1k)
1184 brcmnand_set_sector_size_1k(host,
1185 host->hwcfg.sector_size_1k);
1186 }
1187
1188 /* Re-enable protection is necessary only after erase */
1189 if (command == NAND_CMD_ERASE1)
1190 brcmnand_wp(mtd, 1);
1191}
1192
1193static uint8_t brcmnand_read_byte(struct mtd_info *mtd)
1194{
1195 struct nand_chip *chip = mtd->priv;
1196 struct brcmnand_host *host = chip->priv;
1197 struct brcmnand_controller *ctrl = host->ctrl;
1198 uint8_t ret = 0;
1199 int addr, offs;
1200
1201 switch (host->last_cmd) {
1202 case NAND_CMD_READID:
1203 if (host->last_byte < 4)
1204 ret = brcmnand_read_reg(ctrl, BRCMNAND_ID) >>
1205 (24 - (host->last_byte << 3));
1206 else if (host->last_byte < 8)
1207 ret = brcmnand_read_reg(ctrl, BRCMNAND_ID_EXT) >>
1208 (56 - (host->last_byte << 3));
1209 break;
1210
1211 case NAND_CMD_READOOB:
1212 ret = oob_reg_read(ctrl, host->last_byte);
1213 break;
1214
1215 case NAND_CMD_STATUS:
1216 ret = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
1217 INTFC_FLASH_STATUS;
1218 if (wp_on) /* hide WP status */
1219 ret |= NAND_STATUS_WP;
1220 break;
1221
1222 case NAND_CMD_PARAM:
1223 case NAND_CMD_RNDOUT:
1224 addr = host->last_addr + host->last_byte;
1225 offs = addr & (FC_BYTES - 1);
1226
1227 /* At FC_BYTES boundary, switch to next column */
1228 if (host->last_byte > 0 && offs == 0)
1229 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, addr, -1);
1230
1231 ret = ctrl->flash_cache[offs >> 2] >>
1232 (24 - ((offs & 0x03) << 3));
1233 break;
1234 case NAND_CMD_GET_FEATURES:
1235 if (host->last_byte >= ONFI_SUBFEATURE_PARAM_LEN) {
1236 ret = 0;
1237 } else {
1238 bool last = host->last_byte ==
1239 ONFI_SUBFEATURE_PARAM_LEN - 1;
1240 brcmnand_low_level_op(host, LL_OP_RD, 0, last);
1241 ret = brcmnand_read_reg(ctrl, BRCMNAND_LL_RDATA) & 0xff;
1242 }
1243 }
1244
1245 dev_dbg(ctrl->dev, "read byte = 0x%02x\n", ret);
1246 host->last_byte++;
1247
1248 return ret;
1249}
1250
1251static void brcmnand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1252{
1253 int i;
1254
1255 for (i = 0; i < len; i++, buf++)
1256 *buf = brcmnand_read_byte(mtd);
1257}
1258
1259static void brcmnand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
1260 int len)
1261{
1262 int i;
1263 struct nand_chip *chip = mtd->priv;
1264 struct brcmnand_host *host = chip->priv;
1265
1266 switch (host->last_cmd) {
1267 case NAND_CMD_SET_FEATURES:
1268 for (i = 0; i < len; i++)
1269 brcmnand_low_level_op(host, LL_OP_WR, buf[i],
1270 (i + 1) == len);
1271 break;
1272 default:
1273 BUG();
1274 break;
1275 }
1276}
1277
1278/**
1279 * Construct a FLASH_DMA descriptor as part of a linked list. You must know the
1280 * following ahead of time:
1281 * - Is this descriptor the beginning or end of a linked list?
1282 * - What is the (DMA) address of the next descriptor in the linked list?
1283 */
1284static int brcmnand_fill_dma_desc(struct brcmnand_host *host,
1285 struct brcm_nand_dma_desc *desc, u64 addr,
1286 dma_addr_t buf, u32 len, u8 dma_cmd,
1287 bool begin, bool end,
1288 dma_addr_t next_desc)
1289{
1290 memset(desc, 0, sizeof(*desc));
1291 /* Descriptors are written in native byte order (wordwise) */
1292 desc->next_desc = lower_32_bits(next_desc);
1293 desc->next_desc_ext = upper_32_bits(next_desc);
1294 desc->cmd_irq = (dma_cmd << 24) |
1295 (end ? (0x03 << 8) : 0) | /* IRQ | STOP */
1296 (!!begin) | ((!!end) << 1); /* head, tail */
1297#ifdef CONFIG_CPU_BIG_ENDIAN
1298 desc->cmd_irq |= 0x01 << 12;
1299#endif
1300 desc->dram_addr = lower_32_bits(buf);
1301 desc->dram_addr_ext = upper_32_bits(buf);
1302 desc->tfr_len = len;
1303 desc->total_len = len;
1304 desc->flash_addr = lower_32_bits(addr);
1305 desc->flash_addr_ext = upper_32_bits(addr);
1306 desc->cs = host->cs;
1307 desc->status_valid = 0x01;
1308 return 0;
1309}
1310
1311/**
1312 * Kick the FLASH_DMA engine, with a given DMA descriptor
1313 */
1314static void brcmnand_dma_run(struct brcmnand_host *host, dma_addr_t desc)
1315{
1316 struct brcmnand_controller *ctrl = host->ctrl;
1317 unsigned long timeo = msecs_to_jiffies(100);
1318
1319 flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC, lower_32_bits(desc));
1320 (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC);
1321 flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT, upper_32_bits(desc));
1322 (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT);
1323
1324 /* Start FLASH_DMA engine */
1325 ctrl->dma_pending = true;
1326 mb(); /* flush previous writes */
1327 flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0x03); /* wake | run */
1328
1329 if (wait_for_completion_timeout(&ctrl->dma_done, timeo) <= 0) {
1330 dev_err(ctrl->dev,
1331 "timeout waiting for DMA; status %#x, error status %#x\n",
1332 flash_dma_readl(ctrl, FLASH_DMA_STATUS),
1333 flash_dma_readl(ctrl, FLASH_DMA_ERROR_STATUS));
1334 }
1335 ctrl->dma_pending = false;
1336 flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0); /* force stop */
1337}
1338
1339static int brcmnand_dma_trans(struct brcmnand_host *host, u64 addr, u32 *buf,
1340 u32 len, u8 dma_cmd)
1341{
1342 struct brcmnand_controller *ctrl = host->ctrl;
1343 dma_addr_t buf_pa;
1344 int dir = dma_cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1345
1346 buf_pa = dma_map_single(ctrl->dev, buf, len, dir);
1347 if (dma_mapping_error(ctrl->dev, buf_pa)) {
1348 dev_err(ctrl->dev, "unable to map buffer for DMA\n");
1349 return -ENOMEM;
1350 }
1351
1352 brcmnand_fill_dma_desc(host, ctrl->dma_desc, addr, buf_pa, len,
1353 dma_cmd, true, true, 0);
1354
1355 brcmnand_dma_run(host, ctrl->dma_pa);
1356
1357 dma_unmap_single(ctrl->dev, buf_pa, len, dir);
1358
1359 if (ctrl->dma_desc->status_valid & FLASH_DMA_ECC_ERROR)
1360 return -EBADMSG;
1361 else if (ctrl->dma_desc->status_valid & FLASH_DMA_CORR_ERROR)
1362 return -EUCLEAN;
1363
1364 return 0;
1365}
1366
1367/*
1368 * Assumes proper CS is already set
1369 */
1370static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip,
1371 u64 addr, unsigned int trans, u32 *buf,
1372 u8 *oob, u64 *err_addr)
1373{
1374 struct brcmnand_host *host = chip->priv;
1375 struct brcmnand_controller *ctrl = host->ctrl;
1376 int i, j, ret = 0;
1377
1378 /* Clear error addresses */
1379 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_ADDR, 0);
1380 brcmnand_write_reg(ctrl, BRCMNAND_CORR_ADDR, 0);
1381
1382 brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1383 (host->cs << 16) | ((addr >> 32) & 0xffff));
1384 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1385
1386 for (i = 0; i < trans; i++, addr += FC_BYTES) {
1387 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
1388 lower_32_bits(addr));
1389 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1390 /* SPARE_AREA_READ does not use ECC, so just use PAGE_READ */
1391 brcmnand_send_cmd(host, CMD_PAGE_READ);
1392 brcmnand_waitfunc(mtd, chip);
1393
c26211d3
BN		 1394 if (likely(buf)) {
1395 brcmnand_soc_data_bus_prepare(ctrl->soc);
1396
27c5b17c
BN		 1397 for (j = 0; j < FC_WORDS; j++, buf++)
1398 *buf = brcmnand_read_fc(ctrl, j);
1399
c26211d3
BN		 1400 brcmnand_soc_data_bus_unprepare(ctrl->soc);
1401 }
1402
27c5b17c
BN		 1403 if (oob)
1404 oob += read_oob_from_regs(ctrl, i, oob,
1405 mtd->oobsize / trans,
1406 host->hwcfg.sector_size_1k);
1407
1408 if (!ret) {
1409 *err_addr = brcmnand_read_reg(ctrl,
1410 BRCMNAND_UNCORR_ADDR) |
1411 ((u64)(brcmnand_read_reg(ctrl,
1412 BRCMNAND_UNCORR_EXT_ADDR)
1413 & 0xffff) << 32);
1414 if (*err_addr)
1415 ret = -EBADMSG;
1416 }
1417
1418 if (!ret) {
1419 *err_addr = brcmnand_read_reg(ctrl,
1420 BRCMNAND_CORR_ADDR) |
1421 ((u64)(brcmnand_read_reg(ctrl,
1422 BRCMNAND_CORR_EXT_ADDR)
1423 & 0xffff) << 32);
1424 if (*err_addr)
1425 ret = -EUCLEAN;
1426 }
1427 }
1428
1429 return ret;
1430}
1431
1432static int brcmnand_read(struct mtd_info *mtd, struct nand_chip *chip,
1433 u64 addr, unsigned int trans, u32 *buf, u8 *oob)
1434{
1435 struct brcmnand_host *host = chip->priv;
1436 struct brcmnand_controller *ctrl = host->ctrl;
1437 u64 err_addr = 0;
1438 int err;
1439
1440 dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf);
1441
1442 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_COUNT, 0);
1443
1444 if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
1445 err = brcmnand_dma_trans(host, addr, buf, trans * FC_BYTES,
1446 CMD_PAGE_READ);
1447 if (err) {
1448 if (mtd_is_bitflip_or_eccerr(err))
1449 err_addr = addr;
1450 else
1451 return -EIO;
1452 }
1453 } else {
1454 if (oob)
1455 memset(oob, 0x99, mtd->oobsize);
1456
1457 err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf,
1458 oob, &err_addr);
1459 }
1460
1461 if (mtd_is_eccerr(err)) {
1462 dev_dbg(ctrl->dev, "uncorrectable error at 0x%llx\n",
1463 (unsigned long long)err_addr);
1464 mtd->ecc_stats.failed++;
1465 /* NAND layer expects zero on ECC errors */
1466 return 0;
1467 }
1468
1469 if (mtd_is_bitflip(err)) {
1470 unsigned int corrected = brcmnand_count_corrected(ctrl);
1471
1472 dev_dbg(ctrl->dev, "corrected error at 0x%llx\n",
1473 (unsigned long long)err_addr);
1474 mtd->ecc_stats.corrected += corrected;
1475 /* Always exceed the software-imposed threshold */
1476 return max(mtd->bitflip_threshold, corrected);
1477 }
1478
1479 return 0;
1480}
1481
1482static int brcmnand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1483 uint8_t *buf, int oob_required, int page)
1484{
1485 struct brcmnand_host *host = chip->priv;
1486 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
1487
1488 return brcmnand_read(mtd, chip, host->last_addr,
1489 mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
1490}
1491
1492static int brcmnand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1493 uint8_t *buf, int oob_required, int page)
1494{
1495 struct brcmnand_host *host = chip->priv;
1496 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
1497 int ret;
1498
1499 brcmnand_set_ecc_enabled(host, 0);
1500 ret = brcmnand_read(mtd, chip, host->last_addr,
1501 mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
1502 brcmnand_set_ecc_enabled(host, 1);
1503 return ret;
1504}
1505
1506static int brcmnand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
1507 int page)
1508{
1509 return brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
1510 mtd->writesize >> FC_SHIFT,
1511 NULL, (u8 *)chip->oob_poi);
1512}
1513
1514static int brcmnand_read_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
1515 int page)
1516{
1517 struct brcmnand_host *host = chip->priv;
1518
1519 brcmnand_set_ecc_enabled(host, 0);
1520 brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
1521 mtd->writesize >> FC_SHIFT,
1522 NULL, (u8 *)chip->oob_poi);
1523 brcmnand_set_ecc_enabled(host, 1);
1524 return 0;
1525}
1526
1527static int brcmnand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1528 uint32_t data_offs, uint32_t readlen,
1529 uint8_t *bufpoi, int page)
1530{
1531 struct brcmnand_host *host = chip->priv;
1532
1533 return brcmnand_read(mtd, chip, host->last_addr + data_offs,
1534 readlen >> FC_SHIFT, (u32 *)bufpoi, NULL);
1535}
1536
1537static int brcmnand_write(struct mtd_info *mtd, struct nand_chip *chip,
1538 u64 addr, const u32 *buf, u8 *oob)
1539{
1540 struct brcmnand_host *host = chip->priv;
1541 struct brcmnand_controller *ctrl = host->ctrl;
1542 unsigned int i, j, trans = mtd->writesize >> FC_SHIFT;
1543 int status, ret = 0;
1544
1545 dev_dbg(ctrl->dev, "write %llx <- %p\n", (unsigned long long)addr, buf);
1546
3f08b8ba 1547 if (unlikely((unsigned long)buf & 0x03)) {
27c5b17c 1548 dev_warn(ctrl->dev, "unaligned buffer: %p\n", buf);
3f08b8ba 1549 buf = (u32 *)((unsigned long)buf & ~0x03);
27c5b17c
BN		 1550 }
1551
1552 brcmnand_wp(mtd, 0);
1553
1554 for (i = 0; i < ctrl->max_oob; i += 4)
1555 oob_reg_write(ctrl, i, 0xffffffff);
1556
1557 if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
1558 if (brcmnand_dma_trans(host, addr, (u32 *)buf,
1559 mtd->writesize, CMD_PROGRAM_PAGE))
1560 ret = -EIO;
1561 goto out;
1562 }
1563
1564 brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1565 (host->cs << 16) | ((addr >> 32) & 0xffff));
1566 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1567
1568 for (i = 0; i < trans; i++, addr += FC_BYTES) {
1569 /* full address MUST be set before populating FC */
1570 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
1571 lower_32_bits(addr));
1572 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1573
c26211d3
BN		 1574 if (buf) {
1575 brcmnand_soc_data_bus_prepare(ctrl->soc);
1576
27c5b17c
BN		 1577 for (j = 0; j < FC_WORDS; j++, buf++)
1578 brcmnand_write_fc(ctrl, j, *buf);
c26211d3
BN		 1579
1580 brcmnand_soc_data_bus_unprepare(ctrl->soc);
1581 } else if (oob) {
27c5b17c
BN		 1582 for (j = 0; j < FC_WORDS; j++)
1583 brcmnand_write_fc(ctrl, j, 0xffffffff);
c26211d3 1584 }
27c5b17c
BN		 1585
1586 if (oob) {
1587 oob += write_oob_to_regs(ctrl, i, oob,
1588 mtd->oobsize / trans,
1589 host->hwcfg.sector_size_1k);
1590 }
1591
1592 /* we cannot use SPARE_AREA_PROGRAM when PARTIAL_PAGE_EN=0 */
1593 brcmnand_send_cmd(host, CMD_PROGRAM_PAGE);
1594 status = brcmnand_waitfunc(mtd, chip);
1595
1596 if (status & NAND_STATUS_FAIL) {
1597 dev_info(ctrl->dev, "program failed at %llx\n",
1598 (unsigned long long)addr);
1599 ret = -EIO;
1600 goto out;
1601 }
1602 }
1603out:
1604 brcmnand_wp(mtd, 1);
1605 return ret;
1606}
1607
1608static int brcmnand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
45aaeff9 1609 const uint8_t *buf, int oob_required, int page)
27c5b17c
BN		 1610{
1611 struct brcmnand_host *host = chip->priv;
1612 void *oob = oob_required ? chip->oob_poi : NULL;
1613
1614 brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
1615 return 0;
1616}
1617
1618static int brcmnand_write_page_raw(struct mtd_info *mtd,
1619 struct nand_chip *chip, const uint8_t *buf,
45aaeff9 1620 int oob_required, int page)
27c5b17c
BN		 1621{
1622 struct brcmnand_host *host = chip->priv;
1623 void *oob = oob_required ? chip->oob_poi : NULL;
1624
1625 brcmnand_set_ecc_enabled(host, 0);
1626 brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
1627 brcmnand_set_ecc_enabled(host, 1);
1628 return 0;
1629}
1630
1631static int brcmnand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
1632 int page)
1633{
1634 return brcmnand_write(mtd, chip, (u64)page << chip->page_shift,
1635 NULL, chip->oob_poi);
1636}
1637
1638static int brcmnand_write_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
1639 int page)
1640{
1641 struct brcmnand_host *host = chip->priv;
1642 int ret;
1643
1644 brcmnand_set_ecc_enabled(host, 0);
1645 ret = brcmnand_write(mtd, chip, (u64)page << chip->page_shift, NULL,
1646 (u8 *)chip->oob_poi);
1647 brcmnand_set_ecc_enabled(host, 1);
1648
1649 return ret;
1650}
1651
1652/***********************************************************************
1653 * Per-CS setup (1 NAND device)
1654 ***********************************************************************/
1655
1656static int brcmnand_set_cfg(struct brcmnand_host *host,
1657 struct brcmnand_cfg *cfg)
1658{
1659 struct brcmnand_controller *ctrl = host->ctrl;
1660 struct nand_chip *chip = &host->chip;
1661 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
1662 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
1663 BRCMNAND_CS_CFG_EXT);
1664 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
1665 BRCMNAND_CS_ACC_CONTROL);
1666 u8 block_size = 0, page_size = 0, device_size = 0;
1667 u32 tmp;
1668
1669 if (ctrl->block_sizes) {
1670 int i, found;
1671
1672 for (i = 0, found = 0; ctrl->block_sizes[i]; i++)
1673 if (ctrl->block_sizes[i] * 1024 == cfg->block_size) {
1674 block_size = i;
1675 found = 1;
1676 }
1677 if (!found) {
1678 dev_warn(ctrl->dev, "invalid block size %u\n",
1679 cfg->block_size);
1680 return -EINVAL;
1681 }
1682 } else {
1683 block_size = ffs(cfg->block_size) - ffs(BRCMNAND_MIN_BLOCKSIZE);
1684 }
1685
1686 if (cfg->block_size < BRCMNAND_MIN_BLOCKSIZE || (ctrl->max_block_size &&
1687 cfg->block_size > ctrl->max_block_size)) {
1688 dev_warn(ctrl->dev, "invalid block size %u\n",
1689 cfg->block_size);
1690 block_size = 0;
1691 }
1692
1693 if (ctrl->page_sizes) {
1694 int i, found;
1695
1696 for (i = 0, found = 0; ctrl->page_sizes[i]; i++)
1697 if (ctrl->page_sizes[i] == cfg->page_size) {
1698 page_size = i;
1699 found = 1;
1700 }
1701 if (!found) {
1702 dev_warn(ctrl->dev, "invalid page size %u\n",
1703 cfg->page_size);
1704 return -EINVAL;
1705 }
1706 } else {
1707 page_size = ffs(cfg->page_size) - ffs(BRCMNAND_MIN_PAGESIZE);
1708 }
1709
1710 if (cfg->page_size < BRCMNAND_MIN_PAGESIZE || (ctrl->max_page_size &&
1711 cfg->page_size > ctrl->max_page_size)) {
1712 dev_warn(ctrl->dev, "invalid page size %u\n", cfg->page_size);
1713 return -EINVAL;
1714 }
1715
1716 if (fls64(cfg->device_size) < fls64(BRCMNAND_MIN_DEVSIZE)) {
1717 dev_warn(ctrl->dev, "invalid device size 0x%llx\n",
1718 (unsigned long long)cfg->device_size);
1719 return -EINVAL;
1720 }
1721 device_size = fls64(cfg->device_size) - fls64(BRCMNAND_MIN_DEVSIZE);
1722
1723 tmp = (cfg->blk_adr_bytes << 8) |
1724 (cfg->col_adr_bytes << 12) |
1725 (cfg->ful_adr_bytes << 16) |
1726 (!!(cfg->device_width == 16) << 23) |
1727 (device_size << 24);
1728 if (cfg_offs == cfg_ext_offs) {
1729 tmp |= (page_size << 20) | (block_size << 28);
1730 nand_writereg(ctrl, cfg_offs, tmp);
1731 } else {
1732 nand_writereg(ctrl, cfg_offs, tmp);
1733 tmp = page_size | (block_size << 4);
1734 nand_writereg(ctrl, cfg_ext_offs, tmp);
1735 }
1736
1737 tmp = nand_readreg(ctrl, acc_control_offs);
1738 tmp &= ~brcmnand_ecc_level_mask(ctrl);
1739 tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
1740 tmp &= ~brcmnand_spare_area_mask(ctrl);
1741 tmp |= cfg->spare_area_size;
1742 nand_writereg(ctrl, acc_control_offs, tmp);
1743
1744 brcmnand_set_sector_size_1k(host, cfg->sector_size_1k);
1745
1746 /* threshold = ceil(BCH-level * 0.75) */
1747 brcmnand_wr_corr_thresh(host, DIV_ROUND_UP(chip->ecc.strength * 3, 4));
1748
1749 return 0;
1750}
1751
1752static void brcmnand_print_cfg(char *buf, struct brcmnand_cfg *cfg)
1753{
1754 buf += sprintf(buf,
1755 "%lluMiB total, %uKiB blocks, %u%s pages, %uB OOB, %u-bit",
1756 (unsigned long long)cfg->device_size >> 20,
1757 cfg->block_size >> 10,
1758 cfg->page_size >= 1024 ? cfg->page_size >> 10 : cfg->page_size,
1759 cfg->page_size >= 1024 ? "KiB" : "B",
1760 cfg->spare_area_size, cfg->device_width);
1761
1762 /* Account for Hamming ECC and for BCH 512B vs 1KiB sectors */
1763 if (is_hamming_ecc(cfg))
1764 sprintf(buf, ", Hamming ECC");
1765 else if (cfg->sector_size_1k)
1766 sprintf(buf, ", BCH-%u (1KiB sector)", cfg->ecc_level << 1);
1767 else
80204124 1768 sprintf(buf, ", BCH-%u", cfg->ecc_level);
27c5b17c
BN		 1769}
1770
1771/*
1772 * Minimum number of bytes to address a page. Calculated as:
1773 * roundup(log2(size / page-size) / 8)
1774 *
1775 * NB: the following does not "round up" for non-power-of-2 'size'; but this is
1776 * OK because many other things will break if 'size' is irregular...
1777 */
1778static inline int get_blk_adr_bytes(u64 size, u32 writesize)
1779{
1780 return ALIGN(ilog2(size) - ilog2(writesize), 8) >> 3;
1781}
1782
1783static int brcmnand_setup_dev(struct brcmnand_host *host)
1784{
1785 struct mtd_info *mtd = &host->mtd;
1786 struct nand_chip *chip = &host->chip;
1787 struct brcmnand_controller *ctrl = host->ctrl;
1788 struct brcmnand_cfg *cfg = &host->hwcfg;
1789 char msg[128];
1790 u32 offs, tmp, oob_sector;
1791 int ret;
1792
1793 memset(cfg, 0, sizeof(*cfg));
1794
61528d88
MV		 1795 ret = of_property_read_u32(chip->flash_node,
1796 "brcm,nand-oob-sector-size",
27c5b17c
BN		 1797 &oob_sector);
1798 if (ret) {
1799 /* Use detected size */
1800 cfg->spare_area_size = mtd->oobsize /
1801 (mtd->writesize >> FC_SHIFT);
1802 } else {
1803 cfg->spare_area_size = oob_sector;
1804 }
1805 if (cfg->spare_area_size > ctrl->max_oob)
1806 cfg->spare_area_size = ctrl->max_oob;
1807 /*
1808 * Set oobsize to be consistent with controller's spare_area_size, as
1809 * the rest is inaccessible.
1810 */
1811 mtd->oobsize = cfg->spare_area_size * (mtd->writesize >> FC_SHIFT);
1812
1813 cfg->device_size = mtd->size;
1814 cfg->block_size = mtd->erasesize;
1815 cfg->page_size = mtd->writesize;
1816 cfg->device_width = (chip->options & NAND_BUSWIDTH_16) ? 16 : 8;
1817 cfg->col_adr_bytes = 2;
1818 cfg->blk_adr_bytes = get_blk_adr_bytes(mtd->size, mtd->writesize);
1819
1820 switch (chip->ecc.size) {
1821 case 512:
1822 if (chip->ecc.strength == 1) /* Hamming */
1823 cfg->ecc_level = 15;
1824 else
1825 cfg->ecc_level = chip->ecc.strength;
1826 cfg->sector_size_1k = 0;
1827 break;
1828 case 1024:
1829 if (!(ctrl->features & BRCMNAND_HAS_1K_SECTORS)) {
1830 dev_err(ctrl->dev, "1KB sectors not supported\n");
1831 return -EINVAL;
1832 }
1833 if (chip->ecc.strength & 0x1) {
1834 dev_err(ctrl->dev,
1835 "odd ECC not supported with 1KB sectors\n");
1836 return -EINVAL;
1837 }
1838
1839 cfg->ecc_level = chip->ecc.strength >> 1;
1840 cfg->sector_size_1k = 1;
1841 break;
1842 default:
1843 dev_err(ctrl->dev, "unsupported ECC size: %d\n",
1844 chip->ecc.size);
1845 return -EINVAL;
1846 }
1847
1848 cfg->ful_adr_bytes = cfg->blk_adr_bytes;
1849 if (mtd->writesize > 512)
1850 cfg->ful_adr_bytes += cfg->col_adr_bytes;
1851 else
1852 cfg->ful_adr_bytes += 1;
1853
1854 ret = brcmnand_set_cfg(host, cfg);
1855 if (ret)
1856 return ret;
1857
1858 brcmnand_set_ecc_enabled(host, 1);
1859
1860 brcmnand_print_cfg(msg, cfg);
1861 dev_info(ctrl->dev, "detected %s\n", msg);
1862
1863 /* Configure ACC_CONTROL */
1864 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
1865 tmp = nand_readreg(ctrl, offs);
1866 tmp &= ~ACC_CONTROL_PARTIAL_PAGE;
1867 tmp &= ~ACC_CONTROL_RD_ERASED;
1868 tmp &= ~ACC_CONTROL_FAST_PGM_RDIN;
1869 if (ctrl->features & BRCMNAND_HAS_PREFETCH) {
1870 /*
1871 * FIXME: Flash DMA + prefetch may see spurious erased-page ECC
1872 * errors
1873 */
1874 if (has_flash_dma(ctrl))
1875 tmp &= ~ACC_CONTROL_PREFETCH;
1876 else
1877 tmp |= ACC_CONTROL_PREFETCH;
1878 }
1879 nand_writereg(ctrl, offs, tmp);
1880
1881 return 0;
1882}
1883
1884static int brcmnand_init_cs(struct brcmnand_host *host)
1885{
1886 struct brcmnand_controller *ctrl = host->ctrl;
1887 struct device_node *dn = host->of_node;
1888 struct platform_device *pdev = host->pdev;
1889 struct mtd_info *mtd;
1890 struct nand_chip *chip;
5e65d48b 1891 int ret;
27c5b17c
BN		 1892 struct mtd_part_parser_data ppdata = { .of_node = dn };
1893
1894 ret = of_property_read_u32(dn, "reg", &host->cs);
1895 if (ret) {
1896 dev_err(&pdev->dev, "can't get chip-select\n");
1897 return -ENXIO;
1898 }
1899
1900 mtd = &host->mtd;
1901 chip = &host->chip;
1902
61528d88 1903 chip->flash_node = dn;
27c5b17c
BN		 1904 chip->priv = host;
1905 mtd->priv = chip;
1906 mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "brcmnand.%d",
1907 host->cs);
1908 mtd->owner = THIS_MODULE;
1909 mtd->dev.parent = &pdev->dev;
1910
1911 chip->IO_ADDR_R = (void __iomem *)0xdeadbeef;
1912 chip->IO_ADDR_W = (void __iomem *)0xdeadbeef;
1913
1914 chip->cmd_ctrl = brcmnand_cmd_ctrl;
1915 chip->cmdfunc = brcmnand_cmdfunc;
1916 chip->waitfunc = brcmnand_waitfunc;
1917 chip->read_byte = brcmnand_read_byte;
1918 chip->read_buf = brcmnand_read_buf;
1919 chip->write_buf = brcmnand_write_buf;
1920
1921 chip->ecc.mode = NAND_ECC_HW;
1922 chip->ecc.read_page = brcmnand_read_page;
1923 chip->ecc.read_subpage = brcmnand_read_subpage;
1924 chip->ecc.write_page = brcmnand_write_page;
1925 chip->ecc.read_page_raw = brcmnand_read_page_raw;
1926 chip->ecc.write_page_raw = brcmnand_write_page_raw;
1927 chip->ecc.write_oob_raw = brcmnand_write_oob_raw;
1928 chip->ecc.read_oob_raw = brcmnand_read_oob_raw;
1929 chip->ecc.read_oob = brcmnand_read_oob;
1930 chip->ecc.write_oob = brcmnand_write_oob;
1931
1932 chip->controller = &ctrl->controller;
1933
1934 if (nand_scan_ident(mtd, 1, NULL))
1935 return -ENXIO;
1936
1937 chip->options |= NAND_NO_SUBPAGE_WRITE;
1938 /*
1939 * Avoid (for instance) kmap()'d buffers from JFFS2, which we can't DMA
1940 * to/from, and have nand_base pass us a bounce buffer instead, as
1941 * needed.
1942 */
1943 chip->options |= NAND_USE_BOUNCE_BUFFER;
1944
1945 if (of_get_nand_on_flash_bbt(dn))
1946 chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
1947
1948 if (brcmnand_setup_dev(host))
1949 return -ENXIO;
1950
1951 chip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512;
1952 /* only use our internal HW threshold */
1953 mtd->bitflip_threshold = 1;
1954
1955 chip->ecc.layout = brcmstb_choose_ecc_layout(host);
1956 if (!chip->ecc.layout)
1957 return -ENXIO;
1958
1959 if (nand_scan_tail(mtd))
1960 return -ENXIO;
1961
1962 return mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
1963}
1964
1965static void brcmnand_save_restore_cs_config(struct brcmnand_host *host,
1966 int restore)
1967{
1968 struct brcmnand_controller *ctrl = host->ctrl;
1969 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
1970 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
1971 BRCMNAND_CS_CFG_EXT);
1972 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
1973 BRCMNAND_CS_ACC_CONTROL);
1974 u16 t1_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING1);
1975 u16 t2_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING2);
1976
1977 if (restore) {
1978 nand_writereg(ctrl, cfg_offs, host->hwcfg.config);
1979 if (cfg_offs != cfg_ext_offs)
1980 nand_writereg(ctrl, cfg_ext_offs,
1981 host->hwcfg.config_ext);
1982 nand_writereg(ctrl, acc_control_offs, host->hwcfg.acc_control);
1983 nand_writereg(ctrl, t1_offs, host->hwcfg.timing_1);
1984 nand_writereg(ctrl, t2_offs, host->hwcfg.timing_2);
1985 } else {
1986 host->hwcfg.config = nand_readreg(ctrl, cfg_offs);
1987 if (cfg_offs != cfg_ext_offs)
1988 host->hwcfg.config_ext =
1989 nand_readreg(ctrl, cfg_ext_offs);
1990 host->hwcfg.acc_control = nand_readreg(ctrl, acc_control_offs);
1991 host->hwcfg.timing_1 = nand_readreg(ctrl, t1_offs);
1992 host->hwcfg.timing_2 = nand_readreg(ctrl, t2_offs);
1993 }
1994}
1995
1996static int brcmnand_suspend(struct device *dev)
1997{
1998 struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
1999 struct brcmnand_host *host;
2000
2001 list_for_each_entry(host, &ctrl->host_list, node)
2002 brcmnand_save_restore_cs_config(host, 0);
2003
2004 ctrl->nand_cs_nand_select = brcmnand_read_reg(ctrl, BRCMNAND_CS_SELECT);
2005 ctrl->nand_cs_nand_xor = brcmnand_read_reg(ctrl, BRCMNAND_CS_XOR);
2006 ctrl->corr_stat_threshold =
2007 brcmnand_read_reg(ctrl, BRCMNAND_CORR_THRESHOLD);
2008
2009 if (has_flash_dma(ctrl))
2010 ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE);
2011
2012 return 0;
2013}
2014
2015static int brcmnand_resume(struct device *dev)
2016{
2017 struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
2018 struct brcmnand_host *host;
2019
2020 if (has_flash_dma(ctrl)) {
2021 flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode);
2022 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
2023 }
2024
2025 brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select);
2026 brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, ctrl->nand_cs_nand_xor);
2027 brcmnand_write_reg(ctrl, BRCMNAND_CORR_THRESHOLD,
2028 ctrl->corr_stat_threshold);
c26211d3
BN		 2029 if (ctrl->soc) {
2030 /* Clear/re-enable interrupt */
2031 ctrl->soc->ctlrdy_ack(ctrl->soc);
2032 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
2033 }
27c5b17c
BN		 2034
2035 list_for_each_entry(host, &ctrl->host_list, node) {
2036 struct mtd_info *mtd = &host->mtd;
2037 struct nand_chip *chip = mtd->priv;
2038
2039 brcmnand_save_restore_cs_config(host, 1);
2040
2041 /* Reset the chip, required by some chips after power-up */
2042 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2043 }
2044
2045 return 0;
2046}
2047
2048const struct dev_pm_ops brcmnand_pm_ops = {
2049 .suspend = brcmnand_suspend,
2050 .resume = brcmnand_resume,
2051};
2052EXPORT_SYMBOL_GPL(brcmnand_pm_ops);
2053
2054static const struct of_device_id brcmnand_of_match[] = {
2055 { .compatible = "brcm,brcmnand-v4.0" },
2056 { .compatible = "brcm,brcmnand-v5.0" },
2057 { .compatible = "brcm,brcmnand-v6.0" },
2058 { .compatible = "brcm,brcmnand-v6.1" },
2059 { .compatible = "brcm,brcmnand-v7.0" },
2060 { .compatible = "brcm,brcmnand-v7.1" },
2061 {},
2062};
2063MODULE_DEVICE_TABLE(of, brcmnand_of_match);
2064
2065/***********************************************************************
2066 * Platform driver setup (per controller)
2067 ***********************************************************************/
2068
2069int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
2070{
2071 struct device *dev = &pdev->dev;
2072 struct device_node *dn = dev->of_node, *child;
bcb83a19 2073 struct brcmnand_controller *ctrl;
27c5b17c
BN		 2074 struct resource *res;
2075 int ret;
2076
2077 /* We only support device-tree instantiation */
2078 if (!dn)
2079 return -ENODEV;
2080
2081 if (!of_match_node(brcmnand_of_match, dn))
2082 return -ENODEV;
2083
2084 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
2085 if (!ctrl)
2086 return -ENOMEM;
2087
2088 dev_set_drvdata(dev, ctrl);
2089 ctrl->dev = dev;
2090
2091 init_completion(&ctrl->done);
2092 init_completion(&ctrl->dma_done);
2093 spin_lock_init(&ctrl->controller.lock);
2094 init_waitqueue_head(&ctrl->controller.wq);
2095 INIT_LIST_HEAD(&ctrl->host_list);
2096
2097 /* NAND register range */
2098 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2099 ctrl->nand_base = devm_ioremap_resource(dev, res);
2100 if (IS_ERR(ctrl->nand_base))
2101 return PTR_ERR(ctrl->nand_base);
2102
2103 /* Initialize NAND revision */
2104 ret = brcmnand_revision_init(ctrl);
2105 if (ret)
2106 return ret;
2107
2108 /*
2109 * Most chips have this cache at a fixed offset within 'nand' block.
2110 * Some must specify this region separately.
2111 */
2112 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-cache");
2113 if (res) {
2114 ctrl->nand_fc = devm_ioremap_resource(dev, res);
2115 if (IS_ERR(ctrl->nand_fc))
2116 return PTR_ERR(ctrl->nand_fc);
2117 } else {
2118 ctrl->nand_fc = ctrl->nand_base +
2119 ctrl->reg_offsets[BRCMNAND_FC_BASE];
2120 }
2121
2122 /* FLASH_DMA */
2123 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-dma");
2124 if (res) {
2125 ctrl->flash_dma_base = devm_ioremap_resource(dev, res);
2126 if (IS_ERR(ctrl->flash_dma_base))
2127 return PTR_ERR(ctrl->flash_dma_base);
2128
2129 flash_dma_writel(ctrl, FLASH_DMA_MODE, 1); /* linked-list */
2130 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
2131
2132 /* Allocate descriptor(s) */
2133 ctrl->dma_desc = dmam_alloc_coherent(dev,
2134 sizeof(*ctrl->dma_desc),
2135 &ctrl->dma_pa, GFP_KERNEL);
2136 if (!ctrl->dma_desc)
2137 return -ENOMEM;
2138
2139 ctrl->dma_irq = platform_get_irq(pdev, 1);
2140 if ((int)ctrl->dma_irq < 0) {
2141 dev_err(dev, "missing FLASH_DMA IRQ\n");
2142 return -ENODEV;
2143 }
2144
2145 ret = devm_request_irq(dev, ctrl->dma_irq,
2146 brcmnand_dma_irq, 0, DRV_NAME,
2147 ctrl);
2148 if (ret < 0) {
2149 dev_err(dev, "can't allocate IRQ %d: error %d\n",
2150 ctrl->dma_irq, ret);
2151 return ret;
2152 }
2153
2154 dev_info(dev, "enabling FLASH_DMA\n");
2155 }
2156
2157 /* Disable automatic device ID config, direct addressing */
2158 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT,
2159 CS_SELECT_AUTO_DEVICE_ID_CFG | 0xff, 0, 0);
2160 /* Disable XOR addressing */
2161 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_XOR, 0xff, 0, 0);
2162
2163 if (ctrl->features & BRCMNAND_HAS_WP) {
2164 /* Permanently disable write protection */
2165 if (wp_on == 2)
2166 brcmnand_set_wp(ctrl, false);
2167 } else {
2168 wp_on = 0;
2169 }
2170
2171 /* IRQ */
2172 ctrl->irq = platform_get_irq(pdev, 0);
2173 if ((int)ctrl->irq < 0) {
2174 dev_err(dev, "no IRQ defined\n");
2175 return -ENODEV;
2176 }
2177
c26211d3
BN		 2178 /*
2179 * Some SoCs integrate this controller (e.g., its interrupt bits) in
2180 * interesting ways
2181 */
2182 if (soc) {
2183 ctrl->soc = soc;
2184
2185 ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0,
2186 DRV_NAME, ctrl);
2187
2188 /* Enable interrupt */
2189 ctrl->soc->ctlrdy_ack(ctrl->soc);
2190 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
2191 } else {
2192 /* Use standard interrupt infrastructure */
2193 ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0,
2194 DRV_NAME, ctrl);
2195 }
27c5b17c
BN		 2196 if (ret < 0) {
2197 dev_err(dev, "can't allocate IRQ %d: error %d\n",
2198 ctrl->irq, ret);
2199 return ret;
2200 }
2201
2202 for_each_available_child_of_node(dn, child) {
2203 if (of_device_is_compatible(child, "brcm,nandcs")) {
2204 struct brcmnand_host *host;
2205
2206 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
2207 if (!host)
2208 return -ENOMEM;
2209 host->pdev = pdev;
2210 host->ctrl = ctrl;
2211 host->of_node = child;
2212
2213 ret = brcmnand_init_cs(host);
2214 if (ret)
2215 continue; /* Try all chip-selects */
2216
2217 list_add_tail(&host->node, &ctrl->host_list);
2218 }
2219 }
2220
2221 /* No chip-selects could initialize properly */
2222 if (list_empty(&ctrl->host_list))
2223 return -ENODEV;
2224
2225 return 0;
2226}
2227EXPORT_SYMBOL_GPL(brcmnand_probe);
2228
2229int brcmnand_remove(struct platform_device *pdev)
2230{
2231 struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev);
2232 struct brcmnand_host *host;
2233
2234 list_for_each_entry(host, &ctrl->host_list, node)
2235 nand_release(&host->mtd);
2236
2237 dev_set_drvdata(&pdev->dev, NULL);
2238
2239 return 0;
2240}
2241EXPORT_SYMBOL_GPL(brcmnand_remove);
2242
2243MODULE_LICENSE("GPL v2");
2244MODULE_AUTHOR("Kevin Cernekee");
2245MODULE_AUTHOR("Brian Norris");
2246MODULE_DESCRIPTION("NAND driver for Broadcom chips");
2247MODULE_ALIAS("platform:brcmnand");
Linux kernel - Deliverables
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