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mtd: nand: convert to nand_set_flash_node()
[deliverable/linux.git] / drivers / mtd / nand / brcmnand / brcmnand.c
CommitLineData
27c5b17c
BN		 1/*
2 * Copyright © 2010-2015 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/version.h>
15#include <linux/module.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/device.h>
19#include <linux/platform_device.h>
20#include <linux/err.h>
21#include <linux/completion.h>
22#include <linux/interrupt.h>
23#include <linux/spinlock.h>
24#include <linux/dma-mapping.h>
25#include <linux/ioport.h>
26#include <linux/bug.h>
27#include <linux/kernel.h>
28#include <linux/bitops.h>
29#include <linux/mm.h>
30#include <linux/mtd/mtd.h>
31#include <linux/mtd/nand.h>
32#include <linux/mtd/partitions.h>
33#include <linux/of.h>
34#include <linux/of_mtd.h>
35#include <linux/of_platform.h>
36#include <linux/slab.h>
37#include <linux/list.h>
38#include <linux/log2.h>
39
40#include "brcmnand.h"
41
42/*
43 * This flag controls if WP stays on between erase/write commands to mitigate
44 * flash corruption due to power glitches. Values:
45 * 0: NAND_WP is not used or not available
46 * 1: NAND_WP is set by default, cleared for erase/write operations
47 * 2: NAND_WP is always cleared
48 */
49static int wp_on = 1;
50module_param(wp_on, int, 0444);
51
52/***********************************************************************
53 * Definitions
54 ***********************************************************************/
55
56#define DRV_NAME "brcmnand"
57
58#define CMD_NULL 0x00
59#define CMD_PAGE_READ 0x01
60#define CMD_SPARE_AREA_READ 0x02
61#define CMD_STATUS_READ 0x03
62#define CMD_PROGRAM_PAGE 0x04
63#define CMD_PROGRAM_SPARE_AREA 0x05
64#define CMD_COPY_BACK 0x06
65#define CMD_DEVICE_ID_READ 0x07
66#define CMD_BLOCK_ERASE 0x08
67#define CMD_FLASH_RESET 0x09
68#define CMD_BLOCKS_LOCK 0x0a
69#define CMD_BLOCKS_LOCK_DOWN 0x0b
70#define CMD_BLOCKS_UNLOCK 0x0c
71#define CMD_READ_BLOCKS_LOCK_STATUS 0x0d
72#define CMD_PARAMETER_READ 0x0e
73#define CMD_PARAMETER_CHANGE_COL 0x0f
74#define CMD_LOW_LEVEL_OP 0x10
75
76struct brcm_nand_dma_desc {
77 u32 next_desc;
78 u32 next_desc_ext;
79 u32 cmd_irq;
80 u32 dram_addr;
81 u32 dram_addr_ext;
82 u32 tfr_len;
83 u32 total_len;
84 u32 flash_addr;
85 u32 flash_addr_ext;
86 u32 cs;
87 u32 pad2[5];
88 u32 status_valid;
89} __packed;
90
91/* Bitfields for brcm_nand_dma_desc::status_valid */
92#define FLASH_DMA_ECC_ERROR (1 << 8)
93#define FLASH_DMA_CORR_ERROR (1 << 9)
94
95/* 512B flash cache in the NAND controller HW */
96#define FC_SHIFT 9U
97#define FC_BYTES 512U
98#define FC_WORDS (FC_BYTES >> 2)
99
100#define BRCMNAND_MIN_PAGESIZE 512
101#define BRCMNAND_MIN_BLOCKSIZE (8 * 1024)
102#define BRCMNAND_MIN_DEVSIZE (4ULL * 1024 * 1024)
103
104/* Controller feature flags */
105enum {
106 BRCMNAND_HAS_1K_SECTORS = BIT(0),
107 BRCMNAND_HAS_PREFETCH = BIT(1),
108 BRCMNAND_HAS_CACHE_MODE = BIT(2),
109 BRCMNAND_HAS_WP = BIT(3),
110};
111
112struct brcmnand_controller {
113 struct device *dev;
114 struct nand_hw_control controller;
115 void __iomem *nand_base;
116 void __iomem *nand_fc; /* flash cache */
117 void __iomem *flash_dma_base;
118 unsigned int irq;
119 unsigned int dma_irq;
120 int nand_version;
121
c26211d3
BN		 122 /* Some SoCs provide custom interrupt status register(s) */
123 struct brcmnand_soc *soc;
124
27c5b17c
BN		 125 int cmd_pending;
126 bool dma_pending;
127 struct completion done;
128 struct completion dma_done;
129
130 /* List of NAND hosts (one for each chip-select) */
131 struct list_head host_list;
132
133 struct brcm_nand_dma_desc *dma_desc;
134 dma_addr_t dma_pa;
135
136 /* in-memory cache of the FLASH_CACHE, used only for some commands */
137 u32 flash_cache[FC_WORDS];
138
139 /* Controller revision details */
140 const u16 *reg_offsets;
141 unsigned int reg_spacing; /* between CS1, CS2, ... regs */
142 const u8 *cs_offsets; /* within each chip-select */
143 const u8 *cs0_offsets; /* within CS0, if different */
144 unsigned int max_block_size;
145 const unsigned int *block_sizes;
146 unsigned int max_page_size;
147 const unsigned int *page_sizes;
148 unsigned int max_oob;
149 u32 features;
150
151 /* for low-power standby/resume only */
152 u32 nand_cs_nand_select;
153 u32 nand_cs_nand_xor;
154 u32 corr_stat_threshold;
155 u32 flash_dma_mode;
156};
157
158struct brcmnand_cfg {
159 u64 device_size;
160 unsigned int block_size;
161 unsigned int page_size;
162 unsigned int spare_area_size;
163 unsigned int device_width;
164 unsigned int col_adr_bytes;
165 unsigned int blk_adr_bytes;
166 unsigned int ful_adr_bytes;
167 unsigned int sector_size_1k;
168 unsigned int ecc_level;
169 /* use for low-power standby/resume only */
170 u32 acc_control;
171 u32 config;
172 u32 config_ext;
173 u32 timing_1;
174 u32 timing_2;
175};
176
177struct brcmnand_host {
178 struct list_head node;
179 struct device_node *of_node;
180
181 struct nand_chip chip;
182 struct mtd_info mtd;
183 struct platform_device *pdev;
184 int cs;
185
186 unsigned int last_cmd;
187 unsigned int last_byte;
188 u64 last_addr;
189 struct brcmnand_cfg hwcfg;
190 struct brcmnand_controller *ctrl;
191};
192
193enum brcmnand_reg {
194 BRCMNAND_CMD_START = 0,
195 BRCMNAND_CMD_EXT_ADDRESS,
196 BRCMNAND_CMD_ADDRESS,
197 BRCMNAND_INTFC_STATUS,
198 BRCMNAND_CS_SELECT,
199 BRCMNAND_CS_XOR,
200 BRCMNAND_LL_OP,
201 BRCMNAND_CS0_BASE,
202 BRCMNAND_CS1_BASE, /* CS1 regs, if non-contiguous */
203 BRCMNAND_CORR_THRESHOLD,
204 BRCMNAND_CORR_THRESHOLD_EXT,
205 BRCMNAND_UNCORR_COUNT,
206 BRCMNAND_CORR_COUNT,
207 BRCMNAND_CORR_EXT_ADDR,
208 BRCMNAND_CORR_ADDR,
209 BRCMNAND_UNCORR_EXT_ADDR,
210 BRCMNAND_UNCORR_ADDR,
211 BRCMNAND_SEMAPHORE,
212 BRCMNAND_ID,
213 BRCMNAND_ID_EXT,
214 BRCMNAND_LL_RDATA,
215 BRCMNAND_OOB_READ_BASE,
216 BRCMNAND_OOB_READ_10_BASE, /* offset 0x10, if non-contiguous */
217 BRCMNAND_OOB_WRITE_BASE,
218 BRCMNAND_OOB_WRITE_10_BASE, /* offset 0x10, if non-contiguous */
219 BRCMNAND_FC_BASE,
220};
221
222/* BRCMNAND v4.0 */
223static const u16 brcmnand_regs_v40[] = {
224 [BRCMNAND_CMD_START] = 0x04,
225 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
226 [BRCMNAND_CMD_ADDRESS] = 0x0c,
227 [BRCMNAND_INTFC_STATUS] = 0x6c,
228 [BRCMNAND_CS_SELECT] = 0x14,
229 [BRCMNAND_CS_XOR] = 0x18,
230 [BRCMNAND_LL_OP] = 0x178,
231 [BRCMNAND_CS0_BASE] = 0x40,
232 [BRCMNAND_CS1_BASE] = 0xd0,
233 [BRCMNAND_CORR_THRESHOLD] = 0x84,
234 [BRCMNAND_CORR_THRESHOLD_EXT] = 0,
235 [BRCMNAND_UNCORR_COUNT] = 0,
236 [BRCMNAND_CORR_COUNT] = 0,
237 [BRCMNAND_CORR_EXT_ADDR] = 0x70,
238 [BRCMNAND_CORR_ADDR] = 0x74,
239 [BRCMNAND_UNCORR_EXT_ADDR] = 0x78,
240 [BRCMNAND_UNCORR_ADDR] = 0x7c,
241 [BRCMNAND_SEMAPHORE] = 0x58,
242 [BRCMNAND_ID] = 0x60,
243 [BRCMNAND_ID_EXT] = 0x64,
244 [BRCMNAND_LL_RDATA] = 0x17c,
245 [BRCMNAND_OOB_READ_BASE] = 0x20,
246 [BRCMNAND_OOB_READ_10_BASE] = 0x130,
247 [BRCMNAND_OOB_WRITE_BASE] = 0x30,
248 [BRCMNAND_OOB_WRITE_10_BASE] = 0,
249 [BRCMNAND_FC_BASE] = 0x200,
250};
251
252/* BRCMNAND v5.0 */
253static const u16 brcmnand_regs_v50[] = {
254 [BRCMNAND_CMD_START] = 0x04,
255 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
256 [BRCMNAND_CMD_ADDRESS] = 0x0c,
257 [BRCMNAND_INTFC_STATUS] = 0x6c,
258 [BRCMNAND_CS_SELECT] = 0x14,
259 [BRCMNAND_CS_XOR] = 0x18,
260 [BRCMNAND_LL_OP] = 0x178,
261 [BRCMNAND_CS0_BASE] = 0x40,
262 [BRCMNAND_CS1_BASE] = 0xd0,
263 [BRCMNAND_CORR_THRESHOLD] = 0x84,
264 [BRCMNAND_CORR_THRESHOLD_EXT] = 0,
265 [BRCMNAND_UNCORR_COUNT] = 0,
266 [BRCMNAND_CORR_COUNT] = 0,
267 [BRCMNAND_CORR_EXT_ADDR] = 0x70,
268 [BRCMNAND_CORR_ADDR] = 0x74,
269 [BRCMNAND_UNCORR_EXT_ADDR] = 0x78,
270 [BRCMNAND_UNCORR_ADDR] = 0x7c,
271 [BRCMNAND_SEMAPHORE] = 0x58,
272 [BRCMNAND_ID] = 0x60,
273 [BRCMNAND_ID_EXT] = 0x64,
274 [BRCMNAND_LL_RDATA] = 0x17c,
275 [BRCMNAND_OOB_READ_BASE] = 0x20,
276 [BRCMNAND_OOB_READ_10_BASE] = 0x130,
277 [BRCMNAND_OOB_WRITE_BASE] = 0x30,
278 [BRCMNAND_OOB_WRITE_10_BASE] = 0x140,
279 [BRCMNAND_FC_BASE] = 0x200,
280};
281
282/* BRCMNAND v6.0 - v7.1 */
283static const u16 brcmnand_regs_v60[] = {
284 [BRCMNAND_CMD_START] = 0x04,
285 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
286 [BRCMNAND_CMD_ADDRESS] = 0x0c,
287 [BRCMNAND_INTFC_STATUS] = 0x14,
288 [BRCMNAND_CS_SELECT] = 0x18,
289 [BRCMNAND_CS_XOR] = 0x1c,
290 [BRCMNAND_LL_OP] = 0x20,
291 [BRCMNAND_CS0_BASE] = 0x50,
292 [BRCMNAND_CS1_BASE] = 0,
293 [BRCMNAND_CORR_THRESHOLD] = 0xc0,
294 [BRCMNAND_CORR_THRESHOLD_EXT] = 0xc4,
295 [BRCMNAND_UNCORR_COUNT] = 0xfc,
296 [BRCMNAND_CORR_COUNT] = 0x100,
297 [BRCMNAND_CORR_EXT_ADDR] = 0x10c,
298 [BRCMNAND_CORR_ADDR] = 0x110,
299 [BRCMNAND_UNCORR_EXT_ADDR] = 0x114,
300 [BRCMNAND_UNCORR_ADDR] = 0x118,
301 [BRCMNAND_SEMAPHORE] = 0x150,
302 [BRCMNAND_ID] = 0x194,
303 [BRCMNAND_ID_EXT] = 0x198,
304 [BRCMNAND_LL_RDATA] = 0x19c,
305 [BRCMNAND_OOB_READ_BASE] = 0x200,
306 [BRCMNAND_OOB_READ_10_BASE] = 0,
307 [BRCMNAND_OOB_WRITE_BASE] = 0x280,
308 [BRCMNAND_OOB_WRITE_10_BASE] = 0,
309 [BRCMNAND_FC_BASE] = 0x400,
310};
311
312enum brcmnand_cs_reg {
313 BRCMNAND_CS_CFG_EXT = 0,
314 BRCMNAND_CS_CFG,
315 BRCMNAND_CS_ACC_CONTROL,
316 BRCMNAND_CS_TIMING1,
317 BRCMNAND_CS_TIMING2,
318};
319
320/* Per chip-select offsets for v7.1 */
321static const u8 brcmnand_cs_offsets_v71[] = {
322 [BRCMNAND_CS_ACC_CONTROL] = 0x00,
323 [BRCMNAND_CS_CFG_EXT] = 0x04,
324 [BRCMNAND_CS_CFG] = 0x08,
325 [BRCMNAND_CS_TIMING1] = 0x0c,
326 [BRCMNAND_CS_TIMING2] = 0x10,
327};
328
329/* Per chip-select offsets for pre v7.1, except CS0 on <= v5.0 */
330static const u8 brcmnand_cs_offsets[] = {
331 [BRCMNAND_CS_ACC_CONTROL] = 0x00,
332 [BRCMNAND_CS_CFG_EXT] = 0x04,
333 [BRCMNAND_CS_CFG] = 0x04,
334 [BRCMNAND_CS_TIMING1] = 0x08,
335 [BRCMNAND_CS_TIMING2] = 0x0c,
336};
337
338/* Per chip-select offset for <= v5.0 on CS0 only */
339static const u8 brcmnand_cs_offsets_cs0[] = {
340 [BRCMNAND_CS_ACC_CONTROL] = 0x00,
341 [BRCMNAND_CS_CFG_EXT] = 0x08,
342 [BRCMNAND_CS_CFG] = 0x08,
343 [BRCMNAND_CS_TIMING1] = 0x10,
344 [BRCMNAND_CS_TIMING2] = 0x14,
345};
346
3f06d2a9
BN		 347/*
348 * Bitfields for the CFG and CFG_EXT registers. Pre-v7.1 controllers only had
349 * one config register, but once the bitfields overflowed, newer controllers
350 * (v7.1 and newer) added a CFG_EXT register and shuffled a few fields around.
351 */
352enum {
353 CFG_BLK_ADR_BYTES_SHIFT = 8,
354 CFG_COL_ADR_BYTES_SHIFT = 12,
355 CFG_FUL_ADR_BYTES_SHIFT = 16,
356 CFG_BUS_WIDTH_SHIFT = 23,
357 CFG_BUS_WIDTH = BIT(CFG_BUS_WIDTH_SHIFT),
358 CFG_DEVICE_SIZE_SHIFT = 24,
359
360 /* Only for pre-v7.1 (with no CFG_EXT register) */
361 CFG_PAGE_SIZE_SHIFT = 20,
362 CFG_BLK_SIZE_SHIFT = 28,
363
364 /* Only for v7.1+ (with CFG_EXT register) */
365 CFG_EXT_PAGE_SIZE_SHIFT = 0,
366 CFG_EXT_BLK_SIZE_SHIFT = 4,
367};
368
27c5b17c
BN		 369/* BRCMNAND_INTFC_STATUS */
370enum {
371 INTFC_FLASH_STATUS = GENMASK(7, 0),
372
373 INTFC_ERASED = BIT(27),
374 INTFC_OOB_VALID = BIT(28),
375 INTFC_CACHE_VALID = BIT(29),
376 INTFC_FLASH_READY = BIT(30),
377 INTFC_CTLR_READY = BIT(31),
378};
379
380static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs)
381{
382 return brcmnand_readl(ctrl->nand_base + offs);
383}
384
385static inline void nand_writereg(struct brcmnand_controller *ctrl, u32 offs,
386 u32 val)
387{
388 brcmnand_writel(val, ctrl->nand_base + offs);
389}
390
391static int brcmnand_revision_init(struct brcmnand_controller *ctrl)
392{
393 static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 };
394 static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 };
395 static const unsigned int page_sizes[] = { 512, 2048, 4096, 8192, 0 };
396
397 ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff;
398
399 /* Only support v4.0+? */
400 if (ctrl->nand_version < 0x0400) {
401 dev_err(ctrl->dev, "version %#x not supported\n",
402 ctrl->nand_version);
403 return -ENODEV;
404 }
405
406 /* Register offsets */
407 if (ctrl->nand_version >= 0x0600)
408 ctrl->reg_offsets = brcmnand_regs_v60;
409 else if (ctrl->nand_version >= 0x0500)
410 ctrl->reg_offsets = brcmnand_regs_v50;
411 else if (ctrl->nand_version >= 0x0400)
412 ctrl->reg_offsets = brcmnand_regs_v40;
413
414 /* Chip-select stride */
415 if (ctrl->nand_version >= 0x0701)
416 ctrl->reg_spacing = 0x14;
417 else
418 ctrl->reg_spacing = 0x10;
419
420 /* Per chip-select registers */
421 if (ctrl->nand_version >= 0x0701) {
422 ctrl->cs_offsets = brcmnand_cs_offsets_v71;
423 } else {
424 ctrl->cs_offsets = brcmnand_cs_offsets;
425
426 /* v5.0 and earlier has a different CS0 offset layout */
427 if (ctrl->nand_version <= 0x0500)
428 ctrl->cs0_offsets = brcmnand_cs_offsets_cs0;
429 }
430
431 /* Page / block sizes */
432 if (ctrl->nand_version >= 0x0701) {
433 /* >= v7.1 use nice power-of-2 values! */
434 ctrl->max_page_size = 16 * 1024;
435 ctrl->max_block_size = 2 * 1024 * 1024;
436 } else {
437 ctrl->page_sizes = page_sizes;
438 if (ctrl->nand_version >= 0x0600)
439 ctrl->block_sizes = block_sizes_v6;
440 else
441 ctrl->block_sizes = block_sizes_v4;
442
443 if (ctrl->nand_version < 0x0400) {
444 ctrl->max_page_size = 4096;
445 ctrl->max_block_size = 512 * 1024;
446 }
447 }
448
449 /* Maximum spare area sector size (per 512B) */
450 if (ctrl->nand_version >= 0x0600)
451 ctrl->max_oob = 64;
452 else if (ctrl->nand_version >= 0x0500)
453 ctrl->max_oob = 32;
454 else
455 ctrl->max_oob = 16;
456
457 /* v6.0 and newer (except v6.1) have prefetch support */
458 if (ctrl->nand_version >= 0x0600 && ctrl->nand_version != 0x0601)
459 ctrl->features |= BRCMNAND_HAS_PREFETCH;
460
461 /*
462 * v6.x has cache mode, but it's implemented differently. Ignore it for
463 * now.
464 */
465 if (ctrl->nand_version >= 0x0700)
466 ctrl->features |= BRCMNAND_HAS_CACHE_MODE;
467
468 if (ctrl->nand_version >= 0x0500)
469 ctrl->features |= BRCMNAND_HAS_1K_SECTORS;
470
471 if (ctrl->nand_version >= 0x0700)
472 ctrl->features |= BRCMNAND_HAS_WP;
473 else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp"))
474 ctrl->features |= BRCMNAND_HAS_WP;
475
476 return 0;
477}
478
479static inline u32 brcmnand_read_reg(struct brcmnand_controller *ctrl,
480 enum brcmnand_reg reg)
481{
482 u16 offs = ctrl->reg_offsets[reg];
483
484 if (offs)
485 return nand_readreg(ctrl, offs);
486 else
487 return 0;
488}
489
490static inline void brcmnand_write_reg(struct brcmnand_controller *ctrl,
491 enum brcmnand_reg reg, u32 val)
492{
493 u16 offs = ctrl->reg_offsets[reg];
494
495 if (offs)
496 nand_writereg(ctrl, offs, val);
497}
498
499static inline void brcmnand_rmw_reg(struct brcmnand_controller *ctrl,
500 enum brcmnand_reg reg, u32 mask, unsigned
501 int shift, u32 val)
502{
503 u32 tmp = brcmnand_read_reg(ctrl, reg);
504
505 tmp &= ~mask;
506 tmp |= val << shift;
507 brcmnand_write_reg(ctrl, reg, tmp);
508}
509
510static inline u32 brcmnand_read_fc(struct brcmnand_controller *ctrl, int word)
511{
512 return __raw_readl(ctrl->nand_fc + word * 4);
513}
514
515static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl,
516 int word, u32 val)
517{
518 __raw_writel(val, ctrl->nand_fc + word * 4);
519}
520
521static inline u16 brcmnand_cs_offset(struct brcmnand_controller *ctrl, int cs,
522 enum brcmnand_cs_reg reg)
523{
524 u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE];
525 u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE];
526 u8 cs_offs;
527
528 if (cs == 0 && ctrl->cs0_offsets)
529 cs_offs = ctrl->cs0_offsets[reg];
530 else
531 cs_offs = ctrl->cs_offsets[reg];
532
533 if (cs && offs_cs1)
534 return offs_cs1 + (cs - 1) * ctrl->reg_spacing + cs_offs;
535
536 return offs_cs0 + cs * ctrl->reg_spacing + cs_offs;
537}
538
539static inline u32 brcmnand_count_corrected(struct brcmnand_controller *ctrl)
540{
541 if (ctrl->nand_version < 0x0600)
542 return 1;
543 return brcmnand_read_reg(ctrl, BRCMNAND_CORR_COUNT);
544}
545
546static void brcmnand_wr_corr_thresh(struct brcmnand_host *host, u8 val)
547{
548 struct brcmnand_controller *ctrl = host->ctrl;
549 unsigned int shift = 0, bits;
550 enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD;
551 int cs = host->cs;
552
553 if (ctrl->nand_version >= 0x0600)
554 bits = 6;
555 else if (ctrl->nand_version >= 0x0500)
556 bits = 5;
557 else
558 bits = 4;
559
560 if (ctrl->nand_version >= 0x0600) {
561 if (cs >= 5)
562 reg = BRCMNAND_CORR_THRESHOLD_EXT;
563 shift = (cs % 5) * bits;
564 }
565 brcmnand_rmw_reg(ctrl, reg, (bits - 1) << shift, shift, val);
566}
567
568static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl)
569{
570 if (ctrl->nand_version < 0x0700)
571 return 24;
572 return 0;
573}
574
575/***********************************************************************
576 * NAND ACC CONTROL bitfield
577 *
578 * Some bits have remained constant throughout hardware revision, while
579 * others have shifted around.
580 ***********************************************************************/
581
582/* Constant for all versions (where supported) */
583enum {
584 /* See BRCMNAND_HAS_CACHE_MODE */
585 ACC_CONTROL_CACHE_MODE = BIT(22),
586
587 /* See BRCMNAND_HAS_PREFETCH */
588 ACC_CONTROL_PREFETCH = BIT(23),
589
590 ACC_CONTROL_PAGE_HIT = BIT(24),
591 ACC_CONTROL_WR_PREEMPT = BIT(25),
592 ACC_CONTROL_PARTIAL_PAGE = BIT(26),
593 ACC_CONTROL_RD_ERASED = BIT(27),
594 ACC_CONTROL_FAST_PGM_RDIN = BIT(28),
595 ACC_CONTROL_WR_ECC = BIT(30),
596 ACC_CONTROL_RD_ECC = BIT(31),
597};
598
599static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl)
600{
601 if (ctrl->nand_version >= 0x0600)
602 return GENMASK(6, 0);
603 else
604 return GENMASK(5, 0);
605}
606
607#define NAND_ACC_CONTROL_ECC_SHIFT 16
608
609static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl)
610{
611 u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f;
612
613 return mask << NAND_ACC_CONTROL_ECC_SHIFT;
614}
615
616static void brcmnand_set_ecc_enabled(struct brcmnand_host *host, int en)
617{
618 struct brcmnand_controller *ctrl = host->ctrl;
619 u16 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
620 u32 acc_control = nand_readreg(ctrl, offs);
621 u32 ecc_flags = ACC_CONTROL_WR_ECC | ACC_CONTROL_RD_ECC;
622
623 if (en) {
624 acc_control |= ecc_flags; /* enable RD/WR ECC */
625 acc_control |= host->hwcfg.ecc_level
626 << NAND_ACC_CONTROL_ECC_SHIFT;
627 } else {
628 acc_control &= ~ecc_flags; /* disable RD/WR ECC */
629 acc_control &= ~brcmnand_ecc_level_mask(ctrl);
630 }
631
632 nand_writereg(ctrl, offs, acc_control);
633}
634
635static inline int brcmnand_sector_1k_shift(struct brcmnand_controller *ctrl)
636{
637 if (ctrl->nand_version >= 0x0600)
638 return 7;
639 else if (ctrl->nand_version >= 0x0500)
640 return 6;
641 else
642 return -1;
643}
644
645static int brcmnand_get_sector_size_1k(struct brcmnand_host *host)
646{
647 struct brcmnand_controller *ctrl = host->ctrl;
648 int shift = brcmnand_sector_1k_shift(ctrl);
649 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
650 BRCMNAND_CS_ACC_CONTROL);
651
652 if (shift < 0)
653 return 0;
654
655 return (nand_readreg(ctrl, acc_control_offs) >> shift) & 0x1;
656}
657
658static void brcmnand_set_sector_size_1k(struct brcmnand_host *host, int val)
659{
660 struct brcmnand_controller *ctrl = host->ctrl;
661 int shift = brcmnand_sector_1k_shift(ctrl);
662 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
663 BRCMNAND_CS_ACC_CONTROL);
664 u32 tmp;
665
666 if (shift < 0)
667 return;
668
669 tmp = nand_readreg(ctrl, acc_control_offs);
670 tmp &= ~(1 << shift);
671 tmp |= (!!val) << shift;
672 nand_writereg(ctrl, acc_control_offs, tmp);
673}
674
675/***********************************************************************
676 * CS_NAND_SELECT
677 ***********************************************************************/
678
679enum {
680 CS_SELECT_NAND_WP = BIT(29),
681 CS_SELECT_AUTO_DEVICE_ID_CFG = BIT(30),
682};
683
684static inline void brcmnand_set_wp(struct brcmnand_controller *ctrl, bool en)
685{
686 u32 val = en ? CS_SELECT_NAND_WP : 0;
687
688 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, CS_SELECT_NAND_WP, 0, val);
689}
690
691/***********************************************************************
692 * Flash DMA
693 ***********************************************************************/
694
695enum flash_dma_reg {
696 FLASH_DMA_REVISION = 0x00,
697 FLASH_DMA_FIRST_DESC = 0x04,
698 FLASH_DMA_FIRST_DESC_EXT = 0x08,
699 FLASH_DMA_CTRL = 0x0c,
700 FLASH_DMA_MODE = 0x10,
701 FLASH_DMA_STATUS = 0x14,
702 FLASH_DMA_INTERRUPT_DESC = 0x18,
703 FLASH_DMA_INTERRUPT_DESC_EXT = 0x1c,
704 FLASH_DMA_ERROR_STATUS = 0x20,
705 FLASH_DMA_CURRENT_DESC = 0x24,
706 FLASH_DMA_CURRENT_DESC_EXT = 0x28,
707};
708
709static inline bool has_flash_dma(struct brcmnand_controller *ctrl)
710{
711 return ctrl->flash_dma_base;
712}
713
714static inline bool flash_dma_buf_ok(const void *buf)
715{
716 return buf && !is_vmalloc_addr(buf) &&
717 likely(IS_ALIGNED((uintptr_t)buf, 4));
718}
719
720static inline void flash_dma_writel(struct brcmnand_controller *ctrl, u8 offs,
721 u32 val)
722{
723 brcmnand_writel(val, ctrl->flash_dma_base + offs);
724}
725
726static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl, u8 offs)
727{
728 return brcmnand_readl(ctrl->flash_dma_base + offs);
729}
730
731/* Low-level operation types: command, address, write, or read */
732enum brcmnand_llop_type {
733 LL_OP_CMD,
734 LL_OP_ADDR,
735 LL_OP_WR,
736 LL_OP_RD,
737};
738
739/***********************************************************************
740 * Internal support functions
741 ***********************************************************************/
742
743static inline bool is_hamming_ecc(struct brcmnand_cfg *cfg)
744{
745 return cfg->sector_size_1k == 0 && cfg->spare_area_size == 16 &&
746 cfg->ecc_level == 15;
747}
748
749/*
750 * Returns a nand_ecclayout strucutre for the given layout/configuration.
751 * Returns NULL on failure.
752 */
753static struct nand_ecclayout *brcmnand_create_layout(int ecc_level,
754 struct brcmnand_host *host)
755{
756 struct brcmnand_cfg *cfg = &host->hwcfg;
757 int i, j;
758 struct nand_ecclayout *layout;
759 int req;
760 int sectors;
761 int sas;
762 int idx1, idx2;
763
764 layout = devm_kzalloc(&host->pdev->dev, sizeof(*layout), GFP_KERNEL);
765 if (!layout)
766 return NULL;
767
768 sectors = cfg->page_size / (512 << cfg->sector_size_1k);
769 sas = cfg->spare_area_size << cfg->sector_size_1k;
770
771 /* Hamming */
772 if (is_hamming_ecc(cfg)) {
773 for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) {
774 /* First sector of each page may have BBI */
775 if (i == 0) {
776 layout->oobfree[idx2].offset = i * sas + 1;
777 /* Small-page NAND use byte 6 for BBI */
778 if (cfg->page_size == 512)
779 layout->oobfree[idx2].offset--;
780 layout->oobfree[idx2].length = 5;
781 } else {
782 layout->oobfree[idx2].offset = i * sas;
783 layout->oobfree[idx2].length = 6;
784 }
785 idx2++;
786 layout->eccpos[idx1++] = i * sas + 6;
787 layout->eccpos[idx1++] = i * sas + 7;
788 layout->eccpos[idx1++] = i * sas + 8;
789 layout->oobfree[idx2].offset = i * sas + 9;
790 layout->oobfree[idx2].length = 7;
791 idx2++;
792 /* Leave zero-terminated entry for OOBFREE */
793 if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE ||
794 idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1)
795 break;
796 }
797 goto out;
798 }
799
800 /*
801 * CONTROLLER_VERSION:
802 * < v5.0: ECC_REQ = ceil(BCH_T * 13/8)
803 * >= v5.0: ECC_REQ = ceil(BCH_T * 14/8)
804 * But we will just be conservative.
805 */
806 req = DIV_ROUND_UP(ecc_level * 14, 8);
807 if (req >= sas) {
808 dev_err(&host->pdev->dev,
809 "error: ECC too large for OOB (ECC bytes %d, spare sector %d)\n",
810 req, sas);
811 return NULL;
812 }
813
814 layout->eccbytes = req * sectors;
815 for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) {
816 for (j = sas - req; j < sas && idx1 <
817 MTD_MAX_ECCPOS_ENTRIES_LARGE; j++, idx1++)
818 layout->eccpos[idx1] = i * sas + j;
819
820 /* First sector of each page may have BBI */
821 if (i == 0) {
822 if (cfg->page_size == 512 && (sas - req >= 6)) {
823 /* Small-page NAND use byte 6 for BBI */
824 layout->oobfree[idx2].offset = 0;
825 layout->oobfree[idx2].length = 5;
826 idx2++;
827 if (sas - req > 6) {
828 layout->oobfree[idx2].offset = 6;
829 layout->oobfree[idx2].length =
830 sas - req - 6;
831 idx2++;
832 }
833 } else if (sas > req + 1) {
834 layout->oobfree[idx2].offset = i * sas + 1;
835 layout->oobfree[idx2].length = sas - req - 1;
836 idx2++;
837 }
838 } else if (sas > req) {
839 layout->oobfree[idx2].offset = i * sas;
840 layout->oobfree[idx2].length = sas - req;
841 idx2++;
842 }
843 /* Leave zero-terminated entry for OOBFREE */
844 if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE ||
845 idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1)
846 break;
847 }
848out:
849 /* Sum available OOB */
850 for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE; i++)
851 layout->oobavail += layout->oobfree[i].length;
852 return layout;
853}
854
855static struct nand_ecclayout *brcmstb_choose_ecc_layout(
856 struct brcmnand_host *host)
857{
858 struct nand_ecclayout *layout;
859 struct brcmnand_cfg *p = &host->hwcfg;
860 unsigned int ecc_level = p->ecc_level;
861
862 if (p->sector_size_1k)
863 ecc_level <<= 1;
864
865 layout = brcmnand_create_layout(ecc_level, host);
866 if (!layout) {
867 dev_err(&host->pdev->dev,
868 "no proper ecc_layout for this NAND cfg\n");
869 return NULL;
870 }
871
872 return layout;
873}
874
875static void brcmnand_wp(struct mtd_info *mtd, int wp)
876{
877 struct nand_chip *chip = mtd->priv;
878 struct brcmnand_host *host = chip->priv;
879 struct brcmnand_controller *ctrl = host->ctrl;
880
881 if ((ctrl->features & BRCMNAND_HAS_WP) && wp_on == 1) {
882 static int old_wp = -1;
883
884 if (old_wp != wp) {
885 dev_dbg(ctrl->dev, "WP %s\n", wp ? "on" : "off");
886 old_wp = wp;
887 }
888 brcmnand_set_wp(ctrl, wp);
889 }
890}
891
892/* Helper functions for reading and writing OOB registers */
893static inline u8 oob_reg_read(struct brcmnand_controller *ctrl, u32 offs)
894{
895 u16 offset0, offset10, reg_offs;
896
897 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE];
898 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_READ_10_BASE];
899
900 if (offs >= ctrl->max_oob)
901 return 0x77;
902
903 if (offs >= 16 && offset10)
904 reg_offs = offset10 + ((offs - 0x10) & ~0x03);
905 else
906 reg_offs = offset0 + (offs & ~0x03);
907
908 return nand_readreg(ctrl, reg_offs) >> (24 - ((offs & 0x03) << 3));
909}
910
911static inline void oob_reg_write(struct brcmnand_controller *ctrl, u32 offs,
912 u32 data)
913{
914 u16 offset0, offset10, reg_offs;
915
916 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_BASE];
917 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_10_BASE];
918
919 if (offs >= ctrl->max_oob)
920 return;
921
922 if (offs >= 16 && offset10)
923 reg_offs = offset10 + ((offs - 0x10) & ~0x03);
924 else
925 reg_offs = offset0 + (offs & ~0x03);
926
927 nand_writereg(ctrl, reg_offs, data);
928}
929
930/*
931 * read_oob_from_regs - read data from OOB registers
932 * @ctrl: NAND controller
933 * @i: sub-page sector index
934 * @oob: buffer to read to
935 * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
936 * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
937 */
938static int read_oob_from_regs(struct brcmnand_controller *ctrl, int i, u8 *oob,
939 int sas, int sector_1k)
940{
941 int tbytes = sas << sector_1k;
942 int j;
943
944 /* Adjust OOB values for 1K sector size */
945 if (sector_1k && (i & 0x01))
946 tbytes = max(0, tbytes - (int)ctrl->max_oob);
947 tbytes = min_t(int, tbytes, ctrl->max_oob);
948
949 for (j = 0; j < tbytes; j++)
950 oob[j] = oob_reg_read(ctrl, j);
951 return tbytes;
952}
953
954/*
955 * write_oob_to_regs - write data to OOB registers
956 * @i: sub-page sector index
957 * @oob: buffer to write from
958 * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
959 * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
960 */
961static int write_oob_to_regs(struct brcmnand_controller *ctrl, int i,
962 const u8 *oob, int sas, int sector_1k)
963{
964 int tbytes = sas << sector_1k;
965 int j;
966
967 /* Adjust OOB values for 1K sector size */
968 if (sector_1k && (i & 0x01))
969 tbytes = max(0, tbytes - (int)ctrl->max_oob);
970 tbytes = min_t(int, tbytes, ctrl->max_oob);
971
972 for (j = 0; j < tbytes; j += 4)
973 oob_reg_write(ctrl, j,
974 (oob[j + 0] << 24) |
975 (oob[j + 1] << 16) |
976 (oob[j + 2] << 8) |
977 (oob[j + 3] << 0));
978 return tbytes;
979}
980
981static irqreturn_t brcmnand_ctlrdy_irq(int irq, void *data)
982{
983 struct brcmnand_controller *ctrl = data;
984
985 /* Discard all NAND_CTLRDY interrupts during DMA */
986 if (ctrl->dma_pending)
987 return IRQ_HANDLED;
988
989 complete(&ctrl->done);
990 return IRQ_HANDLED;
991}
992
c26211d3
BN		 993/* Handle SoC-specific interrupt hardware */
994static irqreturn_t brcmnand_irq(int irq, void *data)
995{
996 struct brcmnand_controller *ctrl = data;
997
998 if (ctrl->soc->ctlrdy_ack(ctrl->soc))
999 return brcmnand_ctlrdy_irq(irq, data);
1000
1001 return IRQ_NONE;
1002}
1003
27c5b17c
BN		 1004static irqreturn_t brcmnand_dma_irq(int irq, void *data)
1005{
1006 struct brcmnand_controller *ctrl = data;
1007
1008 complete(&ctrl->dma_done);
1009
1010 return IRQ_HANDLED;
1011}
1012
1013static void brcmnand_send_cmd(struct brcmnand_host *host, int cmd)
1014{
1015 struct brcmnand_controller *ctrl = host->ctrl;
1016 u32 intfc;
1017
1018 dev_dbg(ctrl->dev, "send native cmd %d addr_lo 0x%x\n", cmd,
1019 brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS));
1020 BUG_ON(ctrl->cmd_pending != 0);
1021 ctrl->cmd_pending = cmd;
1022
1023 intfc = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS);
1024 BUG_ON(!(intfc & INTFC_CTLR_READY));
1025
1026 mb(); /* flush previous writes */
1027 brcmnand_write_reg(ctrl, BRCMNAND_CMD_START,
1028 cmd << brcmnand_cmd_shift(ctrl));
1029}
1030
1031/***********************************************************************
1032 * NAND MTD API: read/program/erase
1033 ***********************************************************************/
1034
1035static void brcmnand_cmd_ctrl(struct mtd_info *mtd, int dat,
1036 unsigned int ctrl)
1037{
1038 /* intentionally left blank */
1039}
1040
1041static int brcmnand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
1042{
1043 struct nand_chip *chip = mtd->priv;
1044 struct brcmnand_host *host = chip->priv;
1045 struct brcmnand_controller *ctrl = host->ctrl;
1046 unsigned long timeo = msecs_to_jiffies(100);
1047
1048 dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending);
1049 if (ctrl->cmd_pending &&
1050 wait_for_completion_timeout(&ctrl->done, timeo) <= 0) {
1051 u32 cmd = brcmnand_read_reg(ctrl, BRCMNAND_CMD_START)
1052 >> brcmnand_cmd_shift(ctrl);
1053
1054 dev_err_ratelimited(ctrl->dev,
1055 "timeout waiting for command %#02x\n", cmd);
1056 dev_err_ratelimited(ctrl->dev, "intfc status %08x\n",
1057 brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS));
1058 }
1059 ctrl->cmd_pending = 0;
1060 return brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
1061 INTFC_FLASH_STATUS;
1062}
1063
1064enum {
1065 LLOP_RE = BIT(16),
1066 LLOP_WE = BIT(17),
1067 LLOP_ALE = BIT(18),
1068 LLOP_CLE = BIT(19),
1069 LLOP_RETURN_IDLE = BIT(31),
1070
1071 LLOP_DATA_MASK = GENMASK(15, 0),
1072};
1073
1074static int brcmnand_low_level_op(struct brcmnand_host *host,
1075 enum brcmnand_llop_type type, u32 data,
1076 bool last_op)
1077{
1078 struct mtd_info *mtd = &host->mtd;
1079 struct nand_chip *chip = &host->chip;
1080 struct brcmnand_controller *ctrl = host->ctrl;
1081 u32 tmp;
1082
1083 tmp = data & LLOP_DATA_MASK;
1084 switch (type) {
1085 case LL_OP_CMD:
1086 tmp |= LLOP_WE | LLOP_CLE;
1087 break;
1088 case LL_OP_ADDR:
1089 /* WE | ALE */
1090 tmp |= LLOP_WE | LLOP_ALE;
1091 break;
1092 case LL_OP_WR:
1093 /* WE */
1094 tmp |= LLOP_WE;
1095 break;
1096 case LL_OP_RD:
1097 /* RE */
1098 tmp |= LLOP_RE;
1099 break;
1100 }
1101 if (last_op)
1102 /* RETURN_IDLE */
1103 tmp |= LLOP_RETURN_IDLE;
1104
1105 dev_dbg(ctrl->dev, "ll_op cmd %#x\n", tmp);
1106
1107 brcmnand_write_reg(ctrl, BRCMNAND_LL_OP, tmp);
1108 (void)brcmnand_read_reg(ctrl, BRCMNAND_LL_OP);
1109
1110 brcmnand_send_cmd(host, CMD_LOW_LEVEL_OP);
1111 return brcmnand_waitfunc(mtd, chip);
1112}
1113
1114static void brcmnand_cmdfunc(struct mtd_info *mtd, unsigned command,
1115 int column, int page_addr)
1116{
1117 struct nand_chip *chip = mtd->priv;
1118 struct brcmnand_host *host = chip->priv;
1119 struct brcmnand_controller *ctrl = host->ctrl;
1120 u64 addr = (u64)page_addr << chip->page_shift;
1121 int native_cmd = 0;
1122
1123 if (command == NAND_CMD_READID || command == NAND_CMD_PARAM ||
1124 command == NAND_CMD_RNDOUT)
1125 addr = (u64)column;
1126 /* Avoid propagating a negative, don't-care address */
1127 else if (page_addr < 0)
1128 addr = 0;
1129
1130 dev_dbg(ctrl->dev, "cmd 0x%x addr 0x%llx\n", command,
1131 (unsigned long long)addr);
1132
1133 host->last_cmd = command;
1134 host->last_byte = 0;
1135 host->last_addr = addr;
1136
1137 switch (command) {
1138 case NAND_CMD_RESET:
1139 native_cmd = CMD_FLASH_RESET;
1140 break;
1141 case NAND_CMD_STATUS:
1142 native_cmd = CMD_STATUS_READ;
1143 break;
1144 case NAND_CMD_READID:
1145 native_cmd = CMD_DEVICE_ID_READ;
1146 break;
1147 case NAND_CMD_READOOB:
1148 native_cmd = CMD_SPARE_AREA_READ;
1149 break;
1150 case NAND_CMD_ERASE1:
1151 native_cmd = CMD_BLOCK_ERASE;
1152 brcmnand_wp(mtd, 0);
1153 break;
1154 case NAND_CMD_PARAM:
1155 native_cmd = CMD_PARAMETER_READ;
1156 break;
1157 case NAND_CMD_SET_FEATURES:
1158 case NAND_CMD_GET_FEATURES:
1159 brcmnand_low_level_op(host, LL_OP_CMD, command, false);
1160 brcmnand_low_level_op(host, LL_OP_ADDR, column, false);
1161 break;
1162 case NAND_CMD_RNDOUT:
1163 native_cmd = CMD_PARAMETER_CHANGE_COL;
1164 addr &= ~((u64)(FC_BYTES - 1));
1165 /*
1166 * HW quirk: PARAMETER_CHANGE_COL requires SECTOR_SIZE_1K=0
1167 * NB: hwcfg.sector_size_1k may not be initialized yet
1168 */
1169 if (brcmnand_get_sector_size_1k(host)) {
1170 host->hwcfg.sector_size_1k =
1171 brcmnand_get_sector_size_1k(host);
1172 brcmnand_set_sector_size_1k(host, 0);
1173 }
1174 break;
1175 }
1176
1177 if (!native_cmd)
1178 return;
1179
1180 brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1181 (host->cs << 16) | ((addr >> 32) & 0xffff));
1182 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1183 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, lower_32_bits(addr));
1184 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1185
1186 brcmnand_send_cmd(host, native_cmd);
1187 brcmnand_waitfunc(mtd, chip);
1188
1189 if (native_cmd == CMD_PARAMETER_READ ||
1190 native_cmd == CMD_PARAMETER_CHANGE_COL) {
1191 int i;
c26211d3
BN		 1192
1193 brcmnand_soc_data_bus_prepare(ctrl->soc);
1194
27c5b17c
BN		 1195 /*
1196 * Must cache the FLASH_CACHE now, since changes in
1197 * SECTOR_SIZE_1K may invalidate it
1198 */
1199 for (i = 0; i < FC_WORDS; i++)
1200 ctrl->flash_cache[i] = brcmnand_read_fc(ctrl, i);
c26211d3
BN		 1201
1202 brcmnand_soc_data_bus_unprepare(ctrl->soc);
1203
27c5b17c
BN		 1204 /* Cleanup from HW quirk: restore SECTOR_SIZE_1K */
1205 if (host->hwcfg.sector_size_1k)
1206 brcmnand_set_sector_size_1k(host,
1207 host->hwcfg.sector_size_1k);
1208 }
1209
1210 /* Re-enable protection is necessary only after erase */
1211 if (command == NAND_CMD_ERASE1)
1212 brcmnand_wp(mtd, 1);
1213}
1214
1215static uint8_t brcmnand_read_byte(struct mtd_info *mtd)
1216{
1217 struct nand_chip *chip = mtd->priv;
1218 struct brcmnand_host *host = chip->priv;
1219 struct brcmnand_controller *ctrl = host->ctrl;
1220 uint8_t ret = 0;
1221 int addr, offs;
1222
1223 switch (host->last_cmd) {
1224 case NAND_CMD_READID:
1225 if (host->last_byte < 4)
1226 ret = brcmnand_read_reg(ctrl, BRCMNAND_ID) >>
1227 (24 - (host->last_byte << 3));
1228 else if (host->last_byte < 8)
1229 ret = brcmnand_read_reg(ctrl, BRCMNAND_ID_EXT) >>
1230 (56 - (host->last_byte << 3));
1231 break;
1232
1233 case NAND_CMD_READOOB:
1234 ret = oob_reg_read(ctrl, host->last_byte);
1235 break;
1236
1237 case NAND_CMD_STATUS:
1238 ret = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
1239 INTFC_FLASH_STATUS;
1240 if (wp_on) /* hide WP status */
1241 ret |= NAND_STATUS_WP;
1242 break;
1243
1244 case NAND_CMD_PARAM:
1245 case NAND_CMD_RNDOUT:
1246 addr = host->last_addr + host->last_byte;
1247 offs = addr & (FC_BYTES - 1);
1248
1249 /* At FC_BYTES boundary, switch to next column */
1250 if (host->last_byte > 0 && offs == 0)
1251 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, addr, -1);
1252
1253 ret = ctrl->flash_cache[offs >> 2] >>
1254 (24 - ((offs & 0x03) << 3));
1255 break;
1256 case NAND_CMD_GET_FEATURES:
1257 if (host->last_byte >= ONFI_SUBFEATURE_PARAM_LEN) {
1258 ret = 0;
1259 } else {
1260 bool last = host->last_byte ==
1261 ONFI_SUBFEATURE_PARAM_LEN - 1;
1262 brcmnand_low_level_op(host, LL_OP_RD, 0, last);
1263 ret = brcmnand_read_reg(ctrl, BRCMNAND_LL_RDATA) & 0xff;
1264 }
1265 }
1266
1267 dev_dbg(ctrl->dev, "read byte = 0x%02x\n", ret);
1268 host->last_byte++;
1269
1270 return ret;
1271}
1272
1273static void brcmnand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1274{
1275 int i;
1276
1277 for (i = 0; i < len; i++, buf++)
1278 *buf = brcmnand_read_byte(mtd);
1279}
1280
1281static void brcmnand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
1282 int len)
1283{
1284 int i;
1285 struct nand_chip *chip = mtd->priv;
1286 struct brcmnand_host *host = chip->priv;
1287
1288 switch (host->last_cmd) {
1289 case NAND_CMD_SET_FEATURES:
1290 for (i = 0; i < len; i++)
1291 brcmnand_low_level_op(host, LL_OP_WR, buf[i],
1292 (i + 1) == len);
1293 break;
1294 default:
1295 BUG();
1296 break;
1297 }
1298}
1299
1300/**
1301 * Construct a FLASH_DMA descriptor as part of a linked list. You must know the
1302 * following ahead of time:
1303 * - Is this descriptor the beginning or end of a linked list?
1304 * - What is the (DMA) address of the next descriptor in the linked list?
1305 */
1306static int brcmnand_fill_dma_desc(struct brcmnand_host *host,
1307 struct brcm_nand_dma_desc *desc, u64 addr,
1308 dma_addr_t buf, u32 len, u8 dma_cmd,
1309 bool begin, bool end,
1310 dma_addr_t next_desc)
1311{
1312 memset(desc, 0, sizeof(*desc));
1313 /* Descriptors are written in native byte order (wordwise) */
1314 desc->next_desc = lower_32_bits(next_desc);
1315 desc->next_desc_ext = upper_32_bits(next_desc);
1316 desc->cmd_irq = (dma_cmd << 24) |
1317 (end ? (0x03 << 8) : 0) | /* IRQ | STOP */
1318 (!!begin) | ((!!end) << 1); /* head, tail */
1319#ifdef CONFIG_CPU_BIG_ENDIAN
1320 desc->cmd_irq |= 0x01 << 12;
1321#endif
1322 desc->dram_addr = lower_32_bits(buf);
1323 desc->dram_addr_ext = upper_32_bits(buf);
1324 desc->tfr_len = len;
1325 desc->total_len = len;
1326 desc->flash_addr = lower_32_bits(addr);
1327 desc->flash_addr_ext = upper_32_bits(addr);
1328 desc->cs = host->cs;
1329 desc->status_valid = 0x01;
1330 return 0;
1331}
1332
1333/**
1334 * Kick the FLASH_DMA engine, with a given DMA descriptor
1335 */
1336static void brcmnand_dma_run(struct brcmnand_host *host, dma_addr_t desc)
1337{
1338 struct brcmnand_controller *ctrl = host->ctrl;
1339 unsigned long timeo = msecs_to_jiffies(100);
1340
1341 flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC, lower_32_bits(desc));
1342 (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC);
1343 flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT, upper_32_bits(desc));
1344 (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT);
1345
1346 /* Start FLASH_DMA engine */
1347 ctrl->dma_pending = true;
1348 mb(); /* flush previous writes */
1349 flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0x03); /* wake | run */
1350
1351 if (wait_for_completion_timeout(&ctrl->dma_done, timeo) <= 0) {
1352 dev_err(ctrl->dev,
1353 "timeout waiting for DMA; status %#x, error status %#x\n",
1354 flash_dma_readl(ctrl, FLASH_DMA_STATUS),
1355 flash_dma_readl(ctrl, FLASH_DMA_ERROR_STATUS));
1356 }
1357 ctrl->dma_pending = false;
1358 flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0); /* force stop */
1359}
1360
1361static int brcmnand_dma_trans(struct brcmnand_host *host, u64 addr, u32 *buf,
1362 u32 len, u8 dma_cmd)
1363{
1364 struct brcmnand_controller *ctrl = host->ctrl;
1365 dma_addr_t buf_pa;
1366 int dir = dma_cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1367
1368 buf_pa = dma_map_single(ctrl->dev, buf, len, dir);
1369 if (dma_mapping_error(ctrl->dev, buf_pa)) {
1370 dev_err(ctrl->dev, "unable to map buffer for DMA\n");
1371 return -ENOMEM;
1372 }
1373
1374 brcmnand_fill_dma_desc(host, ctrl->dma_desc, addr, buf_pa, len,
1375 dma_cmd, true, true, 0);
1376
1377 brcmnand_dma_run(host, ctrl->dma_pa);
1378
1379 dma_unmap_single(ctrl->dev, buf_pa, len, dir);
1380
1381 if (ctrl->dma_desc->status_valid & FLASH_DMA_ECC_ERROR)
1382 return -EBADMSG;
1383 else if (ctrl->dma_desc->status_valid & FLASH_DMA_CORR_ERROR)
1384 return -EUCLEAN;
1385
1386 return 0;
1387}
1388
1389/*
1390 * Assumes proper CS is already set
1391 */
1392static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip,
1393 u64 addr, unsigned int trans, u32 *buf,
1394 u8 *oob, u64 *err_addr)
1395{
1396 struct brcmnand_host *host = chip->priv;
1397 struct brcmnand_controller *ctrl = host->ctrl;
1398 int i, j, ret = 0;
1399
1400 /* Clear error addresses */
1401 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_ADDR, 0);
1402 brcmnand_write_reg(ctrl, BRCMNAND_CORR_ADDR, 0);
1403
1404 brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1405 (host->cs << 16) | ((addr >> 32) & 0xffff));
1406 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1407
1408 for (i = 0; i < trans; i++, addr += FC_BYTES) {
1409 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
1410 lower_32_bits(addr));
1411 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1412 /* SPARE_AREA_READ does not use ECC, so just use PAGE_READ */
1413 brcmnand_send_cmd(host, CMD_PAGE_READ);
1414 brcmnand_waitfunc(mtd, chip);
1415
c26211d3
BN		 1416 if (likely(buf)) {
1417 brcmnand_soc_data_bus_prepare(ctrl->soc);
1418
27c5b17c
BN		 1419 for (j = 0; j < FC_WORDS; j++, buf++)
1420 *buf = brcmnand_read_fc(ctrl, j);
1421
c26211d3
BN		 1422 brcmnand_soc_data_bus_unprepare(ctrl->soc);
1423 }
1424
27c5b17c
BN		 1425 if (oob)
1426 oob += read_oob_from_regs(ctrl, i, oob,
1427 mtd->oobsize / trans,
1428 host->hwcfg.sector_size_1k);
1429
1430 if (!ret) {
1431 *err_addr = brcmnand_read_reg(ctrl,
1432 BRCMNAND_UNCORR_ADDR) |
1433 ((u64)(brcmnand_read_reg(ctrl,
1434 BRCMNAND_UNCORR_EXT_ADDR)
1435 & 0xffff) << 32);
1436 if (*err_addr)
1437 ret = -EBADMSG;
1438 }
1439
1440 if (!ret) {
1441 *err_addr = brcmnand_read_reg(ctrl,
1442 BRCMNAND_CORR_ADDR) |
1443 ((u64)(brcmnand_read_reg(ctrl,
1444 BRCMNAND_CORR_EXT_ADDR)
1445 & 0xffff) << 32);
1446 if (*err_addr)
1447 ret = -EUCLEAN;
1448 }
1449 }
1450
1451 return ret;
1452}
1453
1454static int brcmnand_read(struct mtd_info *mtd, struct nand_chip *chip,
1455 u64 addr, unsigned int trans, u32 *buf, u8 *oob)
1456{
1457 struct brcmnand_host *host = chip->priv;
1458 struct brcmnand_controller *ctrl = host->ctrl;
1459 u64 err_addr = 0;
1460 int err;
1461
1462 dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf);
1463
1464 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_COUNT, 0);
1465
1466 if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
1467 err = brcmnand_dma_trans(host, addr, buf, trans * FC_BYTES,
1468 CMD_PAGE_READ);
1469 if (err) {
1470 if (mtd_is_bitflip_or_eccerr(err))
1471 err_addr = addr;
1472 else
1473 return -EIO;
1474 }
1475 } else {
1476 if (oob)
1477 memset(oob, 0x99, mtd->oobsize);
1478
1479 err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf,
1480 oob, &err_addr);
1481 }
1482
1483 if (mtd_is_eccerr(err)) {
1484 dev_dbg(ctrl->dev, "uncorrectable error at 0x%llx\n",
1485 (unsigned long long)err_addr);
1486 mtd->ecc_stats.failed++;
1487 /* NAND layer expects zero on ECC errors */
1488 return 0;
1489 }
1490
1491 if (mtd_is_bitflip(err)) {
1492 unsigned int corrected = brcmnand_count_corrected(ctrl);
1493
1494 dev_dbg(ctrl->dev, "corrected error at 0x%llx\n",
1495 (unsigned long long)err_addr);
1496 mtd->ecc_stats.corrected += corrected;
1497 /* Always exceed the software-imposed threshold */
1498 return max(mtd->bitflip_threshold, corrected);
1499 }
1500
1501 return 0;
1502}
1503
1504static int brcmnand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1505 uint8_t *buf, int oob_required, int page)
1506{
1507 struct brcmnand_host *host = chip->priv;
1508 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
1509
1510 return brcmnand_read(mtd, chip, host->last_addr,
1511 mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
1512}
1513
1514static int brcmnand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1515 uint8_t *buf, int oob_required, int page)
1516{
1517 struct brcmnand_host *host = chip->priv;
1518 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
1519 int ret;
1520
1521 brcmnand_set_ecc_enabled(host, 0);
1522 ret = brcmnand_read(mtd, chip, host->last_addr,
1523 mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
1524 brcmnand_set_ecc_enabled(host, 1);
1525 return ret;
1526}
1527
1528static int brcmnand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
1529 int page)
1530{
1531 return brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
1532 mtd->writesize >> FC_SHIFT,
1533 NULL, (u8 *)chip->oob_poi);
1534}
1535
1536static int brcmnand_read_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
1537 int page)
1538{
1539 struct brcmnand_host *host = chip->priv;
1540
1541 brcmnand_set_ecc_enabled(host, 0);
1542 brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
1543 mtd->writesize >> FC_SHIFT,
1544 NULL, (u8 *)chip->oob_poi);
1545 brcmnand_set_ecc_enabled(host, 1);
1546 return 0;
1547}
1548
1549static int brcmnand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1550 uint32_t data_offs, uint32_t readlen,
1551 uint8_t *bufpoi, int page)
1552{
1553 struct brcmnand_host *host = chip->priv;
1554
1555 return brcmnand_read(mtd, chip, host->last_addr + data_offs,
1556 readlen >> FC_SHIFT, (u32 *)bufpoi, NULL);
1557}
1558
1559static int brcmnand_write(struct mtd_info *mtd, struct nand_chip *chip,
1560 u64 addr, const u32 *buf, u8 *oob)
1561{
1562 struct brcmnand_host *host = chip->priv;
1563 struct brcmnand_controller *ctrl = host->ctrl;
1564 unsigned int i, j, trans = mtd->writesize >> FC_SHIFT;
1565 int status, ret = 0;
1566
1567 dev_dbg(ctrl->dev, "write %llx <- %p\n", (unsigned long long)addr, buf);
1568
3f08b8ba 1569 if (unlikely((unsigned long)buf & 0x03)) {
27c5b17c 1570 dev_warn(ctrl->dev, "unaligned buffer: %p\n", buf);
3f08b8ba 1571 buf = (u32 *)((unsigned long)buf & ~0x03);
27c5b17c
BN		 1572 }
1573
1574 brcmnand_wp(mtd, 0);
1575
1576 for (i = 0; i < ctrl->max_oob; i += 4)
1577 oob_reg_write(ctrl, i, 0xffffffff);
1578
1579 if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
1580 if (brcmnand_dma_trans(host, addr, (u32 *)buf,
1581 mtd->writesize, CMD_PROGRAM_PAGE))
1582 ret = -EIO;
1583 goto out;
1584 }
1585
1586 brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1587 (host->cs << 16) | ((addr >> 32) & 0xffff));
1588 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1589
1590 for (i = 0; i < trans; i++, addr += FC_BYTES) {
1591 /* full address MUST be set before populating FC */
1592 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
1593 lower_32_bits(addr));
1594 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1595
c26211d3
BN		 1596 if (buf) {
1597 brcmnand_soc_data_bus_prepare(ctrl->soc);
1598
27c5b17c
BN		 1599 for (j = 0; j < FC_WORDS; j++, buf++)
1600 brcmnand_write_fc(ctrl, j, *buf);
c26211d3
BN		 1601
1602 brcmnand_soc_data_bus_unprepare(ctrl->soc);
1603 } else if (oob) {
27c5b17c
BN		 1604 for (j = 0; j < FC_WORDS; j++)
1605 brcmnand_write_fc(ctrl, j, 0xffffffff);
c26211d3 1606 }
27c5b17c
BN		 1607
1608 if (oob) {
1609 oob += write_oob_to_regs(ctrl, i, oob,
1610 mtd->oobsize / trans,
1611 host->hwcfg.sector_size_1k);
1612 }
1613
1614 /* we cannot use SPARE_AREA_PROGRAM when PARTIAL_PAGE_EN=0 */
1615 brcmnand_send_cmd(host, CMD_PROGRAM_PAGE);
1616 status = brcmnand_waitfunc(mtd, chip);
1617
1618 if (status & NAND_STATUS_FAIL) {
1619 dev_info(ctrl->dev, "program failed at %llx\n",
1620 (unsigned long long)addr);
1621 ret = -EIO;
1622 goto out;
1623 }
1624 }
1625out:
1626 brcmnand_wp(mtd, 1);
1627 return ret;
1628}
1629
1630static int brcmnand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
45aaeff9 1631 const uint8_t *buf, int oob_required, int page)
27c5b17c
BN		 1632{
1633 struct brcmnand_host *host = chip->priv;
1634 void *oob = oob_required ? chip->oob_poi : NULL;
1635
1636 brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
1637 return 0;
1638}
1639
1640static int brcmnand_write_page_raw(struct mtd_info *mtd,
1641 struct nand_chip *chip, const uint8_t *buf,
45aaeff9 1642 int oob_required, int page)
27c5b17c
BN		 1643{
1644 struct brcmnand_host *host = chip->priv;
1645 void *oob = oob_required ? chip->oob_poi : NULL;
1646
1647 brcmnand_set_ecc_enabled(host, 0);
1648 brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
1649 brcmnand_set_ecc_enabled(host, 1);
1650 return 0;
1651}
1652
1653static int brcmnand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
1654 int page)
1655{
1656 return brcmnand_write(mtd, chip, (u64)page << chip->page_shift,
1657 NULL, chip->oob_poi);
1658}
1659
1660static int brcmnand_write_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
1661 int page)
1662{
1663 struct brcmnand_host *host = chip->priv;
1664 int ret;
1665
1666 brcmnand_set_ecc_enabled(host, 0);
1667 ret = brcmnand_write(mtd, chip, (u64)page << chip->page_shift, NULL,
1668 (u8 *)chip->oob_poi);
1669 brcmnand_set_ecc_enabled(host, 1);
1670
1671 return ret;
1672}
1673
1674/***********************************************************************
1675 * Per-CS setup (1 NAND device)
1676 ***********************************************************************/
1677
1678static int brcmnand_set_cfg(struct brcmnand_host *host,
1679 struct brcmnand_cfg *cfg)
1680{
1681 struct brcmnand_controller *ctrl = host->ctrl;
1682 struct nand_chip *chip = &host->chip;
1683 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
1684 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
1685 BRCMNAND_CS_CFG_EXT);
1686 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
1687 BRCMNAND_CS_ACC_CONTROL);
1688 u8 block_size = 0, page_size = 0, device_size = 0;
1689 u32 tmp;
1690
1691 if (ctrl->block_sizes) {
1692 int i, found;
1693
1694 for (i = 0, found = 0; ctrl->block_sizes[i]; i++)
1695 if (ctrl->block_sizes[i] * 1024 == cfg->block_size) {
1696 block_size = i;
1697 found = 1;
1698 }
1699 if (!found) {
1700 dev_warn(ctrl->dev, "invalid block size %u\n",
1701 cfg->block_size);
1702 return -EINVAL;
1703 }
1704 } else {
1705 block_size = ffs(cfg->block_size) - ffs(BRCMNAND_MIN_BLOCKSIZE);
1706 }
1707
1708 if (cfg->block_size < BRCMNAND_MIN_BLOCKSIZE || (ctrl->max_block_size &&
1709 cfg->block_size > ctrl->max_block_size)) {
1710 dev_warn(ctrl->dev, "invalid block size %u\n",
1711 cfg->block_size);
1712 block_size = 0;
1713 }
1714
1715 if (ctrl->page_sizes) {
1716 int i, found;
1717
1718 for (i = 0, found = 0; ctrl->page_sizes[i]; i++)
1719 if (ctrl->page_sizes[i] == cfg->page_size) {
1720 page_size = i;
1721 found = 1;
1722 }
1723 if (!found) {
1724 dev_warn(ctrl->dev, "invalid page size %u\n",
1725 cfg->page_size);
1726 return -EINVAL;
1727 }
1728 } else {
1729 page_size = ffs(cfg->page_size) - ffs(BRCMNAND_MIN_PAGESIZE);
1730 }
1731
1732 if (cfg->page_size < BRCMNAND_MIN_PAGESIZE || (ctrl->max_page_size &&
1733 cfg->page_size > ctrl->max_page_size)) {
1734 dev_warn(ctrl->dev, "invalid page size %u\n", cfg->page_size);
1735 return -EINVAL;
1736 }
1737
1738 if (fls64(cfg->device_size) < fls64(BRCMNAND_MIN_DEVSIZE)) {
1739 dev_warn(ctrl->dev, "invalid device size 0x%llx\n",
1740 (unsigned long long)cfg->device_size);
1741 return -EINVAL;
1742 }
1743 device_size = fls64(cfg->device_size) - fls64(BRCMNAND_MIN_DEVSIZE);
1744
3f06d2a9
BN		 1745 tmp = (cfg->blk_adr_bytes << CFG_BLK_ADR_BYTES_SHIFT) |
1746 (cfg->col_adr_bytes << CFG_COL_ADR_BYTES_SHIFT) |
1747 (cfg->ful_adr_bytes << CFG_FUL_ADR_BYTES_SHIFT) |
1748 (!!(cfg->device_width == 16) << CFG_BUS_WIDTH_SHIFT) |
1749 (device_size << CFG_DEVICE_SIZE_SHIFT);
27c5b17c 1750 if (cfg_offs == cfg_ext_offs) {
3f06d2a9
BN		 1751 tmp |= (page_size << CFG_PAGE_SIZE_SHIFT) |
1752 (block_size << CFG_BLK_SIZE_SHIFT);
27c5b17c
BN		 1753 nand_writereg(ctrl, cfg_offs, tmp);
1754 } else {
1755 nand_writereg(ctrl, cfg_offs, tmp);
3f06d2a9
BN		 1756 tmp = (page_size << CFG_EXT_PAGE_SIZE_SHIFT) |
1757 (block_size << CFG_EXT_BLK_SIZE_SHIFT);
27c5b17c
BN		 1758 nand_writereg(ctrl, cfg_ext_offs, tmp);
1759 }
1760
1761 tmp = nand_readreg(ctrl, acc_control_offs);
1762 tmp &= ~brcmnand_ecc_level_mask(ctrl);
1763 tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
1764 tmp &= ~brcmnand_spare_area_mask(ctrl);
1765 tmp |= cfg->spare_area_size;
1766 nand_writereg(ctrl, acc_control_offs, tmp);
1767
1768 brcmnand_set_sector_size_1k(host, cfg->sector_size_1k);
1769
1770 /* threshold = ceil(BCH-level * 0.75) */
1771 brcmnand_wr_corr_thresh(host, DIV_ROUND_UP(chip->ecc.strength * 3, 4));
1772
1773 return 0;
1774}
1775
1776static void brcmnand_print_cfg(char *buf, struct brcmnand_cfg *cfg)
1777{
1778 buf += sprintf(buf,
1779 "%lluMiB total, %uKiB blocks, %u%s pages, %uB OOB, %u-bit",
1780 (unsigned long long)cfg->device_size >> 20,
1781 cfg->block_size >> 10,
1782 cfg->page_size >= 1024 ? cfg->page_size >> 10 : cfg->page_size,
1783 cfg->page_size >= 1024 ? "KiB" : "B",
1784 cfg->spare_area_size, cfg->device_width);
1785
1786 /* Account for Hamming ECC and for BCH 512B vs 1KiB sectors */
1787 if (is_hamming_ecc(cfg))
1788 sprintf(buf, ", Hamming ECC");
1789 else if (cfg->sector_size_1k)
1790 sprintf(buf, ", BCH-%u (1KiB sector)", cfg->ecc_level << 1);
1791 else
80204124 1792 sprintf(buf, ", BCH-%u", cfg->ecc_level);
27c5b17c
BN		 1793}
1794
1795/*
1796 * Minimum number of bytes to address a page. Calculated as:
1797 * roundup(log2(size / page-size) / 8)
1798 *
1799 * NB: the following does not "round up" for non-power-of-2 'size'; but this is
1800 * OK because many other things will break if 'size' is irregular...
1801 */
1802static inline int get_blk_adr_bytes(u64 size, u32 writesize)
1803{
1804 return ALIGN(ilog2(size) - ilog2(writesize), 8) >> 3;
1805}
1806
1807static int brcmnand_setup_dev(struct brcmnand_host *host)
1808{
1809 struct mtd_info *mtd = &host->mtd;
1810 struct nand_chip *chip = &host->chip;
1811 struct brcmnand_controller *ctrl = host->ctrl;
1812 struct brcmnand_cfg *cfg = &host->hwcfg;
1813 char msg[128];
1814 u32 offs, tmp, oob_sector;
1815 int ret;
1816
1817 memset(cfg, 0, sizeof(*cfg));
1818
61528d88
MV		 1819 ret = of_property_read_u32(chip->flash_node,
1820 "brcm,nand-oob-sector-size",
27c5b17c
BN		 1821 &oob_sector);
1822 if (ret) {
1823 /* Use detected size */
1824 cfg->spare_area_size = mtd->oobsize /
1825 (mtd->writesize >> FC_SHIFT);
1826 } else {
1827 cfg->spare_area_size = oob_sector;
1828 }
1829 if (cfg->spare_area_size > ctrl->max_oob)
1830 cfg->spare_area_size = ctrl->max_oob;
1831 /*
1832 * Set oobsize to be consistent with controller's spare_area_size, as
1833 * the rest is inaccessible.
1834 */
1835 mtd->oobsize = cfg->spare_area_size * (mtd->writesize >> FC_SHIFT);
1836
1837 cfg->device_size = mtd->size;
1838 cfg->block_size = mtd->erasesize;
1839 cfg->page_size = mtd->writesize;
1840 cfg->device_width = (chip->options & NAND_BUSWIDTH_16) ? 16 : 8;
1841 cfg->col_adr_bytes = 2;
1842 cfg->blk_adr_bytes = get_blk_adr_bytes(mtd->size, mtd->writesize);
1843
1844 switch (chip->ecc.size) {
1845 case 512:
1846 if (chip->ecc.strength == 1) /* Hamming */
1847 cfg->ecc_level = 15;
1848 else
1849 cfg->ecc_level = chip->ecc.strength;
1850 cfg->sector_size_1k = 0;
1851 break;
1852 case 1024:
1853 if (!(ctrl->features & BRCMNAND_HAS_1K_SECTORS)) {
1854 dev_err(ctrl->dev, "1KB sectors not supported\n");
1855 return -EINVAL;
1856 }
1857 if (chip->ecc.strength & 0x1) {
1858 dev_err(ctrl->dev,
1859 "odd ECC not supported with 1KB sectors\n");
1860 return -EINVAL;
1861 }
1862
1863 cfg->ecc_level = chip->ecc.strength >> 1;
1864 cfg->sector_size_1k = 1;
1865 break;
1866 default:
1867 dev_err(ctrl->dev, "unsupported ECC size: %d\n",
1868 chip->ecc.size);
1869 return -EINVAL;
1870 }
1871
1872 cfg->ful_adr_bytes = cfg->blk_adr_bytes;
1873 if (mtd->writesize > 512)
1874 cfg->ful_adr_bytes += cfg->col_adr_bytes;
1875 else
1876 cfg->ful_adr_bytes += 1;
1877
1878 ret = brcmnand_set_cfg(host, cfg);
1879 if (ret)
1880 return ret;
1881
1882 brcmnand_set_ecc_enabled(host, 1);
1883
1884 brcmnand_print_cfg(msg, cfg);
1885 dev_info(ctrl->dev, "detected %s\n", msg);
1886
1887 /* Configure ACC_CONTROL */
1888 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
1889 tmp = nand_readreg(ctrl, offs);
1890 tmp &= ~ACC_CONTROL_PARTIAL_PAGE;
1891 tmp &= ~ACC_CONTROL_RD_ERASED;
1892 tmp &= ~ACC_CONTROL_FAST_PGM_RDIN;
1893 if (ctrl->features & BRCMNAND_HAS_PREFETCH) {
1894 /*
1895 * FIXME: Flash DMA + prefetch may see spurious erased-page ECC
1896 * errors
1897 */
1898 if (has_flash_dma(ctrl))
1899 tmp &= ~ACC_CONTROL_PREFETCH;
1900 else
1901 tmp |= ACC_CONTROL_PREFETCH;
1902 }
1903 nand_writereg(ctrl, offs, tmp);
1904
1905 return 0;
1906}
1907
1908static int brcmnand_init_cs(struct brcmnand_host *host)
1909{
1910 struct brcmnand_controller *ctrl = host->ctrl;
1911 struct device_node *dn = host->of_node;
1912 struct platform_device *pdev = host->pdev;
1913 struct mtd_info *mtd;
1914 struct nand_chip *chip;
5e65d48b 1915 int ret;
4d1ea982 1916 u16 cfg_offs;
27c5b17c
BN		 1917 struct mtd_part_parser_data ppdata = { .of_node = dn };
1918
1919 ret = of_property_read_u32(dn, "reg", &host->cs);
1920 if (ret) {
1921 dev_err(&pdev->dev, "can't get chip-select\n");
1922 return -ENXIO;
1923 }
1924
1925 mtd = &host->mtd;
1926 chip = &host->chip;
1927
63752199 1928 nand_set_flash_node(chip, dn);
27c5b17c
BN		 1929 chip->priv = host;
1930 mtd->priv = chip;
1931 mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "brcmnand.%d",
1932 host->cs);
1933 mtd->owner = THIS_MODULE;
1934 mtd->dev.parent = &pdev->dev;
1935
1936 chip->IO_ADDR_R = (void __iomem *)0xdeadbeef;
1937 chip->IO_ADDR_W = (void __iomem *)0xdeadbeef;
1938
1939 chip->cmd_ctrl = brcmnand_cmd_ctrl;
1940 chip->cmdfunc = brcmnand_cmdfunc;
1941 chip->waitfunc = brcmnand_waitfunc;
1942 chip->read_byte = brcmnand_read_byte;
1943 chip->read_buf = brcmnand_read_buf;
1944 chip->write_buf = brcmnand_write_buf;
1945
1946 chip->ecc.mode = NAND_ECC_HW;
1947 chip->ecc.read_page = brcmnand_read_page;
1948 chip->ecc.read_subpage = brcmnand_read_subpage;
1949 chip->ecc.write_page = brcmnand_write_page;
1950 chip->ecc.read_page_raw = brcmnand_read_page_raw;
1951 chip->ecc.write_page_raw = brcmnand_write_page_raw;
1952 chip->ecc.write_oob_raw = brcmnand_write_oob_raw;
1953 chip->ecc.read_oob_raw = brcmnand_read_oob_raw;
1954 chip->ecc.read_oob = brcmnand_read_oob;
1955 chip->ecc.write_oob = brcmnand_write_oob;
1956
1957 chip->controller = &ctrl->controller;
1958
4d1ea982
AP		 1959 /*
1960 * The bootloader might have configured 16bit mode but
1961 * NAND READID command only works in 8bit mode. We force
1962 * 8bit mode here to ensure that NAND READID commands works.
1963 */
1964 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
1965 nand_writereg(ctrl, cfg_offs,
1966 nand_readreg(ctrl, cfg_offs) & ~CFG_BUS_WIDTH);
1967
27c5b17c
BN		 1968 if (nand_scan_ident(mtd, 1, NULL))
1969 return -ENXIO;
1970
1971 chip->options |= NAND_NO_SUBPAGE_WRITE;
1972 /*
1973 * Avoid (for instance) kmap()'d buffers from JFFS2, which we can't DMA
1974 * to/from, and have nand_base pass us a bounce buffer instead, as
1975 * needed.
1976 */
1977 chip->options |= NAND_USE_BOUNCE_BUFFER;
1978
1979 if (of_get_nand_on_flash_bbt(dn))
1980 chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
1981
1982 if (brcmnand_setup_dev(host))
1983 return -ENXIO;
1984
1985 chip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512;
1986 /* only use our internal HW threshold */
1987 mtd->bitflip_threshold = 1;
1988
1989 chip->ecc.layout = brcmstb_choose_ecc_layout(host);
1990 if (!chip->ecc.layout)
1991 return -ENXIO;
1992
1993 if (nand_scan_tail(mtd))
1994 return -ENXIO;
1995
1996 return mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
1997}
1998
1999static void brcmnand_save_restore_cs_config(struct brcmnand_host *host,
2000 int restore)
2001{
2002 struct brcmnand_controller *ctrl = host->ctrl;
2003 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
2004 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
2005 BRCMNAND_CS_CFG_EXT);
2006 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
2007 BRCMNAND_CS_ACC_CONTROL);
2008 u16 t1_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING1);
2009 u16 t2_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING2);
2010
2011 if (restore) {
2012 nand_writereg(ctrl, cfg_offs, host->hwcfg.config);
2013 if (cfg_offs != cfg_ext_offs)
2014 nand_writereg(ctrl, cfg_ext_offs,
2015 host->hwcfg.config_ext);
2016 nand_writereg(ctrl, acc_control_offs, host->hwcfg.acc_control);
2017 nand_writereg(ctrl, t1_offs, host->hwcfg.timing_1);
2018 nand_writereg(ctrl, t2_offs, host->hwcfg.timing_2);
2019 } else {
2020 host->hwcfg.config = nand_readreg(ctrl, cfg_offs);
2021 if (cfg_offs != cfg_ext_offs)
2022 host->hwcfg.config_ext =
2023 nand_readreg(ctrl, cfg_ext_offs);
2024 host->hwcfg.acc_control = nand_readreg(ctrl, acc_control_offs);
2025 host->hwcfg.timing_1 = nand_readreg(ctrl, t1_offs);
2026 host->hwcfg.timing_2 = nand_readreg(ctrl, t2_offs);
2027 }
2028}
2029
2030static int brcmnand_suspend(struct device *dev)
2031{
2032 struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
2033 struct brcmnand_host *host;
2034
2035 list_for_each_entry(host, &ctrl->host_list, node)
2036 brcmnand_save_restore_cs_config(host, 0);
2037
2038 ctrl->nand_cs_nand_select = brcmnand_read_reg(ctrl, BRCMNAND_CS_SELECT);
2039 ctrl->nand_cs_nand_xor = brcmnand_read_reg(ctrl, BRCMNAND_CS_XOR);
2040 ctrl->corr_stat_threshold =
2041 brcmnand_read_reg(ctrl, BRCMNAND_CORR_THRESHOLD);
2042
2043 if (has_flash_dma(ctrl))
2044 ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE);
2045
2046 return 0;
2047}
2048
2049static int brcmnand_resume(struct device *dev)
2050{
2051 struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
2052 struct brcmnand_host *host;
2053
2054 if (has_flash_dma(ctrl)) {
2055 flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode);
2056 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
2057 }
2058
2059 brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select);
2060 brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, ctrl->nand_cs_nand_xor);
2061 brcmnand_write_reg(ctrl, BRCMNAND_CORR_THRESHOLD,
2062 ctrl->corr_stat_threshold);
c26211d3
BN		 2063 if (ctrl->soc) {
2064 /* Clear/re-enable interrupt */
2065 ctrl->soc->ctlrdy_ack(ctrl->soc);
2066 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
2067 }
27c5b17c
BN		 2068
2069 list_for_each_entry(host, &ctrl->host_list, node) {
2070 struct mtd_info *mtd = &host->mtd;
2071 struct nand_chip *chip = mtd->priv;
2072
2073 brcmnand_save_restore_cs_config(host, 1);
2074
2075 /* Reset the chip, required by some chips after power-up */
2076 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2077 }
2078
2079 return 0;
2080}
2081
2082const struct dev_pm_ops brcmnand_pm_ops = {
2083 .suspend = brcmnand_suspend,
2084 .resume = brcmnand_resume,
2085};
2086EXPORT_SYMBOL_GPL(brcmnand_pm_ops);
2087
2088static const struct of_device_id brcmnand_of_match[] = {
2089 { .compatible = "brcm,brcmnand-v4.0" },
2090 { .compatible = "brcm,brcmnand-v5.0" },
2091 { .compatible = "brcm,brcmnand-v6.0" },
2092 { .compatible = "brcm,brcmnand-v6.1" },
2093 { .compatible = "brcm,brcmnand-v7.0" },
2094 { .compatible = "brcm,brcmnand-v7.1" },
2095 {},
2096};
2097MODULE_DEVICE_TABLE(of, brcmnand_of_match);
2098
2099/***********************************************************************
2100 * Platform driver setup (per controller)
2101 ***********************************************************************/
2102
2103int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
2104{
2105 struct device *dev = &pdev->dev;
2106 struct device_node *dn = dev->of_node, *child;
bcb83a19 2107 struct brcmnand_controller *ctrl;
27c5b17c
BN		 2108 struct resource *res;
2109 int ret;
2110
2111 /* We only support device-tree instantiation */
2112 if (!dn)
2113 return -ENODEV;
2114
2115 if (!of_match_node(brcmnand_of_match, dn))
2116 return -ENODEV;
2117
2118 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
2119 if (!ctrl)
2120 return -ENOMEM;
2121
2122 dev_set_drvdata(dev, ctrl);
2123 ctrl->dev = dev;
2124
2125 init_completion(&ctrl->done);
2126 init_completion(&ctrl->dma_done);
2127 spin_lock_init(&ctrl->controller.lock);
2128 init_waitqueue_head(&ctrl->controller.wq);
2129 INIT_LIST_HEAD(&ctrl->host_list);
2130
2131 /* NAND register range */
2132 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2133 ctrl->nand_base = devm_ioremap_resource(dev, res);
2134 if (IS_ERR(ctrl->nand_base))
2135 return PTR_ERR(ctrl->nand_base);
2136
2137 /* Initialize NAND revision */
2138 ret = brcmnand_revision_init(ctrl);
2139 if (ret)
2140 return ret;
2141
2142 /*
2143 * Most chips have this cache at a fixed offset within 'nand' block.
2144 * Some must specify this region separately.
2145 */
2146 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-cache");
2147 if (res) {
2148 ctrl->nand_fc = devm_ioremap_resource(dev, res);
2149 if (IS_ERR(ctrl->nand_fc))
2150 return PTR_ERR(ctrl->nand_fc);
2151 } else {
2152 ctrl->nand_fc = ctrl->nand_base +
2153 ctrl->reg_offsets[BRCMNAND_FC_BASE];
2154 }
2155
2156 /* FLASH_DMA */
2157 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-dma");
2158 if (res) {
2159 ctrl->flash_dma_base = devm_ioremap_resource(dev, res);
2160 if (IS_ERR(ctrl->flash_dma_base))
2161 return PTR_ERR(ctrl->flash_dma_base);
2162
2163 flash_dma_writel(ctrl, FLASH_DMA_MODE, 1); /* linked-list */
2164 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
2165
2166 /* Allocate descriptor(s) */
2167 ctrl->dma_desc = dmam_alloc_coherent(dev,
2168 sizeof(*ctrl->dma_desc),
2169 &ctrl->dma_pa, GFP_KERNEL);
2170 if (!ctrl->dma_desc)
2171 return -ENOMEM;
2172
2173 ctrl->dma_irq = platform_get_irq(pdev, 1);
2174 if ((int)ctrl->dma_irq < 0) {
2175 dev_err(dev, "missing FLASH_DMA IRQ\n");
2176 return -ENODEV;
2177 }
2178
2179 ret = devm_request_irq(dev, ctrl->dma_irq,
2180 brcmnand_dma_irq, 0, DRV_NAME,
2181 ctrl);
2182 if (ret < 0) {
2183 dev_err(dev, "can't allocate IRQ %d: error %d\n",
2184 ctrl->dma_irq, ret);
2185 return ret;
2186 }
2187
2188 dev_info(dev, "enabling FLASH_DMA\n");
2189 }
2190
2191 /* Disable automatic device ID config, direct addressing */
2192 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT,
2193 CS_SELECT_AUTO_DEVICE_ID_CFG | 0xff, 0, 0);
2194 /* Disable XOR addressing */
2195 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_XOR, 0xff, 0, 0);
2196
2197 if (ctrl->features & BRCMNAND_HAS_WP) {
2198 /* Permanently disable write protection */
2199 if (wp_on == 2)
2200 brcmnand_set_wp(ctrl, false);
2201 } else {
2202 wp_on = 0;
2203 }
2204
2205 /* IRQ */
2206 ctrl->irq = platform_get_irq(pdev, 0);
2207 if ((int)ctrl->irq < 0) {
2208 dev_err(dev, "no IRQ defined\n");
2209 return -ENODEV;
2210 }
2211
c26211d3
BN		 2212 /*
2213 * Some SoCs integrate this controller (e.g., its interrupt bits) in
2214 * interesting ways
2215 */
2216 if (soc) {
2217 ctrl->soc = soc;
2218
2219 ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0,
2220 DRV_NAME, ctrl);
2221
2222 /* Enable interrupt */
2223 ctrl->soc->ctlrdy_ack(ctrl->soc);
2224 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
2225 } else {
2226 /* Use standard interrupt infrastructure */
2227 ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0,
2228 DRV_NAME, ctrl);
2229 }
27c5b17c
BN		 2230 if (ret < 0) {
2231 dev_err(dev, "can't allocate IRQ %d: error %d\n",
2232 ctrl->irq, ret);
2233 return ret;
2234 }
2235
2236 for_each_available_child_of_node(dn, child) {
2237 if (of_device_is_compatible(child, "brcm,nandcs")) {
2238 struct brcmnand_host *host;
2239
2240 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
2241 if (!host)
2242 return -ENOMEM;
2243 host->pdev = pdev;
2244 host->ctrl = ctrl;
2245 host->of_node = child;
2246
2247 ret = brcmnand_init_cs(host);
2248 if (ret)
2249 continue; /* Try all chip-selects */
2250
2251 list_add_tail(&host->node, &ctrl->host_list);
2252 }
2253 }
2254
2255 /* No chip-selects could initialize properly */
2256 if (list_empty(&ctrl->host_list))
2257 return -ENODEV;
2258
2259 return 0;
2260}
2261EXPORT_SYMBOL_GPL(brcmnand_probe);
2262
2263int brcmnand_remove(struct platform_device *pdev)
2264{
2265 struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev);
2266 struct brcmnand_host *host;
2267
2268 list_for_each_entry(host, &ctrl->host_list, node)
2269 nand_release(&host->mtd);
2270
2271 dev_set_drvdata(&pdev->dev, NULL);
2272
2273 return 0;
2274}
2275EXPORT_SYMBOL_GPL(brcmnand_remove);
2276
2277MODULE_LICENSE("GPL v2");
2278MODULE_AUTHOR("Kevin Cernekee");
2279MODULE_AUTHOR("Brian Norris");
2280MODULE_DESCRIPTION("NAND driver for Broadcom chips");
2281MODULE_ALIAS("platform:brcmnand");
Linux kernel - Deliverables
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