projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 27c5b17c BN |
1 | /* |
| 2 | * Copyright © 2015 Broadcom Corporation | |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or modify | |
| 5 | * it under the terms of the GNU General Public License version 2 as | |
| 6 | * published by the Free Software Foundation. | |
| 7 | * | |
| 8 | * This program is distributed in the hope that it will be useful, | |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 11 | * GNU General Public License for more details. | |
| 12 | */ | |
| 13 | ||
| 14 | #ifndef __BRCMNAND_H__ | |
| 15 | #define __BRCMNAND_H__ | |
| 16 | ||
| 17 | #include <linux/types.h> | |
| 18 | #include <linux/io.h> | |
| 19 | ||
| 20 | struct platform_device; | |
| 21 | struct dev_pm_ops; | |
| 22 | ||
| 23 | struct brcmnand_soc { | |
| c26211d3 BN |
24 | bool (*ctlrdy_ack)(struct brcmnand_soc *soc); |
| 25 | void (*ctlrdy_set_enabled)(struct brcmnand_soc *soc, bool en); | |
| 26 | void (*prepare_data_bus)(struct brcmnand_soc *soc, bool prepare); | |
| 27c5b17c BN |
27 | }; |
| 28 | ||
| c26211d3 BN |
29 | static inline void brcmnand_soc_data_bus_prepare(struct brcmnand_soc *soc) |
| 30 | { | |
| 31 | if (soc && soc->prepare_data_bus) | |
| 32 | soc->prepare_data_bus(soc, true); | |
| 33 | } | |
| 34 | ||
| 35 | static inline void brcmnand_soc_data_bus_unprepare(struct brcmnand_soc *soc) | |
| 36 | { | |
| 37 | if (soc && soc->prepare_data_bus) | |
| 38 | soc->prepare_data_bus(soc, false); | |
| 39 | } | |
| 40 | ||
| 27c5b17c BN |
41 | static inline u32 brcmnand_readl(void __iomem *addr) |
| 42 | { | |
| 43 | /* | |
| 44 | * MIPS endianness is configured by boot strap, which also reverses all | |
| 45 | * bus endianness (i.e., big-endian CPU + big endian bus ==> native | |
| 46 | * endian I/O). | |
| 47 | * | |
| 48 | * Other architectures (e.g., ARM) either do not support big endian, or | |
| 49 | * else leave I/O in little endian mode. | |
| 50 | */ | |
| ddb2c42b | 51 | if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) |
| 27c5b17c BN |
52 | return __raw_readl(addr); |
| 53 | else | |
| 54 | return readl_relaxed(addr); | |
| 55 | } | |
| 56 | ||
| 57 | static inline void brcmnand_writel(u32 val, void __iomem *addr) | |
| 58 | { | |
| 59 | /* See brcmnand_readl() comments */ | |
| ddb2c42b | 60 | if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) |
| 27c5b17c BN |
61 | __raw_writel(val, addr); |
| 62 | else | |
| 63 | writel_relaxed(val, addr); | |
| 64 | } | |
| 65 | ||
| 66 | int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc); | |
| 67 | int brcmnand_remove(struct platform_device *pdev); | |
| 68 | ||
| 69 | extern const struct dev_pm_ops brcmnand_pm_ops; | |
| 70 | ||
| 71 | #endif /* __BRCMNAND_H__ */ |