Commit | Line | Data |
---|---|---|
c9ac5977 | 1 | /* |
fbad5696 | 2 | * Driver for One Laptop Per Child ‘CAFÉ’ controller, aka Marvell 88ALP01 |
5467fb02 DW |
3 | * |
4 | * Copyright © 2006 Red Hat, Inc. | |
5 | * Copyright © 2006 David Woodhouse <dwmw2@infradead.org> | |
6 | */ | |
7 | ||
8dd851de | 8 | #define DEBUG |
5467fb02 DW |
9 | |
10 | #include <linux/device.h> | |
11 | #undef DEBUG | |
12 | #include <linux/mtd/mtd.h> | |
13 | #include <linux/mtd/nand.h> | |
14 | #include <linux/pci.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/interrupt.h> | |
a1274302 | 17 | #include <linux/dma-mapping.h> |
5467fb02 DW |
18 | #include <asm/io.h> |
19 | ||
20 | #define CAFE_NAND_CTRL1 0x00 | |
21 | #define CAFE_NAND_CTRL2 0x04 | |
22 | #define CAFE_NAND_CTRL3 0x08 | |
23 | #define CAFE_NAND_STATUS 0x0c | |
24 | #define CAFE_NAND_IRQ 0x10 | |
25 | #define CAFE_NAND_IRQ_MASK 0x14 | |
26 | #define CAFE_NAND_DATA_LEN 0x18 | |
27 | #define CAFE_NAND_ADDR1 0x1c | |
28 | #define CAFE_NAND_ADDR2 0x20 | |
29 | #define CAFE_NAND_TIMING1 0x24 | |
30 | #define CAFE_NAND_TIMING2 0x28 | |
31 | #define CAFE_NAND_TIMING3 0x2c | |
32 | #define CAFE_NAND_NONMEM 0x30 | |
04459d7c | 33 | #define CAFE_NAND_ECC_RESULT 0x3C |
fbad5696 DW |
34 | #define CAFE_NAND_DMA_CTRL 0x40 |
35 | #define CAFE_NAND_DMA_ADDR0 0x44 | |
36 | #define CAFE_NAND_DMA_ADDR1 0x48 | |
04459d7c DW |
37 | #define CAFE_NAND_ECC_SYN01 0x50 |
38 | #define CAFE_NAND_ECC_SYN23 0x54 | |
39 | #define CAFE_NAND_ECC_SYN45 0x58 | |
40 | #define CAFE_NAND_ECC_SYN67 0x5c | |
5467fb02 DW |
41 | #define CAFE_NAND_READ_DATA 0x1000 |
42 | #define CAFE_NAND_WRITE_DATA 0x2000 | |
43 | ||
195a253b DW |
44 | #define CAFE_GLOBAL_CTRL 0x3004 |
45 | #define CAFE_GLOBAL_IRQ 0x3008 | |
46 | #define CAFE_GLOBAL_IRQ_MASK 0x300c | |
47 | #define CAFE_NAND_RESET 0x3034 | |
48 | ||
04459d7c DW |
49 | int cafe_correct_ecc(unsigned char *buf, |
50 | unsigned short *chk_syndrome_list); | |
51 | ||
5467fb02 DW |
52 | struct cafe_priv { |
53 | struct nand_chip nand; | |
54 | struct pci_dev *pdev; | |
55 | void __iomem *mmio; | |
56 | uint32_t ctl1; | |
57 | uint32_t ctl2; | |
58 | int datalen; | |
59 | int nr_data; | |
60 | int data_pos; | |
61 | int page_addr; | |
62 | dma_addr_t dmaaddr; | |
63 | unsigned char *dmabuf; | |
5467fb02 DW |
64 | }; |
65 | ||
b478c775 | 66 | static int usedma = 1; |
5467fb02 DW |
67 | module_param(usedma, int, 0644); |
68 | ||
8dd851de DW |
69 | static int skipbbt = 0; |
70 | module_param(skipbbt, int, 0644); | |
71 | ||
72 | static int debug = 0; | |
73 | module_param(debug, int, 0644); | |
74 | ||
be8444bd DW |
75 | static int regdebug = 0; |
76 | module_param(regdebug, int, 0644); | |
77 | ||
b478c775 | 78 | static int checkecc = 1; |
470b0a90 DW |
79 | module_param(checkecc, int, 0644); |
80 | ||
b478c775 DW |
81 | static int slowtiming = 0; |
82 | module_param(slowtiming, int, 0644); | |
83 | ||
04459d7c | 84 | /* Hrm. Why isn't this already conditional on something in the struct device? */ |
8dd851de DW |
85 | #define cafe_dev_dbg(dev, args...) do { if (debug) dev_dbg(dev, ##args); } while(0) |
86 | ||
195a253b DW |
87 | /* Make it easier to switch to PIO if we need to */ |
88 | #define cafe_readl(cafe, addr) readl((cafe)->mmio + CAFE_##addr) | |
89 | #define cafe_writel(cafe, datum, addr) writel(datum, (cafe)->mmio + CAFE_##addr) | |
8dd851de | 90 | |
5467fb02 DW |
91 | static int cafe_device_ready(struct mtd_info *mtd) |
92 | { | |
93 | struct cafe_priv *cafe = mtd->priv; | |
195a253b DW |
94 | int result = !!(cafe_readl(cafe, NAND_STATUS) | 0x40000000); |
95 | uint32_t irqs = cafe_readl(cafe, NAND_IRQ); | |
fbad5696 | 96 | |
195a253b | 97 | cafe_writel(cafe, irqs, NAND_IRQ); |
fbad5696 | 98 | |
8dd851de | 99 | cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n", |
195a253b DW |
100 | result?"":" not", irqs, cafe_readl(cafe, NAND_IRQ), |
101 | cafe_readl(cafe, GLOBAL_IRQ), cafe_readl(cafe, GLOBAL_IRQ_MASK)); | |
fbad5696 | 102 | |
5467fb02 DW |
103 | return result; |
104 | } | |
105 | ||
106 | ||
107 | static void cafe_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) | |
108 | { | |
109 | struct cafe_priv *cafe = mtd->priv; | |
110 | ||
111 | if (usedma) | |
112 | memcpy(cafe->dmabuf + cafe->datalen, buf, len); | |
113 | else | |
114 | memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len); | |
fbad5696 | 115 | |
5467fb02 DW |
116 | cafe->datalen += len; |
117 | ||
8dd851de | 118 | cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes to write buffer. datalen 0x%x\n", |
5467fb02 DW |
119 | len, cafe->datalen); |
120 | } | |
121 | ||
122 | static void cafe_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) | |
123 | { | |
124 | struct cafe_priv *cafe = mtd->priv; | |
125 | ||
126 | if (usedma) | |
127 | memcpy(buf, cafe->dmabuf + cafe->datalen, len); | |
128 | else | |
129 | memcpy_fromio(buf, cafe->mmio + CAFE_NAND_READ_DATA + cafe->datalen, len); | |
130 | ||
8dd851de | 131 | cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes from position 0x%x in read buffer.\n", |
5467fb02 DW |
132 | len, cafe->datalen); |
133 | cafe->datalen += len; | |
134 | } | |
135 | ||
136 | static uint8_t cafe_read_byte(struct mtd_info *mtd) | |
137 | { | |
138 | struct cafe_priv *cafe = mtd->priv; | |
139 | uint8_t d; | |
140 | ||
141 | cafe_read_buf(mtd, &d, 1); | |
8dd851de | 142 | cafe_dev_dbg(&cafe->pdev->dev, "Read %02x\n", d); |
5467fb02 DW |
143 | |
144 | return d; | |
145 | } | |
146 | ||
147 | static void cafe_nand_cmdfunc(struct mtd_info *mtd, unsigned command, | |
148 | int column, int page_addr) | |
149 | { | |
150 | struct cafe_priv *cafe = mtd->priv; | |
151 | int adrbytes = 0; | |
152 | uint32_t ctl1; | |
153 | uint32_t doneint = 0x80000000; | |
5467fb02 | 154 | |
8dd851de | 155 | cafe_dev_dbg(&cafe->pdev->dev, "cmdfunc %02x, 0x%x, 0x%x\n", |
5467fb02 DW |
156 | command, column, page_addr); |
157 | ||
158 | if (command == NAND_CMD_ERASE2 || command == NAND_CMD_PAGEPROG) { | |
159 | /* Second half of a command we already calculated */ | |
195a253b | 160 | cafe_writel(cafe, cafe->ctl2 | 0x100 | command, NAND_CTRL2); |
5467fb02 | 161 | ctl1 = cafe->ctl1; |
cad40654 | 162 | cafe->ctl2 &= ~(1<<30); |
8dd851de | 163 | cafe_dev_dbg(&cafe->pdev->dev, "Continue command, ctl1 %08x, #data %d\n", |
5467fb02 DW |
164 | cafe->ctl1, cafe->nr_data); |
165 | goto do_command; | |
166 | } | |
167 | /* Reset ECC engine */ | |
195a253b | 168 | cafe_writel(cafe, 0, NAND_CTRL2); |
5467fb02 DW |
169 | |
170 | /* Emulate NAND_CMD_READOOB on large-page chips */ | |
171 | if (mtd->writesize > 512 && | |
172 | command == NAND_CMD_READOOB) { | |
173 | column += mtd->writesize; | |
174 | command = NAND_CMD_READ0; | |
175 | } | |
176 | ||
177 | /* FIXME: Do we need to send read command before sending data | |
178 | for small-page chips, to position the buffer correctly? */ | |
179 | ||
180 | if (column != -1) { | |
195a253b | 181 | cafe_writel(cafe, column, NAND_ADDR1); |
5467fb02 DW |
182 | adrbytes = 2; |
183 | if (page_addr != -1) | |
184 | goto write_adr2; | |
185 | } else if (page_addr != -1) { | |
195a253b | 186 | cafe_writel(cafe, page_addr & 0xffff, NAND_ADDR1); |
5467fb02 DW |
187 | page_addr >>= 16; |
188 | write_adr2: | |
195a253b | 189 | cafe_writel(cafe, page_addr, NAND_ADDR2); |
5467fb02 DW |
190 | adrbytes += 2; |
191 | if (mtd->size > mtd->writesize << 16) | |
192 | adrbytes++; | |
193 | } | |
194 | ||
195 | cafe->data_pos = cafe->datalen = 0; | |
196 | ||
197 | /* Set command valid bit */ | |
198 | ctl1 = 0x80000000 | command; | |
199 | ||
200 | /* Set RD or WR bits as appropriate */ | |
201 | if (command == NAND_CMD_READID || command == NAND_CMD_STATUS) { | |
202 | ctl1 |= (1<<26); /* rd */ | |
203 | /* Always 5 bytes, for now */ | |
8dd851de | 204 | cafe->datalen = 4; |
5467fb02 DW |
205 | /* And one address cycle -- even for STATUS, since the controller doesn't work without */ |
206 | adrbytes = 1; | |
207 | } else if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 || | |
208 | command == NAND_CMD_READOOB || command == NAND_CMD_RNDOUT) { | |
209 | ctl1 |= 1<<26; /* rd */ | |
210 | /* For now, assume just read to end of page */ | |
211 | cafe->datalen = mtd->writesize + mtd->oobsize - column; | |
212 | } else if (command == NAND_CMD_SEQIN) | |
213 | ctl1 |= 1<<25; /* wr */ | |
214 | ||
215 | /* Set number of address bytes */ | |
216 | if (adrbytes) | |
217 | ctl1 |= ((adrbytes-1)|8) << 27; | |
218 | ||
219 | if (command == NAND_CMD_SEQIN || command == NAND_CMD_ERASE1) { | |
c9ac5977 | 220 | /* Ignore the first command of a pair; the hardware |
5467fb02 DW |
221 | deals with them both at once, later */ |
222 | cafe->ctl1 = ctl1; | |
8dd851de | 223 | cafe_dev_dbg(&cafe->pdev->dev, "Setup for delayed command, ctl1 %08x, dlen %x\n", |
5467fb02 DW |
224 | cafe->ctl1, cafe->datalen); |
225 | return; | |
226 | } | |
227 | /* RNDOUT and READ0 commands need a following byte */ | |
228 | if (command == NAND_CMD_RNDOUT) | |
195a253b | 229 | cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, NAND_CTRL2); |
5467fb02 | 230 | else if (command == NAND_CMD_READ0 && mtd->writesize > 512) |
195a253b | 231 | cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2); |
5467fb02 DW |
232 | |
233 | do_command: | |
c9ac5977 | 234 | cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n", |
195a253b | 235 | cafe->datalen, ctl1, cafe_readl(cafe, NAND_CTRL2)); |
fbad5696 | 236 | |
5467fb02 | 237 | /* NB: The datasheet lies -- we really should be subtracting 1 here */ |
195a253b DW |
238 | cafe_writel(cafe, cafe->datalen, NAND_DATA_LEN); |
239 | cafe_writel(cafe, 0x90000000, NAND_IRQ); | |
5467fb02 DW |
240 | if (usedma && (ctl1 & (3<<25))) { |
241 | uint32_t dmactl = 0xc0000000 + cafe->datalen; | |
242 | /* If WR or RD bits set, set up DMA */ | |
243 | if (ctl1 & (1<<26)) { | |
244 | /* It's a read */ | |
245 | dmactl |= (1<<29); | |
246 | /* ... so it's done when the DMA is done, not just | |
247 | the command. */ | |
248 | doneint = 0x10000000; | |
249 | } | |
195a253b | 250 | cafe_writel(cafe, dmactl, NAND_DMA_CTRL); |
5467fb02 | 251 | } |
5467fb02 DW |
252 | cafe->datalen = 0; |
253 | ||
be8444bd DW |
254 | if (unlikely(regdebug)) { |
255 | int i; | |
256 | printk("About to write command %08x to register 0\n", ctl1); | |
257 | for (i=4; i< 0x5c; i+=4) | |
258 | printk("Register %x: %08x\n", i, readl(cafe->mmio + i)); | |
fbad5696 | 259 | } |
be8444bd | 260 | |
195a253b | 261 | cafe_writel(cafe, ctl1, NAND_CTRL1); |
5467fb02 DW |
262 | /* Apply this short delay always to ensure that we do wait tWB in |
263 | * any case on any machine. */ | |
264 | ndelay(100); | |
265 | ||
266 | if (1) { | |
8dd851de | 267 | int c = 500000; |
5467fb02 DW |
268 | uint32_t irqs; |
269 | ||
270 | while (c--) { | |
195a253b | 271 | irqs = cafe_readl(cafe, NAND_IRQ); |
5467fb02 DW |
272 | if (irqs & doneint) |
273 | break; | |
274 | udelay(1); | |
8dd851de DW |
275 | if (!(c % 100000)) |
276 | cafe_dev_dbg(&cafe->pdev->dev, "Wait for ready, IRQ %x\n", irqs); | |
5467fb02 DW |
277 | cpu_relax(); |
278 | } | |
195a253b | 279 | cafe_writel(cafe, doneint, NAND_IRQ); |
a020727b | 280 | cafe_dev_dbg(&cafe->pdev->dev, "Command %x completed after %d usec, irqs %x (%x)\n", |
195a253b | 281 | command, 500000-c, irqs, cafe_readl(cafe, NAND_IRQ)); |
5467fb02 DW |
282 | } |
283 | ||
cad40654 | 284 | WARN_ON(cafe->ctl2 & (1<<30)); |
5467fb02 DW |
285 | |
286 | switch (command) { | |
287 | ||
288 | case NAND_CMD_CACHEDPROG: | |
289 | case NAND_CMD_PAGEPROG: | |
290 | case NAND_CMD_ERASE1: | |
291 | case NAND_CMD_ERASE2: | |
292 | case NAND_CMD_SEQIN: | |
293 | case NAND_CMD_RNDIN: | |
294 | case NAND_CMD_STATUS: | |
295 | case NAND_CMD_DEPLETE1: | |
296 | case NAND_CMD_RNDOUT: | |
297 | case NAND_CMD_STATUS_ERROR: | |
298 | case NAND_CMD_STATUS_ERROR0: | |
299 | case NAND_CMD_STATUS_ERROR1: | |
300 | case NAND_CMD_STATUS_ERROR2: | |
301 | case NAND_CMD_STATUS_ERROR3: | |
195a253b | 302 | cafe_writel(cafe, cafe->ctl2, NAND_CTRL2); |
5467fb02 DW |
303 | return; |
304 | } | |
305 | nand_wait_ready(mtd); | |
195a253b | 306 | cafe_writel(cafe, cafe->ctl2, NAND_CTRL2); |
5467fb02 DW |
307 | } |
308 | ||
309 | static void cafe_select_chip(struct mtd_info *mtd, int chipnr) | |
310 | { | |
311 | //struct cafe_priv *cafe = mtd->priv; | |
8dd851de | 312 | // cafe_dev_dbg(&cafe->pdev->dev, "select_chip %d\n", chipnr); |
5467fb02 | 313 | } |
fbad5696 | 314 | |
28bdd4a7 | 315 | static int cafe_nand_interrupt(int irq, void *id) |
5467fb02 DW |
316 | { |
317 | struct mtd_info *mtd = id; | |
318 | struct cafe_priv *cafe = mtd->priv; | |
195a253b DW |
319 | uint32_t irqs = cafe_readl(cafe, NAND_IRQ); |
320 | cafe_writel(cafe, irqs & ~0x90000000, NAND_IRQ); | |
5467fb02 DW |
321 | if (!irqs) |
322 | return IRQ_NONE; | |
323 | ||
195a253b | 324 | cafe_dev_dbg(&cafe->pdev->dev, "irq, bits %x (%x)\n", irqs, cafe_readl(cafe, NAND_IRQ)); |
5467fb02 DW |
325 | return IRQ_HANDLED; |
326 | } | |
327 | ||
328 | static void cafe_nand_bug(struct mtd_info *mtd) | |
329 | { | |
330 | BUG(); | |
331 | } | |
332 | ||
333 | static int cafe_nand_write_oob(struct mtd_info *mtd, | |
334 | struct nand_chip *chip, int page) | |
335 | { | |
336 | int status = 0; | |
337 | ||
5467fb02 DW |
338 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); |
339 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
340 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
341 | status = chip->waitfunc(mtd, chip); | |
342 | ||
343 | return status & NAND_STATUS_FAIL ? -EIO : 0; | |
344 | } | |
345 | ||
346 | /* Don't use -- use nand_read_oob_std for now */ | |
347 | static int cafe_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, | |
348 | int page, int sndcmd) | |
349 | { | |
350 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); | |
351 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
352 | return 1; | |
353 | } | |
354 | /** | |
355 | * cafe_nand_read_page_syndrome - {REPLACABLE] hardware ecc syndrom based page read | |
356 | * @mtd: mtd info structure | |
357 | * @chip: nand chip info structure | |
358 | * @buf: buffer to store read data | |
359 | * | |
360 | * The hw generator calculates the error syndrome automatically. Therefor | |
361 | * we need a special oob layout and handling. | |
362 | */ | |
363 | static int cafe_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip, | |
364 | uint8_t *buf) | |
365 | { | |
366 | struct cafe_priv *cafe = mtd->priv; | |
367 | ||
fbad5696 | 368 | cafe_dev_dbg(&cafe->pdev->dev, "ECC result %08x SYN1,2 %08x\n", |
195a253b DW |
369 | cafe_readl(cafe, NAND_ECC_RESULT), |
370 | cafe_readl(cafe, NAND_ECC_SYN01)); | |
5467fb02 DW |
371 | |
372 | chip->read_buf(mtd, buf, mtd->writesize); | |
373 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
374 | ||
195a253b | 375 | if (checkecc && cafe_readl(cafe, NAND_ECC_RESULT) & (1<<18)) { |
04459d7c DW |
376 | unsigned short syn[8]; |
377 | int i; | |
378 | ||
379 | for (i=0; i<8; i+=2) { | |
195a253b | 380 | uint32_t tmp = cafe_readl(cafe, NAND_ECC_SYN01 + (i*2)); |
04459d7c DW |
381 | syn[i] = tmp & 0xfff; |
382 | syn[i+1] = (tmp >> 16) & 0xfff; | |
c9ac5977 | 383 | } |
04459d7c | 384 | |
63a14237 | 385 | if ((i = cafe_correct_ecc(buf, syn)) < 0) { |
be8444bd DW |
386 | dev_dbg(&cafe->pdev->dev, "Failed to correct ECC at %08x\n", |
387 | cafe_readl(cafe, NAND_ADDR2) * 2048); | |
388 | for (i=0; i< 0x5c; i+=4) | |
389 | printk("Register %x: %08x\n", i, readl(cafe->mmio + i)); | |
04459d7c DW |
390 | mtd->ecc_stats.failed++; |
391 | } else { | |
392 | dev_dbg(&cafe->pdev->dev, "Corrected %d symbol errors\n", i); | |
393 | mtd->ecc_stats.corrected += i; | |
394 | } | |
395 | } | |
396 | ||
397 | ||
5467fb02 DW |
398 | return 0; |
399 | } | |
400 | ||
8dd851de DW |
401 | static struct nand_ecclayout cafe_oobinfo_2048 = { |
402 | .eccbytes = 14, | |
403 | .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, | |
404 | .oobfree = {{14, 50}} | |
405 | }; | |
406 | ||
c9ac5977 | 407 | /* Ick. The BBT code really ought to be able to work this bit out |
fbad5696 DW |
408 | for itself from the above, at least for the 2KiB case */ |
409 | static uint8_t cafe_bbt_pattern_2048[] = { 'B', 'b', 't', '0' }; | |
410 | static uint8_t cafe_mirror_pattern_2048[] = { '1', 't', 'b', 'B' }; | |
411 | ||
412 | static uint8_t cafe_bbt_pattern_512[] = { 0xBB }; | |
413 | static uint8_t cafe_mirror_pattern_512[] = { 0xBC }; | |
414 | ||
8dd851de DW |
415 | |
416 | static struct nand_bbt_descr cafe_bbt_main_descr_2048 = { | |
417 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
418 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
419 | .offs = 14, | |
420 | .len = 4, | |
421 | .veroffs = 18, | |
422 | .maxblocks = 4, | |
fbad5696 | 423 | .pattern = cafe_bbt_pattern_2048 |
8dd851de DW |
424 | }; |
425 | ||
426 | static struct nand_bbt_descr cafe_bbt_mirror_descr_2048 = { | |
427 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
428 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
429 | .offs = 14, | |
430 | .len = 4, | |
431 | .veroffs = 18, | |
432 | .maxblocks = 4, | |
fbad5696 | 433 | .pattern = cafe_mirror_pattern_2048 |
8dd851de DW |
434 | }; |
435 | ||
436 | static struct nand_ecclayout cafe_oobinfo_512 = { | |
437 | .eccbytes = 14, | |
438 | .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, | |
439 | .oobfree = {{14, 2}} | |
440 | }; | |
441 | ||
fbad5696 DW |
442 | static struct nand_bbt_descr cafe_bbt_main_descr_512 = { |
443 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
444 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
445 | .offs = 14, | |
446 | .len = 1, | |
447 | .veroffs = 15, | |
448 | .maxblocks = 4, | |
449 | .pattern = cafe_bbt_pattern_512 | |
450 | }; | |
451 | ||
452 | static struct nand_bbt_descr cafe_bbt_mirror_descr_512 = { | |
453 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
454 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
455 | .offs = 14, | |
456 | .len = 1, | |
457 | .veroffs = 15, | |
458 | .maxblocks = 4, | |
459 | .pattern = cafe_mirror_pattern_512 | |
460 | }; | |
461 | ||
462 | ||
5467fb02 DW |
463 | static void cafe_nand_write_page_lowlevel(struct mtd_info *mtd, |
464 | struct nand_chip *chip, const uint8_t *buf) | |
465 | { | |
466 | struct cafe_priv *cafe = mtd->priv; | |
467 | ||
5467fb02 | 468 | chip->write_buf(mtd, buf, mtd->writesize); |
8dd851de | 469 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); |
5467fb02 DW |
470 | |
471 | /* Set up ECC autogeneration */ | |
cad40654 | 472 | cafe->ctl2 |= (1<<30); |
5467fb02 DW |
473 | } |
474 | ||
475 | static int cafe_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, | |
476 | const uint8_t *buf, int page, int cached, int raw) | |
477 | { | |
478 | int status; | |
479 | ||
5467fb02 DW |
480 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); |
481 | ||
482 | if (unlikely(raw)) | |
483 | chip->ecc.write_page_raw(mtd, chip, buf); | |
484 | else | |
485 | chip->ecc.write_page(mtd, chip, buf); | |
486 | ||
487 | /* | |
488 | * Cached progamming disabled for now, Not sure if its worth the | |
489 | * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s) | |
490 | */ | |
491 | cached = 0; | |
492 | ||
493 | if (!cached || !(chip->options & NAND_CACHEPRG)) { | |
494 | ||
495 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
496 | status = chip->waitfunc(mtd, chip); | |
497 | /* | |
498 | * See if operation failed and additional status checks are | |
499 | * available | |
500 | */ | |
501 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
502 | status = chip->errstat(mtd, chip, FL_WRITING, status, | |
503 | page); | |
504 | ||
505 | if (status & NAND_STATUS_FAIL) | |
506 | return -EIO; | |
507 | } else { | |
508 | chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1); | |
509 | status = chip->waitfunc(mtd, chip); | |
510 | } | |
511 | ||
512 | #ifdef CONFIG_MTD_NAND_VERIFY_WRITE | |
513 | /* Send command to read back the data */ | |
514 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); | |
515 | ||
516 | if (chip->verify_buf(mtd, buf, mtd->writesize)) | |
517 | return -EIO; | |
518 | #endif | |
519 | return 0; | |
520 | } | |
521 | ||
8dd851de DW |
522 | static int cafe_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) |
523 | { | |
524 | return 0; | |
525 | } | |
5467fb02 DW |
526 | |
527 | static int __devinit cafe_nand_probe(struct pci_dev *pdev, | |
528 | const struct pci_device_id *ent) | |
529 | { | |
530 | struct mtd_info *mtd; | |
531 | struct cafe_priv *cafe; | |
532 | uint32_t ctrl; | |
533 | int err = 0; | |
534 | ||
535 | err = pci_enable_device(pdev); | |
536 | if (err) | |
537 | return err; | |
538 | ||
539 | pci_set_master(pdev); | |
540 | ||
541 | mtd = kzalloc(sizeof(*mtd) + sizeof(struct cafe_priv), GFP_KERNEL); | |
542 | if (!mtd) { | |
543 | dev_warn(&pdev->dev, "failed to alloc mtd_info\n"); | |
544 | return -ENOMEM; | |
545 | } | |
546 | cafe = (void *)(&mtd[1]); | |
547 | ||
548 | mtd->priv = cafe; | |
549 | mtd->owner = THIS_MODULE; | |
550 | ||
551 | cafe->pdev = pdev; | |
552 | cafe->mmio = pci_iomap(pdev, 0, 0); | |
553 | if (!cafe->mmio) { | |
554 | dev_warn(&pdev->dev, "failed to iomap\n"); | |
555 | err = -ENOMEM; | |
556 | goto out_free_mtd; | |
557 | } | |
558 | cafe->dmabuf = dma_alloc_coherent(&cafe->pdev->dev, 2112 + sizeof(struct nand_buffers), | |
559 | &cafe->dmaaddr, GFP_KERNEL); | |
560 | if (!cafe->dmabuf) { | |
561 | err = -ENOMEM; | |
562 | goto out_ior; | |
563 | } | |
564 | cafe->nand.buffers = (void *)cafe->dmabuf + 2112; | |
565 | ||
566 | cafe->nand.cmdfunc = cafe_nand_cmdfunc; | |
567 | cafe->nand.dev_ready = cafe_device_ready; | |
568 | cafe->nand.read_byte = cafe_read_byte; | |
569 | cafe->nand.read_buf = cafe_read_buf; | |
570 | cafe->nand.write_buf = cafe_write_buf; | |
571 | cafe->nand.select_chip = cafe_select_chip; | |
572 | ||
573 | cafe->nand.chip_delay = 0; | |
574 | ||
575 | /* Enable the following for a flash based bad block table */ | |
576 | cafe->nand.options = NAND_USE_FLASH_BBT | NAND_NO_AUTOINCR | NAND_OWN_BUFFERS; | |
8dd851de DW |
577 | |
578 | if (skipbbt) { | |
579 | cafe->nand.options |= NAND_SKIP_BBTSCAN; | |
580 | cafe->nand.block_bad = cafe_nand_block_bad; | |
581 | } | |
c9ac5977 | 582 | |
dcc41bc8 | 583 | /* Start off by resetting the NAND controller completely */ |
195a253b DW |
584 | cafe_writel(cafe, 1, NAND_RESET); |
585 | cafe_writel(cafe, 0, NAND_RESET); | |
dcc41bc8 | 586 | |
195a253b | 587 | cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK); |
b478c775 | 588 | |
195a253b | 589 | /* Timings from Marvell's test code (not verified or calculated by us) */ |
b478c775 | 590 | if (!slowtiming) { |
195a253b DW |
591 | cafe_writel(cafe, 0x01010a0a, NAND_TIMING1); |
592 | cafe_writel(cafe, 0x24121212, NAND_TIMING2); | |
593 | cafe_writel(cafe, 0x11000000, NAND_TIMING3); | |
b478c775 | 594 | } else { |
195a253b DW |
595 | cafe_writel(cafe, 0xffffffff, NAND_TIMING1); |
596 | cafe_writel(cafe, 0xffffffff, NAND_TIMING2); | |
597 | cafe_writel(cafe, 0xffffffff, NAND_TIMING3); | |
b478c775 | 598 | } |
195a253b | 599 | cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK); |
5467fb02 DW |
600 | err = request_irq(pdev->irq, &cafe_nand_interrupt, SA_SHIRQ, "CAFE NAND", mtd); |
601 | if (err) { | |
602 | dev_warn(&pdev->dev, "Could not register IRQ %d\n", pdev->irq); | |
c9ac5977 | 603 | |
5467fb02 DW |
604 | goto out_free_dma; |
605 | } | |
606 | #if 1 | |
607 | /* Disable master reset, enable NAND clock */ | |
195a253b | 608 | ctrl = cafe_readl(cafe, GLOBAL_CTRL); |
5467fb02 DW |
609 | ctrl &= 0xffffeff0; |
610 | ctrl |= 0x00007000; | |
195a253b DW |
611 | cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL); |
612 | cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL); | |
613 | cafe_writel(cafe, 0, NAND_DMA_CTRL); | |
5467fb02 | 614 | |
195a253b DW |
615 | cafe_writel(cafe, 0x7006, GLOBAL_CTRL); |
616 | cafe_writel(cafe, 0x700a, GLOBAL_CTRL); | |
5467fb02 DW |
617 | |
618 | /* Set up DMA address */ | |
195a253b | 619 | cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0); |
5467fb02 | 620 | if (sizeof(cafe->dmaaddr) > 4) |
fbad5696 | 621 | /* Shift in two parts to shut the compiler up */ |
195a253b | 622 | cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1); |
5467fb02 | 623 | else |
195a253b | 624 | cafe_writel(cafe, 0, NAND_DMA_ADDR1); |
fbad5696 | 625 | |
8dd851de | 626 | cafe_dev_dbg(&cafe->pdev->dev, "Set DMA address to %x (virt %p)\n", |
195a253b | 627 | cafe_readl(cafe, NAND_DMA_ADDR0), cafe->dmabuf); |
5467fb02 DW |
628 | |
629 | /* Enable NAND IRQ in global IRQ mask register */ | |
195a253b | 630 | cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK); |
8dd851de | 631 | cafe_dev_dbg(&cafe->pdev->dev, "Control %x, IRQ mask %x\n", |
195a253b | 632 | cafe_readl(cafe, GLOBAL_CTRL), cafe_readl(cafe, GLOBAL_IRQ_MASK)); |
5467fb02 DW |
633 | #endif |
634 | #if 1 | |
635 | mtd->writesize=2048; | |
636 | mtd->oobsize = 0x40; | |
8dd851de | 637 | memset(cafe->dmabuf, 0x5a, 2112); |
5467fb02 DW |
638 | cafe->nand.cmdfunc(mtd, NAND_CMD_READID, 0, -1); |
639 | cafe->nand.read_byte(mtd); | |
640 | cafe->nand.read_byte(mtd); | |
641 | cafe->nand.read_byte(mtd); | |
642 | cafe->nand.read_byte(mtd); | |
643 | cafe->nand.read_byte(mtd); | |
644 | #endif | |
645 | #if 0 | |
646 | cafe->nand.cmdfunc(mtd, NAND_CMD_READ0, 0, 0); | |
647 | // nand_wait_ready(mtd); | |
648 | cafe->nand.read_byte(mtd); | |
649 | cafe->nand.read_byte(mtd); | |
650 | cafe->nand.read_byte(mtd); | |
651 | cafe->nand.read_byte(mtd); | |
652 | #endif | |
653 | #if 0 | |
654 | writel(0x84600070, cafe->mmio); | |
655 | udelay(10); | |
195a253b | 656 | cafe_dev_dbg(&cafe->pdev->dev, "Status %x\n", cafe_readl(cafe, NAND_NONMEM)); |
c9ac5977 | 657 | #endif |
5467fb02 DW |
658 | /* Scan to find existance of the device */ |
659 | if (nand_scan_ident(mtd, 1)) { | |
660 | err = -ENXIO; | |
661 | goto out_irq; | |
662 | } | |
663 | ||
664 | cafe->ctl2 = 1<<27; /* Reed-Solomon ECC */ | |
665 | if (mtd->writesize == 2048) | |
666 | cafe->ctl2 |= 1<<29; /* 2KiB page size */ | |
667 | ||
668 | /* Set up ECC according to the type of chip we found */ | |
fbad5696 | 669 | if (mtd->writesize == 2048) { |
8dd851de DW |
670 | cafe->nand.ecc.layout = &cafe_oobinfo_2048; |
671 | cafe->nand.bbt_td = &cafe_bbt_main_descr_2048; | |
672 | cafe->nand.bbt_md = &cafe_bbt_mirror_descr_2048; | |
fbad5696 DW |
673 | } else if (mtd->writesize == 512) { |
674 | cafe->nand.ecc.layout = &cafe_oobinfo_512; | |
675 | cafe->nand.bbt_td = &cafe_bbt_main_descr_512; | |
676 | cafe->nand.bbt_md = &cafe_bbt_mirror_descr_512; | |
5467fb02 | 677 | } else { |
fbad5696 | 678 | printk(KERN_WARNING "Unexpected NAND flash writesize %d. Aborting\n", |
5467fb02 | 679 | mtd->writesize); |
fbad5696 | 680 | goto out_irq; |
5467fb02 | 681 | } |
fbad5696 DW |
682 | cafe->nand.ecc.mode = NAND_ECC_HW_SYNDROME; |
683 | cafe->nand.ecc.size = mtd->writesize; | |
684 | cafe->nand.ecc.bytes = 14; | |
685 | cafe->nand.ecc.hwctl = (void *)cafe_nand_bug; | |
686 | cafe->nand.ecc.calculate = (void *)cafe_nand_bug; | |
687 | cafe->nand.ecc.correct = (void *)cafe_nand_bug; | |
688 | cafe->nand.write_page = cafe_nand_write_page; | |
689 | cafe->nand.ecc.write_page = cafe_nand_write_page_lowlevel; | |
690 | cafe->nand.ecc.write_oob = cafe_nand_write_oob; | |
691 | cafe->nand.ecc.read_page = cafe_nand_read_page; | |
692 | cafe->nand.ecc.read_oob = cafe_nand_read_oob; | |
5467fb02 DW |
693 | |
694 | err = nand_scan_tail(mtd); | |
695 | if (err) | |
696 | goto out_irq; | |
697 | ||
5467fb02 DW |
698 | pci_set_drvdata(pdev, mtd); |
699 | add_mtd_device(mtd); | |
700 | goto out; | |
701 | ||
702 | out_irq: | |
703 | /* Disable NAND IRQ in global IRQ mask register */ | |
195a253b | 704 | cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK); |
5467fb02 DW |
705 | free_irq(pdev->irq, mtd); |
706 | out_free_dma: | |
707 | dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr); | |
708 | out_ior: | |
709 | pci_iounmap(pdev, cafe->mmio); | |
710 | out_free_mtd: | |
711 | kfree(mtd); | |
712 | out: | |
713 | return err; | |
714 | } | |
715 | ||
716 | static void __devexit cafe_nand_remove(struct pci_dev *pdev) | |
717 | { | |
718 | struct mtd_info *mtd = pci_get_drvdata(pdev); | |
719 | struct cafe_priv *cafe = mtd->priv; | |
720 | ||
721 | del_mtd_device(mtd); | |
722 | /* Disable NAND IRQ in global IRQ mask register */ | |
195a253b | 723 | cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK); |
5467fb02 DW |
724 | free_irq(pdev->irq, mtd); |
725 | nand_release(mtd); | |
726 | pci_iounmap(pdev, cafe->mmio); | |
727 | dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr); | |
728 | kfree(mtd); | |
729 | } | |
730 | ||
731 | static struct pci_device_id cafe_nand_tbl[] = { | |
732 | { 0x11ab, 0x4100, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MEMORY_FLASH << 8, 0xFFFF0 } | |
733 | }; | |
734 | ||
735 | MODULE_DEVICE_TABLE(pci, cafe_nand_tbl); | |
736 | ||
737 | static struct pci_driver cafe_nand_pci_driver = { | |
738 | .name = "CAFÉ NAND", | |
739 | .id_table = cafe_nand_tbl, | |
740 | .probe = cafe_nand_probe, | |
741 | .remove = __devexit_p(cafe_nand_remove), | |
742 | #ifdef CONFIG_PMx | |
743 | .suspend = cafe_nand_suspend, | |
744 | .resume = cafe_nand_resume, | |
745 | #endif | |
746 | }; | |
747 | ||
748 | static int cafe_nand_init(void) | |
749 | { | |
750 | return pci_register_driver(&cafe_nand_pci_driver); | |
751 | } | |
752 | ||
753 | static void cafe_nand_exit(void) | |
754 | { | |
755 | pci_unregister_driver(&cafe_nand_pci_driver); | |
756 | } | |
757 | module_init(cafe_nand_init); | |
758 | module_exit(cafe_nand_exit); | |
759 | ||
760 | MODULE_LICENSE("GPL"); | |
761 | MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>"); | |
762 | MODULE_DESCRIPTION("NAND flash driver for OLPC CAFE chip"); | |
763 | ||
764 | /* Correct ECC for 2048 bytes of 0xff: | |
765 | 41 a0 71 65 54 27 f3 93 ec a9 be ed 0b a1 */ | |
8dd851de DW |
766 | |
767 | /* dwmw2's B-test board, in case of completely screwing it: | |
768 | Bad eraseblock 2394 at 0x12b40000 | |
769 | Bad eraseblock 2627 at 0x14860000 | |
770 | Bad eraseblock 3349 at 0x1a2a0000 | |
771 | */ |