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mtd: cafe_nand.c: use mtd_device_parse_register
[deliverable/linux.git] / drivers / mtd / nand / cafe_nand.c
CommitLineData
c9ac5977 1/*
fbad5696 2 * Driver for One Laptop Per Child ‘CAFÉ’ controller, aka Marvell 88ALP01
5467fb02 3 *
514fca43 4 * The data sheet for this device can be found at:
631dd1a8 5 * http://wiki.laptop.org/go/Datasheets
514fca43 6 *
5467fb02
DW		 7 * Copyright © 2006 Red Hat, Inc.
8 * Copyright © 2006 David Woodhouse <dwmw2@infradead.org>
9 */
10
8dd851de 11#define DEBUG
5467fb02
DW		 12
13#include <linux/device.h>
14#undef DEBUG
15#include <linux/mtd/mtd.h>
16#include <linux/mtd/nand.h>
9c37f332 17#include <linux/mtd/partitions.h>
8c61b7a7 18#include <linux/rslib.h>
5467fb02
DW		 19#include <linux/pci.h>
20#include <linux/delay.h>
21#include <linux/interrupt.h>
a1274302 22#include <linux/dma-mapping.h>
5a0e3ad6 23#include <linux/slab.h>
5467fb02
DW		 24#include <asm/io.h>
25
26#define CAFE_NAND_CTRL1 0x00
27#define CAFE_NAND_CTRL2 0x04
28#define CAFE_NAND_CTRL3 0x08
29#define CAFE_NAND_STATUS 0x0c
30#define CAFE_NAND_IRQ 0x10
31#define CAFE_NAND_IRQ_MASK 0x14
32#define CAFE_NAND_DATA_LEN 0x18
33#define CAFE_NAND_ADDR1 0x1c
34#define CAFE_NAND_ADDR2 0x20
35#define CAFE_NAND_TIMING1 0x24
36#define CAFE_NAND_TIMING2 0x28
37#define CAFE_NAND_TIMING3 0x2c
38#define CAFE_NAND_NONMEM 0x30
04459d7c 39#define CAFE_NAND_ECC_RESULT 0x3C
fbad5696
DW		 40#define CAFE_NAND_DMA_CTRL 0x40
41#define CAFE_NAND_DMA_ADDR0 0x44
42#define CAFE_NAND_DMA_ADDR1 0x48
04459d7c
DW		 43#define CAFE_NAND_ECC_SYN01 0x50
44#define CAFE_NAND_ECC_SYN23 0x54
45#define CAFE_NAND_ECC_SYN45 0x58
46#define CAFE_NAND_ECC_SYN67 0x5c
5467fb02
DW		 47#define CAFE_NAND_READ_DATA 0x1000
48#define CAFE_NAND_WRITE_DATA 0x2000
49
195a253b
DW		 50#define CAFE_GLOBAL_CTRL 0x3004
51#define CAFE_GLOBAL_IRQ 0x3008
52#define CAFE_GLOBAL_IRQ_MASK 0x300c
53#define CAFE_NAND_RESET 0x3034
54
048c37b4
DW		 55/* Missing from the datasheet: bit 19 of CTRL1 sets CE0 vs. CE1 */
56#define CTRL1_CHIPSELECT (1<<19)
57
5467fb02
DW		 58struct cafe_priv {
59 struct nand_chip nand;
60 struct pci_dev *pdev;
61 void __iomem *mmio;
8c61b7a7 62 struct rs_control *rs;
5467fb02
DW		 63 uint32_t ctl1;
64 uint32_t ctl2;
65 int datalen;
66 int nr_data;
67 int data_pos;
68 int page_addr;
69 dma_addr_t dmaaddr;
70 unsigned char *dmabuf;
5467fb02
DW		 71};
72
b478c775 73static int usedma = 1;
5467fb02
DW		 74module_param(usedma, int, 0644);
75
8dd851de
DW		 76static int skipbbt = 0;
77module_param(skipbbt, int, 0644);
78
79static int debug = 0;
80module_param(debug, int, 0644);
81
be8444bd
DW		 82static int regdebug = 0;
83module_param(regdebug, int, 0644);
84
b478c775 85static int checkecc = 1;
470b0a90
DW		 86module_param(checkecc, int, 0644);
87
64a6f950 88static unsigned int numtimings;
527a4f45
DW		 89static int timing[3];
90module_param_array(timing, int, &numtimings, 0644);
b478c775 91
68874414 92static const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL };
9c37f332 93
04459d7c 94/* Hrm. Why isn't this already conditional on something in the struct device? */
8dd851de
DW		 95#define cafe_dev_dbg(dev, args...) do { if (debug) dev_dbg(dev, ##args); } while(0)
96
195a253b
DW		 97/* Make it easier to switch to PIO if we need to */
98#define cafe_readl(cafe, addr) readl((cafe)->mmio + CAFE_##addr)
99#define cafe_writel(cafe, datum, addr) writel(datum, (cafe)->mmio + CAFE_##addr)
8dd851de 100
5467fb02
DW		 101static int cafe_device_ready(struct mtd_info *mtd)
102{
103 struct cafe_priv *cafe = mtd->priv;
195a253b
DW		 104 int result = !!(cafe_readl(cafe, NAND_STATUS) | 0x40000000);
105 uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
fbad5696 106
195a253b 107 cafe_writel(cafe, irqs, NAND_IRQ);
fbad5696 108
8dd851de 109 cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n",
195a253b
DW		 110 result?"":" not", irqs, cafe_readl(cafe, NAND_IRQ),
111 cafe_readl(cafe, GLOBAL_IRQ), cafe_readl(cafe, GLOBAL_IRQ_MASK));
fbad5696 112
5467fb02
DW		 113 return result;
114}
115
116
117static void cafe_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
118{
119 struct cafe_priv *cafe = mtd->priv;
120
121 if (usedma)
122 memcpy(cafe->dmabuf + cafe->datalen, buf, len);
123 else
124 memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len);
fbad5696 125
5467fb02
DW		 126 cafe->datalen += len;
127
8dd851de 128 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes to write buffer. datalen 0x%x\n",
5467fb02
DW		 129 len, cafe->datalen);
130}
131
132static void cafe_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
133{
134 struct cafe_priv *cafe = mtd->priv;
135
136 if (usedma)
137 memcpy(buf, cafe->dmabuf + cafe->datalen, len);
138 else
139 memcpy_fromio(buf, cafe->mmio + CAFE_NAND_READ_DATA + cafe->datalen, len);
140
8dd851de 141 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes from position 0x%x in read buffer.\n",
5467fb02
DW		 142 len, cafe->datalen);
143 cafe->datalen += len;
144}
145
146static uint8_t cafe_read_byte(struct mtd_info *mtd)
147{
148 struct cafe_priv *cafe = mtd->priv;
149 uint8_t d;
150
151 cafe_read_buf(mtd, &d, 1);
8dd851de 152 cafe_dev_dbg(&cafe->pdev->dev, "Read %02x\n", d);
5467fb02
DW		 153
154 return d;
155}
156
157static void cafe_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
158 int column, int page_addr)
159{
160 struct cafe_priv *cafe = mtd->priv;
161 int adrbytes = 0;
162 uint32_t ctl1;
163 uint32_t doneint = 0x80000000;
5467fb02 164
8dd851de 165 cafe_dev_dbg(&cafe->pdev->dev, "cmdfunc %02x, 0x%x, 0x%x\n",
5467fb02
DW		 166 command, column, page_addr);
167
168 if (command == NAND_CMD_ERASE2 || command == NAND_CMD_PAGEPROG) {
169 /* Second half of a command we already calculated */
195a253b 170 cafe_writel(cafe, cafe->ctl2 | 0x100 | command, NAND_CTRL2);
5467fb02 171 ctl1 = cafe->ctl1;
cad40654 172 cafe->ctl2 &= ~(1<<30);
8dd851de 173 cafe_dev_dbg(&cafe->pdev->dev, "Continue command, ctl1 %08x, #data %d\n",
5467fb02
DW		 174 cafe->ctl1, cafe->nr_data);
175 goto do_command;
176 }
177 /* Reset ECC engine */
195a253b 178 cafe_writel(cafe, 0, NAND_CTRL2);
5467fb02
DW		 179
180 /* Emulate NAND_CMD_READOOB on large-page chips */
181 if (mtd->writesize > 512 &&
182 command == NAND_CMD_READOOB) {
183 column += mtd->writesize;
184 command = NAND_CMD_READ0;
185 }
186
187 /* FIXME: Do we need to send read command before sending data
188 for small-page chips, to position the buffer correctly? */
189
190 if (column != -1) {
195a253b 191 cafe_writel(cafe, column, NAND_ADDR1);
5467fb02
DW		 192 adrbytes = 2;
193 if (page_addr != -1)
194 goto write_adr2;
195 } else if (page_addr != -1) {
195a253b 196 cafe_writel(cafe, page_addr & 0xffff, NAND_ADDR1);
5467fb02
DW		 197 page_addr >>= 16;
198 write_adr2:
195a253b 199 cafe_writel(cafe, page_addr, NAND_ADDR2);
5467fb02
DW		 200 adrbytes += 2;
201 if (mtd->size > mtd->writesize << 16)
202 adrbytes++;
203 }
204
205 cafe->data_pos = cafe->datalen = 0;
206
048c37b4
DW		 207 /* Set command valid bit, mask in the chip select bit */
208 ctl1 = 0x80000000 | command | (cafe->ctl1 & CTRL1_CHIPSELECT);
5467fb02
DW		 209
210 /* Set RD or WR bits as appropriate */
211 if (command == NAND_CMD_READID || command == NAND_CMD_STATUS) {
212 ctl1 |= (1<<26); /* rd */
213 /* Always 5 bytes, for now */
8dd851de 214 cafe->datalen = 4;
5467fb02
DW		 215 /* And one address cycle -- even for STATUS, since the controller doesn't work without */
216 adrbytes = 1;
217 } else if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 ||
218 command == NAND_CMD_READOOB || command == NAND_CMD_RNDOUT) {
219 ctl1 |= 1<<26; /* rd */
220 /* For now, assume just read to end of page */
221 cafe->datalen = mtd->writesize + mtd->oobsize - column;
222 } else if (command == NAND_CMD_SEQIN)
223 ctl1 |= 1<<25; /* wr */
224
225 /* Set number of address bytes */
226 if (adrbytes)
227 ctl1 |= ((adrbytes-1)|8) << 27;
228
229 if (command == NAND_CMD_SEQIN || command == NAND_CMD_ERASE1) {
c9ac5977 230 /* Ignore the first command of a pair; the hardware
5467fb02
DW		 231 deals with them both at once, later */
232 cafe->ctl1 = ctl1;
8dd851de 233 cafe_dev_dbg(&cafe->pdev->dev, "Setup for delayed command, ctl1 %08x, dlen %x\n",
5467fb02
DW		 234 cafe->ctl1, cafe->datalen);
235 return;
236 }
237 /* RNDOUT and READ0 commands need a following byte */
238 if (command == NAND_CMD_RNDOUT)
195a253b 239 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, NAND_CTRL2);
5467fb02 240 else if (command == NAND_CMD_READ0 && mtd->writesize > 512)
195a253b 241 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2);
5467fb02
DW		 242
243 do_command:
c9ac5977 244 cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n",
195a253b 245 cafe->datalen, ctl1, cafe_readl(cafe, NAND_CTRL2));
fbad5696 246
5467fb02 247 /* NB: The datasheet lies -- we really should be subtracting 1 here */
195a253b
DW		 248 cafe_writel(cafe, cafe->datalen, NAND_DATA_LEN);
249 cafe_writel(cafe, 0x90000000, NAND_IRQ);
5467fb02
DW		 250 if (usedma && (ctl1 & (3<<25))) {
251 uint32_t dmactl = 0xc0000000 + cafe->datalen;
252 /* If WR or RD bits set, set up DMA */
253 if (ctl1 & (1<<26)) {
254 /* It's a read */
255 dmactl |= (1<<29);
256 /* ... so it's done when the DMA is done, not just
257 the command. */
258 doneint = 0x10000000;
259 }
195a253b 260 cafe_writel(cafe, dmactl, NAND_DMA_CTRL);
5467fb02 261 }
5467fb02
DW		 262 cafe->datalen = 0;
263
be8444bd
DW		 264 if (unlikely(regdebug)) {
265 int i;
266 printk("About to write command %08x to register 0\n", ctl1);
267 for (i=4; i< 0x5c; i+=4)
268 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
fbad5696 269 }
be8444bd 270
195a253b 271 cafe_writel(cafe, ctl1, NAND_CTRL1);
5467fb02
DW		 272 /* Apply this short delay always to ensure that we do wait tWB in
273 * any case on any machine. */
274 ndelay(100);
275
276 if (1) {
2a7295b2 277 int c;
5467fb02
DW		 278 uint32_t irqs;
279
2a7295b2 280 for (c = 500000; c != 0; c--) {
195a253b 281 irqs = cafe_readl(cafe, NAND_IRQ);
5467fb02
DW		 282 if (irqs & doneint)
283 break;
284 udelay(1);
8dd851de
DW		 285 if (!(c % 100000))
286 cafe_dev_dbg(&cafe->pdev->dev, "Wait for ready, IRQ %x\n", irqs);
5467fb02
DW		 287 cpu_relax();
288 }
195a253b 289 cafe_writel(cafe, doneint, NAND_IRQ);
a020727b 290 cafe_dev_dbg(&cafe->pdev->dev, "Command %x completed after %d usec, irqs %x (%x)\n",
195a253b 291 command, 500000-c, irqs, cafe_readl(cafe, NAND_IRQ));
5467fb02
DW		 292 }
293
cad40654 294 WARN_ON(cafe->ctl2 & (1<<30));
5467fb02
DW		 295
296 switch (command) {
297
298 case NAND_CMD_CACHEDPROG:
299 case NAND_CMD_PAGEPROG:
300 case NAND_CMD_ERASE1:
301 case NAND_CMD_ERASE2:
302 case NAND_CMD_SEQIN:
303 case NAND_CMD_RNDIN:
304 case NAND_CMD_STATUS:
305 case NAND_CMD_DEPLETE1:
306 case NAND_CMD_RNDOUT:
307 case NAND_CMD_STATUS_ERROR:
308 case NAND_CMD_STATUS_ERROR0:
309 case NAND_CMD_STATUS_ERROR1:
310 case NAND_CMD_STATUS_ERROR2:
311 case NAND_CMD_STATUS_ERROR3:
195a253b 312 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
5467fb02
DW		 313 return;
314 }
315 nand_wait_ready(mtd);
195a253b 316 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
5467fb02
DW		 317}
318
319static void cafe_select_chip(struct mtd_info *mtd, int chipnr)
320{
048c37b4
DW		 321 struct cafe_priv *cafe = mtd->priv;
322
323 cafe_dev_dbg(&cafe->pdev->dev, "select_chip %d\n", chipnr);
324
325 /* Mask the appropriate bit into the stored value of ctl1
326 which will be used by cafe_nand_cmdfunc() */
327 if (chipnr)
328 cafe->ctl1 |= CTRL1_CHIPSELECT;
329 else
330 cafe->ctl1 &= ~CTRL1_CHIPSELECT;
5467fb02 331}
fbad5696 332
67cd724f 333static irqreturn_t cafe_nand_interrupt(int irq, void *id)
5467fb02
DW		 334{
335 struct mtd_info *mtd = id;
336 struct cafe_priv *cafe = mtd->priv;
195a253b
DW		 337 uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
338 cafe_writel(cafe, irqs & ~0x90000000, NAND_IRQ);
5467fb02
DW		 339 if (!irqs)
340 return IRQ_NONE;
341
195a253b 342 cafe_dev_dbg(&cafe->pdev->dev, "irq, bits %x (%x)\n", irqs, cafe_readl(cafe, NAND_IRQ));
5467fb02
DW		 343 return IRQ_HANDLED;
344}
345
346static void cafe_nand_bug(struct mtd_info *mtd)
347{
348 BUG();
349}
350
351static int cafe_nand_write_oob(struct mtd_info *mtd,
352 struct nand_chip *chip, int page)
353{
354 int status = 0;
355
5467fb02
DW		 356 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
357 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
358 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
359 status = chip->waitfunc(mtd, chip);
360
361 return status & NAND_STATUS_FAIL ? -EIO : 0;
362}
363
364/* Don't use -- use nand_read_oob_std for now */
365static int cafe_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
366 int page, int sndcmd)
367{
368 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
369 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
370 return 1;
371}
372/**
373 * cafe_nand_read_page_syndrome - {REPLACABLE] hardware ecc syndrom based page read
374 * @mtd: mtd info structure
375 * @chip: nand chip info structure
376 * @buf: buffer to store read data
377 *
378 * The hw generator calculates the error syndrome automatically. Therefor
379 * we need a special oob layout and handling.
380 */
381static int cafe_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 382 uint8_t *buf, int page)
5467fb02
DW		 383{
384 struct cafe_priv *cafe = mtd->priv;
385
fbad5696 386 cafe_dev_dbg(&cafe->pdev->dev, "ECC result %08x SYN1,2 %08x\n",
195a253b
DW		 387 cafe_readl(cafe, NAND_ECC_RESULT),
388 cafe_readl(cafe, NAND_ECC_SYN01));
5467fb02
DW		 389
390 chip->read_buf(mtd, buf, mtd->writesize);
391 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
392
195a253b 393 if (checkecc && cafe_readl(cafe, NAND_ECC_RESULT) & (1<<18)) {
8c61b7a7
SB		 394 unsigned short syn[8], pat[4];
395 int pos[4];
396 u8 *oob = chip->oob_poi;
397 int i, n;
04459d7c
DW		 398
399 for (i=0; i<8; i+=2) {
195a253b 400 uint32_t tmp = cafe_readl(cafe, NAND_ECC_SYN01 + (i*2));
8c61b7a7
SB		 401 syn[i] = cafe->rs->index_of[tmp & 0xfff];
402 syn[i+1] = cafe->rs->index_of[(tmp >> 16) & 0xfff];
403 }
404
405 n = decode_rs16(cafe->rs, NULL, NULL, 1367, syn, 0, pos, 0,
406 pat);
407
408 for (i = 0; i < n; i++) {
409 int p = pos[i];
410
411 /* The 12-bit symbols are mapped to bytes here */
412
413 if (p > 1374) {
414 /* out of range */
415 n = -1374;
416 } else if (p == 0) {
417 /* high four bits do not correspond to data */
418 if (pat[i] > 0xff)
419 n = -2048;
420 else
421 buf[0] ^= pat[i];
422 } else if (p == 1365) {
423 buf[2047] ^= pat[i] >> 4;
424 oob[0] ^= pat[i] << 4;
425 } else if (p > 1365) {
426 if ((p & 1) == 1) {
427 oob[3*p/2 - 2048] ^= pat[i] >> 4;
428 oob[3*p/2 - 2047] ^= pat[i] << 4;
429 } else {
430 oob[3*p/2 - 2049] ^= pat[i] >> 8;
431 oob[3*p/2 - 2048] ^= pat[i];
432 }
433 } else if ((p & 1) == 1) {
434 buf[3*p/2] ^= pat[i] >> 4;
435 buf[3*p/2 + 1] ^= pat[i] << 4;
436 } else {
437 buf[3*p/2 - 1] ^= pat[i] >> 8;
438 buf[3*p/2] ^= pat[i];
439 }
c9ac5977 440 }
04459d7c 441
8c61b7a7 442 if (n < 0) {
be8444bd
DW		 443 dev_dbg(&cafe->pdev->dev, "Failed to correct ECC at %08x\n",
444 cafe_readl(cafe, NAND_ADDR2) * 2048);
8c61b7a7 445 for (i = 0; i < 0x5c; i += 4)
be8444bd 446 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
04459d7c
DW		 447 mtd->ecc_stats.failed++;
448 } else {
8c61b7a7
SB		 449 dev_dbg(&cafe->pdev->dev, "Corrected %d symbol errors\n", n);
450 mtd->ecc_stats.corrected += n;
04459d7c
DW		 451 }
452 }
453
5467fb02
DW		 454 return 0;
455}
456
8dd851de
DW		 457static struct nand_ecclayout cafe_oobinfo_2048 = {
458 .eccbytes = 14,
459 .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
460 .oobfree = {{14, 50}}
461};
462
c9ac5977 463/* Ick. The BBT code really ought to be able to work this bit out
fbad5696
DW		 464 for itself from the above, at least for the 2KiB case */
465static uint8_t cafe_bbt_pattern_2048[] = { 'B', 'b', 't', '0' };
466static uint8_t cafe_mirror_pattern_2048[] = { '1', 't', 'b', 'B' };
467
468static uint8_t cafe_bbt_pattern_512[] = { 0xBB };
469static uint8_t cafe_mirror_pattern_512[] = { 0xBC };
470
8dd851de
DW		 471
472static struct nand_bbt_descr cafe_bbt_main_descr_2048 = {
473 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
048c37b4 474 | NAND_BBT_2BIT | NAND_BBT_VERSION,
8dd851de
DW		 475 .offs = 14,
476 .len = 4,
477 .veroffs = 18,
478 .maxblocks = 4,
fbad5696 479 .pattern = cafe_bbt_pattern_2048
8dd851de
DW		 480};
481
482static struct nand_bbt_descr cafe_bbt_mirror_descr_2048 = {
483 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
048c37b4 484 | NAND_BBT_2BIT | NAND_BBT_VERSION,
8dd851de
DW		 485 .offs = 14,
486 .len = 4,
487 .veroffs = 18,
488 .maxblocks = 4,
fbad5696 489 .pattern = cafe_mirror_pattern_2048
8dd851de
DW		 490};
491
492static struct nand_ecclayout cafe_oobinfo_512 = {
493 .eccbytes = 14,
494 .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
495 .oobfree = {{14, 2}}
496};
497
fbad5696
DW		 498static struct nand_bbt_descr cafe_bbt_main_descr_512 = {
499 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
048c37b4 500 | NAND_BBT_2BIT | NAND_BBT_VERSION,
fbad5696
DW		 501 .offs = 14,
502 .len = 1,
503 .veroffs = 15,
504 .maxblocks = 4,
505 .pattern = cafe_bbt_pattern_512
506};
507
508static struct nand_bbt_descr cafe_bbt_mirror_descr_512 = {
509 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
048c37b4 510 | NAND_BBT_2BIT | NAND_BBT_VERSION,
fbad5696
DW		 511 .offs = 14,
512 .len = 1,
513 .veroffs = 15,
514 .maxblocks = 4,
515 .pattern = cafe_mirror_pattern_512
516};
517
518
5467fb02
DW		 519static void cafe_nand_write_page_lowlevel(struct mtd_info *mtd,
520 struct nand_chip *chip, const uint8_t *buf)
521{
522 struct cafe_priv *cafe = mtd->priv;
523
5467fb02 524 chip->write_buf(mtd, buf, mtd->writesize);
8dd851de 525 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
5467fb02
DW		 526
527 /* Set up ECC autogeneration */
cad40654 528 cafe->ctl2 |= (1<<30);
5467fb02
DW		 529}
530
531static int cafe_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
532 const uint8_t *buf, int page, int cached, int raw)
533{
534 int status;
535
5467fb02
DW		 536 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
537
538 if (unlikely(raw))
539 chip->ecc.write_page_raw(mtd, chip, buf);
540 else
541 chip->ecc.write_page(mtd, chip, buf);
542
543 /*
544 * Cached progamming disabled for now, Not sure if its worth the
545 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
546 */
547 cached = 0;
548
549 if (!cached || !(chip->options & NAND_CACHEPRG)) {
550
551 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
552 status = chip->waitfunc(mtd, chip);
553 /*
554 * See if operation failed and additional status checks are
555 * available
556 */
557 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
558 status = chip->errstat(mtd, chip, FL_WRITING, status,
559 page);
560
561 if (status & NAND_STATUS_FAIL)
562 return -EIO;
563 } else {
564 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
565 status = chip->waitfunc(mtd, chip);
566 }
567
568#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
569 /* Send command to read back the data */
570 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
571
572 if (chip->verify_buf(mtd, buf, mtd->writesize))
573 return -EIO;
574#endif
575 return 0;
576}
577
8dd851de
DW		 578static int cafe_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
579{
580 return 0;
581}
5467fb02 582
8c61b7a7
SB		 583/* F_2[X]/(X**6+X+1) */
584static unsigned short __devinit gf64_mul(u8 a, u8 b)
585{
586 u8 c;
587 unsigned int i;
588
589 c = 0;
590 for (i = 0; i < 6; i++) {
591 if (a & 1)
592 c ^= b;
593 a >>= 1;
594 b <<= 1;
595 if ((b & 0x40) != 0)
596 b ^= 0x43;
597 }
598
599 return c;
600}
601
602/* F_64[X]/(X**2+X+A**-1) with A the generator of F_64[X] */
603static u16 __devinit gf4096_mul(u16 a, u16 b)
604{
605 u8 ah, al, bh, bl, ch, cl;
606
607 ah = a >> 6;
608 al = a & 0x3f;
609 bh = b >> 6;
610 bl = b & 0x3f;
611
612 ch = gf64_mul(ah ^ al, bh ^ bl) ^ gf64_mul(al, bl);
613 cl = gf64_mul(gf64_mul(ah, bh), 0x21) ^ gf64_mul(al, bl);
614
615 return (ch << 6) ^ cl;
616}
617
618static int __devinit cafe_mul(int x)
619{
620 if (x == 0)
621 return 1;
622 return gf4096_mul(x, 0xe01);
623}
624
5467fb02
DW		 625static int __devinit cafe_nand_probe(struct pci_dev *pdev,
626 const struct pci_device_id *ent)
627{
628 struct mtd_info *mtd;
629 struct cafe_priv *cafe;
630 uint32_t ctrl;
631 int err = 0;
632
06ed24e5
DW		 633 /* Very old versions shared the same PCI ident for all three
634 functions on the chip. Verify the class too... */
635 if ((pdev->class >> 8) != PCI_CLASS_MEMORY_FLASH)
636 return -ENODEV;
637
5467fb02
DW		 638 err = pci_enable_device(pdev);
639 if (err)
640 return err;
641
642 pci_set_master(pdev);
643
644 mtd = kzalloc(sizeof(*mtd) + sizeof(struct cafe_priv), GFP_KERNEL);
645 if (!mtd) {
646 dev_warn(&pdev->dev, "failed to alloc mtd_info\n");
647 return -ENOMEM;
648 }
649 cafe = (void *)(&mtd[1]);
650
c451c7c4 651 mtd->dev.parent = &pdev->dev;
5467fb02
DW		 652 mtd->priv = cafe;
653 mtd->owner = THIS_MODULE;
654
655 cafe->pdev = pdev;
656 cafe->mmio = pci_iomap(pdev, 0, 0);
657 if (!cafe->mmio) {
658 dev_warn(&pdev->dev, "failed to iomap\n");
659 err = -ENOMEM;
660 goto out_free_mtd;
661 }
662 cafe->dmabuf = dma_alloc_coherent(&cafe->pdev->dev, 2112 + sizeof(struct nand_buffers),
663 &cafe->dmaaddr, GFP_KERNEL);
664 if (!cafe->dmabuf) {
665 err = -ENOMEM;
666 goto out_ior;
667 }
668 cafe->nand.buffers = (void *)cafe->dmabuf + 2112;
669
8c61b7a7
SB		 670 cafe->rs = init_rs_non_canonical(12, &cafe_mul, 0, 1, 8);
671 if (!cafe->rs) {
672 err = -ENOMEM;
673 goto out_ior;
674 }
675
5467fb02
DW		 676 cafe->nand.cmdfunc = cafe_nand_cmdfunc;
677 cafe->nand.dev_ready = cafe_device_ready;
678 cafe->nand.read_byte = cafe_read_byte;
679 cafe->nand.read_buf = cafe_read_buf;
680 cafe->nand.write_buf = cafe_write_buf;
681 cafe->nand.select_chip = cafe_select_chip;
682
683 cafe->nand.chip_delay = 0;
684
685 /* Enable the following for a flash based bad block table */
bb9ebd4e 686 cafe->nand.bbt_options = NAND_BBT_USE_FLASH;
a40f7341 687 cafe->nand.options = NAND_NO_AUTOINCR | NAND_OWN_BUFFERS;
8dd851de
DW		 688
689 if (skipbbt) {
690 cafe->nand.options |= NAND_SKIP_BBTSCAN;
691 cafe->nand.block_bad = cafe_nand_block_bad;
692 }
c9ac5977 693
527a4f45
DW		 694 if (numtimings && numtimings != 3) {
695 dev_warn(&cafe->pdev->dev, "%d timing register values ignored; precisely three are required\n", numtimings);
696 }
697
698 if (numtimings == 3) {
527a4f45 699 cafe_dev_dbg(&cafe->pdev->dev, "Using provided timings (%08x %08x %08x)\n",
8e5368a1 700 timing[0], timing[1], timing[2]);
527a4f45 701 } else {
8e5368a1
DW		 702 timing[0] = cafe_readl(cafe, NAND_TIMING1);
703 timing[1] = cafe_readl(cafe, NAND_TIMING2);
704 timing[2] = cafe_readl(cafe, NAND_TIMING3);
527a4f45 705
8e5368a1
DW		 706 if (timing[0] | timing[1] | timing[2]) {
707 cafe_dev_dbg(&cafe->pdev->dev, "Timing registers already set (%08x %08x %08x)\n",
708 timing[0], timing[1], timing[2]);
527a4f45
DW		 709 } else {
710 dev_warn(&cafe->pdev->dev, "Timing registers unset; using most conservative defaults\n");
8e5368a1 711 timing[0] = timing[1] = timing[2] = 0xffffffff;
527a4f45
DW		 712 }
713 }
714
dcc41bc8 715 /* Start off by resetting the NAND controller completely */
195a253b
DW		 716 cafe_writel(cafe, 1, NAND_RESET);
717 cafe_writel(cafe, 0, NAND_RESET);
dcc41bc8 718
8e5368a1
DW		 719 cafe_writel(cafe, timing[0], NAND_TIMING1);
720 cafe_writel(cafe, timing[1], NAND_TIMING2);
721 cafe_writel(cafe, timing[2], NAND_TIMING3);
b478c775 722
195a253b 723 cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
2db6346f
TG		 724 err = request_irq(pdev->irq, &cafe_nand_interrupt, IRQF_SHARED,
725 "CAFE NAND", mtd);
5467fb02
DW		 726 if (err) {
727 dev_warn(&pdev->dev, "Could not register IRQ %d\n", pdev->irq);
5467fb02
DW		 728 goto out_free_dma;
729 }
f7c37d7b 730
5467fb02 731 /* Disable master reset, enable NAND clock */
195a253b 732 ctrl = cafe_readl(cafe, GLOBAL_CTRL);
5467fb02
DW		 733 ctrl &= 0xffffeff0;
734 ctrl |= 0x00007000;
195a253b
DW		 735 cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
736 cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
737 cafe_writel(cafe, 0, NAND_DMA_CTRL);
5467fb02 738
195a253b
DW		 739 cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
740 cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
5467fb02
DW		 741
742 /* Set up DMA address */
195a253b 743 cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0);
5467fb02 744 if (sizeof(cafe->dmaaddr) > 4)
fbad5696 745 /* Shift in two parts to shut the compiler up */
195a253b 746 cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1);
5467fb02 747 else
195a253b 748 cafe_writel(cafe, 0, NAND_DMA_ADDR1);
fbad5696 749
8dd851de 750 cafe_dev_dbg(&cafe->pdev->dev, "Set DMA address to %x (virt %p)\n",
195a253b 751 cafe_readl(cafe, NAND_DMA_ADDR0), cafe->dmabuf);
5467fb02
DW		 752
753 /* Enable NAND IRQ in global IRQ mask register */
195a253b 754 cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
8dd851de 755 cafe_dev_dbg(&cafe->pdev->dev, "Control %x, IRQ mask %x\n",
195a253b 756 cafe_readl(cafe, GLOBAL_CTRL), cafe_readl(cafe, GLOBAL_IRQ_MASK));
f7c37d7b
DW		 757
758 /* Scan to find existence of the device */
5e81e88a 759 if (nand_scan_ident(mtd, 2, NULL)) {
5467fb02
DW		 760 err = -ENXIO;
761 goto out_irq;
762 }
763
764 cafe->ctl2 = 1<<27; /* Reed-Solomon ECC */
765 if (mtd->writesize == 2048)
766 cafe->ctl2 |= 1<<29; /* 2KiB page size */
767
768 /* Set up ECC according to the type of chip we found */
fbad5696 769 if (mtd->writesize == 2048) {
8dd851de
DW		 770 cafe->nand.ecc.layout = &cafe_oobinfo_2048;
771 cafe->nand.bbt_td = &cafe_bbt_main_descr_2048;
772 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_2048;
fbad5696
DW		 773 } else if (mtd->writesize == 512) {
774 cafe->nand.ecc.layout = &cafe_oobinfo_512;
775 cafe->nand.bbt_td = &cafe_bbt_main_descr_512;
776 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_512;
5467fb02 777 } else {
fbad5696 778 printk(KERN_WARNING "Unexpected NAND flash writesize %d. Aborting\n",
5467fb02 779 mtd->writesize);
fbad5696 780 goto out_irq;
5467fb02 781 }
fbad5696
DW		 782 cafe->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
783 cafe->nand.ecc.size = mtd->writesize;
784 cafe->nand.ecc.bytes = 14;
785 cafe->nand.ecc.hwctl = (void *)cafe_nand_bug;
786 cafe->nand.ecc.calculate = (void *)cafe_nand_bug;
787 cafe->nand.ecc.correct = (void *)cafe_nand_bug;
788 cafe->nand.write_page = cafe_nand_write_page;
789 cafe->nand.ecc.write_page = cafe_nand_write_page_lowlevel;
790 cafe->nand.ecc.write_oob = cafe_nand_write_oob;
791 cafe->nand.ecc.read_page = cafe_nand_read_page;
792 cafe->nand.ecc.read_oob = cafe_nand_read_oob;
5467fb02
DW		 793
794 err = nand_scan_tail(mtd);
795 if (err)
796 goto out_irq;
797
5467fb02 798 pci_set_drvdata(pdev, mtd);
9c37f332 799
68874414 800 mtd->name = "cafe_nand";
4d32de81
DES		 801 mtd_device_parse_register(mtd, part_probes, 0, NULL, 0);
802
5467fb02
DW		 803 goto out;
804
805 out_irq:
806 /* Disable NAND IRQ in global IRQ mask register */
195a253b 807 cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
5467fb02
DW		 808 free_irq(pdev->irq, mtd);
809 out_free_dma:
810 dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
811 out_ior:
812 pci_iounmap(pdev, cafe->mmio);
813 out_free_mtd:
814 kfree(mtd);
815 out:
816 return err;
817}
818
819static void __devexit cafe_nand_remove(struct pci_dev *pdev)
820{
821 struct mtd_info *mtd = pci_get_drvdata(pdev);
822 struct cafe_priv *cafe = mtd->priv;
823
5467fb02 824 /* Disable NAND IRQ in global IRQ mask register */
195a253b 825 cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
5467fb02
DW		 826 free_irq(pdev->irq, mtd);
827 nand_release(mtd);
8c61b7a7 828 free_rs(cafe->rs);
5467fb02
DW		 829 pci_iounmap(pdev, cafe->mmio);
830 dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
831 kfree(mtd);
832}
833
377ace08 834static const struct pci_device_id cafe_nand_tbl[] = {
514fca43
DW		 835 { PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_88ALP01_NAND,
836 PCI_ANY_ID, PCI_ANY_ID },
06ed24e5 837 { }
5467fb02
DW		 838};
839
840MODULE_DEVICE_TABLE(pci, cafe_nand_tbl);
841
1fcf8ce5
DW		 842static int cafe_nand_resume(struct pci_dev *pdev)
843{
844 uint32_t ctrl;
845 struct mtd_info *mtd = pci_get_drvdata(pdev);
846 struct cafe_priv *cafe = mtd->priv;
847
848 /* Start off by resetting the NAND controller completely */
849 cafe_writel(cafe, 1, NAND_RESET);
850 cafe_writel(cafe, 0, NAND_RESET);
851 cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
852
853 /* Restore timing configuration */
854 cafe_writel(cafe, timing[0], NAND_TIMING1);
855 cafe_writel(cafe, timing[1], NAND_TIMING2);
856 cafe_writel(cafe, timing[2], NAND_TIMING3);
857
858 /* Disable master reset, enable NAND clock */
859 ctrl = cafe_readl(cafe, GLOBAL_CTRL);
860 ctrl &= 0xffffeff0;
861 ctrl |= 0x00007000;
862 cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
863 cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
864 cafe_writel(cafe, 0, NAND_DMA_CTRL);
865 cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
866 cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
867
868 /* Set up DMA address */
869 cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0);
870 if (sizeof(cafe->dmaaddr) > 4)
871 /* Shift in two parts to shut the compiler up */
872 cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1);
873 else
874 cafe_writel(cafe, 0, NAND_DMA_ADDR1);
875
876 /* Enable NAND IRQ in global IRQ mask register */
877 cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
878 return 0;
879}
880
5467fb02
DW		 881static struct pci_driver cafe_nand_pci_driver = {
882 .name = "CAFÉ NAND",
883 .id_table = cafe_nand_tbl,
884 .probe = cafe_nand_probe,
885 .remove = __devexit_p(cafe_nand_remove),
5467fb02 886 .resume = cafe_nand_resume,
5467fb02
DW		 887};
888
627df23c 889static int __init cafe_nand_init(void)
5467fb02
DW		 890{
891 return pci_register_driver(&cafe_nand_pci_driver);
892}
893
627df23c 894static void __exit cafe_nand_exit(void)
5467fb02
DW		 895{
896 pci_unregister_driver(&cafe_nand_pci_driver);
897}
898module_init(cafe_nand_init);
899module_exit(cafe_nand_exit);
900
901MODULE_LICENSE("GPL");
902MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
f7c37d7b 903MODULE_DESCRIPTION("NAND flash driver for OLPC CAFÉ chip");
Linux kernel - Deliverables
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