Commit | Line | Data |
---|---|---|
c9ac5977 | 1 | /* |
fbad5696 | 2 | * Driver for One Laptop Per Child ‘CAFÉ’ controller, aka Marvell 88ALP01 |
5467fb02 | 3 | * |
514fca43 DW |
4 | * The data sheet for this device can be found at: |
5 | * http://www.marvell.com/products/pcconn/88ALP01.jsp | |
6 | * | |
5467fb02 DW |
7 | * Copyright © 2006 Red Hat, Inc. |
8 | * Copyright © 2006 David Woodhouse <dwmw2@infradead.org> | |
9 | */ | |
10 | ||
8dd851de | 11 | #define DEBUG |
5467fb02 DW |
12 | |
13 | #include <linux/device.h> | |
14 | #undef DEBUG | |
15 | #include <linux/mtd/mtd.h> | |
16 | #include <linux/mtd/nand.h> | |
9c37f332 | 17 | #include <linux/mtd/partitions.h> |
8c61b7a7 | 18 | #include <linux/rslib.h> |
5467fb02 DW |
19 | #include <linux/pci.h> |
20 | #include <linux/delay.h> | |
21 | #include <linux/interrupt.h> | |
a1274302 | 22 | #include <linux/dma-mapping.h> |
5467fb02 DW |
23 | #include <asm/io.h> |
24 | ||
25 | #define CAFE_NAND_CTRL1 0x00 | |
26 | #define CAFE_NAND_CTRL2 0x04 | |
27 | #define CAFE_NAND_CTRL3 0x08 | |
28 | #define CAFE_NAND_STATUS 0x0c | |
29 | #define CAFE_NAND_IRQ 0x10 | |
30 | #define CAFE_NAND_IRQ_MASK 0x14 | |
31 | #define CAFE_NAND_DATA_LEN 0x18 | |
32 | #define CAFE_NAND_ADDR1 0x1c | |
33 | #define CAFE_NAND_ADDR2 0x20 | |
34 | #define CAFE_NAND_TIMING1 0x24 | |
35 | #define CAFE_NAND_TIMING2 0x28 | |
36 | #define CAFE_NAND_TIMING3 0x2c | |
37 | #define CAFE_NAND_NONMEM 0x30 | |
04459d7c | 38 | #define CAFE_NAND_ECC_RESULT 0x3C |
fbad5696 DW |
39 | #define CAFE_NAND_DMA_CTRL 0x40 |
40 | #define CAFE_NAND_DMA_ADDR0 0x44 | |
41 | #define CAFE_NAND_DMA_ADDR1 0x48 | |
04459d7c DW |
42 | #define CAFE_NAND_ECC_SYN01 0x50 |
43 | #define CAFE_NAND_ECC_SYN23 0x54 | |
44 | #define CAFE_NAND_ECC_SYN45 0x58 | |
45 | #define CAFE_NAND_ECC_SYN67 0x5c | |
5467fb02 DW |
46 | #define CAFE_NAND_READ_DATA 0x1000 |
47 | #define CAFE_NAND_WRITE_DATA 0x2000 | |
48 | ||
195a253b DW |
49 | #define CAFE_GLOBAL_CTRL 0x3004 |
50 | #define CAFE_GLOBAL_IRQ 0x3008 | |
51 | #define CAFE_GLOBAL_IRQ_MASK 0x300c | |
52 | #define CAFE_NAND_RESET 0x3034 | |
53 | ||
048c37b4 DW |
54 | /* Missing from the datasheet: bit 19 of CTRL1 sets CE0 vs. CE1 */ |
55 | #define CTRL1_CHIPSELECT (1<<19) | |
56 | ||
5467fb02 DW |
57 | struct cafe_priv { |
58 | struct nand_chip nand; | |
9c37f332 | 59 | struct mtd_partition *parts; |
5467fb02 DW |
60 | struct pci_dev *pdev; |
61 | void __iomem *mmio; | |
8c61b7a7 | 62 | struct rs_control *rs; |
5467fb02 DW |
63 | uint32_t ctl1; |
64 | uint32_t ctl2; | |
65 | int datalen; | |
66 | int nr_data; | |
67 | int data_pos; | |
68 | int page_addr; | |
69 | dma_addr_t dmaaddr; | |
70 | unsigned char *dmabuf; | |
5467fb02 DW |
71 | }; |
72 | ||
b478c775 | 73 | static int usedma = 1; |
5467fb02 DW |
74 | module_param(usedma, int, 0644); |
75 | ||
8dd851de DW |
76 | static int skipbbt = 0; |
77 | module_param(skipbbt, int, 0644); | |
78 | ||
79 | static int debug = 0; | |
80 | module_param(debug, int, 0644); | |
81 | ||
be8444bd DW |
82 | static int regdebug = 0; |
83 | module_param(regdebug, int, 0644); | |
84 | ||
b478c775 | 85 | static int checkecc = 1; |
470b0a90 DW |
86 | module_param(checkecc, int, 0644); |
87 | ||
64a6f950 | 88 | static unsigned int numtimings; |
527a4f45 DW |
89 | static int timing[3]; |
90 | module_param_array(timing, int, &numtimings, 0644); | |
b478c775 | 91 | |
9c37f332 | 92 | #ifdef CONFIG_MTD_PARTITIONS |
68874414 | 93 | static const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL }; |
9c37f332 DW |
94 | #endif |
95 | ||
04459d7c | 96 | /* Hrm. Why isn't this already conditional on something in the struct device? */ |
8dd851de DW |
97 | #define cafe_dev_dbg(dev, args...) do { if (debug) dev_dbg(dev, ##args); } while(0) |
98 | ||
195a253b DW |
99 | /* Make it easier to switch to PIO if we need to */ |
100 | #define cafe_readl(cafe, addr) readl((cafe)->mmio + CAFE_##addr) | |
101 | #define cafe_writel(cafe, datum, addr) writel(datum, (cafe)->mmio + CAFE_##addr) | |
8dd851de | 102 | |
5467fb02 DW |
103 | static int cafe_device_ready(struct mtd_info *mtd) |
104 | { | |
105 | struct cafe_priv *cafe = mtd->priv; | |
195a253b DW |
106 | int result = !!(cafe_readl(cafe, NAND_STATUS) | 0x40000000); |
107 | uint32_t irqs = cafe_readl(cafe, NAND_IRQ); | |
fbad5696 | 108 | |
195a253b | 109 | cafe_writel(cafe, irqs, NAND_IRQ); |
fbad5696 | 110 | |
8dd851de | 111 | cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n", |
195a253b DW |
112 | result?"":" not", irqs, cafe_readl(cafe, NAND_IRQ), |
113 | cafe_readl(cafe, GLOBAL_IRQ), cafe_readl(cafe, GLOBAL_IRQ_MASK)); | |
fbad5696 | 114 | |
5467fb02 DW |
115 | return result; |
116 | } | |
117 | ||
118 | ||
119 | static void cafe_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) | |
120 | { | |
121 | struct cafe_priv *cafe = mtd->priv; | |
122 | ||
123 | if (usedma) | |
124 | memcpy(cafe->dmabuf + cafe->datalen, buf, len); | |
125 | else | |
126 | memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len); | |
fbad5696 | 127 | |
5467fb02 DW |
128 | cafe->datalen += len; |
129 | ||
8dd851de | 130 | cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes to write buffer. datalen 0x%x\n", |
5467fb02 DW |
131 | len, cafe->datalen); |
132 | } | |
133 | ||
134 | static void cafe_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) | |
135 | { | |
136 | struct cafe_priv *cafe = mtd->priv; | |
137 | ||
138 | if (usedma) | |
139 | memcpy(buf, cafe->dmabuf + cafe->datalen, len); | |
140 | else | |
141 | memcpy_fromio(buf, cafe->mmio + CAFE_NAND_READ_DATA + cafe->datalen, len); | |
142 | ||
8dd851de | 143 | cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes from position 0x%x in read buffer.\n", |
5467fb02 DW |
144 | len, cafe->datalen); |
145 | cafe->datalen += len; | |
146 | } | |
147 | ||
148 | static uint8_t cafe_read_byte(struct mtd_info *mtd) | |
149 | { | |
150 | struct cafe_priv *cafe = mtd->priv; | |
151 | uint8_t d; | |
152 | ||
153 | cafe_read_buf(mtd, &d, 1); | |
8dd851de | 154 | cafe_dev_dbg(&cafe->pdev->dev, "Read %02x\n", d); |
5467fb02 DW |
155 | |
156 | return d; | |
157 | } | |
158 | ||
159 | static void cafe_nand_cmdfunc(struct mtd_info *mtd, unsigned command, | |
160 | int column, int page_addr) | |
161 | { | |
162 | struct cafe_priv *cafe = mtd->priv; | |
163 | int adrbytes = 0; | |
164 | uint32_t ctl1; | |
165 | uint32_t doneint = 0x80000000; | |
5467fb02 | 166 | |
8dd851de | 167 | cafe_dev_dbg(&cafe->pdev->dev, "cmdfunc %02x, 0x%x, 0x%x\n", |
5467fb02 DW |
168 | command, column, page_addr); |
169 | ||
170 | if (command == NAND_CMD_ERASE2 || command == NAND_CMD_PAGEPROG) { | |
171 | /* Second half of a command we already calculated */ | |
195a253b | 172 | cafe_writel(cafe, cafe->ctl2 | 0x100 | command, NAND_CTRL2); |
5467fb02 | 173 | ctl1 = cafe->ctl1; |
cad40654 | 174 | cafe->ctl2 &= ~(1<<30); |
8dd851de | 175 | cafe_dev_dbg(&cafe->pdev->dev, "Continue command, ctl1 %08x, #data %d\n", |
5467fb02 DW |
176 | cafe->ctl1, cafe->nr_data); |
177 | goto do_command; | |
178 | } | |
179 | /* Reset ECC engine */ | |
195a253b | 180 | cafe_writel(cafe, 0, NAND_CTRL2); |
5467fb02 DW |
181 | |
182 | /* Emulate NAND_CMD_READOOB on large-page chips */ | |
183 | if (mtd->writesize > 512 && | |
184 | command == NAND_CMD_READOOB) { | |
185 | column += mtd->writesize; | |
186 | command = NAND_CMD_READ0; | |
187 | } | |
188 | ||
189 | /* FIXME: Do we need to send read command before sending data | |
190 | for small-page chips, to position the buffer correctly? */ | |
191 | ||
192 | if (column != -1) { | |
195a253b | 193 | cafe_writel(cafe, column, NAND_ADDR1); |
5467fb02 DW |
194 | adrbytes = 2; |
195 | if (page_addr != -1) | |
196 | goto write_adr2; | |
197 | } else if (page_addr != -1) { | |
195a253b | 198 | cafe_writel(cafe, page_addr & 0xffff, NAND_ADDR1); |
5467fb02 DW |
199 | page_addr >>= 16; |
200 | write_adr2: | |
195a253b | 201 | cafe_writel(cafe, page_addr, NAND_ADDR2); |
5467fb02 DW |
202 | adrbytes += 2; |
203 | if (mtd->size > mtd->writesize << 16) | |
204 | adrbytes++; | |
205 | } | |
206 | ||
207 | cafe->data_pos = cafe->datalen = 0; | |
208 | ||
048c37b4 DW |
209 | /* Set command valid bit, mask in the chip select bit */ |
210 | ctl1 = 0x80000000 | command | (cafe->ctl1 & CTRL1_CHIPSELECT); | |
5467fb02 DW |
211 | |
212 | /* Set RD or WR bits as appropriate */ | |
213 | if (command == NAND_CMD_READID || command == NAND_CMD_STATUS) { | |
214 | ctl1 |= (1<<26); /* rd */ | |
215 | /* Always 5 bytes, for now */ | |
8dd851de | 216 | cafe->datalen = 4; |
5467fb02 DW |
217 | /* And one address cycle -- even for STATUS, since the controller doesn't work without */ |
218 | adrbytes = 1; | |
219 | } else if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 || | |
220 | command == NAND_CMD_READOOB || command == NAND_CMD_RNDOUT) { | |
221 | ctl1 |= 1<<26; /* rd */ | |
222 | /* For now, assume just read to end of page */ | |
223 | cafe->datalen = mtd->writesize + mtd->oobsize - column; | |
224 | } else if (command == NAND_CMD_SEQIN) | |
225 | ctl1 |= 1<<25; /* wr */ | |
226 | ||
227 | /* Set number of address bytes */ | |
228 | if (adrbytes) | |
229 | ctl1 |= ((adrbytes-1)|8) << 27; | |
230 | ||
231 | if (command == NAND_CMD_SEQIN || command == NAND_CMD_ERASE1) { | |
c9ac5977 | 232 | /* Ignore the first command of a pair; the hardware |
5467fb02 DW |
233 | deals with them both at once, later */ |
234 | cafe->ctl1 = ctl1; | |
8dd851de | 235 | cafe_dev_dbg(&cafe->pdev->dev, "Setup for delayed command, ctl1 %08x, dlen %x\n", |
5467fb02 DW |
236 | cafe->ctl1, cafe->datalen); |
237 | return; | |
238 | } | |
239 | /* RNDOUT and READ0 commands need a following byte */ | |
240 | if (command == NAND_CMD_RNDOUT) | |
195a253b | 241 | cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, NAND_CTRL2); |
5467fb02 | 242 | else if (command == NAND_CMD_READ0 && mtd->writesize > 512) |
195a253b | 243 | cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2); |
5467fb02 DW |
244 | |
245 | do_command: | |
c9ac5977 | 246 | cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n", |
195a253b | 247 | cafe->datalen, ctl1, cafe_readl(cafe, NAND_CTRL2)); |
fbad5696 | 248 | |
5467fb02 | 249 | /* NB: The datasheet lies -- we really should be subtracting 1 here */ |
195a253b DW |
250 | cafe_writel(cafe, cafe->datalen, NAND_DATA_LEN); |
251 | cafe_writel(cafe, 0x90000000, NAND_IRQ); | |
5467fb02 DW |
252 | if (usedma && (ctl1 & (3<<25))) { |
253 | uint32_t dmactl = 0xc0000000 + cafe->datalen; | |
254 | /* If WR or RD bits set, set up DMA */ | |
255 | if (ctl1 & (1<<26)) { | |
256 | /* It's a read */ | |
257 | dmactl |= (1<<29); | |
258 | /* ... so it's done when the DMA is done, not just | |
259 | the command. */ | |
260 | doneint = 0x10000000; | |
261 | } | |
195a253b | 262 | cafe_writel(cafe, dmactl, NAND_DMA_CTRL); |
5467fb02 | 263 | } |
5467fb02 DW |
264 | cafe->datalen = 0; |
265 | ||
be8444bd DW |
266 | if (unlikely(regdebug)) { |
267 | int i; | |
268 | printk("About to write command %08x to register 0\n", ctl1); | |
269 | for (i=4; i< 0x5c; i+=4) | |
270 | printk("Register %x: %08x\n", i, readl(cafe->mmio + i)); | |
fbad5696 | 271 | } |
be8444bd | 272 | |
195a253b | 273 | cafe_writel(cafe, ctl1, NAND_CTRL1); |
5467fb02 DW |
274 | /* Apply this short delay always to ensure that we do wait tWB in |
275 | * any case on any machine. */ | |
276 | ndelay(100); | |
277 | ||
278 | if (1) { | |
2a7295b2 | 279 | int c; |
5467fb02 DW |
280 | uint32_t irqs; |
281 | ||
2a7295b2 | 282 | for (c = 500000; c != 0; c--) { |
195a253b | 283 | irqs = cafe_readl(cafe, NAND_IRQ); |
5467fb02 DW |
284 | if (irqs & doneint) |
285 | break; | |
286 | udelay(1); | |
8dd851de DW |
287 | if (!(c % 100000)) |
288 | cafe_dev_dbg(&cafe->pdev->dev, "Wait for ready, IRQ %x\n", irqs); | |
5467fb02 DW |
289 | cpu_relax(); |
290 | } | |
195a253b | 291 | cafe_writel(cafe, doneint, NAND_IRQ); |
a020727b | 292 | cafe_dev_dbg(&cafe->pdev->dev, "Command %x completed after %d usec, irqs %x (%x)\n", |
195a253b | 293 | command, 500000-c, irqs, cafe_readl(cafe, NAND_IRQ)); |
5467fb02 DW |
294 | } |
295 | ||
cad40654 | 296 | WARN_ON(cafe->ctl2 & (1<<30)); |
5467fb02 DW |
297 | |
298 | switch (command) { | |
299 | ||
300 | case NAND_CMD_CACHEDPROG: | |
301 | case NAND_CMD_PAGEPROG: | |
302 | case NAND_CMD_ERASE1: | |
303 | case NAND_CMD_ERASE2: | |
304 | case NAND_CMD_SEQIN: | |
305 | case NAND_CMD_RNDIN: | |
306 | case NAND_CMD_STATUS: | |
307 | case NAND_CMD_DEPLETE1: | |
308 | case NAND_CMD_RNDOUT: | |
309 | case NAND_CMD_STATUS_ERROR: | |
310 | case NAND_CMD_STATUS_ERROR0: | |
311 | case NAND_CMD_STATUS_ERROR1: | |
312 | case NAND_CMD_STATUS_ERROR2: | |
313 | case NAND_CMD_STATUS_ERROR3: | |
195a253b | 314 | cafe_writel(cafe, cafe->ctl2, NAND_CTRL2); |
5467fb02 DW |
315 | return; |
316 | } | |
317 | nand_wait_ready(mtd); | |
195a253b | 318 | cafe_writel(cafe, cafe->ctl2, NAND_CTRL2); |
5467fb02 DW |
319 | } |
320 | ||
321 | static void cafe_select_chip(struct mtd_info *mtd, int chipnr) | |
322 | { | |
048c37b4 DW |
323 | struct cafe_priv *cafe = mtd->priv; |
324 | ||
325 | cafe_dev_dbg(&cafe->pdev->dev, "select_chip %d\n", chipnr); | |
326 | ||
327 | /* Mask the appropriate bit into the stored value of ctl1 | |
328 | which will be used by cafe_nand_cmdfunc() */ | |
329 | if (chipnr) | |
330 | cafe->ctl1 |= CTRL1_CHIPSELECT; | |
331 | else | |
332 | cafe->ctl1 &= ~CTRL1_CHIPSELECT; | |
5467fb02 | 333 | } |
fbad5696 | 334 | |
28bdd4a7 | 335 | static int cafe_nand_interrupt(int irq, void *id) |
5467fb02 DW |
336 | { |
337 | struct mtd_info *mtd = id; | |
338 | struct cafe_priv *cafe = mtd->priv; | |
195a253b DW |
339 | uint32_t irqs = cafe_readl(cafe, NAND_IRQ); |
340 | cafe_writel(cafe, irqs & ~0x90000000, NAND_IRQ); | |
5467fb02 DW |
341 | if (!irqs) |
342 | return IRQ_NONE; | |
343 | ||
195a253b | 344 | cafe_dev_dbg(&cafe->pdev->dev, "irq, bits %x (%x)\n", irqs, cafe_readl(cafe, NAND_IRQ)); |
5467fb02 DW |
345 | return IRQ_HANDLED; |
346 | } | |
347 | ||
348 | static void cafe_nand_bug(struct mtd_info *mtd) | |
349 | { | |
350 | BUG(); | |
351 | } | |
352 | ||
353 | static int cafe_nand_write_oob(struct mtd_info *mtd, | |
354 | struct nand_chip *chip, int page) | |
355 | { | |
356 | int status = 0; | |
357 | ||
5467fb02 DW |
358 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); |
359 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
360 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
361 | status = chip->waitfunc(mtd, chip); | |
362 | ||
363 | return status & NAND_STATUS_FAIL ? -EIO : 0; | |
364 | } | |
365 | ||
366 | /* Don't use -- use nand_read_oob_std for now */ | |
367 | static int cafe_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, | |
368 | int page, int sndcmd) | |
369 | { | |
370 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); | |
371 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
372 | return 1; | |
373 | } | |
374 | /** | |
375 | * cafe_nand_read_page_syndrome - {REPLACABLE] hardware ecc syndrom based page read | |
376 | * @mtd: mtd info structure | |
377 | * @chip: nand chip info structure | |
378 | * @buf: buffer to store read data | |
379 | * | |
380 | * The hw generator calculates the error syndrome automatically. Therefor | |
381 | * we need a special oob layout and handling. | |
382 | */ | |
383 | static int cafe_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip, | |
384 | uint8_t *buf) | |
385 | { | |
386 | struct cafe_priv *cafe = mtd->priv; | |
387 | ||
fbad5696 | 388 | cafe_dev_dbg(&cafe->pdev->dev, "ECC result %08x SYN1,2 %08x\n", |
195a253b DW |
389 | cafe_readl(cafe, NAND_ECC_RESULT), |
390 | cafe_readl(cafe, NAND_ECC_SYN01)); | |
5467fb02 DW |
391 | |
392 | chip->read_buf(mtd, buf, mtd->writesize); | |
393 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
394 | ||
195a253b | 395 | if (checkecc && cafe_readl(cafe, NAND_ECC_RESULT) & (1<<18)) { |
8c61b7a7 SB |
396 | unsigned short syn[8], pat[4]; |
397 | int pos[4]; | |
398 | u8 *oob = chip->oob_poi; | |
399 | int i, n; | |
04459d7c DW |
400 | |
401 | for (i=0; i<8; i+=2) { | |
195a253b | 402 | uint32_t tmp = cafe_readl(cafe, NAND_ECC_SYN01 + (i*2)); |
8c61b7a7 SB |
403 | syn[i] = cafe->rs->index_of[tmp & 0xfff]; |
404 | syn[i+1] = cafe->rs->index_of[(tmp >> 16) & 0xfff]; | |
405 | } | |
406 | ||
407 | n = decode_rs16(cafe->rs, NULL, NULL, 1367, syn, 0, pos, 0, | |
408 | pat); | |
409 | ||
410 | for (i = 0; i < n; i++) { | |
411 | int p = pos[i]; | |
412 | ||
413 | /* The 12-bit symbols are mapped to bytes here */ | |
414 | ||
415 | if (p > 1374) { | |
416 | /* out of range */ | |
417 | n = -1374; | |
418 | } else if (p == 0) { | |
419 | /* high four bits do not correspond to data */ | |
420 | if (pat[i] > 0xff) | |
421 | n = -2048; | |
422 | else | |
423 | buf[0] ^= pat[i]; | |
424 | } else if (p == 1365) { | |
425 | buf[2047] ^= pat[i] >> 4; | |
426 | oob[0] ^= pat[i] << 4; | |
427 | } else if (p > 1365) { | |
428 | if ((p & 1) == 1) { | |
429 | oob[3*p/2 - 2048] ^= pat[i] >> 4; | |
430 | oob[3*p/2 - 2047] ^= pat[i] << 4; | |
431 | } else { | |
432 | oob[3*p/2 - 2049] ^= pat[i] >> 8; | |
433 | oob[3*p/2 - 2048] ^= pat[i]; | |
434 | } | |
435 | } else if ((p & 1) == 1) { | |
436 | buf[3*p/2] ^= pat[i] >> 4; | |
437 | buf[3*p/2 + 1] ^= pat[i] << 4; | |
438 | } else { | |
439 | buf[3*p/2 - 1] ^= pat[i] >> 8; | |
440 | buf[3*p/2] ^= pat[i]; | |
441 | } | |
c9ac5977 | 442 | } |
04459d7c | 443 | |
8c61b7a7 | 444 | if (n < 0) { |
be8444bd DW |
445 | dev_dbg(&cafe->pdev->dev, "Failed to correct ECC at %08x\n", |
446 | cafe_readl(cafe, NAND_ADDR2) * 2048); | |
8c61b7a7 | 447 | for (i = 0; i < 0x5c; i += 4) |
be8444bd | 448 | printk("Register %x: %08x\n", i, readl(cafe->mmio + i)); |
04459d7c DW |
449 | mtd->ecc_stats.failed++; |
450 | } else { | |
8c61b7a7 SB |
451 | dev_dbg(&cafe->pdev->dev, "Corrected %d symbol errors\n", n); |
452 | mtd->ecc_stats.corrected += n; | |
04459d7c DW |
453 | } |
454 | } | |
455 | ||
5467fb02 DW |
456 | return 0; |
457 | } | |
458 | ||
8dd851de DW |
459 | static struct nand_ecclayout cafe_oobinfo_2048 = { |
460 | .eccbytes = 14, | |
461 | .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, | |
462 | .oobfree = {{14, 50}} | |
463 | }; | |
464 | ||
c9ac5977 | 465 | /* Ick. The BBT code really ought to be able to work this bit out |
fbad5696 DW |
466 | for itself from the above, at least for the 2KiB case */ |
467 | static uint8_t cafe_bbt_pattern_2048[] = { 'B', 'b', 't', '0' }; | |
468 | static uint8_t cafe_mirror_pattern_2048[] = { '1', 't', 'b', 'B' }; | |
469 | ||
470 | static uint8_t cafe_bbt_pattern_512[] = { 0xBB }; | |
471 | static uint8_t cafe_mirror_pattern_512[] = { 0xBC }; | |
472 | ||
8dd851de DW |
473 | |
474 | static struct nand_bbt_descr cafe_bbt_main_descr_2048 = { | |
475 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
048c37b4 | 476 | | NAND_BBT_2BIT | NAND_BBT_VERSION, |
8dd851de DW |
477 | .offs = 14, |
478 | .len = 4, | |
479 | .veroffs = 18, | |
480 | .maxblocks = 4, | |
fbad5696 | 481 | .pattern = cafe_bbt_pattern_2048 |
8dd851de DW |
482 | }; |
483 | ||
484 | static struct nand_bbt_descr cafe_bbt_mirror_descr_2048 = { | |
485 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
048c37b4 | 486 | | NAND_BBT_2BIT | NAND_BBT_VERSION, |
8dd851de DW |
487 | .offs = 14, |
488 | .len = 4, | |
489 | .veroffs = 18, | |
490 | .maxblocks = 4, | |
fbad5696 | 491 | .pattern = cafe_mirror_pattern_2048 |
8dd851de DW |
492 | }; |
493 | ||
494 | static struct nand_ecclayout cafe_oobinfo_512 = { | |
495 | .eccbytes = 14, | |
496 | .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, | |
497 | .oobfree = {{14, 2}} | |
498 | }; | |
499 | ||
fbad5696 DW |
500 | static struct nand_bbt_descr cafe_bbt_main_descr_512 = { |
501 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
048c37b4 | 502 | | NAND_BBT_2BIT | NAND_BBT_VERSION, |
fbad5696 DW |
503 | .offs = 14, |
504 | .len = 1, | |
505 | .veroffs = 15, | |
506 | .maxblocks = 4, | |
507 | .pattern = cafe_bbt_pattern_512 | |
508 | }; | |
509 | ||
510 | static struct nand_bbt_descr cafe_bbt_mirror_descr_512 = { | |
511 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
048c37b4 | 512 | | NAND_BBT_2BIT | NAND_BBT_VERSION, |
fbad5696 DW |
513 | .offs = 14, |
514 | .len = 1, | |
515 | .veroffs = 15, | |
516 | .maxblocks = 4, | |
517 | .pattern = cafe_mirror_pattern_512 | |
518 | }; | |
519 | ||
520 | ||
5467fb02 DW |
521 | static void cafe_nand_write_page_lowlevel(struct mtd_info *mtd, |
522 | struct nand_chip *chip, const uint8_t *buf) | |
523 | { | |
524 | struct cafe_priv *cafe = mtd->priv; | |
525 | ||
5467fb02 | 526 | chip->write_buf(mtd, buf, mtd->writesize); |
8dd851de | 527 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); |
5467fb02 DW |
528 | |
529 | /* Set up ECC autogeneration */ | |
cad40654 | 530 | cafe->ctl2 |= (1<<30); |
5467fb02 DW |
531 | } |
532 | ||
533 | static int cafe_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, | |
534 | const uint8_t *buf, int page, int cached, int raw) | |
535 | { | |
536 | int status; | |
537 | ||
5467fb02 DW |
538 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); |
539 | ||
540 | if (unlikely(raw)) | |
541 | chip->ecc.write_page_raw(mtd, chip, buf); | |
542 | else | |
543 | chip->ecc.write_page(mtd, chip, buf); | |
544 | ||
545 | /* | |
546 | * Cached progamming disabled for now, Not sure if its worth the | |
547 | * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s) | |
548 | */ | |
549 | cached = 0; | |
550 | ||
551 | if (!cached || !(chip->options & NAND_CACHEPRG)) { | |
552 | ||
553 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
554 | status = chip->waitfunc(mtd, chip); | |
555 | /* | |
556 | * See if operation failed and additional status checks are | |
557 | * available | |
558 | */ | |
559 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
560 | status = chip->errstat(mtd, chip, FL_WRITING, status, | |
561 | page); | |
562 | ||
563 | if (status & NAND_STATUS_FAIL) | |
564 | return -EIO; | |
565 | } else { | |
566 | chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1); | |
567 | status = chip->waitfunc(mtd, chip); | |
568 | } | |
569 | ||
570 | #ifdef CONFIG_MTD_NAND_VERIFY_WRITE | |
571 | /* Send command to read back the data */ | |
572 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); | |
573 | ||
574 | if (chip->verify_buf(mtd, buf, mtd->writesize)) | |
575 | return -EIO; | |
576 | #endif | |
577 | return 0; | |
578 | } | |
579 | ||
8dd851de DW |
580 | static int cafe_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) |
581 | { | |
582 | return 0; | |
583 | } | |
5467fb02 | 584 | |
8c61b7a7 SB |
585 | /* F_2[X]/(X**6+X+1) */ |
586 | static unsigned short __devinit gf64_mul(u8 a, u8 b) | |
587 | { | |
588 | u8 c; | |
589 | unsigned int i; | |
590 | ||
591 | c = 0; | |
592 | for (i = 0; i < 6; i++) { | |
593 | if (a & 1) | |
594 | c ^= b; | |
595 | a >>= 1; | |
596 | b <<= 1; | |
597 | if ((b & 0x40) != 0) | |
598 | b ^= 0x43; | |
599 | } | |
600 | ||
601 | return c; | |
602 | } | |
603 | ||
604 | /* F_64[X]/(X**2+X+A**-1) with A the generator of F_64[X] */ | |
605 | static u16 __devinit gf4096_mul(u16 a, u16 b) | |
606 | { | |
607 | u8 ah, al, bh, bl, ch, cl; | |
608 | ||
609 | ah = a >> 6; | |
610 | al = a & 0x3f; | |
611 | bh = b >> 6; | |
612 | bl = b & 0x3f; | |
613 | ||
614 | ch = gf64_mul(ah ^ al, bh ^ bl) ^ gf64_mul(al, bl); | |
615 | cl = gf64_mul(gf64_mul(ah, bh), 0x21) ^ gf64_mul(al, bl); | |
616 | ||
617 | return (ch << 6) ^ cl; | |
618 | } | |
619 | ||
620 | static int __devinit cafe_mul(int x) | |
621 | { | |
622 | if (x == 0) | |
623 | return 1; | |
624 | return gf4096_mul(x, 0xe01); | |
625 | } | |
626 | ||
5467fb02 DW |
627 | static int __devinit cafe_nand_probe(struct pci_dev *pdev, |
628 | const struct pci_device_id *ent) | |
629 | { | |
630 | struct mtd_info *mtd; | |
631 | struct cafe_priv *cafe; | |
632 | uint32_t ctrl; | |
633 | int err = 0; | |
437d0d29 TF |
634 | #ifdef CONFIG_MTD_PARTITIONS |
635 | struct mtd_partition *parts; | |
636 | int nr_parts; | |
637 | #endif | |
5467fb02 | 638 | |
06ed24e5 DW |
639 | /* Very old versions shared the same PCI ident for all three |
640 | functions on the chip. Verify the class too... */ | |
641 | if ((pdev->class >> 8) != PCI_CLASS_MEMORY_FLASH) | |
642 | return -ENODEV; | |
643 | ||
5467fb02 DW |
644 | err = pci_enable_device(pdev); |
645 | if (err) | |
646 | return err; | |
647 | ||
648 | pci_set_master(pdev); | |
649 | ||
650 | mtd = kzalloc(sizeof(*mtd) + sizeof(struct cafe_priv), GFP_KERNEL); | |
651 | if (!mtd) { | |
652 | dev_warn(&pdev->dev, "failed to alloc mtd_info\n"); | |
653 | return -ENOMEM; | |
654 | } | |
655 | cafe = (void *)(&mtd[1]); | |
656 | ||
657 | mtd->priv = cafe; | |
658 | mtd->owner = THIS_MODULE; | |
659 | ||
660 | cafe->pdev = pdev; | |
661 | cafe->mmio = pci_iomap(pdev, 0, 0); | |
662 | if (!cafe->mmio) { | |
663 | dev_warn(&pdev->dev, "failed to iomap\n"); | |
664 | err = -ENOMEM; | |
665 | goto out_free_mtd; | |
666 | } | |
667 | cafe->dmabuf = dma_alloc_coherent(&cafe->pdev->dev, 2112 + sizeof(struct nand_buffers), | |
668 | &cafe->dmaaddr, GFP_KERNEL); | |
669 | if (!cafe->dmabuf) { | |
670 | err = -ENOMEM; | |
671 | goto out_ior; | |
672 | } | |
673 | cafe->nand.buffers = (void *)cafe->dmabuf + 2112; | |
674 | ||
8c61b7a7 SB |
675 | cafe->rs = init_rs_non_canonical(12, &cafe_mul, 0, 1, 8); |
676 | if (!cafe->rs) { | |
677 | err = -ENOMEM; | |
678 | goto out_ior; | |
679 | } | |
680 | ||
5467fb02 DW |
681 | cafe->nand.cmdfunc = cafe_nand_cmdfunc; |
682 | cafe->nand.dev_ready = cafe_device_ready; | |
683 | cafe->nand.read_byte = cafe_read_byte; | |
684 | cafe->nand.read_buf = cafe_read_buf; | |
685 | cafe->nand.write_buf = cafe_write_buf; | |
686 | cafe->nand.select_chip = cafe_select_chip; | |
687 | ||
688 | cafe->nand.chip_delay = 0; | |
689 | ||
690 | /* Enable the following for a flash based bad block table */ | |
691 | cafe->nand.options = NAND_USE_FLASH_BBT | NAND_NO_AUTOINCR | NAND_OWN_BUFFERS; | |
8dd851de DW |
692 | |
693 | if (skipbbt) { | |
694 | cafe->nand.options |= NAND_SKIP_BBTSCAN; | |
695 | cafe->nand.block_bad = cafe_nand_block_bad; | |
696 | } | |
c9ac5977 | 697 | |
527a4f45 DW |
698 | if (numtimings && numtimings != 3) { |
699 | dev_warn(&cafe->pdev->dev, "%d timing register values ignored; precisely three are required\n", numtimings); | |
700 | } | |
701 | ||
702 | if (numtimings == 3) { | |
527a4f45 | 703 | cafe_dev_dbg(&cafe->pdev->dev, "Using provided timings (%08x %08x %08x)\n", |
8e5368a1 | 704 | timing[0], timing[1], timing[2]); |
527a4f45 | 705 | } else { |
8e5368a1 DW |
706 | timing[0] = cafe_readl(cafe, NAND_TIMING1); |
707 | timing[1] = cafe_readl(cafe, NAND_TIMING2); | |
708 | timing[2] = cafe_readl(cafe, NAND_TIMING3); | |
527a4f45 | 709 | |
8e5368a1 DW |
710 | if (timing[0] | timing[1] | timing[2]) { |
711 | cafe_dev_dbg(&cafe->pdev->dev, "Timing registers already set (%08x %08x %08x)\n", | |
712 | timing[0], timing[1], timing[2]); | |
527a4f45 DW |
713 | } else { |
714 | dev_warn(&cafe->pdev->dev, "Timing registers unset; using most conservative defaults\n"); | |
8e5368a1 | 715 | timing[0] = timing[1] = timing[2] = 0xffffffff; |
527a4f45 DW |
716 | } |
717 | } | |
718 | ||
dcc41bc8 | 719 | /* Start off by resetting the NAND controller completely */ |
195a253b DW |
720 | cafe_writel(cafe, 1, NAND_RESET); |
721 | cafe_writel(cafe, 0, NAND_RESET); | |
dcc41bc8 | 722 | |
8e5368a1 DW |
723 | cafe_writel(cafe, timing[0], NAND_TIMING1); |
724 | cafe_writel(cafe, timing[1], NAND_TIMING2); | |
725 | cafe_writel(cafe, timing[2], NAND_TIMING3); | |
b478c775 | 726 | |
195a253b | 727 | cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK); |
2db6346f TG |
728 | err = request_irq(pdev->irq, &cafe_nand_interrupt, IRQF_SHARED, |
729 | "CAFE NAND", mtd); | |
5467fb02 DW |
730 | if (err) { |
731 | dev_warn(&pdev->dev, "Could not register IRQ %d\n", pdev->irq); | |
5467fb02 DW |
732 | goto out_free_dma; |
733 | } | |
f7c37d7b | 734 | |
5467fb02 | 735 | /* Disable master reset, enable NAND clock */ |
195a253b | 736 | ctrl = cafe_readl(cafe, GLOBAL_CTRL); |
5467fb02 DW |
737 | ctrl &= 0xffffeff0; |
738 | ctrl |= 0x00007000; | |
195a253b DW |
739 | cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL); |
740 | cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL); | |
741 | cafe_writel(cafe, 0, NAND_DMA_CTRL); | |
5467fb02 | 742 | |
195a253b DW |
743 | cafe_writel(cafe, 0x7006, GLOBAL_CTRL); |
744 | cafe_writel(cafe, 0x700a, GLOBAL_CTRL); | |
5467fb02 DW |
745 | |
746 | /* Set up DMA address */ | |
195a253b | 747 | cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0); |
5467fb02 | 748 | if (sizeof(cafe->dmaaddr) > 4) |
fbad5696 | 749 | /* Shift in two parts to shut the compiler up */ |
195a253b | 750 | cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1); |
5467fb02 | 751 | else |
195a253b | 752 | cafe_writel(cafe, 0, NAND_DMA_ADDR1); |
fbad5696 | 753 | |
8dd851de | 754 | cafe_dev_dbg(&cafe->pdev->dev, "Set DMA address to %x (virt %p)\n", |
195a253b | 755 | cafe_readl(cafe, NAND_DMA_ADDR0), cafe->dmabuf); |
5467fb02 DW |
756 | |
757 | /* Enable NAND IRQ in global IRQ mask register */ | |
195a253b | 758 | cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK); |
8dd851de | 759 | cafe_dev_dbg(&cafe->pdev->dev, "Control %x, IRQ mask %x\n", |
195a253b | 760 | cafe_readl(cafe, GLOBAL_CTRL), cafe_readl(cafe, GLOBAL_IRQ_MASK)); |
f7c37d7b DW |
761 | |
762 | /* Scan to find existence of the device */ | |
048c37b4 | 763 | if (nand_scan_ident(mtd, 2)) { |
5467fb02 DW |
764 | err = -ENXIO; |
765 | goto out_irq; | |
766 | } | |
767 | ||
768 | cafe->ctl2 = 1<<27; /* Reed-Solomon ECC */ | |
769 | if (mtd->writesize == 2048) | |
770 | cafe->ctl2 |= 1<<29; /* 2KiB page size */ | |
771 | ||
772 | /* Set up ECC according to the type of chip we found */ | |
fbad5696 | 773 | if (mtd->writesize == 2048) { |
8dd851de DW |
774 | cafe->nand.ecc.layout = &cafe_oobinfo_2048; |
775 | cafe->nand.bbt_td = &cafe_bbt_main_descr_2048; | |
776 | cafe->nand.bbt_md = &cafe_bbt_mirror_descr_2048; | |
fbad5696 DW |
777 | } else if (mtd->writesize == 512) { |
778 | cafe->nand.ecc.layout = &cafe_oobinfo_512; | |
779 | cafe->nand.bbt_td = &cafe_bbt_main_descr_512; | |
780 | cafe->nand.bbt_md = &cafe_bbt_mirror_descr_512; | |
5467fb02 | 781 | } else { |
fbad5696 | 782 | printk(KERN_WARNING "Unexpected NAND flash writesize %d. Aborting\n", |
5467fb02 | 783 | mtd->writesize); |
fbad5696 | 784 | goto out_irq; |
5467fb02 | 785 | } |
fbad5696 DW |
786 | cafe->nand.ecc.mode = NAND_ECC_HW_SYNDROME; |
787 | cafe->nand.ecc.size = mtd->writesize; | |
788 | cafe->nand.ecc.bytes = 14; | |
789 | cafe->nand.ecc.hwctl = (void *)cafe_nand_bug; | |
790 | cafe->nand.ecc.calculate = (void *)cafe_nand_bug; | |
791 | cafe->nand.ecc.correct = (void *)cafe_nand_bug; | |
792 | cafe->nand.write_page = cafe_nand_write_page; | |
793 | cafe->nand.ecc.write_page = cafe_nand_write_page_lowlevel; | |
794 | cafe->nand.ecc.write_oob = cafe_nand_write_oob; | |
795 | cafe->nand.ecc.read_page = cafe_nand_read_page; | |
796 | cafe->nand.ecc.read_oob = cafe_nand_read_oob; | |
5467fb02 DW |
797 | |
798 | err = nand_scan_tail(mtd); | |
799 | if (err) | |
800 | goto out_irq; | |
801 | ||
5467fb02 | 802 | pci_set_drvdata(pdev, mtd); |
9c37f332 DW |
803 | |
804 | /* We register the whole device first, separate from the partitions */ | |
5467fb02 | 805 | add_mtd_device(mtd); |
9c37f332 DW |
806 | |
807 | #ifdef CONFIG_MTD_PARTITIONS | |
68874414 PR |
808 | #ifdef CONFIG_MTD_CMDLINE_PARTS |
809 | mtd->name = "cafe_nand"; | |
810 | #endif | |
9c37f332 DW |
811 | nr_parts = parse_mtd_partitions(mtd, part_probes, &parts, 0); |
812 | if (nr_parts > 0) { | |
813 | cafe->parts = parts; | |
68874414 | 814 | dev_info(&cafe->pdev->dev, "%d partitions found\n", nr_parts); |
9c37f332 DW |
815 | add_mtd_partitions(mtd, parts, nr_parts); |
816 | } | |
817 | #endif | |
5467fb02 DW |
818 | goto out; |
819 | ||
820 | out_irq: | |
821 | /* Disable NAND IRQ in global IRQ mask register */ | |
195a253b | 822 | cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK); |
5467fb02 DW |
823 | free_irq(pdev->irq, mtd); |
824 | out_free_dma: | |
825 | dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr); | |
826 | out_ior: | |
827 | pci_iounmap(pdev, cafe->mmio); | |
828 | out_free_mtd: | |
829 | kfree(mtd); | |
830 | out: | |
831 | return err; | |
832 | } | |
833 | ||
834 | static void __devexit cafe_nand_remove(struct pci_dev *pdev) | |
835 | { | |
836 | struct mtd_info *mtd = pci_get_drvdata(pdev); | |
837 | struct cafe_priv *cafe = mtd->priv; | |
838 | ||
839 | del_mtd_device(mtd); | |
840 | /* Disable NAND IRQ in global IRQ mask register */ | |
195a253b | 841 | cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK); |
5467fb02 DW |
842 | free_irq(pdev->irq, mtd); |
843 | nand_release(mtd); | |
8c61b7a7 | 844 | free_rs(cafe->rs); |
5467fb02 DW |
845 | pci_iounmap(pdev, cafe->mmio); |
846 | dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr); | |
847 | kfree(mtd); | |
848 | } | |
849 | ||
850 | static struct pci_device_id cafe_nand_tbl[] = { | |
514fca43 DW |
851 | { PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_88ALP01_NAND, |
852 | PCI_ANY_ID, PCI_ANY_ID }, | |
06ed24e5 | 853 | { } |
5467fb02 DW |
854 | }; |
855 | ||
856 | MODULE_DEVICE_TABLE(pci, cafe_nand_tbl); | |
857 | ||
1fcf8ce5 DW |
858 | static int cafe_nand_resume(struct pci_dev *pdev) |
859 | { | |
860 | uint32_t ctrl; | |
861 | struct mtd_info *mtd = pci_get_drvdata(pdev); | |
862 | struct cafe_priv *cafe = mtd->priv; | |
863 | ||
864 | /* Start off by resetting the NAND controller completely */ | |
865 | cafe_writel(cafe, 1, NAND_RESET); | |
866 | cafe_writel(cafe, 0, NAND_RESET); | |
867 | cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK); | |
868 | ||
869 | /* Restore timing configuration */ | |
870 | cafe_writel(cafe, timing[0], NAND_TIMING1); | |
871 | cafe_writel(cafe, timing[1], NAND_TIMING2); | |
872 | cafe_writel(cafe, timing[2], NAND_TIMING3); | |
873 | ||
874 | /* Disable master reset, enable NAND clock */ | |
875 | ctrl = cafe_readl(cafe, GLOBAL_CTRL); | |
876 | ctrl &= 0xffffeff0; | |
877 | ctrl |= 0x00007000; | |
878 | cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL); | |
879 | cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL); | |
880 | cafe_writel(cafe, 0, NAND_DMA_CTRL); | |
881 | cafe_writel(cafe, 0x7006, GLOBAL_CTRL); | |
882 | cafe_writel(cafe, 0x700a, GLOBAL_CTRL); | |
883 | ||
884 | /* Set up DMA address */ | |
885 | cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0); | |
886 | if (sizeof(cafe->dmaaddr) > 4) | |
887 | /* Shift in two parts to shut the compiler up */ | |
888 | cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1); | |
889 | else | |
890 | cafe_writel(cafe, 0, NAND_DMA_ADDR1); | |
891 | ||
892 | /* Enable NAND IRQ in global IRQ mask register */ | |
893 | cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK); | |
894 | return 0; | |
895 | } | |
896 | ||
5467fb02 DW |
897 | static struct pci_driver cafe_nand_pci_driver = { |
898 | .name = "CAFÉ NAND", | |
899 | .id_table = cafe_nand_tbl, | |
900 | .probe = cafe_nand_probe, | |
901 | .remove = __devexit_p(cafe_nand_remove), | |
5467fb02 | 902 | .resume = cafe_nand_resume, |
5467fb02 DW |
903 | }; |
904 | ||
905 | static int cafe_nand_init(void) | |
906 | { | |
907 | return pci_register_driver(&cafe_nand_pci_driver); | |
908 | } | |
909 | ||
910 | static void cafe_nand_exit(void) | |
911 | { | |
912 | pci_unregister_driver(&cafe_nand_pci_driver); | |
913 | } | |
914 | module_init(cafe_nand_init); | |
915 | module_exit(cafe_nand_exit); | |
916 | ||
917 | MODULE_LICENSE("GPL"); | |
918 | MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>"); | |
f7c37d7b | 919 | MODULE_DESCRIPTION("NAND flash driver for OLPC CAFÉ chip"); |