[deliverable/linux.git] / drivers / mtd / nand / cs553x_nand.c

/*
 * drivers/mtd/nand/cs553x_nand.c
 *
 * (C) 2005, 2006 Red Hat Inc.
 *
 * Author: David Woodhouse <dwmw2@infradead.org>
 *	   Tom Sylla <tom.sylla@amd.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  Overview:
 *   This is a device driver for the NAND flash controller found on 
 *   the AMD CS5535/CS5536 companion chipsets for the Geode processor.
 *
 */

#include <linux/slab.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>

#include <asm/msr.h>
#include <asm/io.h>

#define NR_CS553X_CONTROLLERS	4

/* NAND Timing MSRs */
#define MSR_NANDF_DATA		0x5140001b	/* NAND Flash Data Timing MSR */
#define MSR_NANDF_CTL		0x5140001c	/* NAND Flash Control Timing */
#define MSR_NANDF_RSVD		0x5140001d	/* Reserved */

/* NAND BAR MSRs */
#define MSR_DIVIL_LBAR_FLSH0	0x51400010	/* Flash Chip Select 0 */
#define MSR_DIVIL_LBAR_FLSH1	0x51400011	/* Flash Chip Select 1 */
#define MSR_DIVIL_LBAR_FLSH2	0x51400012	/* Flash Chip Select 2 */
#define MSR_DIVIL_LBAR_FLSH3	0x51400013	/* Flash Chip Select 3 */
	/* Each made up of... */
#define FLSH_LBAR_EN		(1ULL<<32)
#define FLSH_NOR_NAND		(1ULL<<33)	/* 1 for NAND */
#define FLSH_MEM_IO		(1ULL<<34)	/* 1 for MMIO */
	/* I/O BARs have BASE_ADDR in bits 15:4, IO_MASK in 47:36 */
	/* MMIO BARs have BASE_ADDR in bits 31:12, MEM_MASK in 63:44 */

/* Pin function selection MSR (IDE vs. flash on the IDE pins) */
#define MSR_DIVIL_BALL_OPTS	0x51400015
#define PIN_OPT_IDE		(1<<0)	/* 0 for flash, 1 for IDE */

/* Registers within the NAND flash controller BAR -- memory mapped */
#define MM_NAND_DATA		0x00	/* 0 to 0x7ff, in fact */
#define MM_NAND_CTL		0x800	/* Any even address 0x800-0x80e */
#define MM_NAND_IO		0x801	/* Any odd address 0x801-0x80f */
#define MM_NAND_STS		0x810
#define MM_NAND_ECC_LSB		0x811
#define MM_NAND_ECC_MSB		0x812
#define MM_NAND_ECC_COL		0x813
#define MM_NAND_LAC		0x814
#define MM_NAND_ECC_CTL		0x815

/* Registers within the NAND flash controller BAR -- I/O mapped */
#define IO_NAND_DATA		0x00	/* 0 to 3, in fact */
#define IO_NAND_CTL		0x04
#define IO_NAND_IO		0x05
#define IO_NAND_STS		0x06
#define IO_NAND_ECC_CTL		0x08
#define IO_NAND_ECC_LSB		0x09
#define IO_NAND_ECC_MSB		0x0a
#define IO_NAND_ECC_COL		0x0b
#define IO_NAND_LAC		0x0c

#define CS_NAND_CTL_DIST_EN	(1<<4)	/* Enable NAND Distract interrupt */
#define CS_NAND_CTL_RDY_INT_MASK	(1<<3)	/* Enable RDY/BUSY# interrupt */
#define CS_NAND_CTL_ALE		(1<<2)
#define CS_NAND_CTL_CLE		(1<<1)
#define CS_NAND_CTL_CE		(1<<0)	/* Keep low; 1 to reset */

#define CS_NAND_STS_FLASH_RDY	(1<<3)
#define CS_NAND_CTLR_BUSY	(1<<2)
#define CS_NAND_CMD_COMP	(1<<1)
#define CS_NAND_DIST_ST		(1<<0)

#define CS_NAND_ECC_PARITY	(1<<2)
#define CS_NAND_ECC_CLRECC	(1<<1)
#define CS_NAND_ECC_ENECC	(1<<0)

static void cs553x_read_buf(struct mtd_info *mtd, u_char *buf, int len)
{
	struct nand_chip *this = mtd->priv;

	while (unlikely(len > 0x800)) {
		memcpy_fromio(buf, this->IO_ADDR_R, 0x800);
		buf += 0x800;
		len -= 0x800;
	}
	memcpy_fromio(buf, this->IO_ADDR_R, len);
}

static void cs553x_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
{
	struct nand_chip *this = mtd->priv;

	while (unlikely(len > 0x800)) {
		memcpy_toio(this->IO_ADDR_R, buf, 0x800);
		buf += 0x800;
		len -= 0x800;
	}
	memcpy_toio(this->IO_ADDR_R, buf, len);
}

static unsigned char cs553x_read_byte(struct mtd_info *mtd)
{
	struct nand_chip *this = mtd->priv;
	return readb(this->IO_ADDR_R);
}

static void cs553x_write_byte(struct mtd_info *mtd, u_char byte)
{
	struct nand_chip *this = mtd->priv;
	int i = 100000;

	while (i && readb(this->IO_ADDR_R + MM_NAND_STS) & CS_NAND_CTLR_BUSY) {
		udelay(1);
		i--;
	}
	writeb(byte, this->IO_ADDR_W + 0x801);
}

static void cs553x_hwcontrol(struct mtd_info *mtd, int cmd)
{
	struct nand_chip *this = mtd->priv;
	void __iomem *mmio_base = this->IO_ADDR_R;
	unsigned char ctl;

	switch (cmd) {
	case NAND_CTL_SETCLE:
		ctl = CS_NAND_CTL_CLE;
		break;

	case NAND_CTL_CLRCLE:
	case NAND_CTL_CLRALE:
	case NAND_CTL_SETNCE:
		ctl = 0;
		break;

	case NAND_CTL_SETALE:
		ctl = CS_NAND_CTL_ALE;
		break;

	default:
	case NAND_CTL_CLRNCE:
		ctl = CS_NAND_CTL_CE;
		break;
	}
	writeb(ctl, mmio_base + MM_NAND_CTL);
}

static int cs553x_device_ready(struct mtd_info *mtd)
{
	struct nand_chip *this = mtd->priv;
	void __iomem *mmio_base = this->IO_ADDR_R;
	unsigned char foo = readb(mmio_base + MM_NAND_STS);

	return (foo & CS_NAND_STS_FLASH_RDY) && !(foo & CS_NAND_CTLR_BUSY);
}

static void cs_enable_hwecc(struct mtd_info *mtd, int mode)
{
	struct nand_chip *this = mtd->priv;
	void __iomem *mmio_base = this->IO_ADDR_R;

	writeb(0x07, mmio_base + MM_NAND_ECC_CTL);
}

static int cs_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
{
	uint32_t ecc;
	struct nand_chip *this = mtd->priv;
	void __iomem *mmio_base = this->IO_ADDR_R;

	ecc = readl(mmio_base + MM_NAND_STS);

	ecc_code[1] = ecc >> 8;
	ecc_code[0] = ecc >> 16;
	ecc_code[2] = ecc >> 24;
	return 0;
}

static struct mtd_info *cs553x_mtd[4];

static int __init cs553x_init_one(int cs, int mmio, unsigned long adr)
{
	int err = 0;
	struct nand_chip *this;
	struct mtd_info *new_mtd;

	printk(KERN_NOTICE "Probing CS553x NAND controller CS#%d at %sIO 0x%08lx\n", cs, mmio?"MM":"P", adr);

	if (!mmio) {
		printk(KERN_NOTICE "PIO mode not yet implemented for CS553X NAND controller\n");
		return -ENXIO;
	}

	/* Allocate memory for MTD device structure and private data */
	new_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
	if (!new_mtd) {
		printk(KERN_WARNING "Unable to allocate CS553X NAND MTD device structure.\n");
		err = -ENOMEM;
		goto out;
	}

	/* Get pointer to private data */
	this = (struct nand_chip *)(&new_mtd[1]);

	/* Initialize structures */
	memset(new_mtd, 0, sizeof(struct mtd_info));
	memset(this, 0, sizeof(struct nand_chip));

	/* Link the private data with the MTD structure */
	new_mtd->priv = this;
	new_mtd->owner = THIS_MODULE;

	/* map physical address */
	this->IO_ADDR_R = this->IO_ADDR_W = ioremap(adr, 4096);
	if (!this->IO_ADDR_R) {
		printk(KERN_WARNING "ioremap cs553x NAND @0x%08lx failed\n", adr);
		err = -EIO;
		goto out_mtd;
	}

	this->hwcontrol = cs553x_hwcontrol;
	this->dev_ready = cs553x_device_ready;
	this->read_byte = cs553x_read_byte;
	this->write_byte = cs553x_write_byte;
	this->read_buf = cs553x_read_buf;
	this->write_buf = cs553x_write_buf;

	this->chip_delay = 0;

	this->ecc.mode = NAND_ECC_HW;
	this->ecc.size = 256;
	this->ecc.bytes = 3;
	this->ecc.hwctl  = cs_enable_hwecc;
	this->ecc.calculate = cs_calculate_ecc;
	this->ecc.correct  = nand_correct_data;

	/* Enable the following for a flash based bad block table */
	this->options = NAND_USE_FLASH_BBT | NAND_NO_AUTOINCR;

	/* Scan to find existance of the device */
	if (nand_scan(new_mtd, 1)) {
		err = -ENXIO;
		goto out_ior;
	}

	cs553x_mtd[cs] = new_mtd;
	goto out;

out_ior:
	iounmap((void *)this->IO_ADDR_R);
out_mtd:
	kfree(new_mtd);
out:
	return err;
}

static int __init cs553x_init(void)
{
	int err = -ENXIO;
	int i;
	uint64_t val;

	/* Check whether we actually have a CS5535 or CS5536 */
	if (!pci_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, NULL) &&
	    !pci_find_device(PCI_VENDOR_ID_NS,  PCI_DEVICE_ID_NS_CS5535_ISA, NULL))
		return -ENXIO;

	rdmsrl(MSR_DIVIL_BALL_OPTS, val);
	if (val & 1) {
		printk(KERN_INFO "CS553x NAND controller: Flash I/O not enabled in MSR_DIVIL_BALL_OPTS.\n");
		return -ENXIO;
	}

	for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
		rdmsrl(MSR_DIVIL_LBAR_FLSH0 + i, val);

		if ((val & (FLSH_LBAR_EN|FLSH_NOR_NAND)) == (FLSH_LBAR_EN|FLSH_NOR_NAND))
			err = cs553x_init_one(i, !!(val & FLSH_MEM_IO), val & 0xFFFFFFFF);
	}

	/* Register all devices together here. This means we can easily hack it to 
	   do mtdconcat etc. if we want to. */
	for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
		if (cs553x_mtd[i]) {
			add_mtd_device(cs553x_mtd[i]);

			/* If any devices registered, return success. Else the last error. */
			err = 0;
		}
	}

	return err;
}

module_init(cs553x_init);

static void __exit cs553x_cleanup(void)
{
	int i;

	for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
		struct mtd_info *mtd = cs553x_mtd[i];
		struct nand_chip *this;
		void __iomem *mmio_base;

		if (!mtd)
			break;

		this = cs553x_mtd[i]->priv;
		mmio_base = this->IO_ADDR_R;

		/* Release resources, unregister device */
		nand_release(cs553x_mtd[i]);
		cs553x_mtd[i] = NULL;

		/* unmap physical adress */
		iounmap(mmio_base);

		/* Free the MTD device structure */
		kfree(mtd);
	}
}

module_exit(cs553x_cleanup);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
MODULE_DESCRIPTION("NAND controller driver for AMD CS5535/CS5536 companion chip");
Commit	Line	Data
179fdc3f DW	1	/*
	2	* drivers/mtd/nand/cs553x_nand.c
	3	*
	4	* (C) 2005, 2006 Red Hat Inc.
	5	*
	6	* Author: David Woodhouse <dwmw2@infradead.org>
9d75414b	7	* Tom Sylla <tom.sylla@amd.com>
179fdc3f DW	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*
	13	* Overview:
	14	* This is a device driver for the NAND flash controller found on
	15	* the AMD CS5535/CS5536 companion chipsets for the Geode processor.
	16	*
	17	*/
	18
	19	#include <linux/slab.h>
	20	#include <linux/init.h>
	21	#include <linux/module.h>
	22	#include <linux/delay.h>
	23	#include <linux/pci.h>
	24	#include <linux/mtd/mtd.h>
	25	#include <linux/mtd/nand.h>
9d75414b	26	#include <linux/mtd/nand_ecc.h>
179fdc3f DW	27	#include <linux/mtd/partitions.h>
	28
	29	#include <asm/msr.h>
	30	#include <asm/io.h>
	31
	32	#define NR_CS553X_CONTROLLERS 4
	33
	34	/* NAND Timing MSRs */
	35	#define MSR_NANDF_DATA 0x5140001b /* NAND Flash Data Timing MSR */
	36	#define MSR_NANDF_CTL 0x5140001c /* NAND Flash Control Timing */
	37	#define MSR_NANDF_RSVD 0x5140001d /* Reserved */
	38
	39	/* NAND BAR MSRs */
	40	#define MSR_DIVIL_LBAR_FLSH0 0x51400010 /* Flash Chip Select 0 */
	41	#define MSR_DIVIL_LBAR_FLSH1 0x51400011 /* Flash Chip Select 1 */
	42	#define MSR_DIVIL_LBAR_FLSH2 0x51400012 /* Flash Chip Select 2 */
	43	#define MSR_DIVIL_LBAR_FLSH3 0x51400013 /* Flash Chip Select 3 */
	44	/* Each made up of... */
	45	#define FLSH_LBAR_EN (1ULL<<32)
	46	#define FLSH_NOR_NAND (1ULL<<33) /* 1 for NAND */
	47	#define FLSH_MEM_IO (1ULL<<34) /* 1 for MMIO */
	48	/* I/O BARs have BASE_ADDR in bits 15:4, IO_MASK in 47:36 */
	49	/* MMIO BARs have BASE_ADDR in bits 31:12, MEM_MASK in 63:44 */
	50
	51	/* Pin function selection MSR (IDE vs. flash on the IDE pins) */
	52	#define MSR_DIVIL_BALL_OPTS 0x51400015
e0c7d767	53	#define PIN_OPT_IDE (1<<0) /* 0 for flash, 1 for IDE */
179fdc3f DW	54
	55	/* Registers within the NAND flash controller BAR -- memory mapped */
	56	#define MM_NAND_DATA 0x00 /* 0 to 0x7ff, in fact */
	57	#define MM_NAND_CTL 0x800 /* Any even address 0x800-0x80e */
	58	#define MM_NAND_IO 0x801 /* Any odd address 0x801-0x80f */
	59	#define MM_NAND_STS 0x810
	60	#define MM_NAND_ECC_LSB 0x811
	61	#define MM_NAND_ECC_MSB 0x812
	62	#define MM_NAND_ECC_COL 0x813
	63	#define MM_NAND_LAC 0x814
	64	#define MM_NAND_ECC_CTL 0x815
	65
	66	/* Registers within the NAND flash controller BAR -- I/O mapped */
	67	#define IO_NAND_DATA 0x00 /* 0 to 3, in fact */
	68	#define IO_NAND_CTL 0x04
	69	#define IO_NAND_IO 0x05
	70	#define IO_NAND_STS 0x06
	71	#define IO_NAND_ECC_CTL 0x08
	72	#define IO_NAND_ECC_LSB 0x09
	73	#define IO_NAND_ECC_MSB 0x0a
	74	#define IO_NAND_ECC_COL 0x0b
	75	#define IO_NAND_LAC 0x0c
	76
	77	#define CS_NAND_CTL_DIST_EN (1<<4) /* Enable NAND Distract interrupt */
	78	#define CS_NAND_CTL_RDY_INT_MASK (1<<3) /* Enable RDY/BUSY# interrupt */
	79	#define CS_NAND_CTL_ALE (1<<2)
	80	#define CS_NAND_CTL_CLE (1<<1)
	81	#define CS_NAND_CTL_CE (1<<0) /* Keep low; 1 to reset */
	82
	83	#define CS_NAND_STS_FLASH_RDY (1<<3)
	84	#define CS_NAND_CTLR_BUSY (1<<2)
	85	#define CS_NAND_CMD_COMP (1<<1)
	86	#define CS_NAND_DIST_ST (1<<0)
	87
	88	#define CS_NAND_ECC_PARITY (1<<2)
	89	#define CS_NAND_ECC_CLRECC (1<<1)
	90	#define CS_NAND_ECC_ENECC (1<<0)
	91
9d75414b DW	92	static void cs553x_read_buf(struct mtd_info mtd, u_char buf, int len)
	93	{
	94	struct nand_chip *this = mtd->priv;
	95
	96	while (unlikely(len > 0x800)) {
	97	memcpy_fromio(buf, this->IO_ADDR_R, 0x800);
	98	buf += 0x800;
	99	len -= 0x800;
	100	}
	101	memcpy_fromio(buf, this->IO_ADDR_R, len);
	102	}
	103
	104	static void cs553x_write_buf(struct mtd_info mtd, const u_char buf, int len)
	105	{
	106	struct nand_chip *this = mtd->priv;
	107
	108	while (unlikely(len > 0x800)) {
	109	memcpy_toio(this->IO_ADDR_R, buf, 0x800);
	110	buf += 0x800;
	111	len -= 0x800;
	112	}
	113	memcpy_toio(this->IO_ADDR_R, buf, len);
	114	}
	115
179fdc3f DW	116	static unsigned char cs553x_read_byte(struct mtd_info *mtd)
	117	{
	118	struct nand_chip *this = mtd->priv;
9d75414b	119	return readb(this->IO_ADDR_R);
179fdc3f DW	120	}
	121
	122	static void cs553x_write_byte(struct mtd_info *mtd, u_char byte)
	123	{
	124	struct nand_chip *this = mtd->priv;
	125	int i = 100000;
	126
	127	while (i && readb(this->IO_ADDR_R + MM_NAND_STS) & CS_NAND_CTLR_BUSY) {
	128	udelay(1);
	129	i--;
	130	}
e0c7d767	131	writeb(byte, this->IO_ADDR_W + 0x801);
179fdc3f DW	132	}
	133
	134	static void cs553x_hwcontrol(struct mtd_info *mtd, int cmd)
	135	{
	136	struct nand_chip *this = mtd->priv;
	137	void __iomem *mmio_base = this->IO_ADDR_R;
9d75414b	138	unsigned char ctl;
179fdc3f	139
e0c7d767	140	switch (cmd) {
179fdc3f	141	case NAND_CTL_SETCLE:
9d75414b	142	ctl = CS_NAND_CTL_CLE;
179fdc3f DW	143	break;
	144
	145	case NAND_CTL_CLRCLE:
179fdc3f	146	case NAND_CTL_CLRALE:
9d75414b DW	147	case NAND_CTL_SETNCE:
9d75414b DW	148	ctl = 0;
179fdc3f DW	149	break;
179fdc3f DW	150
9d75414b DW	151	case NAND_CTL_SETALE:
9d75414b DW	152	ctl = CS_NAND_CTL_ALE;
179fdc3f DW	153	break;
179fdc3f DW	154
9d75414b	155	default:
179fdc3f	156	case NAND_CTL_CLRNCE:
9d75414b	157	ctl = CS_NAND_CTL_CE;
179fdc3f DW	158	break;
179fdc3f DW	159	}
9d75414b	160	writeb(ctl, mmio_base + MM_NAND_CTL);
179fdc3f DW	161	}
179fdc3f DW	162
179fdc3f DW	163	static int cs553x_device_ready(struct mtd_info *mtd)
	164	{
	165	struct nand_chip *this = mtd->priv;
	166	void __iomem *mmio_base = this->IO_ADDR_R;
	167	unsigned char foo = readb(mmio_base + MM_NAND_STS);
	168
e0c7d767	169	return (foo & CS_NAND_STS_FLASH_RDY) && !(foo & CS_NAND_CTLR_BUSY);
179fdc3f DW	170	}
179fdc3f DW	171
9d75414b DW	172	static void cs_enable_hwecc(struct mtd_info *mtd, int mode)
	173	{
	174	struct nand_chip *this = mtd->priv;
	175	void __iomem *mmio_base = this->IO_ADDR_R;
	176
	177	writeb(0x07, mmio_base + MM_NAND_ECC_CTL);
	178	}
	179
	180	static int cs_calculate_ecc(struct mtd_info mtd, const u_char dat, u_char *ecc_code)
	181	{
	182	uint32_t ecc;
	183	struct nand_chip *this = mtd->priv;
	184	void __iomem *mmio_base = this->IO_ADDR_R;
	185
	186	ecc = readl(mmio_base + MM_NAND_STS);
	187
	188	ecc_code[1] = ecc >> 8;
	189	ecc_code[0] = ecc >> 16;
	190	ecc_code[2] = ecc >> 24;
	191	return 0;
	192	}
	193
179fdc3f DW	194	static struct mtd_info *cs553x_mtd[4];
	195
	196	static int __init cs553x_init_one(int cs, int mmio, unsigned long adr)
	197	{
	198	int err = 0;
	199	struct nand_chip *this;
	200	struct mtd_info *new_mtd;
	201
	202	printk(KERN_NOTICE "Probing CS553x NAND controller CS#%d at %sIO 0x%08lx\n", cs, mmio?"MM":"P", adr);
	203
	204	if (!mmio) {
	205	printk(KERN_NOTICE "PIO mode not yet implemented for CS553X NAND controller\n");
	206	return -ENXIO;
	207	}
	208
	209	/* Allocate memory for MTD device structure and private data */
e0c7d767	210	new_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
179fdc3f DW	211	if (!new_mtd) {
	212	printk(KERN_WARNING "Unable to allocate CS553X NAND MTD device structure.\n");
	213	err = -ENOMEM;
	214	goto out;
	215	}
	216
	217	/* Get pointer to private data */
e0c7d767	218	this = (struct nand_chip *)(&new_mtd[1]);
179fdc3f DW	219
179fdc3f DW	220	/* Initialize structures */
9d75414b DW	221	memset(new_mtd, 0, sizeof(struct mtd_info));
9d75414b DW	222	memset(this, 0, sizeof(struct nand_chip));
179fdc3f DW	223
	224	/* Link the private data with the MTD structure */
	225	new_mtd->priv = this;
552d9205	226	new_mtd->owner = THIS_MODULE;
179fdc3f DW	227
	228	/* map physical address */
	229	this->IO_ADDR_R = this->IO_ADDR_W = ioremap(adr, 4096);
	230	if (!this->IO_ADDR_R) {
	231	printk(KERN_WARNING "ioremap cs553x NAND @0x%08lx failed\n", adr);
	232	err = -EIO;
	233	goto out_mtd;
	234	}
	235
	236	this->hwcontrol = cs553x_hwcontrol;
	237	this->dev_ready = cs553x_device_ready;
	238	this->read_byte = cs553x_read_byte;
	239	this->write_byte = cs553x_write_byte;
9d75414b DW	240	this->read_buf = cs553x_read_buf;
9d75414b DW	241	this->write_buf = cs553x_write_buf;
179fdc3f	242
9d75414b	243	this->chip_delay = 0;
179fdc3f	244
6dfc6d25 TG	245	this->ecc.mode = NAND_ECC_HW;
	246	this->ecc.size = 256;
	247	this->ecc.bytes = 3;
	248	this->ecc.hwctl = cs_enable_hwecc;
	249	this->ecc.calculate = cs_calculate_ecc;
	250	this->ecc.correct = nand_correct_data;
	251
179fdc3f	252	/* Enable the following for a flash based bad block table */
9d75414b	253	this->options = NAND_USE_FLASH_BBT \| NAND_NO_AUTOINCR;
179fdc3f DW	254
179fdc3f DW	255	/* Scan to find existance of the device */
9d75414b	256	if (nand_scan(new_mtd, 1)) {
179fdc3f DW	257	err = -ENXIO;
	258	goto out_ior;
	259	}
	260
	261	cs553x_mtd[cs] = new_mtd;
	262	goto out;
	263
	264	out_ior:
	265	iounmap((void *)this->IO_ADDR_R);
	266	out_mtd:
9d75414b	267	kfree(new_mtd);
179fdc3f DW	268	out:
	269	return err;
	270	}
	271
cead4dbc	272	static int __init cs553x_init(void)
179fdc3f DW	273	{
	274	int err = -ENXIO;
	275	int i;
	276	uint64_t val;
	277
	278	/* Check whether we actually have a CS5535 or CS5536 */
	279	if (!pci_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, NULL) &&
	280	!pci_find_device(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_CS5535_ISA, NULL))
	281	return -ENXIO;
	282
	283	rdmsrl(MSR_DIVIL_BALL_OPTS, val);
	284	if (val & 1) {
	285	printk(KERN_INFO "CS553x NAND controller: Flash I/O not enabled in MSR_DIVIL_BALL_OPTS.\n");
	286	return -ENXIO;
	287	}
	288
e0c7d767 DW	289	for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
e0c7d767 DW	290	rdmsrl(MSR_DIVIL_LBAR_FLSH0 + i, val);
179fdc3f DW	291
	292	if ((val & (FLSH_LBAR_EN\|FLSH_NOR_NAND)) == (FLSH_LBAR_EN\|FLSH_NOR_NAND))
	293	err = cs553x_init_one(i, !!(val & FLSH_MEM_IO), val & 0xFFFFFFFF);
	294	}
e0c7d767	295
179fdc3f DW	296	/* Register all devices together here. This means we can easily hack it to
179fdc3f DW	297	do mtdconcat etc. if we want to. */
e0c7d767	298	for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
179fdc3f DW	299	if (cs553x_mtd[i]) {
	300	add_mtd_device(cs553x_mtd[i]);
	301
	302	/* If any devices registered, return success. Else the last error. */
	303	err = 0;
	304	}
	305	}
	306
	307	return err;
	308	}
e0c7d767	309
179fdc3f DW	310	module_init(cs553x_init);
179fdc3f DW	311
e0c7d767	312	static void __exit cs553x_cleanup(void)
179fdc3f DW	313	{
	314	int i;
	315
e0c7d767	316	for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
179fdc3f DW	317	struct mtd_info *mtd = cs553x_mtd[i];
	318	struct nand_chip *this;
	319	void __iomem *mmio_base;
	320
	321	if (!mtd)
	322	break;
	323
	324	this = cs553x_mtd[i]->priv;
	325	mmio_base = this->IO_ADDR_R;
	326
	327	/* Release resources, unregister device */
e0c7d767	328	nand_release(cs553x_mtd[i]);
179fdc3f DW	329	cs553x_mtd[i] = NULL;
	330
	331	/* unmap physical adress */
	332	iounmap(mmio_base);
	333
	334	/* Free the MTD device structure */
9d75414b	335	kfree(mtd);
179fdc3f DW	336	}
179fdc3f DW	337	}
e0c7d767	338
179fdc3f DW	339	module_exit(cs553x_cleanup);
	340
	341	MODULE_LICENSE("GPL");
	342	MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
	343	MODULE_DESCRIPTION("NAND controller driver for AMD CS5535/CS5536 companion chip");