[deliverable/linux.git] / drivers / mtd / nand / cs553x_nand.c

/*
 * drivers/mtd/nand/cs553x_nand.c
 *
 * (C) 2005, 2006 Red Hat Inc.
 *
 * Author: David Woodhouse <dwmw2@infradead.org>
 *	   Tom Sylla <tom.sylla@amd.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  Overview:
 *   This is a device driver for the NAND flash controller found on
 *   the AMD CS5535/CS5536 companion chipsets for the Geode processor.
 *   mtd-id for command line partitioning is cs553x_nand_cs[0-3]
 *   where 0-3 reflects the chip select for NAND.
 *
 */

#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>

#include <asm/msr.h>
#include <asm/io.h>

#define NR_CS553X_CONTROLLERS	4

#define MSR_DIVIL_GLD_CAP	0x51400000	/* DIVIL capabilitiies */
#define CAP_CS5535		0x2df000ULL
#define CAP_CS5536		0x5df500ULL

/* NAND Timing MSRs */
#define MSR_NANDF_DATA		0x5140001b	/* NAND Flash Data Timing MSR */
#define MSR_NANDF_CTL		0x5140001c	/* NAND Flash Control Timing */
#define MSR_NANDF_RSVD		0x5140001d	/* Reserved */

/* NAND BAR MSRs */
#define MSR_DIVIL_LBAR_FLSH0	0x51400010	/* Flash Chip Select 0 */
#define MSR_DIVIL_LBAR_FLSH1	0x51400011	/* Flash Chip Select 1 */
#define MSR_DIVIL_LBAR_FLSH2	0x51400012	/* Flash Chip Select 2 */
#define MSR_DIVIL_LBAR_FLSH3	0x51400013	/* Flash Chip Select 3 */
	/* Each made up of... */
#define FLSH_LBAR_EN		(1ULL<<32)
#define FLSH_NOR_NAND		(1ULL<<33)	/* 1 for NAND */
#define FLSH_MEM_IO		(1ULL<<34)	/* 1 for MMIO */
	/* I/O BARs have BASE_ADDR in bits 15:4, IO_MASK in 47:36 */
	/* MMIO BARs have BASE_ADDR in bits 31:12, MEM_MASK in 63:44 */

/* Pin function selection MSR (IDE vs. flash on the IDE pins) */
#define MSR_DIVIL_BALL_OPTS	0x51400015
#define PIN_OPT_IDE		(1<<0)	/* 0 for flash, 1 for IDE */

/* Registers within the NAND flash controller BAR -- memory mapped */
#define MM_NAND_DATA		0x00	/* 0 to 0x7ff, in fact */
#define MM_NAND_CTL		0x800	/* Any even address 0x800-0x80e */
#define MM_NAND_IO		0x801	/* Any odd address 0x801-0x80f */
#define MM_NAND_STS		0x810
#define MM_NAND_ECC_LSB		0x811
#define MM_NAND_ECC_MSB		0x812
#define MM_NAND_ECC_COL		0x813
#define MM_NAND_LAC		0x814
#define MM_NAND_ECC_CTL		0x815

/* Registers within the NAND flash controller BAR -- I/O mapped */
#define IO_NAND_DATA		0x00	/* 0 to 3, in fact */
#define IO_NAND_CTL		0x04
#define IO_NAND_IO		0x05
#define IO_NAND_STS		0x06
#define IO_NAND_ECC_CTL		0x08
#define IO_NAND_ECC_LSB		0x09
#define IO_NAND_ECC_MSB		0x0a
#define IO_NAND_ECC_COL		0x0b
#define IO_NAND_LAC		0x0c

#define CS_NAND_CTL_DIST_EN	(1<<4)	/* Enable NAND Distract interrupt */
#define CS_NAND_CTL_RDY_INT_MASK	(1<<3)	/* Enable RDY/BUSY# interrupt */
#define CS_NAND_CTL_ALE		(1<<2)
#define CS_NAND_CTL_CLE		(1<<1)
#define CS_NAND_CTL_CE		(1<<0)	/* Keep low; 1 to reset */

#define CS_NAND_STS_FLASH_RDY	(1<<3)
#define CS_NAND_CTLR_BUSY	(1<<2)
#define CS_NAND_CMD_COMP	(1<<1)
#define CS_NAND_DIST_ST		(1<<0)

#define CS_NAND_ECC_PARITY	(1<<2)
#define CS_NAND_ECC_CLRECC	(1<<1)
#define CS_NAND_ECC_ENECC	(1<<0)

static void cs553x_read_buf(struct mtd_info *mtd, u_char *buf, int len)
{
	struct nand_chip *this = mtd->priv;

	while (unlikely(len > 0x800)) {
		memcpy_fromio(buf, this->IO_ADDR_R, 0x800);
		buf += 0x800;
		len -= 0x800;
	}
	memcpy_fromio(buf, this->IO_ADDR_R, len);
}

static void cs553x_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
{
	struct nand_chip *this = mtd->priv;

	while (unlikely(len > 0x800)) {
		memcpy_toio(this->IO_ADDR_R, buf, 0x800);
		buf += 0x800;
		len -= 0x800;
	}
	memcpy_toio(this->IO_ADDR_R, buf, len);
}

static unsigned char cs553x_read_byte(struct mtd_info *mtd)
{
	struct nand_chip *this = mtd->priv;
	return readb(this->IO_ADDR_R);
}

static void cs553x_write_byte(struct mtd_info *mtd, u_char byte)
{
	struct nand_chip *this = mtd->priv;
	int i = 100000;

	while (i && readb(this->IO_ADDR_R + MM_NAND_STS) & CS_NAND_CTLR_BUSY) {
		udelay(1);
		i--;
	}
	writeb(byte, this->IO_ADDR_W + 0x801);
}

static void cs553x_hwcontrol(struct mtd_info *mtd, int cmd,
			     unsigned int ctrl)
{
	struct nand_chip *this = mtd->priv;
	void __iomem *mmio_base = this->IO_ADDR_R;
	if (ctrl & NAND_CTRL_CHANGE) {
		unsigned char ctl = (ctrl & ~NAND_CTRL_CHANGE ) ^ 0x01;
		writeb(ctl, mmio_base + MM_NAND_CTL);
	}
	if (cmd != NAND_CMD_NONE)
		cs553x_write_byte(mtd, cmd);
}

static int cs553x_device_ready(struct mtd_info *mtd)
{
	struct nand_chip *this = mtd->priv;
	void __iomem *mmio_base = this->IO_ADDR_R;
	unsigned char foo = readb(mmio_base + MM_NAND_STS);

	return (foo & CS_NAND_STS_FLASH_RDY) && !(foo & CS_NAND_CTLR_BUSY);
}

static void cs_enable_hwecc(struct mtd_info *mtd, int mode)
{
	struct nand_chip *this = mtd->priv;
	void __iomem *mmio_base = this->IO_ADDR_R;

	writeb(0x07, mmio_base + MM_NAND_ECC_CTL);
}

static int cs_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
{
	uint32_t ecc;
	struct nand_chip *this = mtd->priv;
	void __iomem *mmio_base = this->IO_ADDR_R;

	ecc = readl(mmio_base + MM_NAND_STS);

	ecc_code[1] = ecc >> 8;
	ecc_code[0] = ecc >> 16;
	ecc_code[2] = ecc >> 24;
	return 0;
}

static struct mtd_info *cs553x_mtd[4];

static int __init cs553x_init_one(int cs, int mmio, unsigned long adr)
{
	int err = 0;
	struct nand_chip *this;
	struct mtd_info *new_mtd;

	printk(KERN_NOTICE "Probing CS553x NAND controller CS#%d at %sIO 0x%08lx\n", cs, mmio?"MM":"P", adr);

	if (!mmio) {
		printk(KERN_NOTICE "PIO mode not yet implemented for CS553X NAND controller\n");
		return -ENXIO;
	}

	/* Allocate memory for MTD device structure and private data */
	new_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
	if (!new_mtd) {
		printk(KERN_WARNING "Unable to allocate CS553X NAND MTD device structure.\n");
		err = -ENOMEM;
		goto out;
	}

	/* Get pointer to private data */
	this = (struct nand_chip *)(&new_mtd[1]);

	/* Initialize structures */
	memset(new_mtd, 0, sizeof(struct mtd_info));
	memset(this, 0, sizeof(struct nand_chip));

	/* Link the private data with the MTD structure */
	new_mtd->priv = this;
	new_mtd->owner = THIS_MODULE;

	/* map physical address */
	this->IO_ADDR_R = this->IO_ADDR_W = ioremap(adr, 4096);
	if (!this->IO_ADDR_R) {
		printk(KERN_WARNING "ioremap cs553x NAND @0x%08lx failed\n", adr);
		err = -EIO;
		goto out_mtd;
	}

	this->cmd_ctrl = cs553x_hwcontrol;
	this->dev_ready = cs553x_device_ready;
	this->read_byte = cs553x_read_byte;
	this->read_buf = cs553x_read_buf;
	this->write_buf = cs553x_write_buf;

	this->chip_delay = 0;

	this->ecc.mode = NAND_ECC_HW;
	this->ecc.size = 256;
	this->ecc.bytes = 3;
	this->ecc.hwctl  = cs_enable_hwecc;
	this->ecc.calculate = cs_calculate_ecc;
	this->ecc.correct  = nand_correct_data;

	/* Enable the following for a flash based bad block table */
	this->bbt_options = NAND_BBT_USE_FLASH;
	this->options = NAND_NO_AUTOINCR;

	/* Scan to find existence of the device */
	if (nand_scan(new_mtd, 1)) {
		err = -ENXIO;
		goto out_ior;
	}

	this->ecc.strength = 1;

	new_mtd->name = kasprintf(GFP_KERNEL, "cs553x_nand_cs%d", cs);

	cs553x_mtd[cs] = new_mtd;
	goto out;

out_ior:
	iounmap(this->IO_ADDR_R);
out_mtd:
	kfree(new_mtd);
out:
	return err;
}

static int is_geode(void)
{
	/* These are the CPUs which will have a CS553[56] companion chip */
	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
	    boot_cpu_data.x86 == 5 &&
	    boot_cpu_data.x86_model == 10)
		return 1; /* Geode LX */

	if ((boot_cpu_data.x86_vendor == X86_VENDOR_NSC ||
	     boot_cpu_data.x86_vendor == X86_VENDOR_CYRIX) &&
	    boot_cpu_data.x86 == 5 &&
	    boot_cpu_data.x86_model == 5)
		return 1; /* Geode GX (née GX2) */

	return 0;
}

static int __init cs553x_init(void)
{
	int err = -ENXIO;
	int i;
	uint64_t val;

	/* If the CPU isn't a Geode GX or LX, abort */
	if (!is_geode())
		return -ENXIO;

	/* If it doesn't have the CS553[56], abort */
	rdmsrl(MSR_DIVIL_GLD_CAP, val);
	val &= ~0xFFULL;
	if (val != CAP_CS5535 && val != CAP_CS5536)
		return -ENXIO;

	/* If it doesn't have the NAND controller enabled, abort */
	rdmsrl(MSR_DIVIL_BALL_OPTS, val);
	if (val & PIN_OPT_IDE) {
		printk(KERN_INFO "CS553x NAND controller: Flash I/O not enabled in MSR_DIVIL_BALL_OPTS.\n");
		return -ENXIO;
	}

	for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
		rdmsrl(MSR_DIVIL_LBAR_FLSH0 + i, val);

		if ((val & (FLSH_LBAR_EN|FLSH_NOR_NAND)) == (FLSH_LBAR_EN|FLSH_NOR_NAND))
			err = cs553x_init_one(i, !!(val & FLSH_MEM_IO), val & 0xFFFFFFFF);
	}

	/* Register all devices together here. This means we can easily hack it to
	   do mtdconcat etc. if we want to. */
	for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
		if (cs553x_mtd[i]) {
			/* If any devices registered, return success. Else the last error. */
			mtd_device_parse_register(cs553x_mtd[i], NULL, NULL,
						  NULL, 0);
			err = 0;
		}
	}

	return err;
}

module_init(cs553x_init);

static void __exit cs553x_cleanup(void)
{
	int i;

	for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
		struct mtd_info *mtd = cs553x_mtd[i];
		struct nand_chip *this;
		void __iomem *mmio_base;

		if (!mtd)
			continue;

		this = cs553x_mtd[i]->priv;
		mmio_base = this->IO_ADDR_R;

		/* Release resources, unregister device */
		nand_release(cs553x_mtd[i]);
		kfree(cs553x_mtd[i]->name);
		cs553x_mtd[i] = NULL;

		/* unmap physical address */
		iounmap(mmio_base);

		/* Free the MTD device structure */
		kfree(mtd);
	}
}

module_exit(cs553x_cleanup);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
MODULE_DESCRIPTION("NAND controller driver for AMD CS5535/CS5536 companion chip");
Commit	Line	Data
179fdc3f DW	1	/*
	2	* drivers/mtd/nand/cs553x_nand.c
	3	*
	4	* (C) 2005, 2006 Red Hat Inc.
	5	*
	6	* Author: David Woodhouse <dwmw2@infradead.org>
9d75414b	7	* Tom Sylla <tom.sylla@amd.com>
179fdc3f DW	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*
	13	* Overview:
c9ac5977	14	* This is a device driver for the NAND flash controller found on
179fdc3f	15	* the AMD CS5535/CS5536 companion chipsets for the Geode processor.
641f4366 MR	16	* mtd-id for command line partitioning is cs553x_nand_cs[0-3]
641f4366 MR	17	* where 0-3 reflects the chip select for NAND.
179fdc3f DW	18	*
	19	*/
	20
641f4366	21	#include <linux/kernel.h>
179fdc3f DW	22	#include <linux/slab.h>
	23	#include <linux/init.h>
	24	#include <linux/module.h>
	25	#include <linux/delay.h>
179fdc3f DW	26	#include <linux/mtd/mtd.h>
179fdc3f DW	27	#include <linux/mtd/nand.h>
9d75414b	28	#include <linux/mtd/nand_ecc.h>
179fdc3f DW	29	#include <linux/mtd/partitions.h>
	30
	31	#include <asm/msr.h>
	32	#include <asm/io.h>
	33
	34	#define NR_CS553X_CONTROLLERS 4
	35
e4d222ff DW	36	#define MSR_DIVIL_GLD_CAP 0x51400000 /* DIVIL capabilitiies */
	37	#define CAP_CS5535 0x2df000ULL
	38	#define CAP_CS5536 0x5df500ULL
	39
179fdc3f DW	40	/* NAND Timing MSRs */
	41	#define MSR_NANDF_DATA 0x5140001b /* NAND Flash Data Timing MSR */
	42	#define MSR_NANDF_CTL 0x5140001c /* NAND Flash Control Timing */
	43	#define MSR_NANDF_RSVD 0x5140001d /* Reserved */
	44
	45	/* NAND BAR MSRs */
	46	#define MSR_DIVIL_LBAR_FLSH0 0x51400010 /* Flash Chip Select 0 */
	47	#define MSR_DIVIL_LBAR_FLSH1 0x51400011 /* Flash Chip Select 1 */
	48	#define MSR_DIVIL_LBAR_FLSH2 0x51400012 /* Flash Chip Select 2 */
	49	#define MSR_DIVIL_LBAR_FLSH3 0x51400013 /* Flash Chip Select 3 */
	50	/* Each made up of... */
	51	#define FLSH_LBAR_EN (1ULL<<32)
	52	#define FLSH_NOR_NAND (1ULL<<33) /* 1 for NAND */
	53	#define FLSH_MEM_IO (1ULL<<34) /* 1 for MMIO */
	54	/* I/O BARs have BASE_ADDR in bits 15:4, IO_MASK in 47:36 */
	55	/* MMIO BARs have BASE_ADDR in bits 31:12, MEM_MASK in 63:44 */
	56
	57	/* Pin function selection MSR (IDE vs. flash on the IDE pins) */
	58	#define MSR_DIVIL_BALL_OPTS 0x51400015
e0c7d767	59	#define PIN_OPT_IDE (1<<0) /* 0 for flash, 1 for IDE */
179fdc3f DW	60
	61	/* Registers within the NAND flash controller BAR -- memory mapped */
	62	#define MM_NAND_DATA 0x00 /* 0 to 0x7ff, in fact */
	63	#define MM_NAND_CTL 0x800 /* Any even address 0x800-0x80e */
	64	#define MM_NAND_IO 0x801 /* Any odd address 0x801-0x80f */
	65	#define MM_NAND_STS 0x810
	66	#define MM_NAND_ECC_LSB 0x811
	67	#define MM_NAND_ECC_MSB 0x812
	68	#define MM_NAND_ECC_COL 0x813
	69	#define MM_NAND_LAC 0x814
	70	#define MM_NAND_ECC_CTL 0x815
	71
	72	/* Registers within the NAND flash controller BAR -- I/O mapped */
	73	#define IO_NAND_DATA 0x00 /* 0 to 3, in fact */
	74	#define IO_NAND_CTL 0x04
	75	#define IO_NAND_IO 0x05
	76	#define IO_NAND_STS 0x06
	77	#define IO_NAND_ECC_CTL 0x08
	78	#define IO_NAND_ECC_LSB 0x09
	79	#define IO_NAND_ECC_MSB 0x0a
	80	#define IO_NAND_ECC_COL 0x0b
	81	#define IO_NAND_LAC 0x0c
	82
	83	#define CS_NAND_CTL_DIST_EN (1<<4) /* Enable NAND Distract interrupt */
	84	#define CS_NAND_CTL_RDY_INT_MASK (1<<3) /* Enable RDY/BUSY# interrupt */
	85	#define CS_NAND_CTL_ALE (1<<2)
	86	#define CS_NAND_CTL_CLE (1<<1)
	87	#define CS_NAND_CTL_CE (1<<0) /* Keep low; 1 to reset */
	88
	89	#define CS_NAND_STS_FLASH_RDY (1<<3)
	90	#define CS_NAND_CTLR_BUSY (1<<2)
	91	#define CS_NAND_CMD_COMP (1<<1)
	92	#define CS_NAND_DIST_ST (1<<0)
	93
	94	#define CS_NAND_ECC_PARITY (1<<2)
	95	#define CS_NAND_ECC_CLRECC (1<<1)
	96	#define CS_NAND_ECC_ENECC (1<<0)
	97
9d75414b DW	98	static void cs553x_read_buf(struct mtd_info mtd, u_char buf, int len)
	99	{
	100	struct nand_chip *this = mtd->priv;
	101
	102	while (unlikely(len > 0x800)) {
	103	memcpy_fromio(buf, this->IO_ADDR_R, 0x800);
	104	buf += 0x800;
	105	len -= 0x800;
	106	}
	107	memcpy_fromio(buf, this->IO_ADDR_R, len);
	108	}
	109
	110	static void cs553x_write_buf(struct mtd_info mtd, const u_char buf, int len)
	111	{
	112	struct nand_chip *this = mtd->priv;
	113
	114	while (unlikely(len > 0x800)) {
	115	memcpy_toio(this->IO_ADDR_R, buf, 0x800);
	116	buf += 0x800;
	117	len -= 0x800;
	118	}
	119	memcpy_toio(this->IO_ADDR_R, buf, len);
	120	}
	121
179fdc3f DW	122	static unsigned char cs553x_read_byte(struct mtd_info *mtd)
	123	{
	124	struct nand_chip *this = mtd->priv;
9d75414b	125	return readb(this->IO_ADDR_R);
179fdc3f DW	126	}
	127
	128	static void cs553x_write_byte(struct mtd_info *mtd, u_char byte)
	129	{
	130	struct nand_chip *this = mtd->priv;
	131	int i = 100000;
	132
	133	while (i && readb(this->IO_ADDR_R + MM_NAND_STS) & CS_NAND_CTLR_BUSY) {
	134	udelay(1);
	135	i--;
	136	}
e0c7d767	137	writeb(byte, this->IO_ADDR_W + 0x801);
179fdc3f DW	138	}
179fdc3f DW	139
7abd3ef9 TG	140	static void cs553x_hwcontrol(struct mtd_info *mtd, int cmd,
7abd3ef9 TG	141	unsigned int ctrl)
179fdc3f DW	142	{
	143	struct nand_chip *this = mtd->priv;
	144	void __iomem *mmio_base = this->IO_ADDR_R;
7abd3ef9 TG	145	if (ctrl & NAND_CTRL_CHANGE) {
	146	unsigned char ctl = (ctrl & ~NAND_CTRL_CHANGE ) ^ 0x01;
	147	writeb(ctl, mmio_base + MM_NAND_CTL);
179fdc3f	148	}
7abd3ef9 TG	149	if (cmd != NAND_CMD_NONE)
7abd3ef9 TG	150	cs553x_write_byte(mtd, cmd);
179fdc3f DW	151	}
179fdc3f DW	152
179fdc3f DW	153	static int cs553x_device_ready(struct mtd_info *mtd)
	154	{
	155	struct nand_chip *this = mtd->priv;
	156	void __iomem *mmio_base = this->IO_ADDR_R;
	157	unsigned char foo = readb(mmio_base + MM_NAND_STS);
	158
e0c7d767	159	return (foo & CS_NAND_STS_FLASH_RDY) && !(foo & CS_NAND_CTLR_BUSY);
179fdc3f DW	160	}
179fdc3f DW	161
9d75414b DW	162	static void cs_enable_hwecc(struct mtd_info *mtd, int mode)
	163	{
	164	struct nand_chip *this = mtd->priv;
	165	void __iomem *mmio_base = this->IO_ADDR_R;
	166
	167	writeb(0x07, mmio_base + MM_NAND_ECC_CTL);
	168	}
	169
	170	static int cs_calculate_ecc(struct mtd_info mtd, const u_char dat, u_char *ecc_code)
	171	{
	172	uint32_t ecc;
	173	struct nand_chip *this = mtd->priv;
	174	void __iomem *mmio_base = this->IO_ADDR_R;
	175
	176	ecc = readl(mmio_base + MM_NAND_STS);
	177
	178	ecc_code[1] = ecc >> 8;
	179	ecc_code[0] = ecc >> 16;
	180	ecc_code[2] = ecc >> 24;
	181	return 0;
	182	}
	183
179fdc3f DW	184	static struct mtd_info *cs553x_mtd[4];
	185
	186	static int __init cs553x_init_one(int cs, int mmio, unsigned long adr)
	187	{
	188	int err = 0;
	189	struct nand_chip *this;
	190	struct mtd_info *new_mtd;
	191
	192	printk(KERN_NOTICE "Probing CS553x NAND controller CS#%d at %sIO 0x%08lx\n", cs, mmio?"MM":"P", adr);
	193
	194	if (!mmio) {
	195	printk(KERN_NOTICE "PIO mode not yet implemented for CS553X NAND controller\n");
	196	return -ENXIO;
	197	}
	198
	199	/* Allocate memory for MTD device structure and private data */
e0c7d767	200	new_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
179fdc3f DW	201	if (!new_mtd) {
	202	printk(KERN_WARNING "Unable to allocate CS553X NAND MTD device structure.\n");
	203	err = -ENOMEM;
	204	goto out;
	205	}
	206
	207	/* Get pointer to private data */
e0c7d767	208	this = (struct nand_chip *)(&new_mtd[1]);
179fdc3f DW	209
179fdc3f DW	210	/* Initialize structures */
9d75414b DW	211	memset(new_mtd, 0, sizeof(struct mtd_info));
9d75414b DW	212	memset(this, 0, sizeof(struct nand_chip));
179fdc3f DW	213
	214	/* Link the private data with the MTD structure */
	215	new_mtd->priv = this;
552d9205	216	new_mtd->owner = THIS_MODULE;
179fdc3f DW	217
	218	/* map physical address */
	219	this->IO_ADDR_R = this->IO_ADDR_W = ioremap(adr, 4096);
	220	if (!this->IO_ADDR_R) {
	221	printk(KERN_WARNING "ioremap cs553x NAND @0x%08lx failed\n", adr);
	222	err = -EIO;
	223	goto out_mtd;
	224	}
	225
7abd3ef9	226	this->cmd_ctrl = cs553x_hwcontrol;
179fdc3f DW	227	this->dev_ready = cs553x_device_ready;
179fdc3f DW	228	this->read_byte = cs553x_read_byte;
9d75414b DW	229	this->read_buf = cs553x_read_buf;
9d75414b DW	230	this->write_buf = cs553x_write_buf;
179fdc3f	231
9d75414b	232	this->chip_delay = 0;
179fdc3f	233
6dfc6d25 TG	234	this->ecc.mode = NAND_ECC_HW;
	235	this->ecc.size = 256;
	236	this->ecc.bytes = 3;
	237	this->ecc.hwctl = cs_enable_hwecc;
	238	this->ecc.calculate = cs_calculate_ecc;
	239	this->ecc.correct = nand_correct_data;
	240
179fdc3f	241	/* Enable the following for a flash based bad block table */
bb9ebd4e	242	this->bbt_options = NAND_BBT_USE_FLASH;
a40f7341	243	this->options = NAND_NO_AUTOINCR;
179fdc3f	244
25985edc	245	/* Scan to find existence of the device */
9d75414b	246	if (nand_scan(new_mtd, 1)) {
179fdc3f DW	247	err = -ENXIO;
	248	goto out_ior;
	249	}
	250
6a918bad MD	251	this->ecc.strength = 1;
6a918bad MD	252
641f4366 MR	253	new_mtd->name = kasprintf(GFP_KERNEL, "cs553x_nand_cs%d", cs);
641f4366 MR	254
179fdc3f DW	255	cs553x_mtd[cs] = new_mtd;
	256	goto out;
	257
	258	out_ior:
afc12d30	259	iounmap(this->IO_ADDR_R);
179fdc3f	260	out_mtd:
9d75414b	261	kfree(new_mtd);
179fdc3f DW	262	out:
	263	return err;
	264	}
	265
e4d222ff DW	266	static int is_geode(void)
	267	{
	268	/* These are the CPUs which will have a CS553[56] companion chip */
	269	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
	270	boot_cpu_data.x86 == 5 &&
	271	boot_cpu_data.x86_model == 10)
	272	return 1; /* Geode LX */
	273
	274	if ((boot_cpu_data.x86_vendor == X86_VENDOR_NSC \|\|
	275	boot_cpu_data.x86_vendor == X86_VENDOR_CYRIX) &&
	276	boot_cpu_data.x86 == 5 &&
	277	boot_cpu_data.x86_model == 5)
	278	return 1; /* Geode GX (née GX2) */
	279
	280	return 0;
	281	}
	282
cead4dbc	283	static int __init cs553x_init(void)
179fdc3f DW	284	{
	285	int err = -ENXIO;
	286	int i;
	287	uint64_t val;
641f4366	288
e4d222ff DW	289	/* If the CPU isn't a Geode GX or LX, abort */
	290	if (!is_geode())
	291	return -ENXIO;
	292
	293	/* If it doesn't have the CS553[56], abort */
	294	rdmsrl(MSR_DIVIL_GLD_CAP, val);
	295	val &= ~0xFFULL;
	296	if (val != CAP_CS5535 && val != CAP_CS5536)
179fdc3f DW	297	return -ENXIO;
179fdc3f DW	298
e4d222ff	299	/* If it doesn't have the NAND controller enabled, abort */
179fdc3f	300	rdmsrl(MSR_DIVIL_BALL_OPTS, val);
641f4366	301	if (val & PIN_OPT_IDE) {
179fdc3f DW	302	printk(KERN_INFO "CS553x NAND controller: Flash I/O not enabled in MSR_DIVIL_BALL_OPTS.\n");
	303	return -ENXIO;
	304	}
	305
e0c7d767 DW	306	for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
e0c7d767 DW	307	rdmsrl(MSR_DIVIL_LBAR_FLSH0 + i, val);
179fdc3f DW	308
	309	if ((val & (FLSH_LBAR_EN\|FLSH_NOR_NAND)) == (FLSH_LBAR_EN\|FLSH_NOR_NAND))
	310	err = cs553x_init_one(i, !!(val & FLSH_MEM_IO), val & 0xFFFFFFFF);
	311	}
e0c7d767	312
c9ac5977	313	/* Register all devices together here. This means we can easily hack it to
179fdc3f	314	do mtdconcat etc. if we want to. */
e0c7d767	315	for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
179fdc3f	316	if (cs553x_mtd[i]) {
179fdc3f	317	/* If any devices registered, return success. Else the last error. */
42d7fbe2	318	mtd_device_parse_register(cs553x_mtd[i], NULL, NULL,
bbd86c9c	319	NULL, 0);
179fdc3f DW	320	err = 0;
	321	}
	322	}
	323
	324	return err;
	325	}
e0c7d767	326
179fdc3f DW	327	module_init(cs553x_init);
179fdc3f DW	328
e0c7d767	329	static void __exit cs553x_cleanup(void)
179fdc3f DW	330	{
	331	int i;
	332
e0c7d767	333	for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
179fdc3f DW	334	struct mtd_info *mtd = cs553x_mtd[i];
	335	struct nand_chip *this;
	336	void __iomem *mmio_base;
	337
	338	if (!mtd)
641f4366	339	continue;
179fdc3f DW	340
	341	this = cs553x_mtd[i]->priv;
	342	mmio_base = this->IO_ADDR_R;
	343
	344	/* Release resources, unregister device */
e0c7d767	345	nand_release(cs553x_mtd[i]);
641f4366	346	kfree(cs553x_mtd[i]->name);
179fdc3f DW	347	cs553x_mtd[i] = NULL;
179fdc3f DW	348
8e87d782	349	/* unmap physical address */
179fdc3f DW	350	iounmap(mmio_base);
	351
	352	/* Free the MTD device structure */
9d75414b	353	kfree(mtd);
179fdc3f DW	354	}
179fdc3f DW	355	}
e0c7d767	356
179fdc3f DW	357	module_exit(cs553x_cleanup);
	358
	359	MODULE_LICENSE("GPL");
	360	MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
	361	MODULE_DESCRIPTION("NAND controller driver for AMD CS5535/CS5536 companion chip");