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ff4569c7 DB |
1 | /* |
2 | * davinci_nand.c - NAND Flash Driver for DaVinci family chips | |
3 | * | |
4 | * Copyright © 2006 Texas Instruments. | |
5 | * | |
6 | * Port to 2.6.23 Copyright © 2008 by: | |
7 | * Sander Huijsen <Shuijsen@optelecom-nkf.com> | |
8 | * Troy Kisky <troy.kisky@boundarydevices.com> | |
9 | * Dirk Behme <Dirk.Behme@gmail.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | */ | |
25 | ||
26 | #include <linux/kernel.h> | |
ff4569c7 DB |
27 | #include <linux/module.h> |
28 | #include <linux/platform_device.h> | |
29 | #include <linux/err.h> | |
30 | #include <linux/clk.h> | |
31 | #include <linux/io.h> | |
32 | #include <linux/mtd/nand.h> | |
33 | #include <linux/mtd/partitions.h> | |
5a0e3ad6 | 34 | #include <linux/slab.h> |
cdeadd71 | 35 | #include <linux/of_device.h> |
c4f8cde8 | 36 | #include <linux/of.h> |
75be1ea2 | 37 | #include <linux/of_mtd.h> |
ff4569c7 | 38 | |
ec2a0833 AB |
39 | #include <linux/platform_data/mtd-davinci.h> |
40 | #include <linux/platform_data/mtd-davinci-aemif.h> | |
ff4569c7 | 41 | |
ff4569c7 DB |
42 | /* |
43 | * This is a device driver for the NAND flash controller found on the | |
44 | * various DaVinci family chips. It handles up to four SoC chipselects, | |
45 | * and some flavors of secondary chipselect (e.g. based on A12) as used | |
46 | * with multichip packages. | |
47 | * | |
6a4123e5 | 48 | * The 1-bit ECC hardware is supported, as well as the newer 4-bit ECC |
ff4569c7 DB |
49 | * available on chips like the DM355 and OMAP-L137 and needed with the |
50 | * more error-prone MLC NAND chips. | |
51 | * | |
52 | * This driver assumes EM_WAIT connects all the NAND devices' RDY/nBUSY | |
53 | * outputs in a "wire-AND" configuration, with no per-chip signals. | |
54 | */ | |
55 | struct davinci_nand_info { | |
ff4569c7 DB |
56 | struct nand_chip chip; |
57 | ||
58 | struct device *dev; | |
59 | struct clk *clk; | |
ff4569c7 | 60 | |
6a4123e5 DB |
61 | bool is_readmode; |
62 | ||
ff4569c7 DB |
63 | void __iomem *base; |
64 | void __iomem *vaddr; | |
65 | ||
66 | uint32_t ioaddr; | |
67 | uint32_t current_cs; | |
68 | ||
69 | uint32_t mask_chipsel; | |
70 | uint32_t mask_ale; | |
71 | uint32_t mask_cle; | |
72 | ||
73 | uint32_t core_chipsel; | |
a88dbc5b SN |
74 | |
75 | struct davinci_aemif_timing *timing; | |
ff4569c7 DB |
76 | }; |
77 | ||
78 | static DEFINE_SPINLOCK(davinci_nand_lock); | |
6a4123e5 | 79 | static bool ecc4_busy; |
ff4569c7 | 80 | |
a5cfb4db BB |
81 | static inline struct davinci_nand_info *to_davinci_nand(struct mtd_info *mtd) |
82 | { | |
83 | return container_of(mtd_to_nand(mtd), struct davinci_nand_info, chip); | |
84 | } | |
ff4569c7 DB |
85 | |
86 | static inline unsigned int davinci_nand_readl(struct davinci_nand_info *info, | |
87 | int offset) | |
88 | { | |
89 | return __raw_readl(info->base + offset); | |
90 | } | |
91 | ||
92 | static inline void davinci_nand_writel(struct davinci_nand_info *info, | |
93 | int offset, unsigned long value) | |
94 | { | |
95 | __raw_writel(value, info->base + offset); | |
96 | } | |
97 | ||
98 | /*----------------------------------------------------------------------*/ | |
99 | ||
100 | /* | |
101 | * Access to hardware control lines: ALE, CLE, secondary chipselect. | |
102 | */ | |
103 | ||
104 | static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, | |
105 | unsigned int ctrl) | |
106 | { | |
107 | struct davinci_nand_info *info = to_davinci_nand(mtd); | |
108 | uint32_t addr = info->current_cs; | |
4bd4ebcc | 109 | struct nand_chip *nand = mtd_to_nand(mtd); |
ff4569c7 DB |
110 | |
111 | /* Did the control lines change? */ | |
112 | if (ctrl & NAND_CTRL_CHANGE) { | |
113 | if ((ctrl & NAND_CTRL_CLE) == NAND_CTRL_CLE) | |
114 | addr |= info->mask_cle; | |
115 | else if ((ctrl & NAND_CTRL_ALE) == NAND_CTRL_ALE) | |
116 | addr |= info->mask_ale; | |
117 | ||
118 | nand->IO_ADDR_W = (void __iomem __force *)addr; | |
119 | } | |
120 | ||
121 | if (cmd != NAND_CMD_NONE) | |
122 | iowrite8(cmd, nand->IO_ADDR_W); | |
123 | } | |
124 | ||
125 | static void nand_davinci_select_chip(struct mtd_info *mtd, int chip) | |
126 | { | |
127 | struct davinci_nand_info *info = to_davinci_nand(mtd); | |
128 | uint32_t addr = info->ioaddr; | |
129 | ||
130 | /* maybe kick in a second chipselect */ | |
131 | if (chip > 0) | |
132 | addr |= info->mask_chipsel; | |
133 | info->current_cs = addr; | |
134 | ||
135 | info->chip.IO_ADDR_W = (void __iomem __force *)addr; | |
136 | info->chip.IO_ADDR_R = info->chip.IO_ADDR_W; | |
137 | } | |
138 | ||
139 | /*----------------------------------------------------------------------*/ | |
140 | ||
141 | /* | |
142 | * 1-bit hardware ECC ... context maintained for each core chipselect | |
143 | */ | |
144 | ||
145 | static inline uint32_t nand_davinci_readecc_1bit(struct mtd_info *mtd) | |
146 | { | |
147 | struct davinci_nand_info *info = to_davinci_nand(mtd); | |
148 | ||
149 | return davinci_nand_readl(info, NANDF1ECC_OFFSET | |
150 | + 4 * info->core_chipsel); | |
151 | } | |
152 | ||
153 | static void nand_davinci_hwctl_1bit(struct mtd_info *mtd, int mode) | |
154 | { | |
155 | struct davinci_nand_info *info; | |
156 | uint32_t nandcfr; | |
157 | unsigned long flags; | |
158 | ||
159 | info = to_davinci_nand(mtd); | |
160 | ||
161 | /* Reset ECC hardware */ | |
162 | nand_davinci_readecc_1bit(mtd); | |
163 | ||
164 | spin_lock_irqsave(&davinci_nand_lock, flags); | |
165 | ||
166 | /* Restart ECC hardware */ | |
167 | nandcfr = davinci_nand_readl(info, NANDFCR_OFFSET); | |
168 | nandcfr |= BIT(8 + info->core_chipsel); | |
169 | davinci_nand_writel(info, NANDFCR_OFFSET, nandcfr); | |
170 | ||
171 | spin_unlock_irqrestore(&davinci_nand_lock, flags); | |
172 | } | |
173 | ||
174 | /* | |
175 | * Read hardware ECC value and pack into three bytes | |
176 | */ | |
177 | static int nand_davinci_calculate_1bit(struct mtd_info *mtd, | |
178 | const u_char *dat, u_char *ecc_code) | |
179 | { | |
180 | unsigned int ecc_val = nand_davinci_readecc_1bit(mtd); | |
181 | unsigned int ecc24 = (ecc_val & 0x0fff) | ((ecc_val & 0x0fff0000) >> 4); | |
182 | ||
183 | /* invert so that erased block ecc is correct */ | |
184 | ecc24 = ~ecc24; | |
185 | ecc_code[0] = (u_char)(ecc24); | |
186 | ecc_code[1] = (u_char)(ecc24 >> 8); | |
187 | ecc_code[2] = (u_char)(ecc24 >> 16); | |
188 | ||
189 | return 0; | |
190 | } | |
191 | ||
192 | static int nand_davinci_correct_1bit(struct mtd_info *mtd, u_char *dat, | |
193 | u_char *read_ecc, u_char *calc_ecc) | |
194 | { | |
4bd4ebcc | 195 | struct nand_chip *chip = mtd_to_nand(mtd); |
ff4569c7 DB |
196 | uint32_t eccNand = read_ecc[0] | (read_ecc[1] << 8) | |
197 | (read_ecc[2] << 16); | |
198 | uint32_t eccCalc = calc_ecc[0] | (calc_ecc[1] << 8) | | |
199 | (calc_ecc[2] << 16); | |
200 | uint32_t diff = eccCalc ^ eccNand; | |
201 | ||
202 | if (diff) { | |
203 | if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) { | |
204 | /* Correctable error */ | |
205 | if ((diff >> (12 + 3)) < chip->ecc.size) { | |
206 | dat[diff >> (12 + 3)] ^= BIT((diff >> 12) & 7); | |
207 | return 1; | |
208 | } else { | |
6e941192 | 209 | return -EBADMSG; |
ff4569c7 DB |
210 | } |
211 | } else if (!(diff & (diff - 1))) { | |
212 | /* Single bit ECC error in the ECC itself, | |
213 | * nothing to fix */ | |
214 | return 1; | |
215 | } else { | |
216 | /* Uncorrectable error */ | |
6e941192 | 217 | return -EBADMSG; |
ff4569c7 DB |
218 | } |
219 | ||
220 | } | |
221 | return 0; | |
222 | } | |
223 | ||
224 | /*----------------------------------------------------------------------*/ | |
225 | ||
6a4123e5 DB |
226 | /* |
227 | * 4-bit hardware ECC ... context maintained over entire AEMIF | |
228 | * | |
229 | * This is a syndrome engine, but we avoid NAND_ECC_HW_SYNDROME | |
230 | * since that forces use of a problematic "infix OOB" layout. | |
231 | * Among other things, it trashes manufacturer bad block markers. | |
232 | * Also, and specific to this hardware, it ECC-protects the "prepad" | |
233 | * in the OOB ... while having ECC protection for parts of OOB would | |
234 | * seem useful, the current MTD stack sometimes wants to update the | |
235 | * OOB without recomputing ECC. | |
236 | */ | |
237 | ||
238 | static void nand_davinci_hwctl_4bit(struct mtd_info *mtd, int mode) | |
239 | { | |
240 | struct davinci_nand_info *info = to_davinci_nand(mtd); | |
241 | unsigned long flags; | |
242 | u32 val; | |
243 | ||
244 | spin_lock_irqsave(&davinci_nand_lock, flags); | |
245 | ||
246 | /* Start 4-bit ECC calculation for read/write */ | |
247 | val = davinci_nand_readl(info, NANDFCR_OFFSET); | |
248 | val &= ~(0x03 << 4); | |
249 | val |= (info->core_chipsel << 4) | BIT(12); | |
250 | davinci_nand_writel(info, NANDFCR_OFFSET, val); | |
251 | ||
252 | info->is_readmode = (mode == NAND_ECC_READ); | |
253 | ||
254 | spin_unlock_irqrestore(&davinci_nand_lock, flags); | |
255 | } | |
256 | ||
257 | /* Read raw ECC code after writing to NAND. */ | |
258 | static void | |
259 | nand_davinci_readecc_4bit(struct davinci_nand_info *info, u32 code[4]) | |
260 | { | |
261 | const u32 mask = 0x03ff03ff; | |
262 | ||
263 | code[0] = davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET) & mask; | |
264 | code[1] = davinci_nand_readl(info, NAND_4BIT_ECC2_OFFSET) & mask; | |
265 | code[2] = davinci_nand_readl(info, NAND_4BIT_ECC3_OFFSET) & mask; | |
266 | code[3] = davinci_nand_readl(info, NAND_4BIT_ECC4_OFFSET) & mask; | |
267 | } | |
268 | ||
269 | /* Terminate read ECC; or return ECC (as bytes) of data written to NAND. */ | |
270 | static int nand_davinci_calculate_4bit(struct mtd_info *mtd, | |
271 | const u_char *dat, u_char *ecc_code) | |
272 | { | |
273 | struct davinci_nand_info *info = to_davinci_nand(mtd); | |
274 | u32 raw_ecc[4], *p; | |
275 | unsigned i; | |
276 | ||
277 | /* After a read, terminate ECC calculation by a dummy read | |
278 | * of some 4-bit ECC register. ECC covers everything that | |
279 | * was read; correct() just uses the hardware state, so | |
280 | * ecc_code is not needed. | |
281 | */ | |
282 | if (info->is_readmode) { | |
283 | davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET); | |
284 | return 0; | |
285 | } | |
286 | ||
287 | /* Pack eight raw 10-bit ecc values into ten bytes, making | |
288 | * two passes which each convert four values (in upper and | |
289 | * lower halves of two 32-bit words) into five bytes. The | |
290 | * ROM boot loader uses this same packing scheme. | |
291 | */ | |
292 | nand_davinci_readecc_4bit(info, raw_ecc); | |
293 | for (i = 0, p = raw_ecc; i < 2; i++, p += 2) { | |
294 | *ecc_code++ = p[0] & 0xff; | |
295 | *ecc_code++ = ((p[0] >> 8) & 0x03) | ((p[0] >> 14) & 0xfc); | |
296 | *ecc_code++ = ((p[0] >> 22) & 0x0f) | ((p[1] << 4) & 0xf0); | |
297 | *ecc_code++ = ((p[1] >> 4) & 0x3f) | ((p[1] >> 10) & 0xc0); | |
298 | *ecc_code++ = (p[1] >> 18) & 0xff; | |
299 | } | |
300 | ||
301 | return 0; | |
302 | } | |
303 | ||
304 | /* Correct up to 4 bits in data we just read, using state left in the | |
305 | * hardware plus the ecc_code computed when it was first written. | |
306 | */ | |
307 | static int nand_davinci_correct_4bit(struct mtd_info *mtd, | |
308 | u_char *data, u_char *ecc_code, u_char *null) | |
309 | { | |
310 | int i; | |
311 | struct davinci_nand_info *info = to_davinci_nand(mtd); | |
312 | unsigned short ecc10[8]; | |
313 | unsigned short *ecc16; | |
314 | u32 syndrome[4]; | |
1c3275b6 | 315 | u32 ecc_state; |
6a4123e5 | 316 | unsigned num_errors, corrected; |
2bdb053a | 317 | unsigned long timeo; |
6a4123e5 | 318 | |
6a4123e5 DB |
319 | /* Unpack ten bytes into eight 10 bit values. We know we're |
320 | * little-endian, and use type punning for less shifting/masking. | |
321 | */ | |
322 | if (WARN_ON(0x01 & (unsigned) ecc_code)) | |
323 | return -EINVAL; | |
324 | ecc16 = (unsigned short *)ecc_code; | |
325 | ||
326 | ecc10[0] = (ecc16[0] >> 0) & 0x3ff; | |
327 | ecc10[1] = ((ecc16[0] >> 10) & 0x3f) | ((ecc16[1] << 6) & 0x3c0); | |
328 | ecc10[2] = (ecc16[1] >> 4) & 0x3ff; | |
329 | ecc10[3] = ((ecc16[1] >> 14) & 0x3) | ((ecc16[2] << 2) & 0x3fc); | |
330 | ecc10[4] = (ecc16[2] >> 8) | ((ecc16[3] << 8) & 0x300); | |
331 | ecc10[5] = (ecc16[3] >> 2) & 0x3ff; | |
332 | ecc10[6] = ((ecc16[3] >> 12) & 0xf) | ((ecc16[4] << 4) & 0x3f0); | |
333 | ecc10[7] = (ecc16[4] >> 6) & 0x3ff; | |
334 | ||
335 | /* Tell ECC controller about the expected ECC codes. */ | |
336 | for (i = 7; i >= 0; i--) | |
337 | davinci_nand_writel(info, NAND_4BIT_ECC_LOAD_OFFSET, ecc10[i]); | |
338 | ||
339 | /* Allow time for syndrome calculation ... then read it. | |
340 | * A syndrome of all zeroes 0 means no detected errors. | |
341 | */ | |
342 | davinci_nand_readl(info, NANDFSR_OFFSET); | |
343 | nand_davinci_readecc_4bit(info, syndrome); | |
344 | if (!(syndrome[0] | syndrome[1] | syndrome[2] | syndrome[3])) | |
345 | return 0; | |
346 | ||
f12a9473 SN |
347 | /* |
348 | * Clear any previous address calculation by doing a dummy read of an | |
349 | * error address register. | |
350 | */ | |
351 | davinci_nand_readl(info, NAND_ERR_ADD1_OFFSET); | |
352 | ||
6a4123e5 DB |
353 | /* Start address calculation, and wait for it to complete. |
354 | * We _could_ start reading more data while this is working, | |
355 | * to speed up the overall page read. | |
356 | */ | |
357 | davinci_nand_writel(info, NANDFCR_OFFSET, | |
358 | davinci_nand_readl(info, NANDFCR_OFFSET) | BIT(13)); | |
1c3275b6 SR |
359 | |
360 | /* | |
361 | * ECC_STATE field reads 0x3 (Error correction complete) immediately | |
362 | * after setting the 4BITECC_ADD_CALC_START bit. So if you immediately | |
363 | * begin trying to poll for the state, you may fall right out of your | |
364 | * loop without any of the correction calculations having taken place. | |
eea116ed WS |
365 | * The recommendation from the hardware team is to initially delay as |
366 | * long as ECC_STATE reads less than 4. After that, ECC HW has entered | |
367 | * correction state. | |
1c3275b6 | 368 | */ |
2bdb053a | 369 | timeo = jiffies + usecs_to_jiffies(100); |
1c3275b6 SR |
370 | do { |
371 | ecc_state = (davinci_nand_readl(info, | |
372 | NANDFSR_OFFSET) >> 8) & 0x0f; | |
373 | cpu_relax(); | |
374 | } while ((ecc_state < 4) && time_before(jiffies, timeo)); | |
375 | ||
6a4123e5 DB |
376 | for (;;) { |
377 | u32 fsr = davinci_nand_readl(info, NANDFSR_OFFSET); | |
378 | ||
379 | switch ((fsr >> 8) & 0x0f) { | |
380 | case 0: /* no error, should not happen */ | |
f12a9473 | 381 | davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET); |
6a4123e5 DB |
382 | return 0; |
383 | case 1: /* five or more errors detected */ | |
f12a9473 | 384 | davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET); |
6e941192 | 385 | return -EBADMSG; |
6a4123e5 DB |
386 | case 2: /* error addresses computed */ |
387 | case 3: | |
388 | num_errors = 1 + ((fsr >> 16) & 0x03); | |
389 | goto correct; | |
390 | default: /* still working on it */ | |
391 | cpu_relax(); | |
392 | continue; | |
393 | } | |
394 | } | |
395 | ||
396 | correct: | |
397 | /* correct each error */ | |
398 | for (i = 0, corrected = 0; i < num_errors; i++) { | |
399 | int error_address, error_value; | |
400 | ||
401 | if (i > 1) { | |
402 | error_address = davinci_nand_readl(info, | |
403 | NAND_ERR_ADD2_OFFSET); | |
404 | error_value = davinci_nand_readl(info, | |
405 | NAND_ERR_ERRVAL2_OFFSET); | |
406 | } else { | |
407 | error_address = davinci_nand_readl(info, | |
408 | NAND_ERR_ADD1_OFFSET); | |
409 | error_value = davinci_nand_readl(info, | |
410 | NAND_ERR_ERRVAL1_OFFSET); | |
411 | } | |
412 | ||
413 | if (i & 1) { | |
414 | error_address >>= 16; | |
415 | error_value >>= 16; | |
416 | } | |
417 | error_address &= 0x3ff; | |
418 | error_address = (512 + 7) - error_address; | |
419 | ||
420 | if (error_address < 512) { | |
421 | data[error_address] ^= error_value; | |
422 | corrected++; | |
423 | } | |
424 | } | |
425 | ||
426 | return corrected; | |
427 | } | |
428 | ||
429 | /*----------------------------------------------------------------------*/ | |
430 | ||
ff4569c7 DB |
431 | /* |
432 | * NOTE: NAND boot requires ALE == EM_A[1], CLE == EM_A[2], so that's | |
433 | * how these chips are normally wired. This translates to both 8 and 16 | |
434 | * bit busses using ALE == BIT(3) in byte addresses, and CLE == BIT(4). | |
435 | * | |
436 | * For now we assume that configuration, or any other one which ignores | |
437 | * the two LSBs for NAND access ... so we can issue 32-bit reads/writes | |
438 | * and have that transparently morphed into multiple NAND operations. | |
439 | */ | |
440 | static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) | |
441 | { | |
4bd4ebcc | 442 | struct nand_chip *chip = mtd_to_nand(mtd); |
ff4569c7 DB |
443 | |
444 | if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0) | |
445 | ioread32_rep(chip->IO_ADDR_R, buf, len >> 2); | |
446 | else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0) | |
447 | ioread16_rep(chip->IO_ADDR_R, buf, len >> 1); | |
448 | else | |
449 | ioread8_rep(chip->IO_ADDR_R, buf, len); | |
450 | } | |
451 | ||
452 | static void nand_davinci_write_buf(struct mtd_info *mtd, | |
453 | const uint8_t *buf, int len) | |
454 | { | |
4bd4ebcc | 455 | struct nand_chip *chip = mtd_to_nand(mtd); |
ff4569c7 DB |
456 | |
457 | if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0) | |
458 | iowrite32_rep(chip->IO_ADDR_R, buf, len >> 2); | |
459 | else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0) | |
460 | iowrite16_rep(chip->IO_ADDR_R, buf, len >> 1); | |
461 | else | |
462 | iowrite8_rep(chip->IO_ADDR_R, buf, len); | |
463 | } | |
464 | ||
465 | /* | |
466 | * Check hardware register for wait status. Returns 1 if device is ready, | |
467 | * 0 if it is still busy. | |
468 | */ | |
469 | static int nand_davinci_dev_ready(struct mtd_info *mtd) | |
470 | { | |
471 | struct davinci_nand_info *info = to_davinci_nand(mtd); | |
472 | ||
473 | return davinci_nand_readl(info, NANDFSR_OFFSET) & BIT(0); | |
474 | } | |
475 | ||
ff4569c7 DB |
476 | /*----------------------------------------------------------------------*/ |
477 | ||
6a4123e5 DB |
478 | /* An ECC layout for using 4-bit ECC with small-page flash, storing |
479 | * ten ECC bytes plus the manufacturer's bad block marker byte, and | |
480 | * and not overlapping the default BBT markers. | |
481 | */ | |
e4aacaa1 BB |
482 | static int hwecc4_ooblayout_small_ecc(struct mtd_info *mtd, int section, |
483 | struct mtd_oob_region *oobregion) | |
484 | { | |
485 | if (section > 2) | |
486 | return -ERANGE; | |
487 | ||
488 | if (!section) { | |
489 | oobregion->offset = 0; | |
490 | oobregion->length = 5; | |
491 | } else if (section == 1) { | |
492 | oobregion->offset = 6; | |
493 | oobregion->length = 2; | |
494 | } else { | |
495 | oobregion->offset = 13; | |
496 | oobregion->length = 3; | |
497 | } | |
6a4123e5 | 498 | |
e4aacaa1 BB |
499 | return 0; |
500 | } | |
6a4123e5 | 501 | |
e4aacaa1 BB |
502 | static int hwecc4_ooblayout_small_free(struct mtd_info *mtd, int section, |
503 | struct mtd_oob_region *oobregion) | |
504 | { | |
505 | if (section > 1) | |
506 | return -ERANGE; | |
507 | ||
508 | if (!section) { | |
509 | oobregion->offset = 8; | |
510 | oobregion->length = 5; | |
511 | } else { | |
512 | oobregion->offset = 16; | |
513 | oobregion->length = mtd->oobsize - 16; | |
514 | } | |
515 | ||
516 | return 0; | |
517 | } | |
518 | ||
519 | static const struct mtd_ooblayout_ops hwecc4_small_ooblayout_ops = { | |
520 | .ecc = hwecc4_ooblayout_small_ecc, | |
521 | .free = hwecc4_ooblayout_small_free, | |
a11244c0 SP |
522 | }; |
523 | ||
cdeadd71 HS |
524 | #if defined(CONFIG_OF) |
525 | static const struct of_device_id davinci_nand_of_match[] = { | |
526 | {.compatible = "ti,davinci-nand", }, | |
28c015a9 | 527 | {.compatible = "ti,keystone-nand", }, |
cdeadd71 | 528 | {}, |
13daa22f | 529 | }; |
cdeadd71 HS |
530 | MODULE_DEVICE_TABLE(of, davinci_nand_of_match); |
531 | ||
532 | static struct davinci_nand_pdata | |
533 | *nand_davinci_get_pdata(struct platform_device *pdev) | |
534 | { | |
453810b7 | 535 | if (!dev_get_platdata(&pdev->dev) && pdev->dev.of_node) { |
cdeadd71 HS |
536 | struct davinci_nand_pdata *pdata; |
537 | const char *mode; | |
538 | u32 prop; | |
cdeadd71 HS |
539 | |
540 | pdata = devm_kzalloc(&pdev->dev, | |
541 | sizeof(struct davinci_nand_pdata), | |
542 | GFP_KERNEL); | |
543 | pdev->dev.platform_data = pdata; | |
544 | if (!pdata) | |
f735a4d0 | 545 | return ERR_PTR(-ENOMEM); |
cdeadd71 HS |
546 | if (!of_property_read_u32(pdev->dev.of_node, |
547 | "ti,davinci-chipselect", &prop)) | |
548 | pdev->id = prop; | |
05103825 IK |
549 | else |
550 | return ERR_PTR(-EINVAL); | |
551 | ||
cdeadd71 HS |
552 | if (!of_property_read_u32(pdev->dev.of_node, |
553 | "ti,davinci-mask-ale", &prop)) | |
554 | pdata->mask_ale = prop; | |
555 | if (!of_property_read_u32(pdev->dev.of_node, | |
556 | "ti,davinci-mask-cle", &prop)) | |
557 | pdata->mask_cle = prop; | |
558 | if (!of_property_read_u32(pdev->dev.of_node, | |
559 | "ti,davinci-mask-chipsel", &prop)) | |
560 | pdata->mask_chipsel = prop; | |
561 | if (!of_property_read_string(pdev->dev.of_node, | |
75be1ea2 IK |
562 | "nand-ecc-mode", &mode) || |
563 | !of_property_read_string(pdev->dev.of_node, | |
cdeadd71 HS |
564 | "ti,davinci-ecc-mode", &mode)) { |
565 | if (!strncmp("none", mode, 4)) | |
566 | pdata->ecc_mode = NAND_ECC_NONE; | |
567 | if (!strncmp("soft", mode, 4)) | |
568 | pdata->ecc_mode = NAND_ECC_SOFT; | |
569 | if (!strncmp("hw", mode, 2)) | |
570 | pdata->ecc_mode = NAND_ECC_HW; | |
571 | } | |
572 | if (!of_property_read_u32(pdev->dev.of_node, | |
573 | "ti,davinci-ecc-bits", &prop)) | |
574 | pdata->ecc_bits = prop; | |
75be1ea2 IK |
575 | |
576 | prop = of_get_nand_bus_width(pdev->dev.of_node); | |
577 | if (0 < prop || !of_property_read_u32(pdev->dev.of_node, | |
cdeadd71 HS |
578 | "ti,davinci-nand-buswidth", &prop)) |
579 | if (prop == 16) | |
580 | pdata->options |= NAND_BUSWIDTH_16; | |
75be1ea2 IK |
581 | if (of_property_read_bool(pdev->dev.of_node, |
582 | "nand-on-flash-bbt") || | |
583 | of_property_read_bool(pdev->dev.of_node, | |
584 | "ti,davinci-nand-use-bbt")) | |
cdeadd71 | 585 | pdata->bbt_options = NAND_BBT_USE_FLASH; |
28c015a9 MK |
586 | |
587 | if (of_device_is_compatible(pdev->dev.of_node, | |
588 | "ti,keystone-nand")) { | |
589 | pdata->options |= NAND_NO_SUBPAGE_WRITE; | |
590 | } | |
cdeadd71 HS |
591 | } |
592 | ||
453810b7 | 593 | return dev_get_platdata(&pdev->dev); |
cdeadd71 HS |
594 | } |
595 | #else | |
cdeadd71 HS |
596 | static struct davinci_nand_pdata |
597 | *nand_davinci_get_pdata(struct platform_device *pdev) | |
598 | { | |
453810b7 | 599 | return dev_get_platdata(&pdev->dev); |
cdeadd71 HS |
600 | } |
601 | #endif | |
602 | ||
eaaa4a9a | 603 | static int nand_davinci_probe(struct platform_device *pdev) |
ff4569c7 | 604 | { |
cdeadd71 | 605 | struct davinci_nand_pdata *pdata; |
ff4569c7 DB |
606 | struct davinci_nand_info *info; |
607 | struct resource *res1; | |
608 | struct resource *res2; | |
609 | void __iomem *vaddr; | |
610 | void __iomem *base; | |
611 | int ret; | |
612 | uint32_t val; | |
613 | nand_ecc_modes_t ecc_mode; | |
a5cfb4db | 614 | struct mtd_info *mtd; |
ff4569c7 | 615 | |
cdeadd71 | 616 | pdata = nand_davinci_get_pdata(pdev); |
f735a4d0 IK |
617 | if (IS_ERR(pdata)) |
618 | return PTR_ERR(pdata); | |
619 | ||
533a0149 DB |
620 | /* insist on board-specific configuration */ |
621 | if (!pdata) | |
622 | return -ENODEV; | |
623 | ||
ff4569c7 DB |
624 | /* which external chipselect will we be managing? */ |
625 | if (pdev->id < 0 || pdev->id > 3) | |
626 | return -ENODEV; | |
627 | ||
ef4e0c21 | 628 | info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); |
00669231 | 629 | if (!info) |
30a3970c | 630 | return -ENOMEM; |
ff4569c7 DB |
631 | |
632 | platform_set_drvdata(pdev, info); | |
633 | ||
634 | res1 = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
635 | res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
636 | if (!res1 || !res2) { | |
637 | dev_err(&pdev->dev, "resource missing\n"); | |
30a3970c | 638 | return -EINVAL; |
ff4569c7 DB |
639 | } |
640 | ||
59bff7fb | 641 | vaddr = devm_ioremap_resource(&pdev->dev, res1); |
30a3970c IK |
642 | if (IS_ERR(vaddr)) |
643 | return PTR_ERR(vaddr); | |
644 | ||
0966a416 IK |
645 | /* |
646 | * This registers range is used to setup NAND settings. In case with | |
647 | * TI AEMIF driver, the same memory address range is requested already | |
648 | * by AEMIF, so we cannot request it twice, just ioremap. | |
649 | * The AEMIF and NAND drivers not use the same registers in this range. | |
650 | */ | |
651 | base = devm_ioremap(&pdev->dev, res2->start, resource_size(res2)); | |
652 | if (!base) { | |
653 | dev_err(&pdev->dev, "ioremap failed for resource %pR\n", res2); | |
654 | return -EADDRNOTAVAIL; | |
655 | } | |
ff4569c7 DB |
656 | |
657 | info->dev = &pdev->dev; | |
658 | info->base = base; | |
659 | info->vaddr = vaddr; | |
660 | ||
a5cfb4db | 661 | mtd = nand_to_mtd(&info->chip); |
a5cfb4db | 662 | mtd->dev.parent = &pdev->dev; |
a61ae81a | 663 | nand_set_flash_node(&info->chip, pdev->dev.of_node); |
87f39f04 | 664 | |
ff4569c7 DB |
665 | info->chip.IO_ADDR_R = vaddr; |
666 | info->chip.IO_ADDR_W = vaddr; | |
667 | info->chip.chip_delay = 0; | |
668 | info->chip.select_chip = nand_davinci_select_chip; | |
669 | ||
bb9ebd4e | 670 | /* options such as NAND_BBT_USE_FLASH */ |
a40f7341 BN |
671 | info->chip.bbt_options = pdata->bbt_options; |
672 | /* options such as 16-bit widths */ | |
533a0149 | 673 | info->chip.options = pdata->options; |
f611a79f MG |
674 | info->chip.bbt_td = pdata->bbt_td; |
675 | info->chip.bbt_md = pdata->bbt_md; | |
a88dbc5b | 676 | info->timing = pdata->timing; |
ff4569c7 DB |
677 | |
678 | info->ioaddr = (uint32_t __force) vaddr; | |
679 | ||
680 | info->current_cs = info->ioaddr; | |
681 | info->core_chipsel = pdev->id; | |
682 | info->mask_chipsel = pdata->mask_chipsel; | |
683 | ||
684 | /* use nandboot-capable ALE/CLE masks by default */ | |
5cd0be8e | 685 | info->mask_ale = pdata->mask_ale ? : MASK_ALE; |
533a0149 | 686 | info->mask_cle = pdata->mask_cle ? : MASK_CLE; |
ff4569c7 DB |
687 | |
688 | /* Set address of hardware control function */ | |
689 | info->chip.cmd_ctrl = nand_davinci_hwcontrol; | |
690 | info->chip.dev_ready = nand_davinci_dev_ready; | |
691 | ||
692 | /* Speed up buffer I/O */ | |
693 | info->chip.read_buf = nand_davinci_read_buf; | |
694 | info->chip.write_buf = nand_davinci_write_buf; | |
695 | ||
533a0149 DB |
696 | /* Use board-specific ECC config */ |
697 | ecc_mode = pdata->ecc_mode; | |
ff4569c7 | 698 | |
6a4123e5 | 699 | ret = -EINVAL; |
ff4569c7 DB |
700 | switch (ecc_mode) { |
701 | case NAND_ECC_NONE: | |
702 | case NAND_ECC_SOFT: | |
6a4123e5 | 703 | pdata->ecc_bits = 0; |
ff4569c7 DB |
704 | break; |
705 | case NAND_ECC_HW: | |
6a4123e5 DB |
706 | if (pdata->ecc_bits == 4) { |
707 | /* No sanity checks: CPUs must support this, | |
708 | * and the chips may not use NAND_BUSWIDTH_16. | |
709 | */ | |
710 | ||
711 | /* No sharing 4-bit hardware between chipselects yet */ | |
712 | spin_lock_irq(&davinci_nand_lock); | |
713 | if (ecc4_busy) | |
714 | ret = -EBUSY; | |
715 | else | |
716 | ecc4_busy = true; | |
717 | spin_unlock_irq(&davinci_nand_lock); | |
718 | ||
719 | if (ret == -EBUSY) | |
30a3970c | 720 | return ret; |
6a4123e5 DB |
721 | |
722 | info->chip.ecc.calculate = nand_davinci_calculate_4bit; | |
723 | info->chip.ecc.correct = nand_davinci_correct_4bit; | |
724 | info->chip.ecc.hwctl = nand_davinci_hwctl_4bit; | |
725 | info->chip.ecc.bytes = 10; | |
bc29c95d | 726 | info->chip.ecc.options = NAND_ECC_GENERIC_ERASED_CHECK; |
6a4123e5 DB |
727 | } else { |
728 | info->chip.ecc.calculate = nand_davinci_calculate_1bit; | |
729 | info->chip.ecc.correct = nand_davinci_correct_1bit; | |
730 | info->chip.ecc.hwctl = nand_davinci_hwctl_1bit; | |
731 | info->chip.ecc.bytes = 3; | |
732 | } | |
ff4569c7 | 733 | info->chip.ecc.size = 512; |
6a918bad | 734 | info->chip.ecc.strength = pdata->ecc_bits; |
ff4569c7 | 735 | break; |
ff4569c7 | 736 | default: |
30a3970c | 737 | return -EINVAL; |
ff4569c7 DB |
738 | } |
739 | info->chip.ecc.mode = ecc_mode; | |
740 | ||
ef4e0c21 | 741 | info->clk = devm_clk_get(&pdev->dev, "aemif"); |
ff4569c7 DB |
742 | if (IS_ERR(info->clk)) { |
743 | ret = PTR_ERR(info->clk); | |
cd24f8c1 | 744 | dev_dbg(&pdev->dev, "unable to get AEMIF clock, err %d\n", ret); |
30a3970c | 745 | return ret; |
ff4569c7 DB |
746 | } |
747 | ||
ea73fe7f | 748 | ret = clk_prepare_enable(info->clk); |
ff4569c7 | 749 | if (ret < 0) { |
cd24f8c1 KH |
750 | dev_dbg(&pdev->dev, "unable to enable AEMIF clock, err %d\n", |
751 | ret); | |
ff4569c7 DB |
752 | goto err_clk_enable; |
753 | } | |
754 | ||
ff4569c7 DB |
755 | spin_lock_irq(&davinci_nand_lock); |
756 | ||
757 | /* put CSxNAND into NAND mode */ | |
758 | val = davinci_nand_readl(info, NANDFCR_OFFSET); | |
759 | val |= BIT(info->core_chipsel); | |
760 | davinci_nand_writel(info, NANDFCR_OFFSET, val); | |
761 | ||
762 | spin_unlock_irq(&davinci_nand_lock); | |
763 | ||
764 | /* Scan to find existence of the device(s) */ | |
a5cfb4db | 765 | ret = nand_scan_ident(mtd, pdata->mask_chipsel ? 2 : 1, NULL); |
ff4569c7 DB |
766 | if (ret < 0) { |
767 | dev_dbg(&pdev->dev, "no NAND chip(s) found\n"); | |
30a3970c | 768 | goto err; |
ff4569c7 DB |
769 | } |
770 | ||
6a4123e5 DB |
771 | /* Update ECC layout if needed ... for 1-bit HW ECC, the default |
772 | * is OK, but it allocates 6 bytes when only 3 are needed (for | |
773 | * each 512 bytes). For the 4-bit HW ECC, that default is not | |
774 | * usable: 10 bytes are needed, not 6. | |
775 | */ | |
776 | if (pdata->ecc_bits == 4) { | |
a5cfb4db | 777 | int chunks = mtd->writesize / 512; |
6a4123e5 | 778 | |
a5cfb4db | 779 | if (!chunks || mtd->oobsize < 16) { |
6a4123e5 DB |
780 | dev_dbg(&pdev->dev, "too small\n"); |
781 | ret = -EINVAL; | |
30a3970c | 782 | goto err; |
6a4123e5 DB |
783 | } |
784 | ||
785 | /* For small page chips, preserve the manufacturer's | |
786 | * badblock marking data ... and make sure a flash BBT | |
787 | * table marker fits in the free bytes. | |
788 | */ | |
789 | if (chunks == 1) { | |
e4aacaa1 BB |
790 | mtd_set_ooblayout(mtd, &hwecc4_small_ooblayout_ops); |
791 | } else if (chunks == 4 || chunks == 8) { | |
792 | mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops); | |
a11244c0 | 793 | info->chip.ecc.mode = NAND_ECC_HW_OOB_FIRST; |
e4aacaa1 BB |
794 | } else { |
795 | ret = -EIO; | |
796 | goto err; | |
a11244c0 | 797 | } |
6a4123e5 DB |
798 | } |
799 | ||
a5cfb4db | 800 | ret = nand_scan_tail(mtd); |
6a4123e5 | 801 | if (ret < 0) |
30a3970c | 802 | goto err; |
6a4123e5 | 803 | |
192afdbf | 804 | if (pdata->parts) |
a5cfb4db | 805 | ret = mtd_device_parse_register(mtd, NULL, NULL, |
192afdbf | 806 | pdata->parts, pdata->nr_parts); |
a61ae81a | 807 | else |
a5cfb4db | 808 | ret = mtd_device_register(mtd, NULL, 0); |
ff4569c7 | 809 | if (ret < 0) |
30a3970c | 810 | goto err; |
ff4569c7 DB |
811 | |
812 | val = davinci_nand_readl(info, NRCSR_OFFSET); | |
813 | dev_info(&pdev->dev, "controller rev. %d.%d\n", | |
814 | (val >> 8) & 0xff, val & 0xff); | |
815 | ||
816 | return 0; | |
817 | ||
30a3970c | 818 | err: |
ea73fe7f | 819 | clk_disable_unprepare(info->clk); |
ff4569c7 DB |
820 | |
821 | err_clk_enable: | |
6a4123e5 DB |
822 | spin_lock_irq(&davinci_nand_lock); |
823 | if (ecc_mode == NAND_ECC_HW_SYNDROME) | |
824 | ecc4_busy = false; | |
825 | spin_unlock_irq(&davinci_nand_lock); | |
ff4569c7 DB |
826 | return ret; |
827 | } | |
828 | ||
eaaa4a9a | 829 | static int nand_davinci_remove(struct platform_device *pdev) |
ff4569c7 DB |
830 | { |
831 | struct davinci_nand_info *info = platform_get_drvdata(pdev); | |
ff4569c7 | 832 | |
6a4123e5 DB |
833 | spin_lock_irq(&davinci_nand_lock); |
834 | if (info->chip.ecc.mode == NAND_ECC_HW_SYNDROME) | |
835 | ecc4_busy = false; | |
836 | spin_unlock_irq(&davinci_nand_lock); | |
837 | ||
a5cfb4db | 838 | nand_release(nand_to_mtd(&info->chip)); |
ff4569c7 | 839 | |
ea73fe7f | 840 | clk_disable_unprepare(info->clk); |
ff4569c7 DB |
841 | |
842 | return 0; | |
843 | } | |
844 | ||
845 | static struct platform_driver nand_davinci_driver = { | |
eaaa4a9a IK |
846 | .probe = nand_davinci_probe, |
847 | .remove = nand_davinci_remove, | |
ff4569c7 DB |
848 | .driver = { |
849 | .name = "davinci_nand", | |
c4f8cde8 | 850 | .of_match_table = of_match_ptr(davinci_nand_of_match), |
ff4569c7 DB |
851 | }, |
852 | }; | |
853 | MODULE_ALIAS("platform:davinci_nand"); | |
854 | ||
eaaa4a9a | 855 | module_platform_driver(nand_davinci_driver); |
ff4569c7 DB |
856 | |
857 | MODULE_LICENSE("GPL"); | |
858 | MODULE_AUTHOR("Texas Instruments"); | |
859 | MODULE_DESCRIPTION("Davinci NAND flash driver"); | |
860 |