Commit | Line | Data |
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ce082596 JR |
1 | /* |
2 | * NAND Flash Controller Device Driver | |
3 | * Copyright © 2009-2010, Intel Corporation and its suppliers. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | * | |
18 | */ | |
19 | ||
20 | #include <linux/interrupt.h> | |
21 | #include <linux/delay.h> | |
22 | #include <linux/wait.h> | |
23 | #include <linux/mutex.h> | |
b8664b37 | 24 | #include <linux/slab.h> |
ce082596 JR |
25 | #include <linux/pci.h> |
26 | #include <linux/mtd/mtd.h> | |
27 | #include <linux/module.h> | |
28 | ||
29 | #include "denali.h" | |
30 | ||
31 | MODULE_LICENSE("GPL"); | |
32 | ||
5bac3acf | 33 | /* We define a module parameter that allows the user to override |
ce082596 JR |
34 | * the hardware and decide what timing mode should be used. |
35 | */ | |
36 | #define NAND_DEFAULT_TIMINGS -1 | |
37 | ||
38 | static int onfi_timing_mode = NAND_DEFAULT_TIMINGS; | |
39 | module_param(onfi_timing_mode, int, S_IRUGO); | |
bdca6dae CD |
40 | MODULE_PARM_DESC(onfi_timing_mode, "Overrides default ONFI setting." |
41 | " -1 indicates use default timings"); | |
ce082596 JR |
42 | |
43 | #define DENALI_NAND_NAME "denali-nand" | |
44 | ||
45 | /* We define a macro here that combines all interrupts this driver uses into | |
46 | * a single constant value, for convenience. */ | |
47 | #define DENALI_IRQ_ALL (INTR_STATUS0__DMA_CMD_COMP | \ | |
48 | INTR_STATUS0__ECC_TRANSACTION_DONE | \ | |
49 | INTR_STATUS0__ECC_ERR | \ | |
50 | INTR_STATUS0__PROGRAM_FAIL | \ | |
51 | INTR_STATUS0__LOAD_COMP | \ | |
52 | INTR_STATUS0__PROGRAM_COMP | \ | |
53 | INTR_STATUS0__TIME_OUT | \ | |
54 | INTR_STATUS0__ERASE_FAIL | \ | |
55 | INTR_STATUS0__RST_COMP | \ | |
56 | INTR_STATUS0__ERASE_COMP) | |
57 | ||
5bac3acf | 58 | /* indicates whether or not the internal value for the flash bank is |
ce082596 | 59 | valid or not */ |
5bac3acf | 60 | #define CHIP_SELECT_INVALID -1 |
ce082596 JR |
61 | |
62 | #define SUPPORT_8BITECC 1 | |
63 | ||
5bac3acf | 64 | /* This macro divides two integers and rounds fractional values up |
ce082596 JR |
65 | * to the nearest integer value. */ |
66 | #define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y))) | |
67 | ||
68 | /* this macro allows us to convert from an MTD structure to our own | |
69 | * device context (denali) structure. | |
70 | */ | |
71 | #define mtd_to_denali(m) container_of(m, struct denali_nand_info, mtd) | |
72 | ||
73 | /* These constants are defined by the driver to enable common driver | |
74 | configuration options. */ | |
75 | #define SPARE_ACCESS 0x41 | |
76 | #define MAIN_ACCESS 0x42 | |
77 | #define MAIN_SPARE_ACCESS 0x43 | |
78 | ||
79 | #define DENALI_READ 0 | |
80 | #define DENALI_WRITE 0x100 | |
81 | ||
82 | /* types of device accesses. We can issue commands and get status */ | |
83 | #define COMMAND_CYCLE 0 | |
84 | #define ADDR_CYCLE 1 | |
85 | #define STATUS_CYCLE 2 | |
86 | ||
5bac3acf | 87 | /* this is a helper macro that allows us to |
ce082596 JR |
88 | * format the bank into the proper bits for the controller */ |
89 | #define BANK(x) ((x) << 24) | |
90 | ||
91 | /* List of platforms this NAND controller has be integrated into */ | |
92 | static const struct pci_device_id denali_pci_ids[] = { | |
93 | { PCI_VDEVICE(INTEL, 0x0701), INTEL_CE4100 }, | |
94 | { PCI_VDEVICE(INTEL, 0x0809), INTEL_MRST }, | |
95 | { /* end: all zeroes */ } | |
96 | }; | |
97 | ||
98 | ||
5bac3acf C |
99 | /* these are static lookup tables that give us easy access to |
100 | registers in the NAND controller. | |
ce082596 | 101 | */ |
5bac3acf C |
102 | static const uint32_t intr_status_addresses[4] = {INTR_STATUS0, |
103 | INTR_STATUS1, | |
104 | INTR_STATUS2, | |
ce082596 JR |
105 | INTR_STATUS3}; |
106 | ||
107 | static const uint32_t device_reset_banks[4] = {DEVICE_RESET__BANK0, | |
5bac3acf C |
108 | DEVICE_RESET__BANK1, |
109 | DEVICE_RESET__BANK2, | |
110 | DEVICE_RESET__BANK3}; | |
ce082596 JR |
111 | |
112 | static const uint32_t operation_timeout[4] = {INTR_STATUS0__TIME_OUT, | |
5bac3acf C |
113 | INTR_STATUS1__TIME_OUT, |
114 | INTR_STATUS2__TIME_OUT, | |
115 | INTR_STATUS3__TIME_OUT}; | |
ce082596 JR |
116 | |
117 | static const uint32_t reset_complete[4] = {INTR_STATUS0__RST_COMP, | |
5bac3acf C |
118 | INTR_STATUS1__RST_COMP, |
119 | INTR_STATUS2__RST_COMP, | |
120 | INTR_STATUS3__RST_COMP}; | |
ce082596 JR |
121 | |
122 | /* specifies the debug level of the driver */ | |
a99d1796 | 123 | static int nand_debug_level; |
ce082596 JR |
124 | |
125 | /* forward declarations */ | |
126 | static void clear_interrupts(struct denali_nand_info *denali); | |
bdca6dae CD |
127 | static uint32_t wait_for_irq(struct denali_nand_info *denali, |
128 | uint32_t irq_mask); | |
129 | static void denali_irq_enable(struct denali_nand_info *denali, | |
130 | uint32_t int_mask); | |
ce082596 JR |
131 | static uint32_t read_interrupt_status(struct denali_nand_info *denali); |
132 | ||
133 | #define DEBUG_DENALI 0 | |
134 | ||
135 | /* This is a wrapper for writing to the denali registers. | |
136 | * this allows us to create debug information so we can | |
5bac3acf | 137 | * observe how the driver is programming the device. |
ce082596 JR |
138 | * it uses standard linux convention for (val, addr) */ |
139 | static void denali_write32(uint32_t value, void *addr) | |
140 | { | |
5bac3acf | 141 | iowrite32(value, addr); |
ce082596 JR |
142 | |
143 | #if DEBUG_DENALI | |
bdca6dae CD |
144 | printk(KERN_INFO "wrote: 0x%x -> 0x%x\n", value, |
145 | (uint32_t)((uint32_t)addr & 0x1fff)); | |
ce082596 | 146 | #endif |
5bac3acf | 147 | } |
ce082596 | 148 | |
bdca6dae CD |
149 | /* Certain operations for the denali NAND controller use |
150 | * an indexed mode to read/write data. The operation is | |
151 | * performed by writing the address value of the command | |
152 | * to the device memory followed by the data. This function | |
153 | * abstracts this common operation. | |
ce082596 | 154 | */ |
bdca6dae CD |
155 | static void index_addr(struct denali_nand_info *denali, |
156 | uint32_t address, uint32_t data) | |
ce082596 JR |
157 | { |
158 | denali_write32(address, denali->flash_mem); | |
159 | denali_write32(data, denali->flash_mem + 0x10); | |
160 | } | |
161 | ||
162 | /* Perform an indexed read of the device */ | |
163 | static void index_addr_read_data(struct denali_nand_info *denali, | |
164 | uint32_t address, uint32_t *pdata) | |
165 | { | |
166 | denali_write32(address, denali->flash_mem); | |
167 | *pdata = ioread32(denali->flash_mem + 0x10); | |
168 | } | |
169 | ||
5bac3acf | 170 | /* We need to buffer some data for some of the NAND core routines. |
ce082596 JR |
171 | * The operations manage buffering that data. */ |
172 | static void reset_buf(struct denali_nand_info *denali) | |
173 | { | |
174 | denali->buf.head = denali->buf.tail = 0; | |
175 | } | |
176 | ||
177 | static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte) | |
178 | { | |
179 | BUG_ON(denali->buf.tail >= sizeof(denali->buf.buf)); | |
180 | denali->buf.buf[denali->buf.tail++] = byte; | |
181 | } | |
182 | ||
183 | /* reads the status of the device */ | |
184 | static void read_status(struct denali_nand_info *denali) | |
185 | { | |
186 | uint32_t cmd = 0x0; | |
187 | ||
188 | /* initialize the data buffer to store status */ | |
189 | reset_buf(denali); | |
190 | ||
191 | /* initiate a device status read */ | |
5bac3acf | 192 | cmd = MODE_11 | BANK(denali->flash_bank); |
ce082596 JR |
193 | index_addr(denali, cmd | COMMAND_CYCLE, 0x70); |
194 | denali_write32(cmd | STATUS_CYCLE, denali->flash_mem); | |
195 | ||
196 | /* update buffer with status value */ | |
197 | write_byte_to_buf(denali, ioread32(denali->flash_mem + 0x10)); | |
198 | ||
199 | #if DEBUG_DENALI | |
bdca6dae CD |
200 | printk(KERN_INFO "device reporting status value of 0x%2x\n", |
201 | denali->buf.buf[0]); | |
ce082596 JR |
202 | #endif |
203 | } | |
204 | ||
205 | /* resets a specific device connected to the core */ | |
206 | static void reset_bank(struct denali_nand_info *denali) | |
207 | { | |
208 | uint32_t irq_status = 0; | |
5bac3acf | 209 | uint32_t irq_mask = reset_complete[denali->flash_bank] | |
ce082596 JR |
210 | operation_timeout[denali->flash_bank]; |
211 | int bank = 0; | |
212 | ||
213 | clear_interrupts(denali); | |
214 | ||
215 | bank = device_reset_banks[denali->flash_bank]; | |
216 | denali_write32(bank, denali->flash_reg + DEVICE_RESET); | |
217 | ||
218 | irq_status = wait_for_irq(denali, irq_mask); | |
5bac3acf | 219 | |
ce082596 | 220 | if (irq_status & operation_timeout[denali->flash_bank]) |
ce082596 | 221 | printk(KERN_ERR "reset bank failed.\n"); |
ce082596 JR |
222 | } |
223 | ||
224 | /* Reset the flash controller */ | |
eda936ef | 225 | static uint16_t denali_nand_reset(struct denali_nand_info *denali) |
ce082596 JR |
226 | { |
227 | uint32_t i; | |
228 | ||
229 | nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n", | |
230 | __FILE__, __LINE__, __func__); | |
231 | ||
232 | for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++) | |
233 | denali_write32(reset_complete[i] | operation_timeout[i], | |
234 | denali->flash_reg + intr_status_addresses[i]); | |
235 | ||
236 | for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++) { | |
bdca6dae CD |
237 | denali_write32(device_reset_banks[i], |
238 | denali->flash_reg + DEVICE_RESET); | |
239 | while (!(ioread32(denali->flash_reg + | |
240 | intr_status_addresses[i]) & | |
ce082596 JR |
241 | (reset_complete[i] | operation_timeout[i]))) |
242 | ; | |
243 | if (ioread32(denali->flash_reg + intr_status_addresses[i]) & | |
244 | operation_timeout[i]) | |
245 | nand_dbg_print(NAND_DBG_WARN, | |
246 | "NAND Reset operation timed out on bank %d\n", i); | |
247 | } | |
248 | ||
249 | for (i = 0; i < LLD_MAX_FLASH_BANKS; i++) | |
250 | denali_write32(reset_complete[i] | operation_timeout[i], | |
251 | denali->flash_reg + intr_status_addresses[i]); | |
252 | ||
253 | return PASS; | |
254 | } | |
255 | ||
bdca6dae CD |
256 | /* this routine calculates the ONFI timing values for a given mode and |
257 | * programs the clocking register accordingly. The mode is determined by | |
258 | * the get_onfi_nand_para routine. | |
ce082596 | 259 | */ |
eda936ef | 260 | static void nand_onfi_timing_set(struct denali_nand_info *denali, |
bdca6dae | 261 | uint16_t mode) |
ce082596 JR |
262 | { |
263 | uint16_t Trea[6] = {40, 30, 25, 20, 20, 16}; | |
264 | uint16_t Trp[6] = {50, 25, 17, 15, 12, 10}; | |
265 | uint16_t Treh[6] = {30, 15, 15, 10, 10, 7}; | |
266 | uint16_t Trc[6] = {100, 50, 35, 30, 25, 20}; | |
267 | uint16_t Trhoh[6] = {0, 15, 15, 15, 15, 15}; | |
268 | uint16_t Trloh[6] = {0, 0, 0, 0, 5, 5}; | |
269 | uint16_t Tcea[6] = {100, 45, 30, 25, 25, 25}; | |
270 | uint16_t Tadl[6] = {200, 100, 100, 100, 70, 70}; | |
271 | uint16_t Trhw[6] = {200, 100, 100, 100, 100, 100}; | |
272 | uint16_t Trhz[6] = {200, 100, 100, 100, 100, 100}; | |
273 | uint16_t Twhr[6] = {120, 80, 80, 60, 60, 60}; | |
274 | uint16_t Tcs[6] = {70, 35, 25, 25, 20, 15}; | |
275 | ||
276 | uint16_t TclsRising = 1; | |
277 | uint16_t data_invalid_rhoh, data_invalid_rloh, data_invalid; | |
278 | uint16_t dv_window = 0; | |
279 | uint16_t en_lo, en_hi; | |
280 | uint16_t acc_clks; | |
281 | uint16_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt; | |
282 | ||
283 | nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n", | |
284 | __FILE__, __LINE__, __func__); | |
285 | ||
286 | en_lo = CEIL_DIV(Trp[mode], CLK_X); | |
287 | en_hi = CEIL_DIV(Treh[mode], CLK_X); | |
288 | #if ONFI_BLOOM_TIME | |
289 | if ((en_hi * CLK_X) < (Treh[mode] + 2)) | |
290 | en_hi++; | |
291 | #endif | |
292 | ||
293 | if ((en_lo + en_hi) * CLK_X < Trc[mode]) | |
294 | en_lo += CEIL_DIV((Trc[mode] - (en_lo + en_hi) * CLK_X), CLK_X); | |
295 | ||
296 | if ((en_lo + en_hi) < CLK_MULTI) | |
297 | en_lo += CLK_MULTI - en_lo - en_hi; | |
298 | ||
299 | while (dv_window < 8) { | |
300 | data_invalid_rhoh = en_lo * CLK_X + Trhoh[mode]; | |
301 | ||
302 | data_invalid_rloh = (en_lo + en_hi) * CLK_X + Trloh[mode]; | |
303 | ||
304 | data_invalid = | |
305 | data_invalid_rhoh < | |
306 | data_invalid_rloh ? data_invalid_rhoh : data_invalid_rloh; | |
307 | ||
308 | dv_window = data_invalid - Trea[mode]; | |
309 | ||
310 | if (dv_window < 8) | |
311 | en_lo++; | |
312 | } | |
313 | ||
314 | acc_clks = CEIL_DIV(Trea[mode], CLK_X); | |
315 | ||
316 | while (((acc_clks * CLK_X) - Trea[mode]) < 3) | |
317 | acc_clks++; | |
318 | ||
319 | if ((data_invalid - acc_clks * CLK_X) < 2) | |
320 | nand_dbg_print(NAND_DBG_WARN, "%s, Line %d: Warning!\n", | |
321 | __FILE__, __LINE__); | |
322 | ||
323 | addr_2_data = CEIL_DIV(Tadl[mode], CLK_X); | |
324 | re_2_we = CEIL_DIV(Trhw[mode], CLK_X); | |
325 | re_2_re = CEIL_DIV(Trhz[mode], CLK_X); | |
326 | we_2_re = CEIL_DIV(Twhr[mode], CLK_X); | |
327 | cs_cnt = CEIL_DIV((Tcs[mode] - Trp[mode]), CLK_X); | |
328 | if (!TclsRising) | |
329 | cs_cnt = CEIL_DIV(Tcs[mode], CLK_X); | |
330 | if (cs_cnt == 0) | |
331 | cs_cnt = 1; | |
332 | ||
333 | if (Tcea[mode]) { | |
334 | while (((cs_cnt * CLK_X) + Trea[mode]) < Tcea[mode]) | |
335 | cs_cnt++; | |
336 | } | |
337 | ||
338 | #if MODE5_WORKAROUND | |
339 | if (mode == 5) | |
340 | acc_clks = 5; | |
341 | #endif | |
342 | ||
343 | /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */ | |
344 | if ((ioread32(denali->flash_reg + MANUFACTURER_ID) == 0) && | |
345 | (ioread32(denali->flash_reg + DEVICE_ID) == 0x88)) | |
346 | acc_clks = 6; | |
347 | ||
348 | denali_write32(acc_clks, denali->flash_reg + ACC_CLKS); | |
349 | denali_write32(re_2_we, denali->flash_reg + RE_2_WE); | |
350 | denali_write32(re_2_re, denali->flash_reg + RE_2_RE); | |
351 | denali_write32(we_2_re, denali->flash_reg + WE_2_RE); | |
352 | denali_write32(addr_2_data, denali->flash_reg + ADDR_2_DATA); | |
353 | denali_write32(en_lo, denali->flash_reg + RDWR_EN_LO_CNT); | |
354 | denali_write32(en_hi, denali->flash_reg + RDWR_EN_HI_CNT); | |
355 | denali_write32(cs_cnt, denali->flash_reg + CS_SETUP_CNT); | |
356 | } | |
357 | ||
ce082596 JR |
358 | /* queries the NAND device to see what ONFI modes it supports. */ |
359 | static uint16_t get_onfi_nand_para(struct denali_nand_info *denali) | |
360 | { | |
361 | int i; | |
4c03bbdf CD |
362 | /* we needn't to do a reset here because driver has already |
363 | * reset all the banks before | |
364 | * */ | |
ce082596 JR |
365 | if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) & |
366 | ONFI_TIMING_MODE__VALUE)) | |
367 | return FAIL; | |
368 | ||
369 | for (i = 5; i > 0; i--) { | |
bdca6dae CD |
370 | if (ioread32(denali->flash_reg + ONFI_TIMING_MODE) & |
371 | (0x01 << i)) | |
ce082596 JR |
372 | break; |
373 | } | |
374 | ||
eda936ef | 375 | nand_onfi_timing_set(denali, i); |
ce082596 | 376 | |
ce082596 JR |
377 | /* By now, all the ONFI devices we know support the page cache */ |
378 | /* rw feature. So here we enable the pipeline_rw_ahead feature */ | |
379 | /* iowrite32(1, denali->flash_reg + CACHE_WRITE_ENABLE); */ | |
380 | /* iowrite32(1, denali->flash_reg + CACHE_READ_ENABLE); */ | |
381 | ||
382 | return PASS; | |
383 | } | |
384 | ||
4c03bbdf CD |
385 | static void get_samsung_nand_para(struct denali_nand_info *denali, |
386 | uint8_t device_id) | |
ce082596 | 387 | { |
4c03bbdf | 388 | if (device_id == 0xd3) { /* Samsung K9WAG08U1A */ |
ce082596 JR |
389 | /* Set timing register values according to datasheet */ |
390 | denali_write32(5, denali->flash_reg + ACC_CLKS); | |
391 | denali_write32(20, denali->flash_reg + RE_2_WE); | |
392 | denali_write32(12, denali->flash_reg + WE_2_RE); | |
393 | denali_write32(14, denali->flash_reg + ADDR_2_DATA); | |
394 | denali_write32(3, denali->flash_reg + RDWR_EN_LO_CNT); | |
395 | denali_write32(2, denali->flash_reg + RDWR_EN_HI_CNT); | |
396 | denali_write32(2, denali->flash_reg + CS_SETUP_CNT); | |
397 | } | |
ce082596 JR |
398 | } |
399 | ||
400 | static void get_toshiba_nand_para(struct denali_nand_info *denali) | |
401 | { | |
ce082596 JR |
402 | uint32_t tmp; |
403 | ||
404 | /* Workaround to fix a controller bug which reports a wrong */ | |
405 | /* spare area size for some kind of Toshiba NAND device */ | |
406 | if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) && | |
407 | (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) { | |
408 | denali_write32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); | |
409 | tmp = ioread32(denali->flash_reg + DEVICES_CONNECTED) * | |
410 | ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE); | |
bdca6dae CD |
411 | denali_write32(tmp, |
412 | denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); | |
ce082596 JR |
413 | #if SUPPORT_15BITECC |
414 | denali_write32(15, denali->flash_reg + ECC_CORRECTION); | |
415 | #elif SUPPORT_8BITECC | |
416 | denali_write32(8, denali->flash_reg + ECC_CORRECTION); | |
417 | #endif | |
418 | } | |
ce082596 JR |
419 | } |
420 | ||
ef41e1bb CD |
421 | static void get_hynix_nand_para(struct denali_nand_info *denali, |
422 | uint8_t device_id) | |
ce082596 | 423 | { |
ce082596 JR |
424 | uint32_t main_size, spare_size; |
425 | ||
ef41e1bb | 426 | switch (device_id) { |
ce082596 JR |
427 | case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */ |
428 | case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */ | |
429 | denali_write32(128, denali->flash_reg + PAGES_PER_BLOCK); | |
430 | denali_write32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE); | |
431 | denali_write32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); | |
bdca6dae CD |
432 | main_size = 4096 * |
433 | ioread32(denali->flash_reg + DEVICES_CONNECTED); | |
434 | spare_size = 224 * | |
435 | ioread32(denali->flash_reg + DEVICES_CONNECTED); | |
436 | denali_write32(main_size, | |
437 | denali->flash_reg + LOGICAL_PAGE_DATA_SIZE); | |
438 | denali_write32(spare_size, | |
439 | denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); | |
ce082596 JR |
440 | denali_write32(0, denali->flash_reg + DEVICE_WIDTH); |
441 | #if SUPPORT_15BITECC | |
442 | denali_write32(15, denali->flash_reg + ECC_CORRECTION); | |
443 | #elif SUPPORT_8BITECC | |
444 | denali_write32(8, denali->flash_reg + ECC_CORRECTION); | |
445 | #endif | |
ce082596 JR |
446 | break; |
447 | default: | |
448 | nand_dbg_print(NAND_DBG_WARN, | |
449 | "Spectra: Unknown Hynix NAND (Device ID: 0x%x)." | |
450 | "Will use default parameter values instead.\n", | |
66406524 | 451 | device_id); |
ce082596 | 452 | } |
ce082596 JR |
453 | } |
454 | ||
455 | /* determines how many NAND chips are connected to the controller. Note for | |
5bac3acf | 456 | Intel CE4100 devices we don't support more than one device. |
ce082596 JR |
457 | */ |
458 | static void find_valid_banks(struct denali_nand_info *denali) | |
459 | { | |
460 | uint32_t id[LLD_MAX_FLASH_BANKS]; | |
461 | int i; | |
462 | ||
463 | denali->total_used_banks = 1; | |
464 | for (i = 0; i < LLD_MAX_FLASH_BANKS; i++) { | |
465 | index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 0), 0x90); | |
466 | index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 1), 0); | |
bdca6dae CD |
467 | index_addr_read_data(denali, |
468 | (uint32_t)(MODE_11 | (i << 24) | 2), &id[i]); | |
ce082596 JR |
469 | |
470 | nand_dbg_print(NAND_DBG_DEBUG, | |
471 | "Return 1st ID for bank[%d]: %x\n", i, id[i]); | |
472 | ||
473 | if (i == 0) { | |
474 | if (!(id[i] & 0x0ff)) | |
475 | break; /* WTF? */ | |
476 | } else { | |
477 | if ((id[i] & 0x0ff) == (id[0] & 0x0ff)) | |
478 | denali->total_used_banks++; | |
479 | else | |
480 | break; | |
481 | } | |
482 | } | |
483 | ||
345b1d3b | 484 | if (denali->platform == INTEL_CE4100) { |
ce082596 JR |
485 | /* Platform limitations of the CE4100 device limit |
486 | * users to a single chip solution for NAND. | |
5bac3acf C |
487 | * Multichip support is not enabled. |
488 | */ | |
345b1d3b | 489 | if (denali->total_used_banks != 1) { |
ce082596 JR |
490 | printk(KERN_ERR "Sorry, Intel CE4100 only supports " |
491 | "a single NAND device.\n"); | |
492 | BUG(); | |
493 | } | |
494 | } | |
495 | nand_dbg_print(NAND_DBG_DEBUG, | |
496 | "denali->total_used_banks: %d\n", denali->total_used_banks); | |
497 | } | |
498 | ||
499 | static void detect_partition_feature(struct denali_nand_info *denali) | |
500 | { | |
66406524 CD |
501 | /* For MRST platform, denali->fwblks represent the |
502 | * number of blocks firmware is taken, | |
503 | * FW is in protect partition and MTD driver has no | |
504 | * permission to access it. So let driver know how many | |
505 | * blocks it can't touch. | |
506 | * */ | |
ce082596 JR |
507 | if (ioread32(denali->flash_reg + FEATURES) & FEATURES__PARTITION) { |
508 | if ((ioread32(denali->flash_reg + PERM_SRC_ID_1) & | |
509 | PERM_SRC_ID_1__SRCID) == SPECTRA_PARTITION_ID) { | |
66406524 | 510 | denali->fwblks = |
ce082596 JR |
511 | ((ioread32(denali->flash_reg + MIN_MAX_BANK_1) & |
512 | MIN_MAX_BANK_1__MIN_VALUE) * | |
66406524 | 513 | denali->blksperchip) |
ce082596 JR |
514 | + |
515 | (ioread32(denali->flash_reg + MIN_BLK_ADDR_1) & | |
516 | MIN_BLK_ADDR_1__VALUE); | |
66406524 CD |
517 | } else |
518 | denali->fwblks = SPECTRA_START_BLOCK; | |
519 | } else | |
520 | denali->fwblks = SPECTRA_START_BLOCK; | |
ce082596 JR |
521 | } |
522 | ||
eda936ef | 523 | static uint16_t denali_nand_timing_set(struct denali_nand_info *denali) |
ce082596 JR |
524 | { |
525 | uint16_t status = PASS; | |
ef41e1bb CD |
526 | uint32_t id_bytes[5], addr; |
527 | uint8_t i, maf_id, device_id; | |
ce082596 JR |
528 | |
529 | nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n", | |
530 | __FILE__, __LINE__, __func__); | |
531 | ||
ef41e1bb CD |
532 | /* Use read id method to get device ID and other |
533 | * params. For some NAND chips, controller can't | |
534 | * report the correct device ID by reading from | |
535 | * DEVICE_ID register | |
536 | * */ | |
537 | addr = (uint32_t)MODE_11 | BANK(denali->flash_bank); | |
538 | index_addr(denali, (uint32_t)addr | 0, 0x90); | |
539 | index_addr(denali, (uint32_t)addr | 1, 0); | |
540 | for (i = 0; i < 5; i++) | |
541 | index_addr_read_data(denali, addr | 2, &id_bytes[i]); | |
542 | maf_id = id_bytes[0]; | |
543 | device_id = id_bytes[1]; | |
ce082596 JR |
544 | |
545 | if (ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) & | |
546 | ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */ | |
547 | if (FAIL == get_onfi_nand_para(denali)) | |
548 | return FAIL; | |
ef41e1bb | 549 | } else if (maf_id == 0xEC) { /* Samsung NAND */ |
4c03bbdf | 550 | get_samsung_nand_para(denali, device_id); |
ef41e1bb | 551 | } else if (maf_id == 0x98) { /* Toshiba NAND */ |
ce082596 | 552 | get_toshiba_nand_para(denali); |
ef41e1bb CD |
553 | } else if (maf_id == 0xAD) { /* Hynix NAND */ |
554 | get_hynix_nand_para(denali, device_id); | |
ce082596 JR |
555 | } |
556 | ||
557 | nand_dbg_print(NAND_DBG_DEBUG, "Dump timing register values:" | |
558 | "acc_clks: %d, re_2_we: %d, we_2_re: %d," | |
559 | "addr_2_data: %d, rdwr_en_lo_cnt: %d, " | |
560 | "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n", | |
561 | ioread32(denali->flash_reg + ACC_CLKS), | |
562 | ioread32(denali->flash_reg + RE_2_WE), | |
563 | ioread32(denali->flash_reg + WE_2_RE), | |
564 | ioread32(denali->flash_reg + ADDR_2_DATA), | |
565 | ioread32(denali->flash_reg + RDWR_EN_LO_CNT), | |
566 | ioread32(denali->flash_reg + RDWR_EN_HI_CNT), | |
567 | ioread32(denali->flash_reg + CS_SETUP_CNT)); | |
568 | ||
ce082596 JR |
569 | find_valid_banks(denali); |
570 | ||
571 | detect_partition_feature(denali); | |
572 | ||
ce082596 | 573 | /* If the user specified to override the default timings |
5bac3acf | 574 | * with a specific ONFI mode, we apply those changes here. |
ce082596 JR |
575 | */ |
576 | if (onfi_timing_mode != NAND_DEFAULT_TIMINGS) | |
eda936ef | 577 | nand_onfi_timing_set(denali, onfi_timing_mode); |
ce082596 JR |
578 | |
579 | return status; | |
580 | } | |
581 | ||
eda936ef | 582 | static void denali_set_intr_modes(struct denali_nand_info *denali, |
ce082596 JR |
583 | uint16_t INT_ENABLE) |
584 | { | |
585 | nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n", | |
586 | __FILE__, __LINE__, __func__); | |
587 | ||
588 | if (INT_ENABLE) | |
589 | denali_write32(1, denali->flash_reg + GLOBAL_INT_ENABLE); | |
590 | else | |
591 | denali_write32(0, denali->flash_reg + GLOBAL_INT_ENABLE); | |
592 | } | |
593 | ||
594 | /* validation function to verify that the controlling software is making | |
595 | a valid request | |
596 | */ | |
597 | static inline bool is_flash_bank_valid(int flash_bank) | |
598 | { | |
5bac3acf | 599 | return (flash_bank >= 0 && flash_bank < 4); |
ce082596 JR |
600 | } |
601 | ||
602 | static void denali_irq_init(struct denali_nand_info *denali) | |
603 | { | |
604 | uint32_t int_mask = 0; | |
605 | ||
606 | /* Disable global interrupts */ | |
eda936ef | 607 | denali_set_intr_modes(denali, false); |
ce082596 JR |
608 | |
609 | int_mask = DENALI_IRQ_ALL; | |
610 | ||
611 | /* Clear all status bits */ | |
612 | denali_write32(0xFFFF, denali->flash_reg + INTR_STATUS0); | |
613 | denali_write32(0xFFFF, denali->flash_reg + INTR_STATUS1); | |
614 | denali_write32(0xFFFF, denali->flash_reg + INTR_STATUS2); | |
615 | denali_write32(0xFFFF, denali->flash_reg + INTR_STATUS3); | |
616 | ||
617 | denali_irq_enable(denali, int_mask); | |
618 | } | |
619 | ||
620 | static void denali_irq_cleanup(int irqnum, struct denali_nand_info *denali) | |
621 | { | |
eda936ef | 622 | denali_set_intr_modes(denali, false); |
ce082596 JR |
623 | free_irq(irqnum, denali); |
624 | } | |
625 | ||
bdca6dae CD |
626 | static void denali_irq_enable(struct denali_nand_info *denali, |
627 | uint32_t int_mask) | |
ce082596 JR |
628 | { |
629 | denali_write32(int_mask, denali->flash_reg + INTR_EN0); | |
630 | denali_write32(int_mask, denali->flash_reg + INTR_EN1); | |
631 | denali_write32(int_mask, denali->flash_reg + INTR_EN2); | |
632 | denali_write32(int_mask, denali->flash_reg + INTR_EN3); | |
633 | } | |
634 | ||
635 | /* This function only returns when an interrupt that this driver cares about | |
5bac3acf | 636 | * occurs. This is to reduce the overhead of servicing interrupts |
ce082596 JR |
637 | */ |
638 | static inline uint32_t denali_irq_detected(struct denali_nand_info *denali) | |
639 | { | |
a99d1796 | 640 | return read_interrupt_status(denali) & DENALI_IRQ_ALL; |
ce082596 JR |
641 | } |
642 | ||
643 | /* Interrupts are cleared by writing a 1 to the appropriate status bit */ | |
bdca6dae CD |
644 | static inline void clear_interrupt(struct denali_nand_info *denali, |
645 | uint32_t irq_mask) | |
ce082596 JR |
646 | { |
647 | uint32_t intr_status_reg = 0; | |
648 | ||
649 | intr_status_reg = intr_status_addresses[denali->flash_bank]; | |
650 | ||
651 | denali_write32(irq_mask, denali->flash_reg + intr_status_reg); | |
652 | } | |
653 | ||
654 | static void clear_interrupts(struct denali_nand_info *denali) | |
655 | { | |
656 | uint32_t status = 0x0; | |
657 | spin_lock_irq(&denali->irq_lock); | |
658 | ||
659 | status = read_interrupt_status(denali); | |
660 | ||
661 | #if DEBUG_DENALI | |
662 | denali->irq_debug_array[denali->idx++] = 0x30000000 | status; | |
663 | denali->idx %= 32; | |
664 | #endif | |
665 | ||
666 | denali->irq_status = 0x0; | |
667 | spin_unlock_irq(&denali->irq_lock); | |
668 | } | |
669 | ||
670 | static uint32_t read_interrupt_status(struct denali_nand_info *denali) | |
671 | { | |
672 | uint32_t intr_status_reg = 0; | |
673 | ||
674 | intr_status_reg = intr_status_addresses[denali->flash_bank]; | |
675 | ||
676 | return ioread32(denali->flash_reg + intr_status_reg); | |
677 | } | |
678 | ||
679 | #if DEBUG_DENALI | |
680 | static void print_irq_log(struct denali_nand_info *denali) | |
681 | { | |
682 | int i = 0; | |
683 | ||
bf1806dd | 684 | printk(KERN_INFO "ISR debug log index = %X\n", denali->idx); |
ce082596 | 685 | for (i = 0; i < 32; i++) |
bf1806dd | 686 | printk(KERN_INFO "%08X: %08X\n", i, denali->irq_debug_array[i]); |
ce082596 JR |
687 | } |
688 | #endif | |
689 | ||
5bac3acf C |
690 | /* This is the interrupt service routine. It handles all interrupts |
691 | * sent to this device. Note that on CE4100, this is a shared | |
692 | * interrupt. | |
ce082596 JR |
693 | */ |
694 | static irqreturn_t denali_isr(int irq, void *dev_id) | |
695 | { | |
696 | struct denali_nand_info *denali = dev_id; | |
697 | uint32_t irq_status = 0x0; | |
698 | irqreturn_t result = IRQ_NONE; | |
699 | ||
700 | spin_lock(&denali->irq_lock); | |
701 | ||
5bac3acf C |
702 | /* check to see if a valid NAND chip has |
703 | * been selected. | |
ce082596 | 704 | */ |
345b1d3b | 705 | if (is_flash_bank_valid(denali->flash_bank)) { |
5bac3acf | 706 | /* check to see if controller generated |
ce082596 | 707 | * the interrupt, since this is a shared interrupt */ |
bdca6dae CD |
708 | irq_status = denali_irq_detected(denali); |
709 | if (irq_status != 0) { | |
ce082596 | 710 | #if DEBUG_DENALI |
bdca6dae CD |
711 | denali->irq_debug_array[denali->idx++] = |
712 | 0x10000000 | irq_status; | |
ce082596 JR |
713 | denali->idx %= 32; |
714 | ||
bf1806dd | 715 | printk(KERN_INFO "IRQ status = 0x%04x\n", irq_status); |
ce082596 JR |
716 | #endif |
717 | /* handle interrupt */ | |
718 | /* first acknowledge it */ | |
719 | clear_interrupt(denali, irq_status); | |
720 | /* store the status in the device context for someone | |
721 | to read */ | |
722 | denali->irq_status |= irq_status; | |
723 | /* notify anyone who cares that it happened */ | |
724 | complete(&denali->complete); | |
725 | /* tell the OS that we've handled this */ | |
726 | result = IRQ_HANDLED; | |
727 | } | |
728 | } | |
729 | spin_unlock(&denali->irq_lock); | |
730 | return result; | |
731 | } | |
732 | #define BANK(x) ((x) << 24) | |
733 | ||
734 | static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask) | |
735 | { | |
736 | unsigned long comp_res = 0; | |
737 | uint32_t intr_status = 0; | |
738 | bool retry = false; | |
739 | unsigned long timeout = msecs_to_jiffies(1000); | |
740 | ||
345b1d3b | 741 | do { |
ce082596 | 742 | #if DEBUG_DENALI |
bf1806dd | 743 | printk(KERN_INFO "waiting for 0x%x\n", irq_mask); |
ce082596 | 744 | #endif |
bdca6dae CD |
745 | comp_res = |
746 | wait_for_completion_timeout(&denali->complete, timeout); | |
ce082596 JR |
747 | spin_lock_irq(&denali->irq_lock); |
748 | intr_status = denali->irq_status; | |
749 | ||
750 | #if DEBUG_DENALI | |
bdca6dae CD |
751 | denali->irq_debug_array[denali->idx++] = |
752 | 0x20000000 | (irq_mask << 16) | intr_status; | |
ce082596 JR |
753 | denali->idx %= 32; |
754 | #endif | |
755 | ||
345b1d3b | 756 | if (intr_status & irq_mask) { |
ce082596 JR |
757 | denali->irq_status &= ~irq_mask; |
758 | spin_unlock_irq(&denali->irq_lock); | |
759 | #if DEBUG_DENALI | |
bdca6dae CD |
760 | if (retry) |
761 | printk(KERN_INFO "status on retry = 0x%x\n", | |
762 | intr_status); | |
ce082596 JR |
763 | #endif |
764 | /* our interrupt was detected */ | |
765 | break; | |
345b1d3b | 766 | } else { |
5bac3acf C |
767 | /* these are not the interrupts you are looking for - |
768 | * need to wait again */ | |
ce082596 JR |
769 | spin_unlock_irq(&denali->irq_lock); |
770 | #if DEBUG_DENALI | |
771 | print_irq_log(denali); | |
bdca6dae CD |
772 | printk(KERN_INFO "received irq nobody cared:" |
773 | " irq_status = 0x%x, irq_mask = 0x%x," | |
774 | " timeout = %ld\n", intr_status, | |
775 | irq_mask, comp_res); | |
ce082596 JR |
776 | #endif |
777 | retry = true; | |
778 | } | |
779 | } while (comp_res != 0); | |
780 | ||
345b1d3b | 781 | if (comp_res == 0) { |
ce082596 | 782 | /* timeout */ |
5bac3acf C |
783 | printk(KERN_ERR "timeout occurred, status = 0x%x, mask = 0x%x\n", |
784 | intr_status, irq_mask); | |
ce082596 JR |
785 | |
786 | intr_status = 0; | |
787 | } | |
788 | return intr_status; | |
789 | } | |
790 | ||
5bac3acf | 791 | /* This helper function setups the registers for ECC and whether or not |
ce082596 | 792 | the spare area will be transfered. */ |
5bac3acf | 793 | static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en, |
ce082596 JR |
794 | bool transfer_spare) |
795 | { | |
5bac3acf | 796 | int ecc_en_flag = 0, transfer_spare_flag = 0; |
ce082596 JR |
797 | |
798 | /* set ECC, transfer spare bits if needed */ | |
799 | ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0; | |
800 | transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0; | |
801 | ||
802 | /* Enable spare area/ECC per user's request. */ | |
803 | denali_write32(ecc_en_flag, denali->flash_reg + ECC_ENABLE); | |
bdca6dae CD |
804 | denali_write32(transfer_spare_flag, |
805 | denali->flash_reg + TRANSFER_SPARE_REG); | |
ce082596 JR |
806 | } |
807 | ||
5bac3acf C |
808 | /* sends a pipeline command operation to the controller. See the Denali NAND |
809 | controller's user guide for more information (section 4.2.3.6). | |
ce082596 | 810 | */ |
bdca6dae CD |
811 | static int denali_send_pipeline_cmd(struct denali_nand_info *denali, |
812 | bool ecc_en, | |
813 | bool transfer_spare, | |
814 | int access_type, | |
815 | int op) | |
ce082596 JR |
816 | { |
817 | int status = PASS; | |
5bac3acf | 818 | uint32_t addr = 0x0, cmd = 0x0, page_count = 1, irq_status = 0, |
ce082596 JR |
819 | irq_mask = 0; |
820 | ||
a99d1796 CD |
821 | if (op == DENALI_READ) |
822 | irq_mask = INTR_STATUS0__LOAD_COMP; | |
823 | else if (op == DENALI_WRITE) | |
824 | irq_mask = 0; | |
825 | else | |
826 | BUG(); | |
ce082596 JR |
827 | |
828 | setup_ecc_for_xfer(denali, ecc_en, transfer_spare); | |
829 | ||
830 | #if DEBUG_DENALI | |
831 | spin_lock_irq(&denali->irq_lock); | |
bdca6dae CD |
832 | denali->irq_debug_array[denali->idx++] = |
833 | 0x40000000 | ioread32(denali->flash_reg + ECC_ENABLE) | | |
834 | (access_type << 4); | |
ce082596 JR |
835 | denali->idx %= 32; |
836 | spin_unlock_irq(&denali->irq_lock); | |
837 | #endif | |
838 | ||
839 | ||
840 | /* clear interrupts */ | |
5bac3acf | 841 | clear_interrupts(denali); |
ce082596 JR |
842 | |
843 | addr = BANK(denali->flash_bank) | denali->page; | |
844 | ||
345b1d3b | 845 | if (op == DENALI_WRITE && access_type != SPARE_ACCESS) { |
5bac3acf | 846 | cmd = MODE_01 | addr; |
ce082596 | 847 | denali_write32(cmd, denali->flash_mem); |
345b1d3b | 848 | } else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) { |
ce082596 | 849 | /* read spare area */ |
5bac3acf | 850 | cmd = MODE_10 | addr; |
ce082596 JR |
851 | index_addr(denali, (uint32_t)cmd, access_type); |
852 | ||
5bac3acf | 853 | cmd = MODE_01 | addr; |
ce082596 | 854 | denali_write32(cmd, denali->flash_mem); |
345b1d3b | 855 | } else if (op == DENALI_READ) { |
ce082596 | 856 | /* setup page read request for access type */ |
5bac3acf | 857 | cmd = MODE_10 | addr; |
ce082596 JR |
858 | index_addr(denali, (uint32_t)cmd, access_type); |
859 | ||
860 | /* page 33 of the NAND controller spec indicates we should not | |
5bac3acf | 861 | use the pipeline commands in Spare area only mode. So we |
ce082596 JR |
862 | don't. |
863 | */ | |
345b1d3b | 864 | if (access_type == SPARE_ACCESS) { |
ce082596 JR |
865 | cmd = MODE_01 | addr; |
866 | denali_write32(cmd, denali->flash_mem); | |
345b1d3b | 867 | } else { |
bdca6dae CD |
868 | index_addr(denali, (uint32_t)cmd, |
869 | 0x2000 | op | page_count); | |
5bac3acf C |
870 | |
871 | /* wait for command to be accepted | |
bdca6dae CD |
872 | * can always use status0 bit as the |
873 | * mask is identical for each | |
ce082596 JR |
874 | * bank. */ |
875 | irq_status = wait_for_irq(denali, irq_mask); | |
876 | ||
345b1d3b | 877 | if (irq_status == 0) { |
ce082596 | 878 | printk(KERN_ERR "cmd, page, addr on timeout " |
bdca6dae CD |
879 | "(0x%x, 0x%x, 0x%x)\n", cmd, |
880 | denali->page, addr); | |
ce082596 | 881 | status = FAIL; |
345b1d3b | 882 | } else { |
ce082596 JR |
883 | cmd = MODE_01 | addr; |
884 | denali_write32(cmd, denali->flash_mem); | |
885 | } | |
886 | } | |
887 | } | |
888 | return status; | |
889 | } | |
890 | ||
891 | /* helper function that simply writes a buffer to the flash */ | |
bdca6dae CD |
892 | static int write_data_to_flash_mem(struct denali_nand_info *denali, |
893 | const uint8_t *buf, | |
894 | int len) | |
ce082596 JR |
895 | { |
896 | uint32_t i = 0, *buf32; | |
897 | ||
5bac3acf C |
898 | /* verify that the len is a multiple of 4. see comment in |
899 | * read_data_from_flash_mem() */ | |
ce082596 JR |
900 | BUG_ON((len % 4) != 0); |
901 | ||
902 | /* write the data to the flash memory */ | |
903 | buf32 = (uint32_t *)buf; | |
904 | for (i = 0; i < len / 4; i++) | |
ce082596 | 905 | denali_write32(*buf32++, denali->flash_mem + 0x10); |
5bac3acf | 906 | return i*4; /* intent is to return the number of bytes read */ |
ce082596 JR |
907 | } |
908 | ||
909 | /* helper function that simply reads a buffer from the flash */ | |
bdca6dae CD |
910 | static int read_data_from_flash_mem(struct denali_nand_info *denali, |
911 | uint8_t *buf, | |
912 | int len) | |
ce082596 JR |
913 | { |
914 | uint32_t i = 0, *buf32; | |
915 | ||
916 | /* we assume that len will be a multiple of 4, if not | |
917 | * it would be nice to know about it ASAP rather than | |
5bac3acf C |
918 | * have random failures... |
919 | * This assumption is based on the fact that this | |
920 | * function is designed to be used to read flash pages, | |
ce082596 JR |
921 | * which are typically multiples of 4... |
922 | */ | |
923 | ||
924 | BUG_ON((len % 4) != 0); | |
925 | ||
926 | /* transfer the data from the flash */ | |
927 | buf32 = (uint32_t *)buf; | |
928 | for (i = 0; i < len / 4; i++) | |
ce082596 | 929 | *buf32++ = ioread32(denali->flash_mem + 0x10); |
5bac3acf | 930 | return i*4; /* intent is to return the number of bytes read */ |
ce082596 JR |
931 | } |
932 | ||
933 | /* writes OOB data to the device */ | |
934 | static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) | |
935 | { | |
936 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
937 | uint32_t irq_status = 0; | |
5bac3acf | 938 | uint32_t irq_mask = INTR_STATUS0__PROGRAM_COMP | |
ce082596 JR |
939 | INTR_STATUS0__PROGRAM_FAIL; |
940 | int status = 0; | |
941 | ||
942 | denali->page = page; | |
943 | ||
5bac3acf | 944 | if (denali_send_pipeline_cmd(denali, false, false, SPARE_ACCESS, |
345b1d3b | 945 | DENALI_WRITE) == PASS) { |
ce082596 JR |
946 | write_data_to_flash_mem(denali, buf, mtd->oobsize); |
947 | ||
948 | #if DEBUG_DENALI | |
949 | spin_lock_irq(&denali->irq_lock); | |
bdca6dae CD |
950 | denali->irq_debug_array[denali->idx++] = |
951 | 0x80000000 | mtd->oobsize; | |
ce082596 JR |
952 | denali->idx %= 32; |
953 | spin_unlock_irq(&denali->irq_lock); | |
954 | #endif | |
955 | ||
5bac3acf | 956 | |
ce082596 JR |
957 | /* wait for operation to complete */ |
958 | irq_status = wait_for_irq(denali, irq_mask); | |
959 | ||
345b1d3b | 960 | if (irq_status == 0) { |
ce082596 JR |
961 | printk(KERN_ERR "OOB write failed\n"); |
962 | status = -EIO; | |
963 | } | |
345b1d3b | 964 | } else { |
ce082596 | 965 | printk(KERN_ERR "unable to send pipeline command\n"); |
5bac3acf | 966 | status = -EIO; |
ce082596 JR |
967 | } |
968 | return status; | |
969 | } | |
970 | ||
971 | /* reads OOB data from the device */ | |
972 | static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) | |
973 | { | |
974 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
bdca6dae CD |
975 | uint32_t irq_mask = INTR_STATUS0__LOAD_COMP, |
976 | irq_status = 0, addr = 0x0, cmd = 0x0; | |
ce082596 JR |
977 | |
978 | denali->page = page; | |
979 | ||
980 | #if DEBUG_DENALI | |
bf1806dd | 981 | printk(KERN_INFO "read_oob %d\n", page); |
ce082596 | 982 | #endif |
5bac3acf | 983 | if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS, |
345b1d3b | 984 | DENALI_READ) == PASS) { |
5bac3acf | 985 | read_data_from_flash_mem(denali, buf, mtd->oobsize); |
ce082596 | 986 | |
5bac3acf | 987 | /* wait for command to be accepted |
ce082596 JR |
988 | * can always use status0 bit as the mask is identical for each |
989 | * bank. */ | |
990 | irq_status = wait_for_irq(denali, irq_mask); | |
991 | ||
992 | if (irq_status == 0) | |
bdca6dae CD |
993 | printk(KERN_ERR "page on OOB timeout %d\n", |
994 | denali->page); | |
ce082596 JR |
995 | |
996 | /* We set the device back to MAIN_ACCESS here as I observed | |
997 | * instability with the controller if you do a block erase | |
998 | * and the last transaction was a SPARE_ACCESS. Block erase | |
999 | * is reliable (according to the MTD test infrastructure) | |
5bac3acf | 1000 | * if you are in MAIN_ACCESS. |
ce082596 JR |
1001 | */ |
1002 | addr = BANK(denali->flash_bank) | denali->page; | |
5bac3acf | 1003 | cmd = MODE_10 | addr; |
ce082596 JR |
1004 | index_addr(denali, (uint32_t)cmd, MAIN_ACCESS); |
1005 | ||
1006 | #if DEBUG_DENALI | |
1007 | spin_lock_irq(&denali->irq_lock); | |
bdca6dae CD |
1008 | denali->irq_debug_array[denali->idx++] = |
1009 | 0x60000000 | mtd->oobsize; | |
ce082596 JR |
1010 | denali->idx %= 32; |
1011 | spin_unlock_irq(&denali->irq_lock); | |
1012 | #endif | |
1013 | } | |
1014 | } | |
1015 | ||
5bac3acf | 1016 | /* this function examines buffers to see if they contain data that |
ce082596 JR |
1017 | * indicate that the buffer is part of an erased region of flash. |
1018 | */ | |
1019 | bool is_erased(uint8_t *buf, int len) | |
1020 | { | |
1021 | int i = 0; | |
1022 | for (i = 0; i < len; i++) | |
ce082596 | 1023 | if (buf[i] != 0xFF) |
ce082596 | 1024 | return false; |
ce082596 JR |
1025 | return true; |
1026 | } | |
1027 | #define ECC_SECTOR_SIZE 512 | |
1028 | ||
1029 | #define ECC_SECTOR(x) (((x) & ECC_ERROR_ADDRESS__SECTOR_NR) >> 12) | |
1030 | #define ECC_BYTE(x) (((x) & ECC_ERROR_ADDRESS__OFFSET)) | |
1031 | #define ECC_CORRECTION_VALUE(x) ((x) & ERR_CORRECTION_INFO__BYTEMASK) | |
1032 | #define ECC_ERROR_CORRECTABLE(x) (!((x) & ERR_CORRECTION_INFO)) | |
1033 | #define ECC_ERR_DEVICE(x) ((x) & ERR_CORRECTION_INFO__DEVICE_NR >> 8) | |
1034 | #define ECC_LAST_ERR(x) ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO) | |
1035 | ||
5bac3acf | 1036 | static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf, |
ce082596 JR |
1037 | uint8_t *oobbuf, uint32_t irq_status) |
1038 | { | |
1039 | bool check_erased_page = false; | |
1040 | ||
345b1d3b | 1041 | if (irq_status & INTR_STATUS0__ECC_ERR) { |
ce082596 JR |
1042 | /* read the ECC errors. we'll ignore them for now */ |
1043 | uint32_t err_address = 0, err_correction_info = 0; | |
1044 | uint32_t err_byte = 0, err_sector = 0, err_device = 0; | |
1045 | uint32_t err_correction_value = 0; | |
1046 | ||
345b1d3b | 1047 | do { |
5bac3acf | 1048 | err_address = ioread32(denali->flash_reg + |
ce082596 JR |
1049 | ECC_ERROR_ADDRESS); |
1050 | err_sector = ECC_SECTOR(err_address); | |
1051 | err_byte = ECC_BYTE(err_address); | |
1052 | ||
1053 | ||
5bac3acf | 1054 | err_correction_info = ioread32(denali->flash_reg + |
ce082596 | 1055 | ERR_CORRECTION_INFO); |
5bac3acf | 1056 | err_correction_value = |
ce082596 JR |
1057 | ECC_CORRECTION_VALUE(err_correction_info); |
1058 | err_device = ECC_ERR_DEVICE(err_correction_info); | |
1059 | ||
345b1d3b | 1060 | if (ECC_ERROR_CORRECTABLE(err_correction_info)) { |
ce082596 | 1061 | /* offset in our buffer is computed as: |
5bac3acf | 1062 | sector number * sector size + offset in |
ce082596 JR |
1063 | sector |
1064 | */ | |
5bac3acf | 1065 | int offset = err_sector * ECC_SECTOR_SIZE + |
ce082596 | 1066 | err_byte; |
345b1d3b | 1067 | if (offset < denali->mtd.writesize) { |
ce082596 JR |
1068 | /* correct the ECC error */ |
1069 | buf[offset] ^= err_correction_value; | |
1070 | denali->mtd.ecc_stats.corrected++; | |
345b1d3b | 1071 | } else { |
ce082596 JR |
1072 | /* bummer, couldn't correct the error */ |
1073 | printk(KERN_ERR "ECC offset invalid\n"); | |
1074 | denali->mtd.ecc_stats.failed++; | |
1075 | } | |
345b1d3b | 1076 | } else { |
5bac3acf | 1077 | /* if the error is not correctable, need to |
bdca6dae CD |
1078 | * look at the page to see if it is an erased |
1079 | * page. if so, then it's not a real ECC error | |
1080 | * */ | |
ce082596 JR |
1081 | check_erased_page = true; |
1082 | } | |
1083 | ||
5bac3acf | 1084 | #if DEBUG_DENALI |
bdca6dae CD |
1085 | printk(KERN_INFO "Detected ECC error in page %d:" |
1086 | " err_addr = 0x%08x, info to fix is" | |
1087 | " 0x%08x\n", denali->page, err_address, | |
1088 | err_correction_info); | |
ce082596 JR |
1089 | #endif |
1090 | } while (!ECC_LAST_ERR(err_correction_info)); | |
1091 | } | |
1092 | return check_erased_page; | |
1093 | } | |
1094 | ||
1095 | /* programs the controller to either enable/disable DMA transfers */ | |
aadff49c | 1096 | static void denali_enable_dma(struct denali_nand_info *denali, bool en) |
ce082596 JR |
1097 | { |
1098 | uint32_t reg_val = 0x0; | |
1099 | ||
a99d1796 CD |
1100 | if (en) |
1101 | reg_val = DMA_ENABLE__FLAG; | |
ce082596 JR |
1102 | |
1103 | denali_write32(reg_val, denali->flash_reg + DMA_ENABLE); | |
1104 | ioread32(denali->flash_reg + DMA_ENABLE); | |
1105 | } | |
1106 | ||
1107 | /* setups the HW to perform the data DMA */ | |
aadff49c | 1108 | static void denali_setup_dma(struct denali_nand_info *denali, int op) |
ce082596 JR |
1109 | { |
1110 | uint32_t mode = 0x0; | |
1111 | const int page_count = 1; | |
1112 | dma_addr_t addr = denali->buf.dma_buf; | |
1113 | ||
1114 | mode = MODE_10 | BANK(denali->flash_bank); | |
1115 | ||
1116 | /* DMA is a four step process */ | |
1117 | ||
1118 | /* 1. setup transfer type and # of pages */ | |
1119 | index_addr(denali, mode | denali->page, 0x2000 | op | page_count); | |
1120 | ||
1121 | /* 2. set memory high address bits 23:8 */ | |
1122 | index_addr(denali, mode | ((uint16_t)(addr >> 16) << 8), 0x2200); | |
1123 | ||
1124 | /* 3. set memory low address bits 23:8 */ | |
1125 | index_addr(denali, mode | ((uint16_t)addr << 8), 0x2300); | |
1126 | ||
1127 | /* 4. interrupt when complete, burst len = 64 bytes*/ | |
1128 | index_addr(denali, mode | 0x14000, 0x2400); | |
1129 | } | |
1130 | ||
5bac3acf | 1131 | /* writes a page. user specifies type, and this function handles the |
ce082596 | 1132 | configuration details. */ |
5bac3acf | 1133 | static void write_page(struct mtd_info *mtd, struct nand_chip *chip, |
ce082596 JR |
1134 | const uint8_t *buf, bool raw_xfer) |
1135 | { | |
1136 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1137 | struct pci_dev *pci_dev = denali->dev; | |
1138 | ||
1139 | dma_addr_t addr = denali->buf.dma_buf; | |
1140 | size_t size = denali->mtd.writesize + denali->mtd.oobsize; | |
1141 | ||
1142 | uint32_t irq_status = 0; | |
5bac3acf | 1143 | uint32_t irq_mask = INTR_STATUS0__DMA_CMD_COMP | |
ce082596 JR |
1144 | INTR_STATUS0__PROGRAM_FAIL; |
1145 | ||
1146 | /* if it is a raw xfer, we want to disable ecc, and send | |
1147 | * the spare area. | |
1148 | * !raw_xfer - enable ecc | |
1149 | * raw_xfer - transfer spare | |
1150 | */ | |
1151 | setup_ecc_for_xfer(denali, !raw_xfer, raw_xfer); | |
1152 | ||
1153 | /* copy buffer into DMA buffer */ | |
1154 | memcpy(denali->buf.buf, buf, mtd->writesize); | |
1155 | ||
345b1d3b | 1156 | if (raw_xfer) { |
ce082596 | 1157 | /* transfer the data to the spare area */ |
5bac3acf C |
1158 | memcpy(denali->buf.buf + mtd->writesize, |
1159 | chip->oob_poi, | |
1160 | mtd->oobsize); | |
ce082596 JR |
1161 | } |
1162 | ||
1163 | pci_dma_sync_single_for_device(pci_dev, addr, size, PCI_DMA_TODEVICE); | |
1164 | ||
1165 | clear_interrupts(denali); | |
5bac3acf | 1166 | denali_enable_dma(denali, true); |
ce082596 | 1167 | |
aadff49c | 1168 | denali_setup_dma(denali, DENALI_WRITE); |
ce082596 JR |
1169 | |
1170 | /* wait for operation to complete */ | |
1171 | irq_status = wait_for_irq(denali, irq_mask); | |
1172 | ||
345b1d3b | 1173 | if (irq_status == 0) { |
bdca6dae CD |
1174 | printk(KERN_ERR "timeout on write_page" |
1175 | " (type = %d)\n", raw_xfer); | |
5bac3acf | 1176 | denali->status = |
bdca6dae CD |
1177 | (irq_status & INTR_STATUS0__PROGRAM_FAIL) ? |
1178 | NAND_STATUS_FAIL : PASS; | |
ce082596 JR |
1179 | } |
1180 | ||
5bac3acf | 1181 | denali_enable_dma(denali, false); |
ce082596 JR |
1182 | pci_dma_sync_single_for_cpu(pci_dev, addr, size, PCI_DMA_TODEVICE); |
1183 | } | |
1184 | ||
1185 | /* NAND core entry points */ | |
1186 | ||
5bac3acf C |
1187 | /* this is the callback that the NAND core calls to write a page. Since |
1188 | writing a page with ECC or without is similar, all the work is done | |
ce082596 | 1189 | by write_page above. */ |
5bac3acf | 1190 | static void denali_write_page(struct mtd_info *mtd, struct nand_chip *chip, |
ce082596 JR |
1191 | const uint8_t *buf) |
1192 | { | |
1193 | /* for regular page writes, we let HW handle all the ECC | |
5bac3acf | 1194 | * data written to the device. */ |
ce082596 JR |
1195 | write_page(mtd, chip, buf, false); |
1196 | } | |
1197 | ||
5bac3acf | 1198 | /* This is the callback that the NAND core calls to write a page without ECC. |
ce082596 | 1199 | raw access is similiar to ECC page writes, so all the work is done in the |
5bac3acf | 1200 | write_page() function above. |
ce082596 | 1201 | */ |
5bac3acf | 1202 | static void denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
ce082596 JR |
1203 | const uint8_t *buf) |
1204 | { | |
5bac3acf | 1205 | /* for raw page writes, we want to disable ECC and simply write |
ce082596 JR |
1206 | whatever data is in the buffer. */ |
1207 | write_page(mtd, chip, buf, true); | |
1208 | } | |
1209 | ||
5bac3acf | 1210 | static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip, |
ce082596 JR |
1211 | int page) |
1212 | { | |
5bac3acf | 1213 | return write_oob_data(mtd, chip->oob_poi, page); |
ce082596 JR |
1214 | } |
1215 | ||
5bac3acf | 1216 | static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip, |
ce082596 JR |
1217 | int page, int sndcmd) |
1218 | { | |
1219 | read_oob_data(mtd, chip->oob_poi, page); | |
1220 | ||
5bac3acf C |
1221 | return 0; /* notify NAND core to send command to |
1222 | NAND device. */ | |
ce082596 JR |
1223 | } |
1224 | ||
1225 | static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip, | |
1226 | uint8_t *buf, int page) | |
1227 | { | |
1228 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1229 | struct pci_dev *pci_dev = denali->dev; | |
1230 | ||
1231 | dma_addr_t addr = denali->buf.dma_buf; | |
1232 | size_t size = denali->mtd.writesize + denali->mtd.oobsize; | |
1233 | ||
1234 | uint32_t irq_status = 0; | |
5bac3acf | 1235 | uint32_t irq_mask = INTR_STATUS0__ECC_TRANSACTION_DONE | |
ce082596 JR |
1236 | INTR_STATUS0__ECC_ERR; |
1237 | bool check_erased_page = false; | |
1238 | ||
1239 | setup_ecc_for_xfer(denali, true, false); | |
1240 | ||
aadff49c | 1241 | denali_enable_dma(denali, true); |
ce082596 JR |
1242 | pci_dma_sync_single_for_device(pci_dev, addr, size, PCI_DMA_FROMDEVICE); |
1243 | ||
1244 | clear_interrupts(denali); | |
aadff49c | 1245 | denali_setup_dma(denali, DENALI_READ); |
ce082596 JR |
1246 | |
1247 | /* wait for operation to complete */ | |
1248 | irq_status = wait_for_irq(denali, irq_mask); | |
1249 | ||
1250 | pci_dma_sync_single_for_cpu(pci_dev, addr, size, PCI_DMA_FROMDEVICE); | |
1251 | ||
1252 | memcpy(buf, denali->buf.buf, mtd->writesize); | |
5bac3acf | 1253 | |
ce082596 | 1254 | check_erased_page = handle_ecc(denali, buf, chip->oob_poi, irq_status); |
aadff49c | 1255 | denali_enable_dma(denali, false); |
ce082596 | 1256 | |
345b1d3b | 1257 | if (check_erased_page) { |
ce082596 JR |
1258 | read_oob_data(&denali->mtd, chip->oob_poi, denali->page); |
1259 | ||
1260 | /* check ECC failures that may have occurred on erased pages */ | |
345b1d3b | 1261 | if (check_erased_page) { |
ce082596 | 1262 | if (!is_erased(buf, denali->mtd.writesize)) |
ce082596 | 1263 | denali->mtd.ecc_stats.failed++; |
ce082596 | 1264 | if (!is_erased(buf, denali->mtd.oobsize)) |
ce082596 | 1265 | denali->mtd.ecc_stats.failed++; |
5bac3acf | 1266 | } |
ce082596 JR |
1267 | } |
1268 | return 0; | |
1269 | } | |
1270 | ||
1271 | static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
1272 | uint8_t *buf, int page) | |
1273 | { | |
1274 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1275 | struct pci_dev *pci_dev = denali->dev; | |
1276 | ||
1277 | dma_addr_t addr = denali->buf.dma_buf; | |
1278 | size_t size = denali->mtd.writesize + denali->mtd.oobsize; | |
1279 | ||
1280 | uint32_t irq_status = 0; | |
1281 | uint32_t irq_mask = INTR_STATUS0__DMA_CMD_COMP; | |
5bac3acf | 1282 | |
ce082596 | 1283 | setup_ecc_for_xfer(denali, false, true); |
aadff49c | 1284 | denali_enable_dma(denali, true); |
ce082596 JR |
1285 | |
1286 | pci_dma_sync_single_for_device(pci_dev, addr, size, PCI_DMA_FROMDEVICE); | |
1287 | ||
1288 | clear_interrupts(denali); | |
aadff49c | 1289 | denali_setup_dma(denali, DENALI_READ); |
ce082596 JR |
1290 | |
1291 | /* wait for operation to complete */ | |
1292 | irq_status = wait_for_irq(denali, irq_mask); | |
1293 | ||
1294 | pci_dma_sync_single_for_cpu(pci_dev, addr, size, PCI_DMA_FROMDEVICE); | |
1295 | ||
aadff49c | 1296 | denali_enable_dma(denali, false); |
ce082596 JR |
1297 | |
1298 | memcpy(buf, denali->buf.buf, mtd->writesize); | |
1299 | memcpy(chip->oob_poi, denali->buf.buf + mtd->writesize, mtd->oobsize); | |
1300 | ||
1301 | return 0; | |
1302 | } | |
1303 | ||
1304 | static uint8_t denali_read_byte(struct mtd_info *mtd) | |
1305 | { | |
1306 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1307 | uint8_t result = 0xff; | |
1308 | ||
1309 | if (denali->buf.head < denali->buf.tail) | |
ce082596 | 1310 | result = denali->buf.buf[denali->buf.head++]; |
ce082596 JR |
1311 | |
1312 | #if DEBUG_DENALI | |
bf1806dd | 1313 | printk(KERN_INFO "read byte -> 0x%02x\n", result); |
ce082596 JR |
1314 | #endif |
1315 | return result; | |
1316 | } | |
1317 | ||
1318 | static void denali_select_chip(struct mtd_info *mtd, int chip) | |
1319 | { | |
1320 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1321 | #if DEBUG_DENALI | |
bf1806dd | 1322 | printk(KERN_INFO "denali select chip %d\n", chip); |
ce082596 JR |
1323 | #endif |
1324 | spin_lock_irq(&denali->irq_lock); | |
1325 | denali->flash_bank = chip; | |
1326 | spin_unlock_irq(&denali->irq_lock); | |
1327 | } | |
1328 | ||
1329 | static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip) | |
1330 | { | |
1331 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1332 | int status = denali->status; | |
1333 | denali->status = 0; | |
1334 | ||
1335 | #if DEBUG_DENALI | |
bf1806dd | 1336 | printk(KERN_INFO "waitfunc %d\n", status); |
ce082596 JR |
1337 | #endif |
1338 | return status; | |
1339 | } | |
1340 | ||
1341 | static void denali_erase(struct mtd_info *mtd, int page) | |
1342 | { | |
1343 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1344 | ||
1345 | uint32_t cmd = 0x0, irq_status = 0; | |
1346 | ||
1347 | #if DEBUG_DENALI | |
bf1806dd | 1348 | printk(KERN_INFO "erase page: %d\n", page); |
ce082596 JR |
1349 | #endif |
1350 | /* clear interrupts */ | |
5bac3acf | 1351 | clear_interrupts(denali); |
ce082596 JR |
1352 | |
1353 | /* setup page read request for access type */ | |
1354 | cmd = MODE_10 | BANK(denali->flash_bank) | page; | |
1355 | index_addr(denali, (uint32_t)cmd, 0x1); | |
1356 | ||
1357 | /* wait for erase to complete or failure to occur */ | |
5bac3acf | 1358 | irq_status = wait_for_irq(denali, INTR_STATUS0__ERASE_COMP | |
ce082596 JR |
1359 | INTR_STATUS0__ERASE_FAIL); |
1360 | ||
bdca6dae CD |
1361 | denali->status = (irq_status & INTR_STATUS0__ERASE_FAIL) ? |
1362 | NAND_STATUS_FAIL : PASS; | |
ce082596 JR |
1363 | } |
1364 | ||
5bac3acf | 1365 | static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, |
ce082596 JR |
1366 | int page) |
1367 | { | |
1368 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
ef41e1bb CD |
1369 | uint32_t addr, id; |
1370 | int i; | |
ce082596 JR |
1371 | |
1372 | #if DEBUG_DENALI | |
bf1806dd | 1373 | printk(KERN_INFO "cmdfunc: 0x%x %d %d\n", cmd, col, page); |
ce082596 | 1374 | #endif |
345b1d3b | 1375 | switch (cmd) { |
a99d1796 CD |
1376 | case NAND_CMD_PAGEPROG: |
1377 | break; | |
1378 | case NAND_CMD_STATUS: | |
1379 | read_status(denali); | |
1380 | break; | |
1381 | case NAND_CMD_READID: | |
1382 | reset_buf(denali); | |
ef41e1bb CD |
1383 | /*sometimes ManufactureId read from register is not right |
1384 | * e.g. some of Micron MT29F32G08QAA MLC NAND chips | |
1385 | * So here we send READID cmd to NAND insteand | |
1386 | * */ | |
1387 | addr = (uint32_t)MODE_11 | BANK(denali->flash_bank); | |
1388 | index_addr(denali, (uint32_t)addr | 0, 0x90); | |
1389 | index_addr(denali, (uint32_t)addr | 1, 0); | |
1390 | for (i = 0; i < 5; i++) { | |
1391 | index_addr_read_data(denali, | |
1392 | (uint32_t)addr | 2, | |
1393 | &id); | |
1394 | write_byte_to_buf(denali, id); | |
a99d1796 CD |
1395 | } |
1396 | break; | |
1397 | case NAND_CMD_READ0: | |
1398 | case NAND_CMD_SEQIN: | |
1399 | denali->page = page; | |
1400 | break; | |
1401 | case NAND_CMD_RESET: | |
1402 | reset_bank(denali); | |
1403 | break; | |
1404 | case NAND_CMD_READOOB: | |
1405 | /* TODO: Read OOB data */ | |
1406 | break; | |
1407 | default: | |
1408 | printk(KERN_ERR ": unsupported command" | |
1409 | " received 0x%x\n", cmd); | |
1410 | break; | |
ce082596 JR |
1411 | } |
1412 | } | |
1413 | ||
1414 | /* stubs for ECC functions not used by the NAND core */ | |
5bac3acf | 1415 | static int denali_ecc_calculate(struct mtd_info *mtd, const uint8_t *data, |
ce082596 JR |
1416 | uint8_t *ecc_code) |
1417 | { | |
1418 | printk(KERN_ERR "denali_ecc_calculate called unexpectedly\n"); | |
1419 | BUG(); | |
1420 | return -EIO; | |
1421 | } | |
1422 | ||
5bac3acf | 1423 | static int denali_ecc_correct(struct mtd_info *mtd, uint8_t *data, |
ce082596 JR |
1424 | uint8_t *read_ecc, uint8_t *calc_ecc) |
1425 | { | |
1426 | printk(KERN_ERR "denali_ecc_correct called unexpectedly\n"); | |
1427 | BUG(); | |
1428 | return -EIO; | |
1429 | } | |
1430 | ||
1431 | static void denali_ecc_hwctl(struct mtd_info *mtd, int mode) | |
1432 | { | |
1433 | printk(KERN_ERR "denali_ecc_hwctl called unexpectedly\n"); | |
1434 | BUG(); | |
1435 | } | |
1436 | /* end NAND core entry points */ | |
1437 | ||
1438 | /* Initialization code to bring the device up to a known good state */ | |
1439 | static void denali_hw_init(struct denali_nand_info *denali) | |
1440 | { | |
db9a3210 CD |
1441 | /* tell driver how many bit controller will skip before |
1442 | * writing ECC code in OOB, this register may be already | |
1443 | * set by firmware. So we read this value out. | |
1444 | * if this value is 0, just let it be. | |
1445 | * */ | |
1446 | denali->bbtskipbytes = ioread32(denali->flash_reg + | |
1447 | SPARE_AREA_SKIP_BYTES); | |
ce082596 | 1448 | denali_irq_init(denali); |
eda936ef | 1449 | denali_nand_reset(denali); |
ce082596 | 1450 | denali_write32(0x0F, denali->flash_reg + RB_PIN_ENABLED); |
bdca6dae CD |
1451 | denali_write32(CHIP_EN_DONT_CARE__FLAG, |
1452 | denali->flash_reg + CHIP_ENABLE_DONT_CARE); | |
ce082596 JR |
1453 | |
1454 | denali_write32(0x0, denali->flash_reg + SPARE_AREA_SKIP_BYTES); | |
1455 | denali_write32(0xffff, denali->flash_reg + SPARE_AREA_MARKER); | |
1456 | ||
1457 | /* Should set value for these registers when init */ | |
1458 | denali_write32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES); | |
1459 | denali_write32(1, denali->flash_reg + ECC_ENABLE); | |
1460 | } | |
1461 | ||
db9a3210 CD |
1462 | /* Althogh controller spec said SLC ECC is forceb to be 4bit, |
1463 | * but denali controller in MRST only support 15bit and 8bit ECC | |
1464 | * correction | |
1465 | * */ | |
1466 | #define ECC_8BITS 14 | |
1467 | static struct nand_ecclayout nand_8bit_oob = { | |
1468 | .eccbytes = 14, | |
ce082596 JR |
1469 | }; |
1470 | ||
db9a3210 CD |
1471 | #define ECC_15BITS 26 |
1472 | static struct nand_ecclayout nand_15bit_oob = { | |
1473 | .eccbytes = 26, | |
ce082596 JR |
1474 | }; |
1475 | ||
1476 | static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' }; | |
1477 | static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' }; | |
1478 | ||
1479 | static struct nand_bbt_descr bbt_main_descr = { | |
1480 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
1481 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
1482 | .offs = 8, | |
1483 | .len = 4, | |
1484 | .veroffs = 12, | |
1485 | .maxblocks = 4, | |
1486 | .pattern = bbt_pattern, | |
1487 | }; | |
1488 | ||
1489 | static struct nand_bbt_descr bbt_mirror_descr = { | |
1490 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
1491 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
1492 | .offs = 8, | |
1493 | .len = 4, | |
1494 | .veroffs = 12, | |
1495 | .maxblocks = 4, | |
1496 | .pattern = mirror_pattern, | |
1497 | }; | |
1498 | ||
1499 | /* initalize driver data structures */ | |
1500 | void denali_drv_init(struct denali_nand_info *denali) | |
1501 | { | |
1502 | denali->idx = 0; | |
1503 | ||
1504 | /* setup interrupt handler */ | |
5bac3acf | 1505 | /* the completion object will be used to notify |
ce082596 JR |
1506 | * the callee that the interrupt is done */ |
1507 | init_completion(&denali->complete); | |
1508 | ||
1509 | /* the spinlock will be used to synchronize the ISR | |
5bac3acf | 1510 | * with any element that might be access shared |
ce082596 JR |
1511 | * data (interrupt status) */ |
1512 | spin_lock_init(&denali->irq_lock); | |
1513 | ||
1514 | /* indicate that MTD has not selected a valid bank yet */ | |
1515 | denali->flash_bank = CHIP_SELECT_INVALID; | |
1516 | ||
1517 | /* initialize our irq_status variable to indicate no interrupts */ | |
1518 | denali->irq_status = 0; | |
1519 | } | |
1520 | ||
1521 | /* driver entry point */ | |
1522 | static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) | |
1523 | { | |
1524 | int ret = -ENODEV; | |
1525 | resource_size_t csr_base, mem_base; | |
1526 | unsigned long csr_len, mem_len; | |
1527 | struct denali_nand_info *denali; | |
1528 | ||
1529 | nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n", | |
1530 | __FILE__, __LINE__, __func__); | |
1531 | ||
1532 | denali = kzalloc(sizeof(*denali), GFP_KERNEL); | |
1533 | if (!denali) | |
1534 | return -ENOMEM; | |
1535 | ||
1536 | ret = pci_enable_device(dev); | |
1537 | if (ret) { | |
1538 | printk(KERN_ERR "Spectra: pci_enable_device failed.\n"); | |
1539 | goto failed_enable; | |
1540 | } | |
1541 | ||
1542 | if (id->driver_data == INTEL_CE4100) { | |
5bac3acf C |
1543 | /* Due to a silicon limitation, we can only support |
1544 | * ONFI timing mode 1 and below. | |
1545 | */ | |
345b1d3b | 1546 | if (onfi_timing_mode < -1 || onfi_timing_mode > 1) { |
bdca6dae CD |
1547 | printk(KERN_ERR "Intel CE4100 only supports" |
1548 | " ONFI timing mode 1 or below\n"); | |
ce082596 JR |
1549 | ret = -EINVAL; |
1550 | goto failed_enable; | |
1551 | } | |
1552 | denali->platform = INTEL_CE4100; | |
1553 | mem_base = pci_resource_start(dev, 0); | |
1554 | mem_len = pci_resource_len(dev, 1); | |
1555 | csr_base = pci_resource_start(dev, 1); | |
1556 | csr_len = pci_resource_len(dev, 1); | |
1557 | } else { | |
1558 | denali->platform = INTEL_MRST; | |
1559 | csr_base = pci_resource_start(dev, 0); | |
1560 | csr_len = pci_resource_start(dev, 0); | |
1561 | mem_base = pci_resource_start(dev, 1); | |
1562 | mem_len = pci_resource_len(dev, 1); | |
1563 | if (!mem_len) { | |
1564 | mem_base = csr_base + csr_len; | |
1565 | mem_len = csr_len; | |
1566 | nand_dbg_print(NAND_DBG_WARN, | |
bdca6dae CD |
1567 | "Spectra: No second" |
1568 | " BAR for PCI device;" | |
1569 | " assuming %08Lx\n", | |
ce082596 JR |
1570 | (uint64_t)csr_base); |
1571 | } | |
1572 | } | |
1573 | ||
1574 | /* Is 32-bit DMA supported? */ | |
1575 | ret = pci_set_dma_mask(dev, DMA_BIT_MASK(32)); | |
1576 | ||
345b1d3b | 1577 | if (ret) { |
ce082596 JR |
1578 | printk(KERN_ERR "Spectra: no usable DMA configuration\n"); |
1579 | goto failed_enable; | |
1580 | } | |
bdca6dae CD |
1581 | denali->buf.dma_buf = |
1582 | pci_map_single(dev, denali->buf.buf, | |
1583 | DENALI_BUF_SIZE, | |
1584 | PCI_DMA_BIDIRECTIONAL); | |
ce082596 | 1585 | |
345b1d3b | 1586 | if (pci_dma_mapping_error(dev, denali->buf.dma_buf)) { |
ce082596 JR |
1587 | printk(KERN_ERR "Spectra: failed to map DMA buffer\n"); |
1588 | goto failed_enable; | |
1589 | } | |
1590 | ||
1591 | pci_set_master(dev); | |
1592 | denali->dev = dev; | |
1593 | ||
1594 | ret = pci_request_regions(dev, DENALI_NAND_NAME); | |
1595 | if (ret) { | |
1596 | printk(KERN_ERR "Spectra: Unable to request memory regions\n"); | |
1597 | goto failed_req_csr; | |
1598 | } | |
1599 | ||
1600 | denali->flash_reg = ioremap_nocache(csr_base, csr_len); | |
1601 | if (!denali->flash_reg) { | |
1602 | printk(KERN_ERR "Spectra: Unable to remap memory region\n"); | |
1603 | ret = -ENOMEM; | |
1604 | goto failed_remap_csr; | |
1605 | } | |
1606 | nand_dbg_print(NAND_DBG_DEBUG, "Spectra: CSR 0x%08Lx -> 0x%p (0x%lx)\n", | |
1607 | (uint64_t)csr_base, denali->flash_reg, csr_len); | |
1608 | ||
1609 | denali->flash_mem = ioremap_nocache(mem_base, mem_len); | |
1610 | if (!denali->flash_mem) { | |
1611 | printk(KERN_ERR "Spectra: ioremap_nocache failed!"); | |
1612 | iounmap(denali->flash_reg); | |
1613 | ret = -ENOMEM; | |
1614 | goto failed_remap_csr; | |
1615 | } | |
1616 | ||
1617 | nand_dbg_print(NAND_DBG_WARN, | |
1618 | "Spectra: Remapped flash base address: " | |
1619 | "0x%p, len: %ld\n", | |
1620 | denali->flash_mem, csr_len); | |
1621 | ||
1622 | denali_hw_init(denali); | |
1623 | denali_drv_init(denali); | |
1624 | ||
1625 | nand_dbg_print(NAND_DBG_DEBUG, "Spectra: IRQ %d\n", dev->irq); | |
1626 | if (request_irq(dev->irq, denali_isr, IRQF_SHARED, | |
1627 | DENALI_NAND_NAME, denali)) { | |
1628 | printk(KERN_ERR "Spectra: Unable to allocate IRQ\n"); | |
1629 | ret = -ENODEV; | |
1630 | goto failed_request_irq; | |
1631 | } | |
1632 | ||
1633 | /* now that our ISR is registered, we can enable interrupts */ | |
eda936ef | 1634 | denali_set_intr_modes(denali, true); |
ce082596 JR |
1635 | |
1636 | pci_set_drvdata(dev, denali); | |
1637 | ||
eda936ef | 1638 | denali_nand_timing_set(denali); |
ce082596 | 1639 | |
ce082596 JR |
1640 | nand_dbg_print(NAND_DBG_DEBUG, "Dump timing register values:" |
1641 | "acc_clks: %d, re_2_we: %d, we_2_re: %d," | |
1642 | "addr_2_data: %d, rdwr_en_lo_cnt: %d, " | |
1643 | "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n", | |
1644 | ioread32(denali->flash_reg + ACC_CLKS), | |
1645 | ioread32(denali->flash_reg + RE_2_WE), | |
1646 | ioread32(denali->flash_reg + WE_2_RE), | |
1647 | ioread32(denali->flash_reg + ADDR_2_DATA), | |
1648 | ioread32(denali->flash_reg + RDWR_EN_LO_CNT), | |
1649 | ioread32(denali->flash_reg + RDWR_EN_HI_CNT), | |
1650 | ioread32(denali->flash_reg + CS_SETUP_CNT)); | |
1651 | ||
1652 | denali->mtd.name = "Denali NAND"; | |
1653 | denali->mtd.owner = THIS_MODULE; | |
1654 | denali->mtd.priv = &denali->nand; | |
1655 | ||
1656 | /* register the driver with the NAND core subsystem */ | |
1657 | denali->nand.select_chip = denali_select_chip; | |
1658 | denali->nand.cmdfunc = denali_cmdfunc; | |
1659 | denali->nand.read_byte = denali_read_byte; | |
1660 | denali->nand.waitfunc = denali_waitfunc; | |
1661 | ||
5bac3acf | 1662 | /* scan for NAND devices attached to the controller |
ce082596 | 1663 | * this is the first stage in a two step process to register |
5bac3acf | 1664 | * with the nand subsystem */ |
345b1d3b | 1665 | if (nand_scan_ident(&denali->mtd, LLD_MAX_FLASH_BANKS, NULL)) { |
ce082596 JR |
1666 | ret = -ENXIO; |
1667 | goto failed_nand; | |
1668 | } | |
5bac3acf | 1669 | |
66406524 CD |
1670 | /* MTD supported page sizes vary by kernel. We validate our |
1671 | * kernel supports the device here. | |
1672 | */ | |
1673 | if (denali->mtd.writesize > NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE) { | |
1674 | ret = -ENODEV; | |
1675 | printk(KERN_ERR "Spectra: device size not supported by this " | |
1676 | "version of MTD."); | |
1677 | goto failed_nand; | |
1678 | } | |
1679 | ||
08b9ab99 CD |
1680 | /* support for multi nand |
1681 | * MTD known nothing about multi nand, | |
1682 | * so we should tell it the real pagesize | |
1683 | * and anything necessery | |
1684 | */ | |
1685 | denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED); | |
1686 | denali->nand.chipsize <<= (denali->devnum - 1); | |
1687 | denali->nand.page_shift += (denali->devnum - 1); | |
1688 | denali->nand.pagemask = (denali->nand.chipsize >> | |
1689 | denali->nand.page_shift) - 1; | |
1690 | denali->nand.bbt_erase_shift += (denali->devnum - 1); | |
1691 | denali->nand.phys_erase_shift = denali->nand.bbt_erase_shift; | |
1692 | denali->nand.chip_shift += (denali->devnum - 1); | |
1693 | denali->mtd.writesize <<= (denali->devnum - 1); | |
1694 | denali->mtd.oobsize <<= (denali->devnum - 1); | |
1695 | denali->mtd.erasesize <<= (denali->devnum - 1); | |
1696 | denali->mtd.size = denali->nand.numchips * denali->nand.chipsize; | |
1697 | denali->bbtskipbytes *= denali->devnum; | |
1698 | ||
5bac3acf C |
1699 | /* second stage of the NAND scan |
1700 | * this stage requires information regarding ECC and | |
1701 | * bad block management. */ | |
ce082596 JR |
1702 | |
1703 | /* Bad block management */ | |
1704 | denali->nand.bbt_td = &bbt_main_descr; | |
1705 | denali->nand.bbt_md = &bbt_mirror_descr; | |
1706 | ||
1707 | /* skip the scan for now until we have OOB read and write support */ | |
1708 | denali->nand.options |= NAND_USE_FLASH_BBT | NAND_SKIP_BBTSCAN; | |
1709 | denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME; | |
1710 | ||
db9a3210 CD |
1711 | /* Denali Controller only support 15bit and 8bit ECC in MRST, |
1712 | * so just let controller do 15bit ECC for MLC and 8bit ECC for | |
1713 | * SLC if possible. | |
1714 | * */ | |
1715 | if (denali->nand.cellinfo & 0xc && | |
1716 | (denali->mtd.oobsize > (denali->bbtskipbytes + | |
1717 | ECC_15BITS * (denali->mtd.writesize / | |
1718 | ECC_SECTOR_SIZE)))) { | |
1719 | /* if MLC OOB size is large enough, use 15bit ECC*/ | |
1720 | denali->nand.ecc.layout = &nand_15bit_oob; | |
1721 | denali->nand.ecc.bytes = ECC_15BITS; | |
1722 | denali_write32(15, denali->flash_reg + ECC_CORRECTION); | |
1723 | } else if (denali->mtd.oobsize < (denali->bbtskipbytes + | |
1724 | ECC_8BITS * (denali->mtd.writesize / | |
1725 | ECC_SECTOR_SIZE))) { | |
1726 | printk(KERN_ERR "Your NAND chip OOB is not large enough to" | |
1727 | " contain 8bit ECC correction codes"); | |
1728 | goto failed_nand; | |
1729 | } else { | |
1730 | denali->nand.ecc.layout = &nand_8bit_oob; | |
1731 | denali->nand.ecc.bytes = ECC_8BITS; | |
1732 | denali_write32(8, denali->flash_reg + ECC_CORRECTION); | |
ce082596 JR |
1733 | } |
1734 | ||
08b9ab99 | 1735 | denali->nand.ecc.bytes *= denali->devnum; |
db9a3210 CD |
1736 | denali->nand.ecc.layout->eccbytes *= |
1737 | denali->mtd.writesize / ECC_SECTOR_SIZE; | |
1738 | denali->nand.ecc.layout->oobfree[0].offset = | |
1739 | denali->bbtskipbytes + denali->nand.ecc.layout->eccbytes; | |
1740 | denali->nand.ecc.layout->oobfree[0].length = | |
1741 | denali->mtd.oobsize - denali->nand.ecc.layout->eccbytes - | |
1742 | denali->bbtskipbytes; | |
1743 | ||
66406524 CD |
1744 | /* Let driver know the total blocks number and |
1745 | * how many blocks contained by each nand chip. | |
1746 | * blksperchip will help driver to know how many | |
1747 | * blocks is taken by FW. | |
1748 | * */ | |
1749 | denali->totalblks = denali->mtd.size >> | |
1750 | denali->nand.phys_erase_shift; | |
1751 | denali->blksperchip = denali->totalblks / denali->nand.numchips; | |
1752 | ||
5bac3acf C |
1753 | /* These functions are required by the NAND core framework, otherwise, |
1754 | * the NAND core will assert. However, we don't need them, so we'll stub | |
1755 | * them out. */ | |
ce082596 JR |
1756 | denali->nand.ecc.calculate = denali_ecc_calculate; |
1757 | denali->nand.ecc.correct = denali_ecc_correct; | |
1758 | denali->nand.ecc.hwctl = denali_ecc_hwctl; | |
1759 | ||
1760 | /* override the default read operations */ | |
08b9ab99 | 1761 | denali->nand.ecc.size = ECC_SECTOR_SIZE * denali->devnum; |
ce082596 JR |
1762 | denali->nand.ecc.read_page = denali_read_page; |
1763 | denali->nand.ecc.read_page_raw = denali_read_page_raw; | |
1764 | denali->nand.ecc.write_page = denali_write_page; | |
1765 | denali->nand.ecc.write_page_raw = denali_write_page_raw; | |
1766 | denali->nand.ecc.read_oob = denali_read_oob; | |
1767 | denali->nand.ecc.write_oob = denali_write_oob; | |
1768 | denali->nand.erase_cmd = denali_erase; | |
1769 | ||
345b1d3b | 1770 | if (nand_scan_tail(&denali->mtd)) { |
ce082596 JR |
1771 | ret = -ENXIO; |
1772 | goto failed_nand; | |
1773 | } | |
1774 | ||
1775 | ret = add_mtd_device(&denali->mtd); | |
1776 | if (ret) { | |
bdca6dae CD |
1777 | printk(KERN_ERR "Spectra: Failed to register" |
1778 | " MTD device: %d\n", ret); | |
ce082596 JR |
1779 | goto failed_nand; |
1780 | } | |
1781 | return 0; | |
1782 | ||
1783 | failed_nand: | |
1784 | denali_irq_cleanup(dev->irq, denali); | |
1785 | failed_request_irq: | |
1786 | iounmap(denali->flash_reg); | |
1787 | iounmap(denali->flash_mem); | |
1788 | failed_remap_csr: | |
1789 | pci_release_regions(dev); | |
1790 | failed_req_csr: | |
5bac3acf | 1791 | pci_unmap_single(dev, denali->buf.dma_buf, DENALI_BUF_SIZE, |
ce082596 JR |
1792 | PCI_DMA_BIDIRECTIONAL); |
1793 | failed_enable: | |
1794 | kfree(denali); | |
1795 | return ret; | |
1796 | } | |
1797 | ||
1798 | /* driver exit point */ | |
1799 | static void denali_pci_remove(struct pci_dev *dev) | |
1800 | { | |
1801 | struct denali_nand_info *denali = pci_get_drvdata(dev); | |
1802 | ||
1803 | nand_dbg_print(NAND_DBG_WARN, "%s, Line %d, Function: %s\n", | |
1804 | __FILE__, __LINE__, __func__); | |
1805 | ||
1806 | nand_release(&denali->mtd); | |
1807 | del_mtd_device(&denali->mtd); | |
1808 | ||
1809 | denali_irq_cleanup(dev->irq, denali); | |
1810 | ||
1811 | iounmap(denali->flash_reg); | |
1812 | iounmap(denali->flash_mem); | |
1813 | pci_release_regions(dev); | |
1814 | pci_disable_device(dev); | |
5bac3acf | 1815 | pci_unmap_single(dev, denali->buf.dma_buf, DENALI_BUF_SIZE, |
ce082596 JR |
1816 | PCI_DMA_BIDIRECTIONAL); |
1817 | pci_set_drvdata(dev, NULL); | |
1818 | kfree(denali); | |
1819 | } | |
1820 | ||
1821 | MODULE_DEVICE_TABLE(pci, denali_pci_ids); | |
1822 | ||
1823 | static struct pci_driver denali_pci_driver = { | |
1824 | .name = DENALI_NAND_NAME, | |
1825 | .id_table = denali_pci_ids, | |
1826 | .probe = denali_pci_probe, | |
1827 | .remove = denali_pci_remove, | |
1828 | }; | |
1829 | ||
1830 | static int __devinit denali_init(void) | |
1831 | { | |
bdca6dae CD |
1832 | printk(KERN_INFO "Spectra MTD driver built on %s @ %s\n", |
1833 | __DATE__, __TIME__); | |
ce082596 JR |
1834 | return pci_register_driver(&denali_pci_driver); |
1835 | } | |
1836 | ||
1837 | /* Free memory */ | |
1838 | static void __devexit denali_exit(void) | |
1839 | { | |
1840 | pci_unregister_driver(&denali_pci_driver); | |
1841 | } | |
1842 | ||
1843 | module_init(denali_init); | |
1844 | module_exit(denali_exit); |