Commit | Line | Data |
---|---|---|
ce082596 JR |
1 | /* |
2 | * NAND Flash Controller Device Driver | |
3 | * Copyright © 2009-2010, Intel Corporation and its suppliers. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | * | |
18 | */ | |
ce082596 JR |
19 | #include <linux/interrupt.h> |
20 | #include <linux/delay.h> | |
84457949 | 21 | #include <linux/dma-mapping.h> |
ce082596 JR |
22 | #include <linux/wait.h> |
23 | #include <linux/mutex.h> | |
b8664b37 | 24 | #include <linux/slab.h> |
ce082596 JR |
25 | #include <linux/mtd/mtd.h> |
26 | #include <linux/module.h> | |
27 | ||
28 | #include "denali.h" | |
29 | ||
30 | MODULE_LICENSE("GPL"); | |
31 | ||
5bac3acf | 32 | /* We define a module parameter that allows the user to override |
ce082596 JR |
33 | * the hardware and decide what timing mode should be used. |
34 | */ | |
35 | #define NAND_DEFAULT_TIMINGS -1 | |
36 | ||
37 | static int onfi_timing_mode = NAND_DEFAULT_TIMINGS; | |
38 | module_param(onfi_timing_mode, int, S_IRUGO); | |
bdca6dae CD |
39 | MODULE_PARM_DESC(onfi_timing_mode, "Overrides default ONFI setting." |
40 | " -1 indicates use default timings"); | |
ce082596 JR |
41 | |
42 | #define DENALI_NAND_NAME "denali-nand" | |
43 | ||
44 | /* We define a macro here that combines all interrupts this driver uses into | |
45 | * a single constant value, for convenience. */ | |
9589bf5b JI |
46 | #define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \ |
47 | INTR_STATUS__ECC_TRANSACTION_DONE | \ | |
48 | INTR_STATUS__ECC_ERR | \ | |
49 | INTR_STATUS__PROGRAM_FAIL | \ | |
50 | INTR_STATUS__LOAD_COMP | \ | |
51 | INTR_STATUS__PROGRAM_COMP | \ | |
52 | INTR_STATUS__TIME_OUT | \ | |
53 | INTR_STATUS__ERASE_FAIL | \ | |
54 | INTR_STATUS__RST_COMP | \ | |
55 | INTR_STATUS__ERASE_COMP) | |
ce082596 | 56 | |
5bac3acf | 57 | /* indicates whether or not the internal value for the flash bank is |
b292c341 | 58 | * valid or not */ |
5bac3acf | 59 | #define CHIP_SELECT_INVALID -1 |
ce082596 JR |
60 | |
61 | #define SUPPORT_8BITECC 1 | |
62 | ||
5bac3acf | 63 | /* This macro divides two integers and rounds fractional values up |
ce082596 JR |
64 | * to the nearest integer value. */ |
65 | #define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y))) | |
66 | ||
67 | /* this macro allows us to convert from an MTD structure to our own | |
68 | * device context (denali) structure. | |
69 | */ | |
70 | #define mtd_to_denali(m) container_of(m, struct denali_nand_info, mtd) | |
71 | ||
72 | /* These constants are defined by the driver to enable common driver | |
b292c341 | 73 | * configuration options. */ |
ce082596 JR |
74 | #define SPARE_ACCESS 0x41 |
75 | #define MAIN_ACCESS 0x42 | |
76 | #define MAIN_SPARE_ACCESS 0x43 | |
77 | ||
78 | #define DENALI_READ 0 | |
79 | #define DENALI_WRITE 0x100 | |
80 | ||
81 | /* types of device accesses. We can issue commands and get status */ | |
82 | #define COMMAND_CYCLE 0 | |
83 | #define ADDR_CYCLE 1 | |
84 | #define STATUS_CYCLE 2 | |
85 | ||
5bac3acf | 86 | /* this is a helper macro that allows us to |
ce082596 JR |
87 | * format the bank into the proper bits for the controller */ |
88 | #define BANK(x) ((x) << 24) | |
89 | ||
ce082596 JR |
90 | /* forward declarations */ |
91 | static void clear_interrupts(struct denali_nand_info *denali); | |
bdca6dae CD |
92 | static uint32_t wait_for_irq(struct denali_nand_info *denali, |
93 | uint32_t irq_mask); | |
94 | static void denali_irq_enable(struct denali_nand_info *denali, | |
95 | uint32_t int_mask); | |
ce082596 JR |
96 | static uint32_t read_interrupt_status(struct denali_nand_info *denali); |
97 | ||
bdca6dae CD |
98 | /* Certain operations for the denali NAND controller use |
99 | * an indexed mode to read/write data. The operation is | |
100 | * performed by writing the address value of the command | |
101 | * to the device memory followed by the data. This function | |
102 | * abstracts this common operation. | |
ce082596 | 103 | */ |
bdca6dae CD |
104 | static void index_addr(struct denali_nand_info *denali, |
105 | uint32_t address, uint32_t data) | |
ce082596 | 106 | { |
24c3fa36 CD |
107 | iowrite32(address, denali->flash_mem); |
108 | iowrite32(data, denali->flash_mem + 0x10); | |
ce082596 JR |
109 | } |
110 | ||
111 | /* Perform an indexed read of the device */ | |
112 | static void index_addr_read_data(struct denali_nand_info *denali, | |
113 | uint32_t address, uint32_t *pdata) | |
114 | { | |
24c3fa36 | 115 | iowrite32(address, denali->flash_mem); |
ce082596 JR |
116 | *pdata = ioread32(denali->flash_mem + 0x10); |
117 | } | |
118 | ||
5bac3acf | 119 | /* We need to buffer some data for some of the NAND core routines. |
ce082596 JR |
120 | * The operations manage buffering that data. */ |
121 | static void reset_buf(struct denali_nand_info *denali) | |
122 | { | |
123 | denali->buf.head = denali->buf.tail = 0; | |
124 | } | |
125 | ||
126 | static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte) | |
127 | { | |
ce082596 JR |
128 | denali->buf.buf[denali->buf.tail++] = byte; |
129 | } | |
130 | ||
131 | /* reads the status of the device */ | |
132 | static void read_status(struct denali_nand_info *denali) | |
133 | { | |
134 | uint32_t cmd = 0x0; | |
135 | ||
136 | /* initialize the data buffer to store status */ | |
137 | reset_buf(denali); | |
138 | ||
f0bc0c77 CD |
139 | cmd = ioread32(denali->flash_reg + WRITE_PROTECT); |
140 | if (cmd) | |
141 | write_byte_to_buf(denali, NAND_STATUS_WP); | |
142 | else | |
143 | write_byte_to_buf(denali, 0); | |
ce082596 JR |
144 | } |
145 | ||
146 | /* resets a specific device connected to the core */ | |
147 | static void reset_bank(struct denali_nand_info *denali) | |
148 | { | |
149 | uint32_t irq_status = 0; | |
9589bf5b JI |
150 | uint32_t irq_mask = INTR_STATUS__RST_COMP | |
151 | INTR_STATUS__TIME_OUT; | |
ce082596 JR |
152 | |
153 | clear_interrupts(denali); | |
154 | ||
9589bf5b | 155 | iowrite32(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET); |
ce082596 JR |
156 | |
157 | irq_status = wait_for_irq(denali, irq_mask); | |
5bac3acf | 158 | |
9589bf5b | 159 | if (irq_status & INTR_STATUS__TIME_OUT) |
84457949 | 160 | dev_err(denali->dev, "reset bank failed.\n"); |
ce082596 JR |
161 | } |
162 | ||
163 | /* Reset the flash controller */ | |
eda936ef | 164 | static uint16_t denali_nand_reset(struct denali_nand_info *denali) |
ce082596 JR |
165 | { |
166 | uint32_t i; | |
167 | ||
84457949 | 168 | dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", |
ce082596 JR |
169 | __FILE__, __LINE__, __func__); |
170 | ||
c89eeda8 | 171 | for (i = 0 ; i < denali->max_banks; i++) |
9589bf5b JI |
172 | iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT, |
173 | denali->flash_reg + INTR_STATUS(i)); | |
ce082596 | 174 | |
c89eeda8 | 175 | for (i = 0 ; i < denali->max_banks; i++) { |
9589bf5b | 176 | iowrite32(1 << i, denali->flash_reg + DEVICE_RESET); |
bdca6dae | 177 | while (!(ioread32(denali->flash_reg + |
9589bf5b JI |
178 | INTR_STATUS(i)) & |
179 | (INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT))) | |
628bfd41 | 180 | cpu_relax(); |
9589bf5b JI |
181 | if (ioread32(denali->flash_reg + INTR_STATUS(i)) & |
182 | INTR_STATUS__TIME_OUT) | |
84457949 | 183 | dev_dbg(denali->dev, |
ce082596 JR |
184 | "NAND Reset operation timed out on bank %d\n", i); |
185 | } | |
186 | ||
c89eeda8 | 187 | for (i = 0; i < denali->max_banks; i++) |
9589bf5b JI |
188 | iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT, |
189 | denali->flash_reg + INTR_STATUS(i)); | |
ce082596 JR |
190 | |
191 | return PASS; | |
192 | } | |
193 | ||
bdca6dae CD |
194 | /* this routine calculates the ONFI timing values for a given mode and |
195 | * programs the clocking register accordingly. The mode is determined by | |
196 | * the get_onfi_nand_para routine. | |
ce082596 | 197 | */ |
eda936ef | 198 | static void nand_onfi_timing_set(struct denali_nand_info *denali, |
bdca6dae | 199 | uint16_t mode) |
ce082596 JR |
200 | { |
201 | uint16_t Trea[6] = {40, 30, 25, 20, 20, 16}; | |
202 | uint16_t Trp[6] = {50, 25, 17, 15, 12, 10}; | |
203 | uint16_t Treh[6] = {30, 15, 15, 10, 10, 7}; | |
204 | uint16_t Trc[6] = {100, 50, 35, 30, 25, 20}; | |
205 | uint16_t Trhoh[6] = {0, 15, 15, 15, 15, 15}; | |
206 | uint16_t Trloh[6] = {0, 0, 0, 0, 5, 5}; | |
207 | uint16_t Tcea[6] = {100, 45, 30, 25, 25, 25}; | |
208 | uint16_t Tadl[6] = {200, 100, 100, 100, 70, 70}; | |
209 | uint16_t Trhw[6] = {200, 100, 100, 100, 100, 100}; | |
210 | uint16_t Trhz[6] = {200, 100, 100, 100, 100, 100}; | |
211 | uint16_t Twhr[6] = {120, 80, 80, 60, 60, 60}; | |
212 | uint16_t Tcs[6] = {70, 35, 25, 25, 20, 15}; | |
213 | ||
214 | uint16_t TclsRising = 1; | |
215 | uint16_t data_invalid_rhoh, data_invalid_rloh, data_invalid; | |
216 | uint16_t dv_window = 0; | |
217 | uint16_t en_lo, en_hi; | |
218 | uint16_t acc_clks; | |
219 | uint16_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt; | |
220 | ||
84457949 | 221 | dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", |
ce082596 JR |
222 | __FILE__, __LINE__, __func__); |
223 | ||
224 | en_lo = CEIL_DIV(Trp[mode], CLK_X); | |
225 | en_hi = CEIL_DIV(Treh[mode], CLK_X); | |
226 | #if ONFI_BLOOM_TIME | |
227 | if ((en_hi * CLK_X) < (Treh[mode] + 2)) | |
228 | en_hi++; | |
229 | #endif | |
230 | ||
231 | if ((en_lo + en_hi) * CLK_X < Trc[mode]) | |
232 | en_lo += CEIL_DIV((Trc[mode] - (en_lo + en_hi) * CLK_X), CLK_X); | |
233 | ||
234 | if ((en_lo + en_hi) < CLK_MULTI) | |
235 | en_lo += CLK_MULTI - en_lo - en_hi; | |
236 | ||
237 | while (dv_window < 8) { | |
238 | data_invalid_rhoh = en_lo * CLK_X + Trhoh[mode]; | |
239 | ||
240 | data_invalid_rloh = (en_lo + en_hi) * CLK_X + Trloh[mode]; | |
241 | ||
242 | data_invalid = | |
243 | data_invalid_rhoh < | |
244 | data_invalid_rloh ? data_invalid_rhoh : data_invalid_rloh; | |
245 | ||
246 | dv_window = data_invalid - Trea[mode]; | |
247 | ||
248 | if (dv_window < 8) | |
249 | en_lo++; | |
250 | } | |
251 | ||
252 | acc_clks = CEIL_DIV(Trea[mode], CLK_X); | |
253 | ||
254 | while (((acc_clks * CLK_X) - Trea[mode]) < 3) | |
255 | acc_clks++; | |
256 | ||
257 | if ((data_invalid - acc_clks * CLK_X) < 2) | |
84457949 | 258 | dev_warn(denali->dev, "%s, Line %d: Warning!\n", |
ce082596 JR |
259 | __FILE__, __LINE__); |
260 | ||
261 | addr_2_data = CEIL_DIV(Tadl[mode], CLK_X); | |
262 | re_2_we = CEIL_DIV(Trhw[mode], CLK_X); | |
263 | re_2_re = CEIL_DIV(Trhz[mode], CLK_X); | |
264 | we_2_re = CEIL_DIV(Twhr[mode], CLK_X); | |
265 | cs_cnt = CEIL_DIV((Tcs[mode] - Trp[mode]), CLK_X); | |
266 | if (!TclsRising) | |
267 | cs_cnt = CEIL_DIV(Tcs[mode], CLK_X); | |
268 | if (cs_cnt == 0) | |
269 | cs_cnt = 1; | |
270 | ||
271 | if (Tcea[mode]) { | |
272 | while (((cs_cnt * CLK_X) + Trea[mode]) < Tcea[mode]) | |
273 | cs_cnt++; | |
274 | } | |
275 | ||
276 | #if MODE5_WORKAROUND | |
277 | if (mode == 5) | |
278 | acc_clks = 5; | |
279 | #endif | |
280 | ||
281 | /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */ | |
282 | if ((ioread32(denali->flash_reg + MANUFACTURER_ID) == 0) && | |
283 | (ioread32(denali->flash_reg + DEVICE_ID) == 0x88)) | |
284 | acc_clks = 6; | |
285 | ||
24c3fa36 CD |
286 | iowrite32(acc_clks, denali->flash_reg + ACC_CLKS); |
287 | iowrite32(re_2_we, denali->flash_reg + RE_2_WE); | |
288 | iowrite32(re_2_re, denali->flash_reg + RE_2_RE); | |
289 | iowrite32(we_2_re, denali->flash_reg + WE_2_RE); | |
290 | iowrite32(addr_2_data, denali->flash_reg + ADDR_2_DATA); | |
291 | iowrite32(en_lo, denali->flash_reg + RDWR_EN_LO_CNT); | |
292 | iowrite32(en_hi, denali->flash_reg + RDWR_EN_HI_CNT); | |
293 | iowrite32(cs_cnt, denali->flash_reg + CS_SETUP_CNT); | |
ce082596 JR |
294 | } |
295 | ||
ce082596 JR |
296 | /* queries the NAND device to see what ONFI modes it supports. */ |
297 | static uint16_t get_onfi_nand_para(struct denali_nand_info *denali) | |
298 | { | |
299 | int i; | |
4c03bbdf CD |
300 | /* we needn't to do a reset here because driver has already |
301 | * reset all the banks before | |
302 | * */ | |
ce082596 JR |
303 | if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) & |
304 | ONFI_TIMING_MODE__VALUE)) | |
305 | return FAIL; | |
306 | ||
307 | for (i = 5; i > 0; i--) { | |
bdca6dae CD |
308 | if (ioread32(denali->flash_reg + ONFI_TIMING_MODE) & |
309 | (0x01 << i)) | |
ce082596 JR |
310 | break; |
311 | } | |
312 | ||
eda936ef | 313 | nand_onfi_timing_set(denali, i); |
ce082596 JR |
314 | |
315 | /* By now, all the ONFI devices we know support the page cache */ | |
316 | /* rw feature. So here we enable the pipeline_rw_ahead feature */ | |
317 | /* iowrite32(1, denali->flash_reg + CACHE_WRITE_ENABLE); */ | |
318 | /* iowrite32(1, denali->flash_reg + CACHE_READ_ENABLE); */ | |
319 | ||
320 | return PASS; | |
321 | } | |
322 | ||
4c03bbdf CD |
323 | static void get_samsung_nand_para(struct denali_nand_info *denali, |
324 | uint8_t device_id) | |
ce082596 | 325 | { |
4c03bbdf | 326 | if (device_id == 0xd3) { /* Samsung K9WAG08U1A */ |
ce082596 | 327 | /* Set timing register values according to datasheet */ |
24c3fa36 CD |
328 | iowrite32(5, denali->flash_reg + ACC_CLKS); |
329 | iowrite32(20, denali->flash_reg + RE_2_WE); | |
330 | iowrite32(12, denali->flash_reg + WE_2_RE); | |
331 | iowrite32(14, denali->flash_reg + ADDR_2_DATA); | |
332 | iowrite32(3, denali->flash_reg + RDWR_EN_LO_CNT); | |
333 | iowrite32(2, denali->flash_reg + RDWR_EN_HI_CNT); | |
334 | iowrite32(2, denali->flash_reg + CS_SETUP_CNT); | |
ce082596 | 335 | } |
ce082596 JR |
336 | } |
337 | ||
338 | static void get_toshiba_nand_para(struct denali_nand_info *denali) | |
339 | { | |
ce082596 JR |
340 | uint32_t tmp; |
341 | ||
342 | /* Workaround to fix a controller bug which reports a wrong */ | |
343 | /* spare area size for some kind of Toshiba NAND device */ | |
344 | if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) && | |
345 | (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) { | |
24c3fa36 | 346 | iowrite32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); |
ce082596 JR |
347 | tmp = ioread32(denali->flash_reg + DEVICES_CONNECTED) * |
348 | ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE); | |
24c3fa36 | 349 | iowrite32(tmp, |
bdca6dae | 350 | denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); |
ce082596 | 351 | #if SUPPORT_15BITECC |
24c3fa36 | 352 | iowrite32(15, denali->flash_reg + ECC_CORRECTION); |
ce082596 | 353 | #elif SUPPORT_8BITECC |
24c3fa36 | 354 | iowrite32(8, denali->flash_reg + ECC_CORRECTION); |
ce082596 JR |
355 | #endif |
356 | } | |
ce082596 JR |
357 | } |
358 | ||
ef41e1bb CD |
359 | static void get_hynix_nand_para(struct denali_nand_info *denali, |
360 | uint8_t device_id) | |
ce082596 | 361 | { |
ce082596 JR |
362 | uint32_t main_size, spare_size; |
363 | ||
ef41e1bb | 364 | switch (device_id) { |
ce082596 JR |
365 | case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */ |
366 | case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */ | |
24c3fa36 CD |
367 | iowrite32(128, denali->flash_reg + PAGES_PER_BLOCK); |
368 | iowrite32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE); | |
369 | iowrite32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); | |
bdca6dae CD |
370 | main_size = 4096 * |
371 | ioread32(denali->flash_reg + DEVICES_CONNECTED); | |
372 | spare_size = 224 * | |
373 | ioread32(denali->flash_reg + DEVICES_CONNECTED); | |
24c3fa36 | 374 | iowrite32(main_size, |
bdca6dae | 375 | denali->flash_reg + LOGICAL_PAGE_DATA_SIZE); |
24c3fa36 | 376 | iowrite32(spare_size, |
bdca6dae | 377 | denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); |
24c3fa36 | 378 | iowrite32(0, denali->flash_reg + DEVICE_WIDTH); |
ce082596 | 379 | #if SUPPORT_15BITECC |
24c3fa36 | 380 | iowrite32(15, denali->flash_reg + ECC_CORRECTION); |
ce082596 | 381 | #elif SUPPORT_8BITECC |
24c3fa36 | 382 | iowrite32(8, denali->flash_reg + ECC_CORRECTION); |
ce082596 | 383 | #endif |
ce082596 JR |
384 | break; |
385 | default: | |
84457949 | 386 | dev_warn(denali->dev, |
ce082596 JR |
387 | "Spectra: Unknown Hynix NAND (Device ID: 0x%x)." |
388 | "Will use default parameter values instead.\n", | |
66406524 | 389 | device_id); |
ce082596 JR |
390 | } |
391 | } | |
392 | ||
393 | /* determines how many NAND chips are connected to the controller. Note for | |
b292c341 | 394 | * Intel CE4100 devices we don't support more than one device. |
ce082596 JR |
395 | */ |
396 | static void find_valid_banks(struct denali_nand_info *denali) | |
397 | { | |
c89eeda8 | 398 | uint32_t id[denali->max_banks]; |
ce082596 JR |
399 | int i; |
400 | ||
401 | denali->total_used_banks = 1; | |
c89eeda8 | 402 | for (i = 0; i < denali->max_banks; i++) { |
ce082596 JR |
403 | index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 0), 0x90); |
404 | index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 1), 0); | |
bdca6dae CD |
405 | index_addr_read_data(denali, |
406 | (uint32_t)(MODE_11 | (i << 24) | 2), &id[i]); | |
ce082596 | 407 | |
84457949 | 408 | dev_dbg(denali->dev, |
ce082596 JR |
409 | "Return 1st ID for bank[%d]: %x\n", i, id[i]); |
410 | ||
411 | if (i == 0) { | |
412 | if (!(id[i] & 0x0ff)) | |
413 | break; /* WTF? */ | |
414 | } else { | |
415 | if ((id[i] & 0x0ff) == (id[0] & 0x0ff)) | |
416 | denali->total_used_banks++; | |
417 | else | |
418 | break; | |
419 | } | |
420 | } | |
421 | ||
345b1d3b | 422 | if (denali->platform == INTEL_CE4100) { |
ce082596 JR |
423 | /* Platform limitations of the CE4100 device limit |
424 | * users to a single chip solution for NAND. | |
5bac3acf C |
425 | * Multichip support is not enabled. |
426 | */ | |
345b1d3b | 427 | if (denali->total_used_banks != 1) { |
84457949 | 428 | dev_err(denali->dev, |
7cfffac0 | 429 | "Sorry, Intel CE4100 only supports " |
ce082596 JR |
430 | "a single NAND device.\n"); |
431 | BUG(); | |
432 | } | |
433 | } | |
84457949 | 434 | dev_dbg(denali->dev, |
ce082596 JR |
435 | "denali->total_used_banks: %d\n", denali->total_used_banks); |
436 | } | |
437 | ||
c89eeda8 JI |
438 | /* |
439 | * Use the configuration feature register to determine the maximum number of | |
440 | * banks that the hardware supports. | |
441 | */ | |
442 | static void detect_max_banks(struct denali_nand_info *denali) | |
443 | { | |
444 | uint32_t features = ioread32(denali->flash_reg + FEATURES); | |
445 | ||
446 | denali->max_banks = 2 << (features & FEATURES__N_BANKS); | |
447 | } | |
448 | ||
ce082596 JR |
449 | static void detect_partition_feature(struct denali_nand_info *denali) |
450 | { | |
66406524 CD |
451 | /* For MRST platform, denali->fwblks represent the |
452 | * number of blocks firmware is taken, | |
453 | * FW is in protect partition and MTD driver has no | |
454 | * permission to access it. So let driver know how many | |
455 | * blocks it can't touch. | |
456 | * */ | |
ce082596 | 457 | if (ioread32(denali->flash_reg + FEATURES) & FEATURES__PARTITION) { |
9589bf5b JI |
458 | if ((ioread32(denali->flash_reg + PERM_SRC_ID(1)) & |
459 | PERM_SRC_ID__SRCID) == SPECTRA_PARTITION_ID) { | |
66406524 | 460 | denali->fwblks = |
9589bf5b JI |
461 | ((ioread32(denali->flash_reg + MIN_MAX_BANK(1)) & |
462 | MIN_MAX_BANK__MIN_VALUE) * | |
66406524 | 463 | denali->blksperchip) |
ce082596 | 464 | + |
9589bf5b JI |
465 | (ioread32(denali->flash_reg + MIN_BLK_ADDR(1)) & |
466 | MIN_BLK_ADDR__VALUE); | |
66406524 CD |
467 | } else |
468 | denali->fwblks = SPECTRA_START_BLOCK; | |
469 | } else | |
470 | denali->fwblks = SPECTRA_START_BLOCK; | |
ce082596 JR |
471 | } |
472 | ||
eda936ef | 473 | static uint16_t denali_nand_timing_set(struct denali_nand_info *denali) |
ce082596 JR |
474 | { |
475 | uint16_t status = PASS; | |
d68a5c3d | 476 | uint32_t id_bytes[8], addr; |
ef41e1bb | 477 | uint8_t i, maf_id, device_id; |
ce082596 | 478 | |
84457949 | 479 | dev_dbg(denali->dev, |
7cfffac0 CD |
480 | "%s, Line %d, Function: %s\n", |
481 | __FILE__, __LINE__, __func__); | |
ce082596 | 482 | |
ef41e1bb CD |
483 | /* Use read id method to get device ID and other |
484 | * params. For some NAND chips, controller can't | |
485 | * report the correct device ID by reading from | |
486 | * DEVICE_ID register | |
487 | * */ | |
488 | addr = (uint32_t)MODE_11 | BANK(denali->flash_bank); | |
489 | index_addr(denali, (uint32_t)addr | 0, 0x90); | |
490 | index_addr(denali, (uint32_t)addr | 1, 0); | |
d68a5c3d | 491 | for (i = 0; i < 8; i++) |
ef41e1bb CD |
492 | index_addr_read_data(denali, addr | 2, &id_bytes[i]); |
493 | maf_id = id_bytes[0]; | |
494 | device_id = id_bytes[1]; | |
ce082596 JR |
495 | |
496 | if (ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) & | |
497 | ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */ | |
498 | if (FAIL == get_onfi_nand_para(denali)) | |
499 | return FAIL; | |
ef41e1bb | 500 | } else if (maf_id == 0xEC) { /* Samsung NAND */ |
4c03bbdf | 501 | get_samsung_nand_para(denali, device_id); |
ef41e1bb | 502 | } else if (maf_id == 0x98) { /* Toshiba NAND */ |
ce082596 | 503 | get_toshiba_nand_para(denali); |
ef41e1bb CD |
504 | } else if (maf_id == 0xAD) { /* Hynix NAND */ |
505 | get_hynix_nand_para(denali, device_id); | |
ce082596 JR |
506 | } |
507 | ||
84457949 | 508 | dev_info(denali->dev, |
7cfffac0 CD |
509 | "Dump timing register values:" |
510 | "acc_clks: %d, re_2_we: %d, re_2_re: %d\n" | |
511 | "we_2_re: %d, addr_2_data: %d, rdwr_en_lo_cnt: %d\n" | |
ce082596 JR |
512 | "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n", |
513 | ioread32(denali->flash_reg + ACC_CLKS), | |
514 | ioread32(denali->flash_reg + RE_2_WE), | |
7cfffac0 | 515 | ioread32(denali->flash_reg + RE_2_RE), |
ce082596 JR |
516 | ioread32(denali->flash_reg + WE_2_RE), |
517 | ioread32(denali->flash_reg + ADDR_2_DATA), | |
518 | ioread32(denali->flash_reg + RDWR_EN_LO_CNT), | |
519 | ioread32(denali->flash_reg + RDWR_EN_HI_CNT), | |
520 | ioread32(denali->flash_reg + CS_SETUP_CNT)); | |
521 | ||
ce082596 JR |
522 | find_valid_banks(denali); |
523 | ||
524 | detect_partition_feature(denali); | |
525 | ||
ce082596 | 526 | /* If the user specified to override the default timings |
5bac3acf | 527 | * with a specific ONFI mode, we apply those changes here. |
ce082596 JR |
528 | */ |
529 | if (onfi_timing_mode != NAND_DEFAULT_TIMINGS) | |
eda936ef | 530 | nand_onfi_timing_set(denali, onfi_timing_mode); |
ce082596 JR |
531 | |
532 | return status; | |
533 | } | |
534 | ||
eda936ef | 535 | static void denali_set_intr_modes(struct denali_nand_info *denali, |
ce082596 JR |
536 | uint16_t INT_ENABLE) |
537 | { | |
84457949 | 538 | dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", |
ce082596 JR |
539 | __FILE__, __LINE__, __func__); |
540 | ||
541 | if (INT_ENABLE) | |
24c3fa36 | 542 | iowrite32(1, denali->flash_reg + GLOBAL_INT_ENABLE); |
ce082596 | 543 | else |
24c3fa36 | 544 | iowrite32(0, denali->flash_reg + GLOBAL_INT_ENABLE); |
ce082596 JR |
545 | } |
546 | ||
547 | /* validation function to verify that the controlling software is making | |
b292c341 | 548 | * a valid request |
ce082596 JR |
549 | */ |
550 | static inline bool is_flash_bank_valid(int flash_bank) | |
551 | { | |
5bac3acf | 552 | return (flash_bank >= 0 && flash_bank < 4); |
ce082596 JR |
553 | } |
554 | ||
555 | static void denali_irq_init(struct denali_nand_info *denali) | |
556 | { | |
557 | uint32_t int_mask = 0; | |
9589bf5b | 558 | int i; |
ce082596 JR |
559 | |
560 | /* Disable global interrupts */ | |
eda936ef | 561 | denali_set_intr_modes(denali, false); |
ce082596 JR |
562 | |
563 | int_mask = DENALI_IRQ_ALL; | |
564 | ||
565 | /* Clear all status bits */ | |
c89eeda8 | 566 | for (i = 0; i < denali->max_banks; ++i) |
9589bf5b | 567 | iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS(i)); |
ce082596 JR |
568 | |
569 | denali_irq_enable(denali, int_mask); | |
570 | } | |
571 | ||
572 | static void denali_irq_cleanup(int irqnum, struct denali_nand_info *denali) | |
573 | { | |
eda936ef | 574 | denali_set_intr_modes(denali, false); |
ce082596 JR |
575 | free_irq(irqnum, denali); |
576 | } | |
577 | ||
bdca6dae CD |
578 | static void denali_irq_enable(struct denali_nand_info *denali, |
579 | uint32_t int_mask) | |
ce082596 | 580 | { |
9589bf5b JI |
581 | int i; |
582 | ||
c89eeda8 | 583 | for (i = 0; i < denali->max_banks; ++i) |
9589bf5b | 584 | iowrite32(int_mask, denali->flash_reg + INTR_EN(i)); |
ce082596 JR |
585 | } |
586 | ||
587 | /* This function only returns when an interrupt that this driver cares about | |
5bac3acf | 588 | * occurs. This is to reduce the overhead of servicing interrupts |
ce082596 JR |
589 | */ |
590 | static inline uint32_t denali_irq_detected(struct denali_nand_info *denali) | |
591 | { | |
a99d1796 | 592 | return read_interrupt_status(denali) & DENALI_IRQ_ALL; |
ce082596 JR |
593 | } |
594 | ||
595 | /* Interrupts are cleared by writing a 1 to the appropriate status bit */ | |
bdca6dae CD |
596 | static inline void clear_interrupt(struct denali_nand_info *denali, |
597 | uint32_t irq_mask) | |
ce082596 JR |
598 | { |
599 | uint32_t intr_status_reg = 0; | |
600 | ||
9589bf5b | 601 | intr_status_reg = INTR_STATUS(denali->flash_bank); |
ce082596 | 602 | |
24c3fa36 | 603 | iowrite32(irq_mask, denali->flash_reg + intr_status_reg); |
ce082596 JR |
604 | } |
605 | ||
606 | static void clear_interrupts(struct denali_nand_info *denali) | |
607 | { | |
608 | uint32_t status = 0x0; | |
609 | spin_lock_irq(&denali->irq_lock); | |
610 | ||
611 | status = read_interrupt_status(denali); | |
8ae61ebd | 612 | clear_interrupt(denali, status); |
ce082596 | 613 | |
ce082596 JR |
614 | denali->irq_status = 0x0; |
615 | spin_unlock_irq(&denali->irq_lock); | |
616 | } | |
617 | ||
618 | static uint32_t read_interrupt_status(struct denali_nand_info *denali) | |
619 | { | |
620 | uint32_t intr_status_reg = 0; | |
621 | ||
9589bf5b | 622 | intr_status_reg = INTR_STATUS(denali->flash_bank); |
ce082596 JR |
623 | |
624 | return ioread32(denali->flash_reg + intr_status_reg); | |
625 | } | |
626 | ||
5bac3acf C |
627 | /* This is the interrupt service routine. It handles all interrupts |
628 | * sent to this device. Note that on CE4100, this is a shared | |
629 | * interrupt. | |
ce082596 JR |
630 | */ |
631 | static irqreturn_t denali_isr(int irq, void *dev_id) | |
632 | { | |
633 | struct denali_nand_info *denali = dev_id; | |
634 | uint32_t irq_status = 0x0; | |
635 | irqreturn_t result = IRQ_NONE; | |
636 | ||
637 | spin_lock(&denali->irq_lock); | |
638 | ||
5bac3acf C |
639 | /* check to see if a valid NAND chip has |
640 | * been selected. | |
ce082596 | 641 | */ |
345b1d3b | 642 | if (is_flash_bank_valid(denali->flash_bank)) { |
5bac3acf | 643 | /* check to see if controller generated |
ce082596 | 644 | * the interrupt, since this is a shared interrupt */ |
bdca6dae CD |
645 | irq_status = denali_irq_detected(denali); |
646 | if (irq_status != 0) { | |
ce082596 JR |
647 | /* handle interrupt */ |
648 | /* first acknowledge it */ | |
649 | clear_interrupt(denali, irq_status); | |
650 | /* store the status in the device context for someone | |
651 | to read */ | |
652 | denali->irq_status |= irq_status; | |
653 | /* notify anyone who cares that it happened */ | |
654 | complete(&denali->complete); | |
655 | /* tell the OS that we've handled this */ | |
656 | result = IRQ_HANDLED; | |
657 | } | |
658 | } | |
659 | spin_unlock(&denali->irq_lock); | |
660 | return result; | |
661 | } | |
662 | #define BANK(x) ((x) << 24) | |
663 | ||
664 | static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask) | |
665 | { | |
666 | unsigned long comp_res = 0; | |
667 | uint32_t intr_status = 0; | |
668 | bool retry = false; | |
669 | unsigned long timeout = msecs_to_jiffies(1000); | |
670 | ||
345b1d3b | 671 | do { |
bdca6dae CD |
672 | comp_res = |
673 | wait_for_completion_timeout(&denali->complete, timeout); | |
ce082596 JR |
674 | spin_lock_irq(&denali->irq_lock); |
675 | intr_status = denali->irq_status; | |
676 | ||
345b1d3b | 677 | if (intr_status & irq_mask) { |
ce082596 JR |
678 | denali->irq_status &= ~irq_mask; |
679 | spin_unlock_irq(&denali->irq_lock); | |
ce082596 JR |
680 | /* our interrupt was detected */ |
681 | break; | |
345b1d3b | 682 | } else { |
5bac3acf C |
683 | /* these are not the interrupts you are looking for - |
684 | * need to wait again */ | |
ce082596 | 685 | spin_unlock_irq(&denali->irq_lock); |
ce082596 JR |
686 | retry = true; |
687 | } | |
688 | } while (comp_res != 0); | |
689 | ||
345b1d3b | 690 | if (comp_res == 0) { |
ce082596 | 691 | /* timeout */ |
2a0a288e | 692 | pr_err("timeout occurred, status = 0x%x, mask = 0x%x\n", |
5bac3acf | 693 | intr_status, irq_mask); |
ce082596 JR |
694 | |
695 | intr_status = 0; | |
696 | } | |
697 | return intr_status; | |
698 | } | |
699 | ||
5bac3acf | 700 | /* This helper function setups the registers for ECC and whether or not |
25985edc | 701 | * the spare area will be transferred. */ |
5bac3acf | 702 | static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en, |
ce082596 JR |
703 | bool transfer_spare) |
704 | { | |
5bac3acf | 705 | int ecc_en_flag = 0, transfer_spare_flag = 0; |
ce082596 JR |
706 | |
707 | /* set ECC, transfer spare bits if needed */ | |
708 | ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0; | |
709 | transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0; | |
710 | ||
711 | /* Enable spare area/ECC per user's request. */ | |
24c3fa36 CD |
712 | iowrite32(ecc_en_flag, denali->flash_reg + ECC_ENABLE); |
713 | iowrite32(transfer_spare_flag, | |
bdca6dae | 714 | denali->flash_reg + TRANSFER_SPARE_REG); |
ce082596 JR |
715 | } |
716 | ||
5bac3acf | 717 | /* sends a pipeline command operation to the controller. See the Denali NAND |
b292c341 | 718 | * controller's user guide for more information (section 4.2.3.6). |
ce082596 | 719 | */ |
bdca6dae CD |
720 | static int denali_send_pipeline_cmd(struct denali_nand_info *denali, |
721 | bool ecc_en, | |
722 | bool transfer_spare, | |
723 | int access_type, | |
724 | int op) | |
ce082596 JR |
725 | { |
726 | int status = PASS; | |
5bac3acf | 727 | uint32_t addr = 0x0, cmd = 0x0, page_count = 1, irq_status = 0, |
ce082596 JR |
728 | irq_mask = 0; |
729 | ||
a99d1796 | 730 | if (op == DENALI_READ) |
9589bf5b | 731 | irq_mask = INTR_STATUS__LOAD_COMP; |
a99d1796 CD |
732 | else if (op == DENALI_WRITE) |
733 | irq_mask = 0; | |
734 | else | |
735 | BUG(); | |
ce082596 JR |
736 | |
737 | setup_ecc_for_xfer(denali, ecc_en, transfer_spare); | |
738 | ||
ce082596 | 739 | /* clear interrupts */ |
5bac3acf | 740 | clear_interrupts(denali); |
ce082596 JR |
741 | |
742 | addr = BANK(denali->flash_bank) | denali->page; | |
743 | ||
345b1d3b | 744 | if (op == DENALI_WRITE && access_type != SPARE_ACCESS) { |
5bac3acf | 745 | cmd = MODE_01 | addr; |
24c3fa36 | 746 | iowrite32(cmd, denali->flash_mem); |
345b1d3b | 747 | } else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) { |
ce082596 | 748 | /* read spare area */ |
5bac3acf | 749 | cmd = MODE_10 | addr; |
ce082596 JR |
750 | index_addr(denali, (uint32_t)cmd, access_type); |
751 | ||
5bac3acf | 752 | cmd = MODE_01 | addr; |
24c3fa36 | 753 | iowrite32(cmd, denali->flash_mem); |
345b1d3b | 754 | } else if (op == DENALI_READ) { |
ce082596 | 755 | /* setup page read request for access type */ |
5bac3acf | 756 | cmd = MODE_10 | addr; |
ce082596 JR |
757 | index_addr(denali, (uint32_t)cmd, access_type); |
758 | ||
759 | /* page 33 of the NAND controller spec indicates we should not | |
5bac3acf | 760 | use the pipeline commands in Spare area only mode. So we |
ce082596 JR |
761 | don't. |
762 | */ | |
345b1d3b | 763 | if (access_type == SPARE_ACCESS) { |
ce082596 | 764 | cmd = MODE_01 | addr; |
24c3fa36 | 765 | iowrite32(cmd, denali->flash_mem); |
345b1d3b | 766 | } else { |
bdca6dae CD |
767 | index_addr(denali, (uint32_t)cmd, |
768 | 0x2000 | op | page_count); | |
5bac3acf C |
769 | |
770 | /* wait for command to be accepted | |
bdca6dae CD |
771 | * can always use status0 bit as the |
772 | * mask is identical for each | |
ce082596 JR |
773 | * bank. */ |
774 | irq_status = wait_for_irq(denali, irq_mask); | |
775 | ||
345b1d3b | 776 | if (irq_status == 0) { |
84457949 | 777 | dev_err(denali->dev, |
7cfffac0 CD |
778 | "cmd, page, addr on timeout " |
779 | "(0x%x, 0x%x, 0x%x)\n", | |
780 | cmd, denali->page, addr); | |
ce082596 | 781 | status = FAIL; |
345b1d3b | 782 | } else { |
ce082596 | 783 | cmd = MODE_01 | addr; |
24c3fa36 | 784 | iowrite32(cmd, denali->flash_mem); |
ce082596 JR |
785 | } |
786 | } | |
787 | } | |
788 | return status; | |
789 | } | |
790 | ||
791 | /* helper function that simply writes a buffer to the flash */ | |
bdca6dae CD |
792 | static int write_data_to_flash_mem(struct denali_nand_info *denali, |
793 | const uint8_t *buf, | |
794 | int len) | |
ce082596 JR |
795 | { |
796 | uint32_t i = 0, *buf32; | |
797 | ||
5bac3acf C |
798 | /* verify that the len is a multiple of 4. see comment in |
799 | * read_data_from_flash_mem() */ | |
ce082596 JR |
800 | BUG_ON((len % 4) != 0); |
801 | ||
802 | /* write the data to the flash memory */ | |
803 | buf32 = (uint32_t *)buf; | |
804 | for (i = 0; i < len / 4; i++) | |
24c3fa36 | 805 | iowrite32(*buf32++, denali->flash_mem + 0x10); |
5bac3acf | 806 | return i*4; /* intent is to return the number of bytes read */ |
ce082596 JR |
807 | } |
808 | ||
809 | /* helper function that simply reads a buffer from the flash */ | |
bdca6dae CD |
810 | static int read_data_from_flash_mem(struct denali_nand_info *denali, |
811 | uint8_t *buf, | |
812 | int len) | |
ce082596 JR |
813 | { |
814 | uint32_t i = 0, *buf32; | |
815 | ||
816 | /* we assume that len will be a multiple of 4, if not | |
817 | * it would be nice to know about it ASAP rather than | |
5bac3acf C |
818 | * have random failures... |
819 | * This assumption is based on the fact that this | |
820 | * function is designed to be used to read flash pages, | |
ce082596 JR |
821 | * which are typically multiples of 4... |
822 | */ | |
823 | ||
824 | BUG_ON((len % 4) != 0); | |
825 | ||
826 | /* transfer the data from the flash */ | |
827 | buf32 = (uint32_t *)buf; | |
828 | for (i = 0; i < len / 4; i++) | |
ce082596 | 829 | *buf32++ = ioread32(denali->flash_mem + 0x10); |
5bac3acf | 830 | return i*4; /* intent is to return the number of bytes read */ |
ce082596 JR |
831 | } |
832 | ||
833 | /* writes OOB data to the device */ | |
834 | static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) | |
835 | { | |
836 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
837 | uint32_t irq_status = 0; | |
9589bf5b JI |
838 | uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP | |
839 | INTR_STATUS__PROGRAM_FAIL; | |
ce082596 JR |
840 | int status = 0; |
841 | ||
842 | denali->page = page; | |
843 | ||
5bac3acf | 844 | if (denali_send_pipeline_cmd(denali, false, false, SPARE_ACCESS, |
345b1d3b | 845 | DENALI_WRITE) == PASS) { |
ce082596 JR |
846 | write_data_to_flash_mem(denali, buf, mtd->oobsize); |
847 | ||
ce082596 JR |
848 | /* wait for operation to complete */ |
849 | irq_status = wait_for_irq(denali, irq_mask); | |
850 | ||
345b1d3b | 851 | if (irq_status == 0) { |
84457949 | 852 | dev_err(denali->dev, "OOB write failed\n"); |
ce082596 JR |
853 | status = -EIO; |
854 | } | |
345b1d3b | 855 | } else { |
84457949 | 856 | dev_err(denali->dev, "unable to send pipeline command\n"); |
5bac3acf | 857 | status = -EIO; |
ce082596 JR |
858 | } |
859 | return status; | |
860 | } | |
861 | ||
862 | /* reads OOB data from the device */ | |
863 | static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) | |
864 | { | |
865 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
9589bf5b | 866 | uint32_t irq_mask = INTR_STATUS__LOAD_COMP, |
bdca6dae | 867 | irq_status = 0, addr = 0x0, cmd = 0x0; |
ce082596 JR |
868 | |
869 | denali->page = page; | |
870 | ||
5bac3acf | 871 | if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS, |
345b1d3b | 872 | DENALI_READ) == PASS) { |
5bac3acf | 873 | read_data_from_flash_mem(denali, buf, mtd->oobsize); |
ce082596 | 874 | |
5bac3acf | 875 | /* wait for command to be accepted |
ce082596 JR |
876 | * can always use status0 bit as the mask is identical for each |
877 | * bank. */ | |
878 | irq_status = wait_for_irq(denali, irq_mask); | |
879 | ||
880 | if (irq_status == 0) | |
84457949 | 881 | dev_err(denali->dev, "page on OOB timeout %d\n", |
bdca6dae | 882 | denali->page); |
ce082596 JR |
883 | |
884 | /* We set the device back to MAIN_ACCESS here as I observed | |
885 | * instability with the controller if you do a block erase | |
886 | * and the last transaction was a SPARE_ACCESS. Block erase | |
887 | * is reliable (according to the MTD test infrastructure) | |
5bac3acf | 888 | * if you are in MAIN_ACCESS. |
ce082596 JR |
889 | */ |
890 | addr = BANK(denali->flash_bank) | denali->page; | |
5bac3acf | 891 | cmd = MODE_10 | addr; |
ce082596 | 892 | index_addr(denali, (uint32_t)cmd, MAIN_ACCESS); |
ce082596 JR |
893 | } |
894 | } | |
895 | ||
5bac3acf | 896 | /* this function examines buffers to see if they contain data that |
ce082596 JR |
897 | * indicate that the buffer is part of an erased region of flash. |
898 | */ | |
919193ce | 899 | static bool is_erased(uint8_t *buf, int len) |
ce082596 JR |
900 | { |
901 | int i = 0; | |
902 | for (i = 0; i < len; i++) | |
ce082596 | 903 | if (buf[i] != 0xFF) |
ce082596 | 904 | return false; |
ce082596 JR |
905 | return true; |
906 | } | |
907 | #define ECC_SECTOR_SIZE 512 | |
908 | ||
909 | #define ECC_SECTOR(x) (((x) & ECC_ERROR_ADDRESS__SECTOR_NR) >> 12) | |
910 | #define ECC_BYTE(x) (((x) & ECC_ERROR_ADDRESS__OFFSET)) | |
911 | #define ECC_CORRECTION_VALUE(x) ((x) & ERR_CORRECTION_INFO__BYTEMASK) | |
8ae61ebd CD |
912 | #define ECC_ERROR_CORRECTABLE(x) (!((x) & ERR_CORRECTION_INFO__ERROR_TYPE)) |
913 | #define ECC_ERR_DEVICE(x) (((x) & ERR_CORRECTION_INFO__DEVICE_NR) >> 8) | |
ce082596 JR |
914 | #define ECC_LAST_ERR(x) ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO) |
915 | ||
5bac3acf | 916 | static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf, |
3f91e94f | 917 | uint32_t irq_status, unsigned int *max_bitflips) |
ce082596 JR |
918 | { |
919 | bool check_erased_page = false; | |
3f91e94f | 920 | unsigned int bitflips = 0; |
ce082596 | 921 | |
9589bf5b | 922 | if (irq_status & INTR_STATUS__ECC_ERR) { |
ce082596 JR |
923 | /* read the ECC errors. we'll ignore them for now */ |
924 | uint32_t err_address = 0, err_correction_info = 0; | |
925 | uint32_t err_byte = 0, err_sector = 0, err_device = 0; | |
926 | uint32_t err_correction_value = 0; | |
8ae61ebd | 927 | denali_set_intr_modes(denali, false); |
ce082596 | 928 | |
345b1d3b | 929 | do { |
5bac3acf | 930 | err_address = ioread32(denali->flash_reg + |
ce082596 JR |
931 | ECC_ERROR_ADDRESS); |
932 | err_sector = ECC_SECTOR(err_address); | |
933 | err_byte = ECC_BYTE(err_address); | |
934 | ||
5bac3acf | 935 | err_correction_info = ioread32(denali->flash_reg + |
ce082596 | 936 | ERR_CORRECTION_INFO); |
5bac3acf | 937 | err_correction_value = |
ce082596 JR |
938 | ECC_CORRECTION_VALUE(err_correction_info); |
939 | err_device = ECC_ERR_DEVICE(err_correction_info); | |
940 | ||
345b1d3b | 941 | if (ECC_ERROR_CORRECTABLE(err_correction_info)) { |
8ae61ebd | 942 | /* If err_byte is larger than ECC_SECTOR_SIZE, |
25985edc | 943 | * means error happened in OOB, so we ignore |
8ae61ebd CD |
944 | * it. It's no need for us to correct it |
945 | * err_device is represented the NAND error | |
946 | * bits are happened in if there are more | |
947 | * than one NAND connected. | |
948 | * */ | |
949 | if (err_byte < ECC_SECTOR_SIZE) { | |
950 | int offset; | |
951 | offset = (err_sector * | |
952 | ECC_SECTOR_SIZE + | |
953 | err_byte) * | |
954 | denali->devnum + | |
955 | err_device; | |
ce082596 JR |
956 | /* correct the ECC error */ |
957 | buf[offset] ^= err_correction_value; | |
958 | denali->mtd.ecc_stats.corrected++; | |
3f91e94f | 959 | bitflips++; |
ce082596 | 960 | } |
345b1d3b | 961 | } else { |
5bac3acf | 962 | /* if the error is not correctable, need to |
bdca6dae CD |
963 | * look at the page to see if it is an erased |
964 | * page. if so, then it's not a real ECC error | |
965 | * */ | |
ce082596 JR |
966 | check_erased_page = true; |
967 | } | |
ce082596 | 968 | } while (!ECC_LAST_ERR(err_correction_info)); |
8ae61ebd CD |
969 | /* Once handle all ecc errors, controller will triger |
970 | * a ECC_TRANSACTION_DONE interrupt, so here just wait | |
971 | * for a while for this interrupt | |
972 | * */ | |
973 | while (!(read_interrupt_status(denali) & | |
9589bf5b | 974 | INTR_STATUS__ECC_TRANSACTION_DONE)) |
8ae61ebd CD |
975 | cpu_relax(); |
976 | clear_interrupts(denali); | |
977 | denali_set_intr_modes(denali, true); | |
ce082596 | 978 | } |
3f91e94f | 979 | *max_bitflips = bitflips; |
ce082596 JR |
980 | return check_erased_page; |
981 | } | |
982 | ||
983 | /* programs the controller to either enable/disable DMA transfers */ | |
aadff49c | 984 | static void denali_enable_dma(struct denali_nand_info *denali, bool en) |
ce082596 JR |
985 | { |
986 | uint32_t reg_val = 0x0; | |
987 | ||
a99d1796 CD |
988 | if (en) |
989 | reg_val = DMA_ENABLE__FLAG; | |
ce082596 | 990 | |
24c3fa36 | 991 | iowrite32(reg_val, denali->flash_reg + DMA_ENABLE); |
ce082596 JR |
992 | ioread32(denali->flash_reg + DMA_ENABLE); |
993 | } | |
994 | ||
995 | /* setups the HW to perform the data DMA */ | |
aadff49c | 996 | static void denali_setup_dma(struct denali_nand_info *denali, int op) |
ce082596 JR |
997 | { |
998 | uint32_t mode = 0x0; | |
999 | const int page_count = 1; | |
1000 | dma_addr_t addr = denali->buf.dma_buf; | |
1001 | ||
1002 | mode = MODE_10 | BANK(denali->flash_bank); | |
1003 | ||
1004 | /* DMA is a four step process */ | |
1005 | ||
1006 | /* 1. setup transfer type and # of pages */ | |
1007 | index_addr(denali, mode | denali->page, 0x2000 | op | page_count); | |
1008 | ||
1009 | /* 2. set memory high address bits 23:8 */ | |
1010 | index_addr(denali, mode | ((uint16_t)(addr >> 16) << 8), 0x2200); | |
1011 | ||
1012 | /* 3. set memory low address bits 23:8 */ | |
1013 | index_addr(denali, mode | ((uint16_t)addr << 8), 0x2300); | |
1014 | ||
1015 | /* 4. interrupt when complete, burst len = 64 bytes*/ | |
1016 | index_addr(denali, mode | 0x14000, 0x2400); | |
1017 | } | |
1018 | ||
5bac3acf | 1019 | /* writes a page. user specifies type, and this function handles the |
b292c341 | 1020 | * configuration details. */ |
fdbad98d | 1021 | static int write_page(struct mtd_info *mtd, struct nand_chip *chip, |
ce082596 JR |
1022 | const uint8_t *buf, bool raw_xfer) |
1023 | { | |
1024 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
ce082596 JR |
1025 | |
1026 | dma_addr_t addr = denali->buf.dma_buf; | |
1027 | size_t size = denali->mtd.writesize + denali->mtd.oobsize; | |
1028 | ||
1029 | uint32_t irq_status = 0; | |
9589bf5b JI |
1030 | uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP | |
1031 | INTR_STATUS__PROGRAM_FAIL; | |
ce082596 JR |
1032 | |
1033 | /* if it is a raw xfer, we want to disable ecc, and send | |
1034 | * the spare area. | |
1035 | * !raw_xfer - enable ecc | |
1036 | * raw_xfer - transfer spare | |
1037 | */ | |
1038 | setup_ecc_for_xfer(denali, !raw_xfer, raw_xfer); | |
1039 | ||
1040 | /* copy buffer into DMA buffer */ | |
1041 | memcpy(denali->buf.buf, buf, mtd->writesize); | |
1042 | ||
345b1d3b | 1043 | if (raw_xfer) { |
ce082596 | 1044 | /* transfer the data to the spare area */ |
5bac3acf C |
1045 | memcpy(denali->buf.buf + mtd->writesize, |
1046 | chip->oob_poi, | |
1047 | mtd->oobsize); | |
ce082596 JR |
1048 | } |
1049 | ||
84457949 | 1050 | dma_sync_single_for_device(denali->dev, addr, size, DMA_TO_DEVICE); |
ce082596 JR |
1051 | |
1052 | clear_interrupts(denali); | |
5bac3acf | 1053 | denali_enable_dma(denali, true); |
ce082596 | 1054 | |
aadff49c | 1055 | denali_setup_dma(denali, DENALI_WRITE); |
ce082596 JR |
1056 | |
1057 | /* wait for operation to complete */ | |
1058 | irq_status = wait_for_irq(denali, irq_mask); | |
1059 | ||
345b1d3b | 1060 | if (irq_status == 0) { |
84457949 | 1061 | dev_err(denali->dev, |
7cfffac0 CD |
1062 | "timeout on write_page (type = %d)\n", |
1063 | raw_xfer); | |
5bac3acf | 1064 | denali->status = |
9589bf5b | 1065 | (irq_status & INTR_STATUS__PROGRAM_FAIL) ? |
bdca6dae | 1066 | NAND_STATUS_FAIL : PASS; |
ce082596 JR |
1067 | } |
1068 | ||
5bac3acf | 1069 | denali_enable_dma(denali, false); |
84457949 | 1070 | dma_sync_single_for_cpu(denali->dev, addr, size, DMA_TO_DEVICE); |
fdbad98d JW |
1071 | |
1072 | return 0; | |
ce082596 JR |
1073 | } |
1074 | ||
1075 | /* NAND core entry points */ | |
1076 | ||
5bac3acf | 1077 | /* this is the callback that the NAND core calls to write a page. Since |
b292c341 CD |
1078 | * writing a page with ECC or without is similar, all the work is done |
1079 | * by write_page above. | |
1080 | * */ | |
fdbad98d | 1081 | static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1082 | const uint8_t *buf, int oob_required) |
ce082596 JR |
1083 | { |
1084 | /* for regular page writes, we let HW handle all the ECC | |
5bac3acf | 1085 | * data written to the device. */ |
fdbad98d | 1086 | return write_page(mtd, chip, buf, false); |
ce082596 JR |
1087 | } |
1088 | ||
5bac3acf | 1089 | /* This is the callback that the NAND core calls to write a page without ECC. |
25985edc | 1090 | * raw access is similar to ECC page writes, so all the work is done in the |
b292c341 | 1091 | * write_page() function above. |
ce082596 | 1092 | */ |
fdbad98d | 1093 | static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1094 | const uint8_t *buf, int oob_required) |
ce082596 | 1095 | { |
5bac3acf | 1096 | /* for raw page writes, we want to disable ECC and simply write |
ce082596 | 1097 | whatever data is in the buffer. */ |
fdbad98d | 1098 | return write_page(mtd, chip, buf, true); |
ce082596 JR |
1099 | } |
1100 | ||
5bac3acf | 1101 | static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip, |
ce082596 JR |
1102 | int page) |
1103 | { | |
5bac3acf | 1104 | return write_oob_data(mtd, chip->oob_poi, page); |
ce082596 JR |
1105 | } |
1106 | ||
5bac3acf | 1107 | static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip, |
5c2ffb11 | 1108 | int page) |
ce082596 JR |
1109 | { |
1110 | read_oob_data(mtd, chip->oob_poi, page); | |
1111 | ||
5c2ffb11 | 1112 | return 0; |
ce082596 JR |
1113 | } |
1114 | ||
1115 | static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 1116 | uint8_t *buf, int oob_required, int page) |
ce082596 | 1117 | { |
3f91e94f | 1118 | unsigned int max_bitflips; |
ce082596 | 1119 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
ce082596 JR |
1120 | |
1121 | dma_addr_t addr = denali->buf.dma_buf; | |
1122 | size_t size = denali->mtd.writesize + denali->mtd.oobsize; | |
1123 | ||
1124 | uint32_t irq_status = 0; | |
9589bf5b JI |
1125 | uint32_t irq_mask = INTR_STATUS__ECC_TRANSACTION_DONE | |
1126 | INTR_STATUS__ECC_ERR; | |
ce082596 JR |
1127 | bool check_erased_page = false; |
1128 | ||
7d8a26fd | 1129 | if (page != denali->page) { |
84457949 | 1130 | dev_err(denali->dev, "IN %s: page %d is not" |
7d8a26fd CD |
1131 | " equal to denali->page %d, investigate!!", |
1132 | __func__, page, denali->page); | |
1133 | BUG(); | |
1134 | } | |
1135 | ||
ce082596 JR |
1136 | setup_ecc_for_xfer(denali, true, false); |
1137 | ||
aadff49c | 1138 | denali_enable_dma(denali, true); |
84457949 | 1139 | dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE); |
ce082596 JR |
1140 | |
1141 | clear_interrupts(denali); | |
aadff49c | 1142 | denali_setup_dma(denali, DENALI_READ); |
ce082596 JR |
1143 | |
1144 | /* wait for operation to complete */ | |
1145 | irq_status = wait_for_irq(denali, irq_mask); | |
1146 | ||
84457949 | 1147 | dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE); |
ce082596 JR |
1148 | |
1149 | memcpy(buf, denali->buf.buf, mtd->writesize); | |
5bac3acf | 1150 | |
3f91e94f | 1151 | check_erased_page = handle_ecc(denali, buf, irq_status, &max_bitflips); |
aadff49c | 1152 | denali_enable_dma(denali, false); |
ce082596 | 1153 | |
345b1d3b | 1154 | if (check_erased_page) { |
ce082596 JR |
1155 | read_oob_data(&denali->mtd, chip->oob_poi, denali->page); |
1156 | ||
1157 | /* check ECC failures that may have occurred on erased pages */ | |
345b1d3b | 1158 | if (check_erased_page) { |
ce082596 | 1159 | if (!is_erased(buf, denali->mtd.writesize)) |
ce082596 | 1160 | denali->mtd.ecc_stats.failed++; |
ce082596 | 1161 | if (!is_erased(buf, denali->mtd.oobsize)) |
ce082596 | 1162 | denali->mtd.ecc_stats.failed++; |
5bac3acf | 1163 | } |
ce082596 | 1164 | } |
3f91e94f | 1165 | return max_bitflips; |
ce082596 JR |
1166 | } |
1167 | ||
1168 | static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 1169 | uint8_t *buf, int oob_required, int page) |
ce082596 JR |
1170 | { |
1171 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
ce082596 JR |
1172 | |
1173 | dma_addr_t addr = denali->buf.dma_buf; | |
1174 | size_t size = denali->mtd.writesize + denali->mtd.oobsize; | |
1175 | ||
1176 | uint32_t irq_status = 0; | |
9589bf5b | 1177 | uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP; |
5bac3acf | 1178 | |
7d8a26fd | 1179 | if (page != denali->page) { |
84457949 | 1180 | dev_err(denali->dev, "IN %s: page %d is not" |
7d8a26fd CD |
1181 | " equal to denali->page %d, investigate!!", |
1182 | __func__, page, denali->page); | |
1183 | BUG(); | |
1184 | } | |
1185 | ||
ce082596 | 1186 | setup_ecc_for_xfer(denali, false, true); |
aadff49c | 1187 | denali_enable_dma(denali, true); |
ce082596 | 1188 | |
84457949 | 1189 | dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE); |
ce082596 JR |
1190 | |
1191 | clear_interrupts(denali); | |
aadff49c | 1192 | denali_setup_dma(denali, DENALI_READ); |
ce082596 JR |
1193 | |
1194 | /* wait for operation to complete */ | |
1195 | irq_status = wait_for_irq(denali, irq_mask); | |
1196 | ||
84457949 | 1197 | dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE); |
ce082596 | 1198 | |
aadff49c | 1199 | denali_enable_dma(denali, false); |
ce082596 JR |
1200 | |
1201 | memcpy(buf, denali->buf.buf, mtd->writesize); | |
1202 | memcpy(chip->oob_poi, denali->buf.buf + mtd->writesize, mtd->oobsize); | |
1203 | ||
1204 | return 0; | |
1205 | } | |
1206 | ||
1207 | static uint8_t denali_read_byte(struct mtd_info *mtd) | |
1208 | { | |
1209 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1210 | uint8_t result = 0xff; | |
1211 | ||
1212 | if (denali->buf.head < denali->buf.tail) | |
ce082596 | 1213 | result = denali->buf.buf[denali->buf.head++]; |
ce082596 | 1214 | |
ce082596 JR |
1215 | return result; |
1216 | } | |
1217 | ||
1218 | static void denali_select_chip(struct mtd_info *mtd, int chip) | |
1219 | { | |
1220 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
7cfffac0 | 1221 | |
ce082596 JR |
1222 | spin_lock_irq(&denali->irq_lock); |
1223 | denali->flash_bank = chip; | |
1224 | spin_unlock_irq(&denali->irq_lock); | |
1225 | } | |
1226 | ||
1227 | static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip) | |
1228 | { | |
1229 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1230 | int status = denali->status; | |
1231 | denali->status = 0; | |
1232 | ||
ce082596 JR |
1233 | return status; |
1234 | } | |
1235 | ||
49c50b97 | 1236 | static int denali_erase(struct mtd_info *mtd, int page) |
ce082596 JR |
1237 | { |
1238 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1239 | ||
1240 | uint32_t cmd = 0x0, irq_status = 0; | |
1241 | ||
ce082596 | 1242 | /* clear interrupts */ |
5bac3acf | 1243 | clear_interrupts(denali); |
ce082596 JR |
1244 | |
1245 | /* setup page read request for access type */ | |
1246 | cmd = MODE_10 | BANK(denali->flash_bank) | page; | |
1247 | index_addr(denali, (uint32_t)cmd, 0x1); | |
1248 | ||
1249 | /* wait for erase to complete or failure to occur */ | |
9589bf5b JI |
1250 | irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP | |
1251 | INTR_STATUS__ERASE_FAIL); | |
ce082596 | 1252 | |
49c50b97 | 1253 | return (irq_status & INTR_STATUS__ERASE_FAIL) ? NAND_STATUS_FAIL : PASS; |
ce082596 JR |
1254 | } |
1255 | ||
5bac3acf | 1256 | static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, |
ce082596 JR |
1257 | int page) |
1258 | { | |
1259 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
ef41e1bb CD |
1260 | uint32_t addr, id; |
1261 | int i; | |
ce082596 | 1262 | |
345b1d3b | 1263 | switch (cmd) { |
a99d1796 CD |
1264 | case NAND_CMD_PAGEPROG: |
1265 | break; | |
1266 | case NAND_CMD_STATUS: | |
1267 | read_status(denali); | |
1268 | break; | |
1269 | case NAND_CMD_READID: | |
42af8b58 | 1270 | case NAND_CMD_PARAM: |
a99d1796 | 1271 | reset_buf(denali); |
ef41e1bb CD |
1272 | /*sometimes ManufactureId read from register is not right |
1273 | * e.g. some of Micron MT29F32G08QAA MLC NAND chips | |
1274 | * So here we send READID cmd to NAND insteand | |
1275 | * */ | |
1276 | addr = (uint32_t)MODE_11 | BANK(denali->flash_bank); | |
1277 | index_addr(denali, (uint32_t)addr | 0, 0x90); | |
1278 | index_addr(denali, (uint32_t)addr | 1, 0); | |
d68a5c3d | 1279 | for (i = 0; i < 8; i++) { |
ef41e1bb CD |
1280 | index_addr_read_data(denali, |
1281 | (uint32_t)addr | 2, | |
1282 | &id); | |
1283 | write_byte_to_buf(denali, id); | |
a99d1796 CD |
1284 | } |
1285 | break; | |
1286 | case NAND_CMD_READ0: | |
1287 | case NAND_CMD_SEQIN: | |
1288 | denali->page = page; | |
1289 | break; | |
1290 | case NAND_CMD_RESET: | |
1291 | reset_bank(denali); | |
1292 | break; | |
1293 | case NAND_CMD_READOOB: | |
1294 | /* TODO: Read OOB data */ | |
1295 | break; | |
1296 | default: | |
2a0a288e | 1297 | pr_err(": unsupported command received 0x%x\n", cmd); |
a99d1796 | 1298 | break; |
ce082596 JR |
1299 | } |
1300 | } | |
1301 | ||
1302 | /* stubs for ECC functions not used by the NAND core */ | |
5bac3acf | 1303 | static int denali_ecc_calculate(struct mtd_info *mtd, const uint8_t *data, |
ce082596 JR |
1304 | uint8_t *ecc_code) |
1305 | { | |
7cfffac0 | 1306 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
84457949 | 1307 | dev_err(denali->dev, |
7cfffac0 | 1308 | "denali_ecc_calculate called unexpectedly\n"); |
ce082596 JR |
1309 | BUG(); |
1310 | return -EIO; | |
1311 | } | |
1312 | ||
5bac3acf | 1313 | static int denali_ecc_correct(struct mtd_info *mtd, uint8_t *data, |
ce082596 JR |
1314 | uint8_t *read_ecc, uint8_t *calc_ecc) |
1315 | { | |
7cfffac0 | 1316 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
84457949 | 1317 | dev_err(denali->dev, |
7cfffac0 | 1318 | "denali_ecc_correct called unexpectedly\n"); |
ce082596 JR |
1319 | BUG(); |
1320 | return -EIO; | |
1321 | } | |
1322 | ||
1323 | static void denali_ecc_hwctl(struct mtd_info *mtd, int mode) | |
1324 | { | |
7cfffac0 | 1325 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
84457949 | 1326 | dev_err(denali->dev, |
7cfffac0 | 1327 | "denali_ecc_hwctl called unexpectedly\n"); |
ce082596 JR |
1328 | BUG(); |
1329 | } | |
1330 | /* end NAND core entry points */ | |
1331 | ||
1332 | /* Initialization code to bring the device up to a known good state */ | |
1333 | static void denali_hw_init(struct denali_nand_info *denali) | |
1334 | { | |
db9a3210 CD |
1335 | /* tell driver how many bit controller will skip before |
1336 | * writing ECC code in OOB, this register may be already | |
1337 | * set by firmware. So we read this value out. | |
1338 | * if this value is 0, just let it be. | |
1339 | * */ | |
1340 | denali->bbtskipbytes = ioread32(denali->flash_reg + | |
1341 | SPARE_AREA_SKIP_BYTES); | |
bc27ede3 | 1342 | detect_max_banks(denali); |
eda936ef | 1343 | denali_nand_reset(denali); |
24c3fa36 CD |
1344 | iowrite32(0x0F, denali->flash_reg + RB_PIN_ENABLED); |
1345 | iowrite32(CHIP_EN_DONT_CARE__FLAG, | |
bdca6dae | 1346 | denali->flash_reg + CHIP_ENABLE_DONT_CARE); |
ce082596 | 1347 | |
24c3fa36 | 1348 | iowrite32(0xffff, denali->flash_reg + SPARE_AREA_MARKER); |
ce082596 JR |
1349 | |
1350 | /* Should set value for these registers when init */ | |
24c3fa36 CD |
1351 | iowrite32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES); |
1352 | iowrite32(1, denali->flash_reg + ECC_ENABLE); | |
5eab6aaa CD |
1353 | denali_nand_timing_set(denali); |
1354 | denali_irq_init(denali); | |
ce082596 JR |
1355 | } |
1356 | ||
db9a3210 CD |
1357 | /* Althogh controller spec said SLC ECC is forceb to be 4bit, |
1358 | * but denali controller in MRST only support 15bit and 8bit ECC | |
1359 | * correction | |
1360 | * */ | |
1361 | #define ECC_8BITS 14 | |
1362 | static struct nand_ecclayout nand_8bit_oob = { | |
1363 | .eccbytes = 14, | |
ce082596 JR |
1364 | }; |
1365 | ||
db9a3210 CD |
1366 | #define ECC_15BITS 26 |
1367 | static struct nand_ecclayout nand_15bit_oob = { | |
1368 | .eccbytes = 26, | |
ce082596 JR |
1369 | }; |
1370 | ||
1371 | static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' }; | |
1372 | static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' }; | |
1373 | ||
1374 | static struct nand_bbt_descr bbt_main_descr = { | |
1375 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
1376 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
1377 | .offs = 8, | |
1378 | .len = 4, | |
1379 | .veroffs = 12, | |
1380 | .maxblocks = 4, | |
1381 | .pattern = bbt_pattern, | |
1382 | }; | |
1383 | ||
1384 | static struct nand_bbt_descr bbt_mirror_descr = { | |
1385 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
1386 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
1387 | .offs = 8, | |
1388 | .len = 4, | |
1389 | .veroffs = 12, | |
1390 | .maxblocks = 4, | |
1391 | .pattern = mirror_pattern, | |
1392 | }; | |
1393 | ||
421f91d2 | 1394 | /* initialize driver data structures */ |
8c519436 | 1395 | static void denali_drv_init(struct denali_nand_info *denali) |
ce082596 JR |
1396 | { |
1397 | denali->idx = 0; | |
1398 | ||
1399 | /* setup interrupt handler */ | |
5bac3acf | 1400 | /* the completion object will be used to notify |
ce082596 JR |
1401 | * the callee that the interrupt is done */ |
1402 | init_completion(&denali->complete); | |
1403 | ||
1404 | /* the spinlock will be used to synchronize the ISR | |
5bac3acf | 1405 | * with any element that might be access shared |
ce082596 JR |
1406 | * data (interrupt status) */ |
1407 | spin_lock_init(&denali->irq_lock); | |
1408 | ||
1409 | /* indicate that MTD has not selected a valid bank yet */ | |
1410 | denali->flash_bank = CHIP_SELECT_INVALID; | |
1411 | ||
1412 | /* initialize our irq_status variable to indicate no interrupts */ | |
1413 | denali->irq_status = 0; | |
1414 | } | |
1415 | ||
2a0a288e | 1416 | int denali_init(struct denali_nand_info *denali) |
ce082596 | 1417 | { |
2a0a288e | 1418 | int ret; |
ce082596 | 1419 | |
2a0a288e | 1420 | if (denali->platform == INTEL_CE4100) { |
5bac3acf C |
1421 | /* Due to a silicon limitation, we can only support |
1422 | * ONFI timing mode 1 and below. | |
1423 | */ | |
345b1d3b | 1424 | if (onfi_timing_mode < -1 || onfi_timing_mode > 1) { |
2a0a288e DN |
1425 | pr_err("Intel CE4100 only supports ONFI timing mode 1 or below\n"); |
1426 | return -EINVAL; | |
ce082596 JR |
1427 | } |
1428 | } | |
1429 | ||
e07caa36 HS |
1430 | /* allocate a temporary buffer for nand_scan_ident() */ |
1431 | denali->buf.buf = devm_kzalloc(denali->dev, PAGE_SIZE, | |
1432 | GFP_DMA | GFP_KERNEL); | |
1433 | if (!denali->buf.buf) | |
1434 | return -ENOMEM; | |
ce082596 | 1435 | |
2a0a288e | 1436 | denali->mtd.dev.parent = denali->dev; |
ce082596 JR |
1437 | denali_hw_init(denali); |
1438 | denali_drv_init(denali); | |
1439 | ||
5eab6aaa CD |
1440 | /* denali_isr register is done after all the hardware |
1441 | * initilization is finished*/ | |
2a0a288e | 1442 | if (request_irq(denali->irq, denali_isr, IRQF_SHARED, |
ce082596 | 1443 | DENALI_NAND_NAME, denali)) { |
2a0a288e DN |
1444 | pr_err("Spectra: Unable to allocate IRQ\n"); |
1445 | return -ENODEV; | |
ce082596 JR |
1446 | } |
1447 | ||
1448 | /* now that our ISR is registered, we can enable interrupts */ | |
eda936ef | 1449 | denali_set_intr_modes(denali, true); |
5eab6aaa | 1450 | denali->mtd.name = "denali-nand"; |
ce082596 JR |
1451 | denali->mtd.owner = THIS_MODULE; |
1452 | denali->mtd.priv = &denali->nand; | |
1453 | ||
1454 | /* register the driver with the NAND core subsystem */ | |
1455 | denali->nand.select_chip = denali_select_chip; | |
1456 | denali->nand.cmdfunc = denali_cmdfunc; | |
1457 | denali->nand.read_byte = denali_read_byte; | |
1458 | denali->nand.waitfunc = denali_waitfunc; | |
1459 | ||
5bac3acf | 1460 | /* scan for NAND devices attached to the controller |
ce082596 | 1461 | * this is the first stage in a two step process to register |
5bac3acf | 1462 | * with the nand subsystem */ |
c89eeda8 | 1463 | if (nand_scan_ident(&denali->mtd, denali->max_banks, NULL)) { |
ce082596 | 1464 | ret = -ENXIO; |
5c0eb900 | 1465 | goto failed_req_irq; |
ce082596 | 1466 | } |
5bac3acf | 1467 | |
e07caa36 HS |
1468 | /* allocate the right size buffer now */ |
1469 | devm_kfree(denali->dev, denali->buf.buf); | |
1470 | denali->buf.buf = devm_kzalloc(denali->dev, | |
1471 | denali->mtd.writesize + denali->mtd.oobsize, | |
1472 | GFP_KERNEL); | |
1473 | if (!denali->buf.buf) { | |
1474 | ret = -ENOMEM; | |
1475 | goto failed_req_irq; | |
1476 | } | |
1477 | ||
1478 | /* Is 32-bit DMA supported? */ | |
1479 | ret = dma_set_mask(denali->dev, DMA_BIT_MASK(32)); | |
1480 | if (ret) { | |
1481 | pr_err("Spectra: no usable DMA configuration\n"); | |
1482 | goto failed_req_irq; | |
1483 | } | |
1484 | ||
1485 | denali->buf.dma_buf = dma_map_single(denali->dev, denali->buf.buf, | |
1486 | denali->mtd.writesize + denali->mtd.oobsize, | |
1487 | DMA_BIDIRECTIONAL); | |
1488 | if (dma_mapping_error(denali->dev, denali->buf.dma_buf)) { | |
1489 | dev_err(denali->dev, "Spectra: failed to map DMA buffer\n"); | |
1490 | ret = -EIO; | |
5c0eb900 | 1491 | goto failed_req_irq; |
66406524 CD |
1492 | } |
1493 | ||
08b9ab99 CD |
1494 | /* support for multi nand |
1495 | * MTD known nothing about multi nand, | |
1496 | * so we should tell it the real pagesize | |
1497 | * and anything necessery | |
1498 | */ | |
1499 | denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED); | |
1500 | denali->nand.chipsize <<= (denali->devnum - 1); | |
1501 | denali->nand.page_shift += (denali->devnum - 1); | |
1502 | denali->nand.pagemask = (denali->nand.chipsize >> | |
1503 | denali->nand.page_shift) - 1; | |
1504 | denali->nand.bbt_erase_shift += (denali->devnum - 1); | |
1505 | denali->nand.phys_erase_shift = denali->nand.bbt_erase_shift; | |
1506 | denali->nand.chip_shift += (denali->devnum - 1); | |
1507 | denali->mtd.writesize <<= (denali->devnum - 1); | |
1508 | denali->mtd.oobsize <<= (denali->devnum - 1); | |
1509 | denali->mtd.erasesize <<= (denali->devnum - 1); | |
1510 | denali->mtd.size = denali->nand.numchips * denali->nand.chipsize; | |
1511 | denali->bbtskipbytes *= denali->devnum; | |
1512 | ||
5bac3acf C |
1513 | /* second stage of the NAND scan |
1514 | * this stage requires information regarding ECC and | |
1515 | * bad block management. */ | |
ce082596 JR |
1516 | |
1517 | /* Bad block management */ | |
1518 | denali->nand.bbt_td = &bbt_main_descr; | |
1519 | denali->nand.bbt_md = &bbt_mirror_descr; | |
1520 | ||
1521 | /* skip the scan for now until we have OOB read and write support */ | |
bb9ebd4e | 1522 | denali->nand.bbt_options |= NAND_BBT_USE_FLASH; |
a40f7341 | 1523 | denali->nand.options |= NAND_SKIP_BBTSCAN; |
ce082596 JR |
1524 | denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME; |
1525 | ||
db9a3210 CD |
1526 | /* Denali Controller only support 15bit and 8bit ECC in MRST, |
1527 | * so just let controller do 15bit ECC for MLC and 8bit ECC for | |
1528 | * SLC if possible. | |
1529 | * */ | |
1d0ed69d | 1530 | if (!nand_is_slc(&denali->nand) && |
db9a3210 CD |
1531 | (denali->mtd.oobsize > (denali->bbtskipbytes + |
1532 | ECC_15BITS * (denali->mtd.writesize / | |
1533 | ECC_SECTOR_SIZE)))) { | |
1534 | /* if MLC OOB size is large enough, use 15bit ECC*/ | |
6a918bad | 1535 | denali->nand.ecc.strength = 15; |
db9a3210 CD |
1536 | denali->nand.ecc.layout = &nand_15bit_oob; |
1537 | denali->nand.ecc.bytes = ECC_15BITS; | |
24c3fa36 | 1538 | iowrite32(15, denali->flash_reg + ECC_CORRECTION); |
db9a3210 CD |
1539 | } else if (denali->mtd.oobsize < (denali->bbtskipbytes + |
1540 | ECC_8BITS * (denali->mtd.writesize / | |
1541 | ECC_SECTOR_SIZE))) { | |
2a0a288e DN |
1542 | pr_err("Your NAND chip OOB is not large enough to \ |
1543 | contain 8bit ECC correction codes"); | |
5c0eb900 | 1544 | goto failed_req_irq; |
db9a3210 | 1545 | } else { |
6a918bad | 1546 | denali->nand.ecc.strength = 8; |
db9a3210 CD |
1547 | denali->nand.ecc.layout = &nand_8bit_oob; |
1548 | denali->nand.ecc.bytes = ECC_8BITS; | |
24c3fa36 | 1549 | iowrite32(8, denali->flash_reg + ECC_CORRECTION); |
ce082596 JR |
1550 | } |
1551 | ||
08b9ab99 | 1552 | denali->nand.ecc.bytes *= denali->devnum; |
6a918bad | 1553 | denali->nand.ecc.strength *= denali->devnum; |
db9a3210 CD |
1554 | denali->nand.ecc.layout->eccbytes *= |
1555 | denali->mtd.writesize / ECC_SECTOR_SIZE; | |
1556 | denali->nand.ecc.layout->oobfree[0].offset = | |
1557 | denali->bbtskipbytes + denali->nand.ecc.layout->eccbytes; | |
1558 | denali->nand.ecc.layout->oobfree[0].length = | |
1559 | denali->mtd.oobsize - denali->nand.ecc.layout->eccbytes - | |
1560 | denali->bbtskipbytes; | |
1561 | ||
66406524 CD |
1562 | /* Let driver know the total blocks number and |
1563 | * how many blocks contained by each nand chip. | |
1564 | * blksperchip will help driver to know how many | |
1565 | * blocks is taken by FW. | |
1566 | * */ | |
1567 | denali->totalblks = denali->mtd.size >> | |
1568 | denali->nand.phys_erase_shift; | |
1569 | denali->blksperchip = denali->totalblks / denali->nand.numchips; | |
1570 | ||
5bac3acf C |
1571 | /* These functions are required by the NAND core framework, otherwise, |
1572 | * the NAND core will assert. However, we don't need them, so we'll stub | |
1573 | * them out. */ | |
ce082596 JR |
1574 | denali->nand.ecc.calculate = denali_ecc_calculate; |
1575 | denali->nand.ecc.correct = denali_ecc_correct; | |
1576 | denali->nand.ecc.hwctl = denali_ecc_hwctl; | |
1577 | ||
1578 | /* override the default read operations */ | |
08b9ab99 | 1579 | denali->nand.ecc.size = ECC_SECTOR_SIZE * denali->devnum; |
ce082596 JR |
1580 | denali->nand.ecc.read_page = denali_read_page; |
1581 | denali->nand.ecc.read_page_raw = denali_read_page_raw; | |
1582 | denali->nand.ecc.write_page = denali_write_page; | |
1583 | denali->nand.ecc.write_page_raw = denali_write_page_raw; | |
1584 | denali->nand.ecc.read_oob = denali_read_oob; | |
1585 | denali->nand.ecc.write_oob = denali_write_oob; | |
49c50b97 | 1586 | denali->nand.erase = denali_erase; |
ce082596 | 1587 | |
345b1d3b | 1588 | if (nand_scan_tail(&denali->mtd)) { |
ce082596 | 1589 | ret = -ENXIO; |
5c0eb900 | 1590 | goto failed_req_irq; |
ce082596 JR |
1591 | } |
1592 | ||
ee0e87b1 | 1593 | ret = mtd_device_register(&denali->mtd, NULL, 0); |
ce082596 | 1594 | if (ret) { |
2a0a288e | 1595 | dev_err(denali->dev, "Spectra: Failed to register MTD: %d\n", |
7cfffac0 | 1596 | ret); |
5c0eb900 | 1597 | goto failed_req_irq; |
ce082596 JR |
1598 | } |
1599 | return 0; | |
1600 | ||
5c0eb900 | 1601 | failed_req_irq: |
2a0a288e DN |
1602 | denali_irq_cleanup(denali->irq, denali); |
1603 | ||
ce082596 JR |
1604 | return ret; |
1605 | } | |
2a0a288e | 1606 | EXPORT_SYMBOL(denali_init); |
ce082596 JR |
1607 | |
1608 | /* driver exit point */ | |
2a0a288e | 1609 | void denali_remove(struct denali_nand_info *denali) |
ce082596 | 1610 | { |
2a0a288e | 1611 | denali_irq_cleanup(denali->irq, denali); |
e07caa36 HS |
1612 | dma_unmap_single(denali->dev, denali->buf.dma_buf, |
1613 | denali->mtd.writesize + denali->mtd.oobsize, | |
2a0a288e | 1614 | DMA_BIDIRECTIONAL); |
ce082596 | 1615 | } |
2a0a288e | 1616 | EXPORT_SYMBOL(denali_remove); |