Commit | Line | Data |
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ce082596 JR |
1 | /* |
2 | * NAND Flash Controller Device Driver | |
3 | * Copyright © 2009-2010, Intel Corporation and its suppliers. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | * | |
18 | */ | |
19 | ||
20 | #include <linux/interrupt.h> | |
21 | #include <linux/delay.h> | |
84457949 | 22 | #include <linux/dma-mapping.h> |
ce082596 JR |
23 | #include <linux/wait.h> |
24 | #include <linux/mutex.h> | |
b8664b37 | 25 | #include <linux/slab.h> |
ce082596 JR |
26 | #include <linux/pci.h> |
27 | #include <linux/mtd/mtd.h> | |
28 | #include <linux/module.h> | |
29 | ||
30 | #include "denali.h" | |
31 | ||
32 | MODULE_LICENSE("GPL"); | |
33 | ||
5bac3acf | 34 | /* We define a module parameter that allows the user to override |
ce082596 JR |
35 | * the hardware and decide what timing mode should be used. |
36 | */ | |
37 | #define NAND_DEFAULT_TIMINGS -1 | |
38 | ||
39 | static int onfi_timing_mode = NAND_DEFAULT_TIMINGS; | |
40 | module_param(onfi_timing_mode, int, S_IRUGO); | |
bdca6dae CD |
41 | MODULE_PARM_DESC(onfi_timing_mode, "Overrides default ONFI setting." |
42 | " -1 indicates use default timings"); | |
ce082596 JR |
43 | |
44 | #define DENALI_NAND_NAME "denali-nand" | |
45 | ||
46 | /* We define a macro here that combines all interrupts this driver uses into | |
47 | * a single constant value, for convenience. */ | |
9589bf5b JI |
48 | #define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \ |
49 | INTR_STATUS__ECC_TRANSACTION_DONE | \ | |
50 | INTR_STATUS__ECC_ERR | \ | |
51 | INTR_STATUS__PROGRAM_FAIL | \ | |
52 | INTR_STATUS__LOAD_COMP | \ | |
53 | INTR_STATUS__PROGRAM_COMP | \ | |
54 | INTR_STATUS__TIME_OUT | \ | |
55 | INTR_STATUS__ERASE_FAIL | \ | |
56 | INTR_STATUS__RST_COMP | \ | |
57 | INTR_STATUS__ERASE_COMP) | |
ce082596 | 58 | |
5bac3acf | 59 | /* indicates whether or not the internal value for the flash bank is |
b292c341 | 60 | * valid or not */ |
5bac3acf | 61 | #define CHIP_SELECT_INVALID -1 |
ce082596 JR |
62 | |
63 | #define SUPPORT_8BITECC 1 | |
64 | ||
5bac3acf | 65 | /* This macro divides two integers and rounds fractional values up |
ce082596 JR |
66 | * to the nearest integer value. */ |
67 | #define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y))) | |
68 | ||
69 | /* this macro allows us to convert from an MTD structure to our own | |
70 | * device context (denali) structure. | |
71 | */ | |
72 | #define mtd_to_denali(m) container_of(m, struct denali_nand_info, mtd) | |
73 | ||
74 | /* These constants are defined by the driver to enable common driver | |
b292c341 | 75 | * configuration options. */ |
ce082596 JR |
76 | #define SPARE_ACCESS 0x41 |
77 | #define MAIN_ACCESS 0x42 | |
78 | #define MAIN_SPARE_ACCESS 0x43 | |
79 | ||
80 | #define DENALI_READ 0 | |
81 | #define DENALI_WRITE 0x100 | |
82 | ||
83 | /* types of device accesses. We can issue commands and get status */ | |
84 | #define COMMAND_CYCLE 0 | |
85 | #define ADDR_CYCLE 1 | |
86 | #define STATUS_CYCLE 2 | |
87 | ||
5bac3acf | 88 | /* this is a helper macro that allows us to |
ce082596 JR |
89 | * format the bank into the proper bits for the controller */ |
90 | #define BANK(x) ((x) << 24) | |
91 | ||
92 | /* List of platforms this NAND controller has be integrated into */ | |
93 | static const struct pci_device_id denali_pci_ids[] = { | |
94 | { PCI_VDEVICE(INTEL, 0x0701), INTEL_CE4100 }, | |
95 | { PCI_VDEVICE(INTEL, 0x0809), INTEL_MRST }, | |
96 | { /* end: all zeroes */ } | |
97 | }; | |
98 | ||
ce082596 JR |
99 | /* forward declarations */ |
100 | static void clear_interrupts(struct denali_nand_info *denali); | |
bdca6dae CD |
101 | static uint32_t wait_for_irq(struct denali_nand_info *denali, |
102 | uint32_t irq_mask); | |
103 | static void denali_irq_enable(struct denali_nand_info *denali, | |
104 | uint32_t int_mask); | |
ce082596 JR |
105 | static uint32_t read_interrupt_status(struct denali_nand_info *denali); |
106 | ||
bdca6dae CD |
107 | /* Certain operations for the denali NAND controller use |
108 | * an indexed mode to read/write data. The operation is | |
109 | * performed by writing the address value of the command | |
110 | * to the device memory followed by the data. This function | |
111 | * abstracts this common operation. | |
ce082596 | 112 | */ |
bdca6dae CD |
113 | static void index_addr(struct denali_nand_info *denali, |
114 | uint32_t address, uint32_t data) | |
ce082596 | 115 | { |
24c3fa36 CD |
116 | iowrite32(address, denali->flash_mem); |
117 | iowrite32(data, denali->flash_mem + 0x10); | |
ce082596 JR |
118 | } |
119 | ||
120 | /* Perform an indexed read of the device */ | |
121 | static void index_addr_read_data(struct denali_nand_info *denali, | |
122 | uint32_t address, uint32_t *pdata) | |
123 | { | |
24c3fa36 | 124 | iowrite32(address, denali->flash_mem); |
ce082596 JR |
125 | *pdata = ioread32(denali->flash_mem + 0x10); |
126 | } | |
127 | ||
5bac3acf | 128 | /* We need to buffer some data for some of the NAND core routines. |
ce082596 JR |
129 | * The operations manage buffering that data. */ |
130 | static void reset_buf(struct denali_nand_info *denali) | |
131 | { | |
132 | denali->buf.head = denali->buf.tail = 0; | |
133 | } | |
134 | ||
135 | static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte) | |
136 | { | |
137 | BUG_ON(denali->buf.tail >= sizeof(denali->buf.buf)); | |
138 | denali->buf.buf[denali->buf.tail++] = byte; | |
139 | } | |
140 | ||
141 | /* reads the status of the device */ | |
142 | static void read_status(struct denali_nand_info *denali) | |
143 | { | |
144 | uint32_t cmd = 0x0; | |
145 | ||
146 | /* initialize the data buffer to store status */ | |
147 | reset_buf(denali); | |
148 | ||
f0bc0c77 CD |
149 | cmd = ioread32(denali->flash_reg + WRITE_PROTECT); |
150 | if (cmd) | |
151 | write_byte_to_buf(denali, NAND_STATUS_WP); | |
152 | else | |
153 | write_byte_to_buf(denali, 0); | |
ce082596 JR |
154 | } |
155 | ||
156 | /* resets a specific device connected to the core */ | |
157 | static void reset_bank(struct denali_nand_info *denali) | |
158 | { | |
159 | uint32_t irq_status = 0; | |
9589bf5b JI |
160 | uint32_t irq_mask = INTR_STATUS__RST_COMP | |
161 | INTR_STATUS__TIME_OUT; | |
ce082596 JR |
162 | |
163 | clear_interrupts(denali); | |
164 | ||
9589bf5b | 165 | iowrite32(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET); |
ce082596 JR |
166 | |
167 | irq_status = wait_for_irq(denali, irq_mask); | |
5bac3acf | 168 | |
9589bf5b | 169 | if (irq_status & INTR_STATUS__TIME_OUT) |
84457949 | 170 | dev_err(denali->dev, "reset bank failed.\n"); |
ce082596 JR |
171 | } |
172 | ||
173 | /* Reset the flash controller */ | |
eda936ef | 174 | static uint16_t denali_nand_reset(struct denali_nand_info *denali) |
ce082596 JR |
175 | { |
176 | uint32_t i; | |
177 | ||
84457949 | 178 | dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", |
ce082596 JR |
179 | __FILE__, __LINE__, __func__); |
180 | ||
181 | for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++) | |
9589bf5b JI |
182 | iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT, |
183 | denali->flash_reg + INTR_STATUS(i)); | |
ce082596 JR |
184 | |
185 | for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++) { | |
9589bf5b | 186 | iowrite32(1 << i, denali->flash_reg + DEVICE_RESET); |
bdca6dae | 187 | while (!(ioread32(denali->flash_reg + |
9589bf5b JI |
188 | INTR_STATUS(i)) & |
189 | (INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT))) | |
628bfd41 | 190 | cpu_relax(); |
9589bf5b JI |
191 | if (ioread32(denali->flash_reg + INTR_STATUS(i)) & |
192 | INTR_STATUS__TIME_OUT) | |
84457949 | 193 | dev_dbg(denali->dev, |
ce082596 JR |
194 | "NAND Reset operation timed out on bank %d\n", i); |
195 | } | |
196 | ||
197 | for (i = 0; i < LLD_MAX_FLASH_BANKS; i++) | |
9589bf5b JI |
198 | iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT, |
199 | denali->flash_reg + INTR_STATUS(i)); | |
ce082596 JR |
200 | |
201 | return PASS; | |
202 | } | |
203 | ||
bdca6dae CD |
204 | /* this routine calculates the ONFI timing values for a given mode and |
205 | * programs the clocking register accordingly. The mode is determined by | |
206 | * the get_onfi_nand_para routine. | |
ce082596 | 207 | */ |
eda936ef | 208 | static void nand_onfi_timing_set(struct denali_nand_info *denali, |
bdca6dae | 209 | uint16_t mode) |
ce082596 JR |
210 | { |
211 | uint16_t Trea[6] = {40, 30, 25, 20, 20, 16}; | |
212 | uint16_t Trp[6] = {50, 25, 17, 15, 12, 10}; | |
213 | uint16_t Treh[6] = {30, 15, 15, 10, 10, 7}; | |
214 | uint16_t Trc[6] = {100, 50, 35, 30, 25, 20}; | |
215 | uint16_t Trhoh[6] = {0, 15, 15, 15, 15, 15}; | |
216 | uint16_t Trloh[6] = {0, 0, 0, 0, 5, 5}; | |
217 | uint16_t Tcea[6] = {100, 45, 30, 25, 25, 25}; | |
218 | uint16_t Tadl[6] = {200, 100, 100, 100, 70, 70}; | |
219 | uint16_t Trhw[6] = {200, 100, 100, 100, 100, 100}; | |
220 | uint16_t Trhz[6] = {200, 100, 100, 100, 100, 100}; | |
221 | uint16_t Twhr[6] = {120, 80, 80, 60, 60, 60}; | |
222 | uint16_t Tcs[6] = {70, 35, 25, 25, 20, 15}; | |
223 | ||
224 | uint16_t TclsRising = 1; | |
225 | uint16_t data_invalid_rhoh, data_invalid_rloh, data_invalid; | |
226 | uint16_t dv_window = 0; | |
227 | uint16_t en_lo, en_hi; | |
228 | uint16_t acc_clks; | |
229 | uint16_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt; | |
230 | ||
84457949 | 231 | dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", |
ce082596 JR |
232 | __FILE__, __LINE__, __func__); |
233 | ||
234 | en_lo = CEIL_DIV(Trp[mode], CLK_X); | |
235 | en_hi = CEIL_DIV(Treh[mode], CLK_X); | |
236 | #if ONFI_BLOOM_TIME | |
237 | if ((en_hi * CLK_X) < (Treh[mode] + 2)) | |
238 | en_hi++; | |
239 | #endif | |
240 | ||
241 | if ((en_lo + en_hi) * CLK_X < Trc[mode]) | |
242 | en_lo += CEIL_DIV((Trc[mode] - (en_lo + en_hi) * CLK_X), CLK_X); | |
243 | ||
244 | if ((en_lo + en_hi) < CLK_MULTI) | |
245 | en_lo += CLK_MULTI - en_lo - en_hi; | |
246 | ||
247 | while (dv_window < 8) { | |
248 | data_invalid_rhoh = en_lo * CLK_X + Trhoh[mode]; | |
249 | ||
250 | data_invalid_rloh = (en_lo + en_hi) * CLK_X + Trloh[mode]; | |
251 | ||
252 | data_invalid = | |
253 | data_invalid_rhoh < | |
254 | data_invalid_rloh ? data_invalid_rhoh : data_invalid_rloh; | |
255 | ||
256 | dv_window = data_invalid - Trea[mode]; | |
257 | ||
258 | if (dv_window < 8) | |
259 | en_lo++; | |
260 | } | |
261 | ||
262 | acc_clks = CEIL_DIV(Trea[mode], CLK_X); | |
263 | ||
264 | while (((acc_clks * CLK_X) - Trea[mode]) < 3) | |
265 | acc_clks++; | |
266 | ||
267 | if ((data_invalid - acc_clks * CLK_X) < 2) | |
84457949 | 268 | dev_warn(denali->dev, "%s, Line %d: Warning!\n", |
ce082596 JR |
269 | __FILE__, __LINE__); |
270 | ||
271 | addr_2_data = CEIL_DIV(Tadl[mode], CLK_X); | |
272 | re_2_we = CEIL_DIV(Trhw[mode], CLK_X); | |
273 | re_2_re = CEIL_DIV(Trhz[mode], CLK_X); | |
274 | we_2_re = CEIL_DIV(Twhr[mode], CLK_X); | |
275 | cs_cnt = CEIL_DIV((Tcs[mode] - Trp[mode]), CLK_X); | |
276 | if (!TclsRising) | |
277 | cs_cnt = CEIL_DIV(Tcs[mode], CLK_X); | |
278 | if (cs_cnt == 0) | |
279 | cs_cnt = 1; | |
280 | ||
281 | if (Tcea[mode]) { | |
282 | while (((cs_cnt * CLK_X) + Trea[mode]) < Tcea[mode]) | |
283 | cs_cnt++; | |
284 | } | |
285 | ||
286 | #if MODE5_WORKAROUND | |
287 | if (mode == 5) | |
288 | acc_clks = 5; | |
289 | #endif | |
290 | ||
291 | /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */ | |
292 | if ((ioread32(denali->flash_reg + MANUFACTURER_ID) == 0) && | |
293 | (ioread32(denali->flash_reg + DEVICE_ID) == 0x88)) | |
294 | acc_clks = 6; | |
295 | ||
24c3fa36 CD |
296 | iowrite32(acc_clks, denali->flash_reg + ACC_CLKS); |
297 | iowrite32(re_2_we, denali->flash_reg + RE_2_WE); | |
298 | iowrite32(re_2_re, denali->flash_reg + RE_2_RE); | |
299 | iowrite32(we_2_re, denali->flash_reg + WE_2_RE); | |
300 | iowrite32(addr_2_data, denali->flash_reg + ADDR_2_DATA); | |
301 | iowrite32(en_lo, denali->flash_reg + RDWR_EN_LO_CNT); | |
302 | iowrite32(en_hi, denali->flash_reg + RDWR_EN_HI_CNT); | |
303 | iowrite32(cs_cnt, denali->flash_reg + CS_SETUP_CNT); | |
ce082596 JR |
304 | } |
305 | ||
ce082596 JR |
306 | /* queries the NAND device to see what ONFI modes it supports. */ |
307 | static uint16_t get_onfi_nand_para(struct denali_nand_info *denali) | |
308 | { | |
309 | int i; | |
4c03bbdf CD |
310 | /* we needn't to do a reset here because driver has already |
311 | * reset all the banks before | |
312 | * */ | |
ce082596 JR |
313 | if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) & |
314 | ONFI_TIMING_MODE__VALUE)) | |
315 | return FAIL; | |
316 | ||
317 | for (i = 5; i > 0; i--) { | |
bdca6dae CD |
318 | if (ioread32(denali->flash_reg + ONFI_TIMING_MODE) & |
319 | (0x01 << i)) | |
ce082596 JR |
320 | break; |
321 | } | |
322 | ||
eda936ef | 323 | nand_onfi_timing_set(denali, i); |
ce082596 JR |
324 | |
325 | /* By now, all the ONFI devices we know support the page cache */ | |
326 | /* rw feature. So here we enable the pipeline_rw_ahead feature */ | |
327 | /* iowrite32(1, denali->flash_reg + CACHE_WRITE_ENABLE); */ | |
328 | /* iowrite32(1, denali->flash_reg + CACHE_READ_ENABLE); */ | |
329 | ||
330 | return PASS; | |
331 | } | |
332 | ||
4c03bbdf CD |
333 | static void get_samsung_nand_para(struct denali_nand_info *denali, |
334 | uint8_t device_id) | |
ce082596 | 335 | { |
4c03bbdf | 336 | if (device_id == 0xd3) { /* Samsung K9WAG08U1A */ |
ce082596 | 337 | /* Set timing register values according to datasheet */ |
24c3fa36 CD |
338 | iowrite32(5, denali->flash_reg + ACC_CLKS); |
339 | iowrite32(20, denali->flash_reg + RE_2_WE); | |
340 | iowrite32(12, denali->flash_reg + WE_2_RE); | |
341 | iowrite32(14, denali->flash_reg + ADDR_2_DATA); | |
342 | iowrite32(3, denali->flash_reg + RDWR_EN_LO_CNT); | |
343 | iowrite32(2, denali->flash_reg + RDWR_EN_HI_CNT); | |
344 | iowrite32(2, denali->flash_reg + CS_SETUP_CNT); | |
ce082596 | 345 | } |
ce082596 JR |
346 | } |
347 | ||
348 | static void get_toshiba_nand_para(struct denali_nand_info *denali) | |
349 | { | |
ce082596 JR |
350 | uint32_t tmp; |
351 | ||
352 | /* Workaround to fix a controller bug which reports a wrong */ | |
353 | /* spare area size for some kind of Toshiba NAND device */ | |
354 | if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) && | |
355 | (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) { | |
24c3fa36 | 356 | iowrite32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); |
ce082596 JR |
357 | tmp = ioread32(denali->flash_reg + DEVICES_CONNECTED) * |
358 | ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE); | |
24c3fa36 | 359 | iowrite32(tmp, |
bdca6dae | 360 | denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); |
ce082596 | 361 | #if SUPPORT_15BITECC |
24c3fa36 | 362 | iowrite32(15, denali->flash_reg + ECC_CORRECTION); |
ce082596 | 363 | #elif SUPPORT_8BITECC |
24c3fa36 | 364 | iowrite32(8, denali->flash_reg + ECC_CORRECTION); |
ce082596 JR |
365 | #endif |
366 | } | |
ce082596 JR |
367 | } |
368 | ||
ef41e1bb CD |
369 | static void get_hynix_nand_para(struct denali_nand_info *denali, |
370 | uint8_t device_id) | |
ce082596 | 371 | { |
ce082596 JR |
372 | uint32_t main_size, spare_size; |
373 | ||
ef41e1bb | 374 | switch (device_id) { |
ce082596 JR |
375 | case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */ |
376 | case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */ | |
24c3fa36 CD |
377 | iowrite32(128, denali->flash_reg + PAGES_PER_BLOCK); |
378 | iowrite32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE); | |
379 | iowrite32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); | |
bdca6dae CD |
380 | main_size = 4096 * |
381 | ioread32(denali->flash_reg + DEVICES_CONNECTED); | |
382 | spare_size = 224 * | |
383 | ioread32(denali->flash_reg + DEVICES_CONNECTED); | |
24c3fa36 | 384 | iowrite32(main_size, |
bdca6dae | 385 | denali->flash_reg + LOGICAL_PAGE_DATA_SIZE); |
24c3fa36 | 386 | iowrite32(spare_size, |
bdca6dae | 387 | denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); |
24c3fa36 | 388 | iowrite32(0, denali->flash_reg + DEVICE_WIDTH); |
ce082596 | 389 | #if SUPPORT_15BITECC |
24c3fa36 | 390 | iowrite32(15, denali->flash_reg + ECC_CORRECTION); |
ce082596 | 391 | #elif SUPPORT_8BITECC |
24c3fa36 | 392 | iowrite32(8, denali->flash_reg + ECC_CORRECTION); |
ce082596 | 393 | #endif |
ce082596 JR |
394 | break; |
395 | default: | |
84457949 | 396 | dev_warn(denali->dev, |
ce082596 JR |
397 | "Spectra: Unknown Hynix NAND (Device ID: 0x%x)." |
398 | "Will use default parameter values instead.\n", | |
66406524 | 399 | device_id); |
ce082596 JR |
400 | } |
401 | } | |
402 | ||
403 | /* determines how many NAND chips are connected to the controller. Note for | |
b292c341 | 404 | * Intel CE4100 devices we don't support more than one device. |
ce082596 JR |
405 | */ |
406 | static void find_valid_banks(struct denali_nand_info *denali) | |
407 | { | |
408 | uint32_t id[LLD_MAX_FLASH_BANKS]; | |
409 | int i; | |
410 | ||
411 | denali->total_used_banks = 1; | |
412 | for (i = 0; i < LLD_MAX_FLASH_BANKS; i++) { | |
413 | index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 0), 0x90); | |
414 | index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 1), 0); | |
bdca6dae CD |
415 | index_addr_read_data(denali, |
416 | (uint32_t)(MODE_11 | (i << 24) | 2), &id[i]); | |
ce082596 | 417 | |
84457949 | 418 | dev_dbg(denali->dev, |
ce082596 JR |
419 | "Return 1st ID for bank[%d]: %x\n", i, id[i]); |
420 | ||
421 | if (i == 0) { | |
422 | if (!(id[i] & 0x0ff)) | |
423 | break; /* WTF? */ | |
424 | } else { | |
425 | if ((id[i] & 0x0ff) == (id[0] & 0x0ff)) | |
426 | denali->total_used_banks++; | |
427 | else | |
428 | break; | |
429 | } | |
430 | } | |
431 | ||
345b1d3b | 432 | if (denali->platform == INTEL_CE4100) { |
ce082596 JR |
433 | /* Platform limitations of the CE4100 device limit |
434 | * users to a single chip solution for NAND. | |
5bac3acf C |
435 | * Multichip support is not enabled. |
436 | */ | |
345b1d3b | 437 | if (denali->total_used_banks != 1) { |
84457949 | 438 | dev_err(denali->dev, |
7cfffac0 | 439 | "Sorry, Intel CE4100 only supports " |
ce082596 JR |
440 | "a single NAND device.\n"); |
441 | BUG(); | |
442 | } | |
443 | } | |
84457949 | 444 | dev_dbg(denali->dev, |
ce082596 JR |
445 | "denali->total_used_banks: %d\n", denali->total_used_banks); |
446 | } | |
447 | ||
448 | static void detect_partition_feature(struct denali_nand_info *denali) | |
449 | { | |
66406524 CD |
450 | /* For MRST platform, denali->fwblks represent the |
451 | * number of blocks firmware is taken, | |
452 | * FW is in protect partition and MTD driver has no | |
453 | * permission to access it. So let driver know how many | |
454 | * blocks it can't touch. | |
455 | * */ | |
ce082596 | 456 | if (ioread32(denali->flash_reg + FEATURES) & FEATURES__PARTITION) { |
9589bf5b JI |
457 | if ((ioread32(denali->flash_reg + PERM_SRC_ID(1)) & |
458 | PERM_SRC_ID__SRCID) == SPECTRA_PARTITION_ID) { | |
66406524 | 459 | denali->fwblks = |
9589bf5b JI |
460 | ((ioread32(denali->flash_reg + MIN_MAX_BANK(1)) & |
461 | MIN_MAX_BANK__MIN_VALUE) * | |
66406524 | 462 | denali->blksperchip) |
ce082596 | 463 | + |
9589bf5b JI |
464 | (ioread32(denali->flash_reg + MIN_BLK_ADDR(1)) & |
465 | MIN_BLK_ADDR__VALUE); | |
66406524 CD |
466 | } else |
467 | denali->fwblks = SPECTRA_START_BLOCK; | |
468 | } else | |
469 | denali->fwblks = SPECTRA_START_BLOCK; | |
ce082596 JR |
470 | } |
471 | ||
eda936ef | 472 | static uint16_t denali_nand_timing_set(struct denali_nand_info *denali) |
ce082596 JR |
473 | { |
474 | uint16_t status = PASS; | |
ef41e1bb CD |
475 | uint32_t id_bytes[5], addr; |
476 | uint8_t i, maf_id, device_id; | |
ce082596 | 477 | |
84457949 | 478 | dev_dbg(denali->dev, |
7cfffac0 CD |
479 | "%s, Line %d, Function: %s\n", |
480 | __FILE__, __LINE__, __func__); | |
ce082596 | 481 | |
ef41e1bb CD |
482 | /* Use read id method to get device ID and other |
483 | * params. For some NAND chips, controller can't | |
484 | * report the correct device ID by reading from | |
485 | * DEVICE_ID register | |
486 | * */ | |
487 | addr = (uint32_t)MODE_11 | BANK(denali->flash_bank); | |
488 | index_addr(denali, (uint32_t)addr | 0, 0x90); | |
489 | index_addr(denali, (uint32_t)addr | 1, 0); | |
490 | for (i = 0; i < 5; i++) | |
491 | index_addr_read_data(denali, addr | 2, &id_bytes[i]); | |
492 | maf_id = id_bytes[0]; | |
493 | device_id = id_bytes[1]; | |
ce082596 JR |
494 | |
495 | if (ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) & | |
496 | ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */ | |
497 | if (FAIL == get_onfi_nand_para(denali)) | |
498 | return FAIL; | |
ef41e1bb | 499 | } else if (maf_id == 0xEC) { /* Samsung NAND */ |
4c03bbdf | 500 | get_samsung_nand_para(denali, device_id); |
ef41e1bb | 501 | } else if (maf_id == 0x98) { /* Toshiba NAND */ |
ce082596 | 502 | get_toshiba_nand_para(denali); |
ef41e1bb CD |
503 | } else if (maf_id == 0xAD) { /* Hynix NAND */ |
504 | get_hynix_nand_para(denali, device_id); | |
ce082596 JR |
505 | } |
506 | ||
84457949 | 507 | dev_info(denali->dev, |
7cfffac0 CD |
508 | "Dump timing register values:" |
509 | "acc_clks: %d, re_2_we: %d, re_2_re: %d\n" | |
510 | "we_2_re: %d, addr_2_data: %d, rdwr_en_lo_cnt: %d\n" | |
ce082596 JR |
511 | "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n", |
512 | ioread32(denali->flash_reg + ACC_CLKS), | |
513 | ioread32(denali->flash_reg + RE_2_WE), | |
7cfffac0 | 514 | ioread32(denali->flash_reg + RE_2_RE), |
ce082596 JR |
515 | ioread32(denali->flash_reg + WE_2_RE), |
516 | ioread32(denali->flash_reg + ADDR_2_DATA), | |
517 | ioread32(denali->flash_reg + RDWR_EN_LO_CNT), | |
518 | ioread32(denali->flash_reg + RDWR_EN_HI_CNT), | |
519 | ioread32(denali->flash_reg + CS_SETUP_CNT)); | |
520 | ||
ce082596 JR |
521 | find_valid_banks(denali); |
522 | ||
523 | detect_partition_feature(denali); | |
524 | ||
ce082596 | 525 | /* If the user specified to override the default timings |
5bac3acf | 526 | * with a specific ONFI mode, we apply those changes here. |
ce082596 JR |
527 | */ |
528 | if (onfi_timing_mode != NAND_DEFAULT_TIMINGS) | |
eda936ef | 529 | nand_onfi_timing_set(denali, onfi_timing_mode); |
ce082596 JR |
530 | |
531 | return status; | |
532 | } | |
533 | ||
eda936ef | 534 | static void denali_set_intr_modes(struct denali_nand_info *denali, |
ce082596 JR |
535 | uint16_t INT_ENABLE) |
536 | { | |
84457949 | 537 | dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", |
ce082596 JR |
538 | __FILE__, __LINE__, __func__); |
539 | ||
540 | if (INT_ENABLE) | |
24c3fa36 | 541 | iowrite32(1, denali->flash_reg + GLOBAL_INT_ENABLE); |
ce082596 | 542 | else |
24c3fa36 | 543 | iowrite32(0, denali->flash_reg + GLOBAL_INT_ENABLE); |
ce082596 JR |
544 | } |
545 | ||
546 | /* validation function to verify that the controlling software is making | |
b292c341 | 547 | * a valid request |
ce082596 JR |
548 | */ |
549 | static inline bool is_flash_bank_valid(int flash_bank) | |
550 | { | |
5bac3acf | 551 | return (flash_bank >= 0 && flash_bank < 4); |
ce082596 JR |
552 | } |
553 | ||
554 | static void denali_irq_init(struct denali_nand_info *denali) | |
555 | { | |
556 | uint32_t int_mask = 0; | |
9589bf5b | 557 | int i; |
ce082596 JR |
558 | |
559 | /* Disable global interrupts */ | |
eda936ef | 560 | denali_set_intr_modes(denali, false); |
ce082596 JR |
561 | |
562 | int_mask = DENALI_IRQ_ALL; | |
563 | ||
564 | /* Clear all status bits */ | |
9589bf5b JI |
565 | for (i = 0; i < LLD_MAX_FLASH_BANKS; ++i) |
566 | iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS(i)); | |
ce082596 JR |
567 | |
568 | denali_irq_enable(denali, int_mask); | |
569 | } | |
570 | ||
571 | static void denali_irq_cleanup(int irqnum, struct denali_nand_info *denali) | |
572 | { | |
eda936ef | 573 | denali_set_intr_modes(denali, false); |
ce082596 JR |
574 | free_irq(irqnum, denali); |
575 | } | |
576 | ||
bdca6dae CD |
577 | static void denali_irq_enable(struct denali_nand_info *denali, |
578 | uint32_t int_mask) | |
ce082596 | 579 | { |
9589bf5b JI |
580 | int i; |
581 | ||
582 | for (i = 0; i < LLD_MAX_FLASH_BANKS; ++i) | |
583 | iowrite32(int_mask, denali->flash_reg + INTR_EN(i)); | |
ce082596 JR |
584 | } |
585 | ||
586 | /* This function only returns when an interrupt that this driver cares about | |
5bac3acf | 587 | * occurs. This is to reduce the overhead of servicing interrupts |
ce082596 JR |
588 | */ |
589 | static inline uint32_t denali_irq_detected(struct denali_nand_info *denali) | |
590 | { | |
a99d1796 | 591 | return read_interrupt_status(denali) & DENALI_IRQ_ALL; |
ce082596 JR |
592 | } |
593 | ||
594 | /* Interrupts are cleared by writing a 1 to the appropriate status bit */ | |
bdca6dae CD |
595 | static inline void clear_interrupt(struct denali_nand_info *denali, |
596 | uint32_t irq_mask) | |
ce082596 JR |
597 | { |
598 | uint32_t intr_status_reg = 0; | |
599 | ||
9589bf5b | 600 | intr_status_reg = INTR_STATUS(denali->flash_bank); |
ce082596 | 601 | |
24c3fa36 | 602 | iowrite32(irq_mask, denali->flash_reg + intr_status_reg); |
ce082596 JR |
603 | } |
604 | ||
605 | static void clear_interrupts(struct denali_nand_info *denali) | |
606 | { | |
607 | uint32_t status = 0x0; | |
608 | spin_lock_irq(&denali->irq_lock); | |
609 | ||
610 | status = read_interrupt_status(denali); | |
8ae61ebd | 611 | clear_interrupt(denali, status); |
ce082596 | 612 | |
ce082596 JR |
613 | denali->irq_status = 0x0; |
614 | spin_unlock_irq(&denali->irq_lock); | |
615 | } | |
616 | ||
617 | static uint32_t read_interrupt_status(struct denali_nand_info *denali) | |
618 | { | |
619 | uint32_t intr_status_reg = 0; | |
620 | ||
9589bf5b | 621 | intr_status_reg = INTR_STATUS(denali->flash_bank); |
ce082596 JR |
622 | |
623 | return ioread32(denali->flash_reg + intr_status_reg); | |
624 | } | |
625 | ||
5bac3acf C |
626 | /* This is the interrupt service routine. It handles all interrupts |
627 | * sent to this device. Note that on CE4100, this is a shared | |
628 | * interrupt. | |
ce082596 JR |
629 | */ |
630 | static irqreturn_t denali_isr(int irq, void *dev_id) | |
631 | { | |
632 | struct denali_nand_info *denali = dev_id; | |
633 | uint32_t irq_status = 0x0; | |
634 | irqreturn_t result = IRQ_NONE; | |
635 | ||
636 | spin_lock(&denali->irq_lock); | |
637 | ||
5bac3acf C |
638 | /* check to see if a valid NAND chip has |
639 | * been selected. | |
ce082596 | 640 | */ |
345b1d3b | 641 | if (is_flash_bank_valid(denali->flash_bank)) { |
5bac3acf | 642 | /* check to see if controller generated |
ce082596 | 643 | * the interrupt, since this is a shared interrupt */ |
bdca6dae CD |
644 | irq_status = denali_irq_detected(denali); |
645 | if (irq_status != 0) { | |
ce082596 JR |
646 | /* handle interrupt */ |
647 | /* first acknowledge it */ | |
648 | clear_interrupt(denali, irq_status); | |
649 | /* store the status in the device context for someone | |
650 | to read */ | |
651 | denali->irq_status |= irq_status; | |
652 | /* notify anyone who cares that it happened */ | |
653 | complete(&denali->complete); | |
654 | /* tell the OS that we've handled this */ | |
655 | result = IRQ_HANDLED; | |
656 | } | |
657 | } | |
658 | spin_unlock(&denali->irq_lock); | |
659 | return result; | |
660 | } | |
661 | #define BANK(x) ((x) << 24) | |
662 | ||
663 | static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask) | |
664 | { | |
665 | unsigned long comp_res = 0; | |
666 | uint32_t intr_status = 0; | |
667 | bool retry = false; | |
668 | unsigned long timeout = msecs_to_jiffies(1000); | |
669 | ||
345b1d3b | 670 | do { |
bdca6dae CD |
671 | comp_res = |
672 | wait_for_completion_timeout(&denali->complete, timeout); | |
ce082596 JR |
673 | spin_lock_irq(&denali->irq_lock); |
674 | intr_status = denali->irq_status; | |
675 | ||
345b1d3b | 676 | if (intr_status & irq_mask) { |
ce082596 JR |
677 | denali->irq_status &= ~irq_mask; |
678 | spin_unlock_irq(&denali->irq_lock); | |
ce082596 JR |
679 | /* our interrupt was detected */ |
680 | break; | |
345b1d3b | 681 | } else { |
5bac3acf C |
682 | /* these are not the interrupts you are looking for - |
683 | * need to wait again */ | |
ce082596 | 684 | spin_unlock_irq(&denali->irq_lock); |
ce082596 JR |
685 | retry = true; |
686 | } | |
687 | } while (comp_res != 0); | |
688 | ||
345b1d3b | 689 | if (comp_res == 0) { |
ce082596 | 690 | /* timeout */ |
5bac3acf C |
691 | printk(KERN_ERR "timeout occurred, status = 0x%x, mask = 0x%x\n", |
692 | intr_status, irq_mask); | |
ce082596 JR |
693 | |
694 | intr_status = 0; | |
695 | } | |
696 | return intr_status; | |
697 | } | |
698 | ||
5bac3acf | 699 | /* This helper function setups the registers for ECC and whether or not |
25985edc | 700 | * the spare area will be transferred. */ |
5bac3acf | 701 | static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en, |
ce082596 JR |
702 | bool transfer_spare) |
703 | { | |
5bac3acf | 704 | int ecc_en_flag = 0, transfer_spare_flag = 0; |
ce082596 JR |
705 | |
706 | /* set ECC, transfer spare bits if needed */ | |
707 | ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0; | |
708 | transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0; | |
709 | ||
710 | /* Enable spare area/ECC per user's request. */ | |
24c3fa36 CD |
711 | iowrite32(ecc_en_flag, denali->flash_reg + ECC_ENABLE); |
712 | iowrite32(transfer_spare_flag, | |
bdca6dae | 713 | denali->flash_reg + TRANSFER_SPARE_REG); |
ce082596 JR |
714 | } |
715 | ||
5bac3acf | 716 | /* sends a pipeline command operation to the controller. See the Denali NAND |
b292c341 | 717 | * controller's user guide for more information (section 4.2.3.6). |
ce082596 | 718 | */ |
bdca6dae CD |
719 | static int denali_send_pipeline_cmd(struct denali_nand_info *denali, |
720 | bool ecc_en, | |
721 | bool transfer_spare, | |
722 | int access_type, | |
723 | int op) | |
ce082596 JR |
724 | { |
725 | int status = PASS; | |
5bac3acf | 726 | uint32_t addr = 0x0, cmd = 0x0, page_count = 1, irq_status = 0, |
ce082596 JR |
727 | irq_mask = 0; |
728 | ||
a99d1796 | 729 | if (op == DENALI_READ) |
9589bf5b | 730 | irq_mask = INTR_STATUS__LOAD_COMP; |
a99d1796 CD |
731 | else if (op == DENALI_WRITE) |
732 | irq_mask = 0; | |
733 | else | |
734 | BUG(); | |
ce082596 JR |
735 | |
736 | setup_ecc_for_xfer(denali, ecc_en, transfer_spare); | |
737 | ||
ce082596 | 738 | /* clear interrupts */ |
5bac3acf | 739 | clear_interrupts(denali); |
ce082596 JR |
740 | |
741 | addr = BANK(denali->flash_bank) | denali->page; | |
742 | ||
345b1d3b | 743 | if (op == DENALI_WRITE && access_type != SPARE_ACCESS) { |
5bac3acf | 744 | cmd = MODE_01 | addr; |
24c3fa36 | 745 | iowrite32(cmd, denali->flash_mem); |
345b1d3b | 746 | } else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) { |
ce082596 | 747 | /* read spare area */ |
5bac3acf | 748 | cmd = MODE_10 | addr; |
ce082596 JR |
749 | index_addr(denali, (uint32_t)cmd, access_type); |
750 | ||
5bac3acf | 751 | cmd = MODE_01 | addr; |
24c3fa36 | 752 | iowrite32(cmd, denali->flash_mem); |
345b1d3b | 753 | } else if (op == DENALI_READ) { |
ce082596 | 754 | /* setup page read request for access type */ |
5bac3acf | 755 | cmd = MODE_10 | addr; |
ce082596 JR |
756 | index_addr(denali, (uint32_t)cmd, access_type); |
757 | ||
758 | /* page 33 of the NAND controller spec indicates we should not | |
5bac3acf | 759 | use the pipeline commands in Spare area only mode. So we |
ce082596 JR |
760 | don't. |
761 | */ | |
345b1d3b | 762 | if (access_type == SPARE_ACCESS) { |
ce082596 | 763 | cmd = MODE_01 | addr; |
24c3fa36 | 764 | iowrite32(cmd, denali->flash_mem); |
345b1d3b | 765 | } else { |
bdca6dae CD |
766 | index_addr(denali, (uint32_t)cmd, |
767 | 0x2000 | op | page_count); | |
5bac3acf C |
768 | |
769 | /* wait for command to be accepted | |
bdca6dae CD |
770 | * can always use status0 bit as the |
771 | * mask is identical for each | |
ce082596 JR |
772 | * bank. */ |
773 | irq_status = wait_for_irq(denali, irq_mask); | |
774 | ||
345b1d3b | 775 | if (irq_status == 0) { |
84457949 | 776 | dev_err(denali->dev, |
7cfffac0 CD |
777 | "cmd, page, addr on timeout " |
778 | "(0x%x, 0x%x, 0x%x)\n", | |
779 | cmd, denali->page, addr); | |
ce082596 | 780 | status = FAIL; |
345b1d3b | 781 | } else { |
ce082596 | 782 | cmd = MODE_01 | addr; |
24c3fa36 | 783 | iowrite32(cmd, denali->flash_mem); |
ce082596 JR |
784 | } |
785 | } | |
786 | } | |
787 | return status; | |
788 | } | |
789 | ||
790 | /* helper function that simply writes a buffer to the flash */ | |
bdca6dae CD |
791 | static int write_data_to_flash_mem(struct denali_nand_info *denali, |
792 | const uint8_t *buf, | |
793 | int len) | |
ce082596 JR |
794 | { |
795 | uint32_t i = 0, *buf32; | |
796 | ||
5bac3acf C |
797 | /* verify that the len is a multiple of 4. see comment in |
798 | * read_data_from_flash_mem() */ | |
ce082596 JR |
799 | BUG_ON((len % 4) != 0); |
800 | ||
801 | /* write the data to the flash memory */ | |
802 | buf32 = (uint32_t *)buf; | |
803 | for (i = 0; i < len / 4; i++) | |
24c3fa36 | 804 | iowrite32(*buf32++, denali->flash_mem + 0x10); |
5bac3acf | 805 | return i*4; /* intent is to return the number of bytes read */ |
ce082596 JR |
806 | } |
807 | ||
808 | /* helper function that simply reads a buffer from the flash */ | |
bdca6dae CD |
809 | static int read_data_from_flash_mem(struct denali_nand_info *denali, |
810 | uint8_t *buf, | |
811 | int len) | |
ce082596 JR |
812 | { |
813 | uint32_t i = 0, *buf32; | |
814 | ||
815 | /* we assume that len will be a multiple of 4, if not | |
816 | * it would be nice to know about it ASAP rather than | |
5bac3acf C |
817 | * have random failures... |
818 | * This assumption is based on the fact that this | |
819 | * function is designed to be used to read flash pages, | |
ce082596 JR |
820 | * which are typically multiples of 4... |
821 | */ | |
822 | ||
823 | BUG_ON((len % 4) != 0); | |
824 | ||
825 | /* transfer the data from the flash */ | |
826 | buf32 = (uint32_t *)buf; | |
827 | for (i = 0; i < len / 4; i++) | |
ce082596 | 828 | *buf32++ = ioread32(denali->flash_mem + 0x10); |
5bac3acf | 829 | return i*4; /* intent is to return the number of bytes read */ |
ce082596 JR |
830 | } |
831 | ||
832 | /* writes OOB data to the device */ | |
833 | static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) | |
834 | { | |
835 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
836 | uint32_t irq_status = 0; | |
9589bf5b JI |
837 | uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP | |
838 | INTR_STATUS__PROGRAM_FAIL; | |
ce082596 JR |
839 | int status = 0; |
840 | ||
841 | denali->page = page; | |
842 | ||
5bac3acf | 843 | if (denali_send_pipeline_cmd(denali, false, false, SPARE_ACCESS, |
345b1d3b | 844 | DENALI_WRITE) == PASS) { |
ce082596 JR |
845 | write_data_to_flash_mem(denali, buf, mtd->oobsize); |
846 | ||
ce082596 JR |
847 | /* wait for operation to complete */ |
848 | irq_status = wait_for_irq(denali, irq_mask); | |
849 | ||
345b1d3b | 850 | if (irq_status == 0) { |
84457949 | 851 | dev_err(denali->dev, "OOB write failed\n"); |
ce082596 JR |
852 | status = -EIO; |
853 | } | |
345b1d3b | 854 | } else { |
84457949 | 855 | dev_err(denali->dev, "unable to send pipeline command\n"); |
5bac3acf | 856 | status = -EIO; |
ce082596 JR |
857 | } |
858 | return status; | |
859 | } | |
860 | ||
861 | /* reads OOB data from the device */ | |
862 | static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) | |
863 | { | |
864 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
9589bf5b | 865 | uint32_t irq_mask = INTR_STATUS__LOAD_COMP, |
bdca6dae | 866 | irq_status = 0, addr = 0x0, cmd = 0x0; |
ce082596 JR |
867 | |
868 | denali->page = page; | |
869 | ||
5bac3acf | 870 | if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS, |
345b1d3b | 871 | DENALI_READ) == PASS) { |
5bac3acf | 872 | read_data_from_flash_mem(denali, buf, mtd->oobsize); |
ce082596 | 873 | |
5bac3acf | 874 | /* wait for command to be accepted |
ce082596 JR |
875 | * can always use status0 bit as the mask is identical for each |
876 | * bank. */ | |
877 | irq_status = wait_for_irq(denali, irq_mask); | |
878 | ||
879 | if (irq_status == 0) | |
84457949 | 880 | dev_err(denali->dev, "page on OOB timeout %d\n", |
bdca6dae | 881 | denali->page); |
ce082596 JR |
882 | |
883 | /* We set the device back to MAIN_ACCESS here as I observed | |
884 | * instability with the controller if you do a block erase | |
885 | * and the last transaction was a SPARE_ACCESS. Block erase | |
886 | * is reliable (according to the MTD test infrastructure) | |
5bac3acf | 887 | * if you are in MAIN_ACCESS. |
ce082596 JR |
888 | */ |
889 | addr = BANK(denali->flash_bank) | denali->page; | |
5bac3acf | 890 | cmd = MODE_10 | addr; |
ce082596 | 891 | index_addr(denali, (uint32_t)cmd, MAIN_ACCESS); |
ce082596 JR |
892 | } |
893 | } | |
894 | ||
5bac3acf | 895 | /* this function examines buffers to see if they contain data that |
ce082596 JR |
896 | * indicate that the buffer is part of an erased region of flash. |
897 | */ | |
898 | bool is_erased(uint8_t *buf, int len) | |
899 | { | |
900 | int i = 0; | |
901 | for (i = 0; i < len; i++) | |
ce082596 | 902 | if (buf[i] != 0xFF) |
ce082596 | 903 | return false; |
ce082596 JR |
904 | return true; |
905 | } | |
906 | #define ECC_SECTOR_SIZE 512 | |
907 | ||
908 | #define ECC_SECTOR(x) (((x) & ECC_ERROR_ADDRESS__SECTOR_NR) >> 12) | |
909 | #define ECC_BYTE(x) (((x) & ECC_ERROR_ADDRESS__OFFSET)) | |
910 | #define ECC_CORRECTION_VALUE(x) ((x) & ERR_CORRECTION_INFO__BYTEMASK) | |
8ae61ebd CD |
911 | #define ECC_ERROR_CORRECTABLE(x) (!((x) & ERR_CORRECTION_INFO__ERROR_TYPE)) |
912 | #define ECC_ERR_DEVICE(x) (((x) & ERR_CORRECTION_INFO__DEVICE_NR) >> 8) | |
ce082596 JR |
913 | #define ECC_LAST_ERR(x) ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO) |
914 | ||
5bac3acf | 915 | static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf, |
8ae61ebd | 916 | uint32_t irq_status) |
ce082596 JR |
917 | { |
918 | bool check_erased_page = false; | |
919 | ||
9589bf5b | 920 | if (irq_status & INTR_STATUS__ECC_ERR) { |
ce082596 JR |
921 | /* read the ECC errors. we'll ignore them for now */ |
922 | uint32_t err_address = 0, err_correction_info = 0; | |
923 | uint32_t err_byte = 0, err_sector = 0, err_device = 0; | |
924 | uint32_t err_correction_value = 0; | |
8ae61ebd | 925 | denali_set_intr_modes(denali, false); |
ce082596 | 926 | |
345b1d3b | 927 | do { |
5bac3acf | 928 | err_address = ioread32(denali->flash_reg + |
ce082596 JR |
929 | ECC_ERROR_ADDRESS); |
930 | err_sector = ECC_SECTOR(err_address); | |
931 | err_byte = ECC_BYTE(err_address); | |
932 | ||
5bac3acf | 933 | err_correction_info = ioread32(denali->flash_reg + |
ce082596 | 934 | ERR_CORRECTION_INFO); |
5bac3acf | 935 | err_correction_value = |
ce082596 JR |
936 | ECC_CORRECTION_VALUE(err_correction_info); |
937 | err_device = ECC_ERR_DEVICE(err_correction_info); | |
938 | ||
345b1d3b | 939 | if (ECC_ERROR_CORRECTABLE(err_correction_info)) { |
8ae61ebd | 940 | /* If err_byte is larger than ECC_SECTOR_SIZE, |
25985edc | 941 | * means error happened in OOB, so we ignore |
8ae61ebd CD |
942 | * it. It's no need for us to correct it |
943 | * err_device is represented the NAND error | |
944 | * bits are happened in if there are more | |
945 | * than one NAND connected. | |
946 | * */ | |
947 | if (err_byte < ECC_SECTOR_SIZE) { | |
948 | int offset; | |
949 | offset = (err_sector * | |
950 | ECC_SECTOR_SIZE + | |
951 | err_byte) * | |
952 | denali->devnum + | |
953 | err_device; | |
ce082596 JR |
954 | /* correct the ECC error */ |
955 | buf[offset] ^= err_correction_value; | |
956 | denali->mtd.ecc_stats.corrected++; | |
ce082596 | 957 | } |
345b1d3b | 958 | } else { |
5bac3acf | 959 | /* if the error is not correctable, need to |
bdca6dae CD |
960 | * look at the page to see if it is an erased |
961 | * page. if so, then it's not a real ECC error | |
962 | * */ | |
ce082596 JR |
963 | check_erased_page = true; |
964 | } | |
ce082596 | 965 | } while (!ECC_LAST_ERR(err_correction_info)); |
8ae61ebd CD |
966 | /* Once handle all ecc errors, controller will triger |
967 | * a ECC_TRANSACTION_DONE interrupt, so here just wait | |
968 | * for a while for this interrupt | |
969 | * */ | |
970 | while (!(read_interrupt_status(denali) & | |
9589bf5b | 971 | INTR_STATUS__ECC_TRANSACTION_DONE)) |
8ae61ebd CD |
972 | cpu_relax(); |
973 | clear_interrupts(denali); | |
974 | denali_set_intr_modes(denali, true); | |
ce082596 JR |
975 | } |
976 | return check_erased_page; | |
977 | } | |
978 | ||
979 | /* programs the controller to either enable/disable DMA transfers */ | |
aadff49c | 980 | static void denali_enable_dma(struct denali_nand_info *denali, bool en) |
ce082596 JR |
981 | { |
982 | uint32_t reg_val = 0x0; | |
983 | ||
a99d1796 CD |
984 | if (en) |
985 | reg_val = DMA_ENABLE__FLAG; | |
ce082596 | 986 | |
24c3fa36 | 987 | iowrite32(reg_val, denali->flash_reg + DMA_ENABLE); |
ce082596 JR |
988 | ioread32(denali->flash_reg + DMA_ENABLE); |
989 | } | |
990 | ||
991 | /* setups the HW to perform the data DMA */ | |
aadff49c | 992 | static void denali_setup_dma(struct denali_nand_info *denali, int op) |
ce082596 JR |
993 | { |
994 | uint32_t mode = 0x0; | |
995 | const int page_count = 1; | |
996 | dma_addr_t addr = denali->buf.dma_buf; | |
997 | ||
998 | mode = MODE_10 | BANK(denali->flash_bank); | |
999 | ||
1000 | /* DMA is a four step process */ | |
1001 | ||
1002 | /* 1. setup transfer type and # of pages */ | |
1003 | index_addr(denali, mode | denali->page, 0x2000 | op | page_count); | |
1004 | ||
1005 | /* 2. set memory high address bits 23:8 */ | |
1006 | index_addr(denali, mode | ((uint16_t)(addr >> 16) << 8), 0x2200); | |
1007 | ||
1008 | /* 3. set memory low address bits 23:8 */ | |
1009 | index_addr(denali, mode | ((uint16_t)addr << 8), 0x2300); | |
1010 | ||
1011 | /* 4. interrupt when complete, burst len = 64 bytes*/ | |
1012 | index_addr(denali, mode | 0x14000, 0x2400); | |
1013 | } | |
1014 | ||
5bac3acf | 1015 | /* writes a page. user specifies type, and this function handles the |
b292c341 | 1016 | * configuration details. */ |
5bac3acf | 1017 | static void write_page(struct mtd_info *mtd, struct nand_chip *chip, |
ce082596 JR |
1018 | const uint8_t *buf, bool raw_xfer) |
1019 | { | |
1020 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
ce082596 JR |
1021 | |
1022 | dma_addr_t addr = denali->buf.dma_buf; | |
1023 | size_t size = denali->mtd.writesize + denali->mtd.oobsize; | |
1024 | ||
1025 | uint32_t irq_status = 0; | |
9589bf5b JI |
1026 | uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP | |
1027 | INTR_STATUS__PROGRAM_FAIL; | |
ce082596 JR |
1028 | |
1029 | /* if it is a raw xfer, we want to disable ecc, and send | |
1030 | * the spare area. | |
1031 | * !raw_xfer - enable ecc | |
1032 | * raw_xfer - transfer spare | |
1033 | */ | |
1034 | setup_ecc_for_xfer(denali, !raw_xfer, raw_xfer); | |
1035 | ||
1036 | /* copy buffer into DMA buffer */ | |
1037 | memcpy(denali->buf.buf, buf, mtd->writesize); | |
1038 | ||
345b1d3b | 1039 | if (raw_xfer) { |
ce082596 | 1040 | /* transfer the data to the spare area */ |
5bac3acf C |
1041 | memcpy(denali->buf.buf + mtd->writesize, |
1042 | chip->oob_poi, | |
1043 | mtd->oobsize); | |
ce082596 JR |
1044 | } |
1045 | ||
84457949 | 1046 | dma_sync_single_for_device(denali->dev, addr, size, DMA_TO_DEVICE); |
ce082596 JR |
1047 | |
1048 | clear_interrupts(denali); | |
5bac3acf | 1049 | denali_enable_dma(denali, true); |
ce082596 | 1050 | |
aadff49c | 1051 | denali_setup_dma(denali, DENALI_WRITE); |
ce082596 JR |
1052 | |
1053 | /* wait for operation to complete */ | |
1054 | irq_status = wait_for_irq(denali, irq_mask); | |
1055 | ||
345b1d3b | 1056 | if (irq_status == 0) { |
84457949 | 1057 | dev_err(denali->dev, |
7cfffac0 CD |
1058 | "timeout on write_page (type = %d)\n", |
1059 | raw_xfer); | |
5bac3acf | 1060 | denali->status = |
9589bf5b | 1061 | (irq_status & INTR_STATUS__PROGRAM_FAIL) ? |
bdca6dae | 1062 | NAND_STATUS_FAIL : PASS; |
ce082596 JR |
1063 | } |
1064 | ||
5bac3acf | 1065 | denali_enable_dma(denali, false); |
84457949 | 1066 | dma_sync_single_for_cpu(denali->dev, addr, size, DMA_TO_DEVICE); |
ce082596 JR |
1067 | } |
1068 | ||
1069 | /* NAND core entry points */ | |
1070 | ||
5bac3acf | 1071 | /* this is the callback that the NAND core calls to write a page. Since |
b292c341 CD |
1072 | * writing a page with ECC or without is similar, all the work is done |
1073 | * by write_page above. | |
1074 | * */ | |
5bac3acf | 1075 | static void denali_write_page(struct mtd_info *mtd, struct nand_chip *chip, |
ce082596 JR |
1076 | const uint8_t *buf) |
1077 | { | |
1078 | /* for regular page writes, we let HW handle all the ECC | |
5bac3acf | 1079 | * data written to the device. */ |
ce082596 JR |
1080 | write_page(mtd, chip, buf, false); |
1081 | } | |
1082 | ||
5bac3acf | 1083 | /* This is the callback that the NAND core calls to write a page without ECC. |
25985edc | 1084 | * raw access is similar to ECC page writes, so all the work is done in the |
b292c341 | 1085 | * write_page() function above. |
ce082596 | 1086 | */ |
5bac3acf | 1087 | static void denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
ce082596 JR |
1088 | const uint8_t *buf) |
1089 | { | |
5bac3acf | 1090 | /* for raw page writes, we want to disable ECC and simply write |
ce082596 JR |
1091 | whatever data is in the buffer. */ |
1092 | write_page(mtd, chip, buf, true); | |
1093 | } | |
1094 | ||
5bac3acf | 1095 | static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip, |
ce082596 JR |
1096 | int page) |
1097 | { | |
5bac3acf | 1098 | return write_oob_data(mtd, chip->oob_poi, page); |
ce082596 JR |
1099 | } |
1100 | ||
5bac3acf | 1101 | static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip, |
ce082596 JR |
1102 | int page, int sndcmd) |
1103 | { | |
1104 | read_oob_data(mtd, chip->oob_poi, page); | |
1105 | ||
5bac3acf C |
1106 | return 0; /* notify NAND core to send command to |
1107 | NAND device. */ | |
ce082596 JR |
1108 | } |
1109 | ||
1110 | static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip, | |
1111 | uint8_t *buf, int page) | |
1112 | { | |
1113 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
ce082596 JR |
1114 | |
1115 | dma_addr_t addr = denali->buf.dma_buf; | |
1116 | size_t size = denali->mtd.writesize + denali->mtd.oobsize; | |
1117 | ||
1118 | uint32_t irq_status = 0; | |
9589bf5b JI |
1119 | uint32_t irq_mask = INTR_STATUS__ECC_TRANSACTION_DONE | |
1120 | INTR_STATUS__ECC_ERR; | |
ce082596 JR |
1121 | bool check_erased_page = false; |
1122 | ||
7d8a26fd | 1123 | if (page != denali->page) { |
84457949 | 1124 | dev_err(denali->dev, "IN %s: page %d is not" |
7d8a26fd CD |
1125 | " equal to denali->page %d, investigate!!", |
1126 | __func__, page, denali->page); | |
1127 | BUG(); | |
1128 | } | |
1129 | ||
ce082596 JR |
1130 | setup_ecc_for_xfer(denali, true, false); |
1131 | ||
aadff49c | 1132 | denali_enable_dma(denali, true); |
84457949 | 1133 | dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE); |
ce082596 JR |
1134 | |
1135 | clear_interrupts(denali); | |
aadff49c | 1136 | denali_setup_dma(denali, DENALI_READ); |
ce082596 JR |
1137 | |
1138 | /* wait for operation to complete */ | |
1139 | irq_status = wait_for_irq(denali, irq_mask); | |
1140 | ||
84457949 | 1141 | dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE); |
ce082596 JR |
1142 | |
1143 | memcpy(buf, denali->buf.buf, mtd->writesize); | |
5bac3acf | 1144 | |
8ae61ebd | 1145 | check_erased_page = handle_ecc(denali, buf, irq_status); |
aadff49c | 1146 | denali_enable_dma(denali, false); |
ce082596 | 1147 | |
345b1d3b | 1148 | if (check_erased_page) { |
ce082596 JR |
1149 | read_oob_data(&denali->mtd, chip->oob_poi, denali->page); |
1150 | ||
1151 | /* check ECC failures that may have occurred on erased pages */ | |
345b1d3b | 1152 | if (check_erased_page) { |
ce082596 | 1153 | if (!is_erased(buf, denali->mtd.writesize)) |
ce082596 | 1154 | denali->mtd.ecc_stats.failed++; |
ce082596 | 1155 | if (!is_erased(buf, denali->mtd.oobsize)) |
ce082596 | 1156 | denali->mtd.ecc_stats.failed++; |
5bac3acf | 1157 | } |
ce082596 JR |
1158 | } |
1159 | return 0; | |
1160 | } | |
1161 | ||
1162 | static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
1163 | uint8_t *buf, int page) | |
1164 | { | |
1165 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
ce082596 JR |
1166 | |
1167 | dma_addr_t addr = denali->buf.dma_buf; | |
1168 | size_t size = denali->mtd.writesize + denali->mtd.oobsize; | |
1169 | ||
1170 | uint32_t irq_status = 0; | |
9589bf5b | 1171 | uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP; |
5bac3acf | 1172 | |
7d8a26fd | 1173 | if (page != denali->page) { |
84457949 | 1174 | dev_err(denali->dev, "IN %s: page %d is not" |
7d8a26fd CD |
1175 | " equal to denali->page %d, investigate!!", |
1176 | __func__, page, denali->page); | |
1177 | BUG(); | |
1178 | } | |
1179 | ||
ce082596 | 1180 | setup_ecc_for_xfer(denali, false, true); |
aadff49c | 1181 | denali_enable_dma(denali, true); |
ce082596 | 1182 | |
84457949 | 1183 | dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE); |
ce082596 JR |
1184 | |
1185 | clear_interrupts(denali); | |
aadff49c | 1186 | denali_setup_dma(denali, DENALI_READ); |
ce082596 JR |
1187 | |
1188 | /* wait for operation to complete */ | |
1189 | irq_status = wait_for_irq(denali, irq_mask); | |
1190 | ||
84457949 | 1191 | dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE); |
ce082596 | 1192 | |
aadff49c | 1193 | denali_enable_dma(denali, false); |
ce082596 JR |
1194 | |
1195 | memcpy(buf, denali->buf.buf, mtd->writesize); | |
1196 | memcpy(chip->oob_poi, denali->buf.buf + mtd->writesize, mtd->oobsize); | |
1197 | ||
1198 | return 0; | |
1199 | } | |
1200 | ||
1201 | static uint8_t denali_read_byte(struct mtd_info *mtd) | |
1202 | { | |
1203 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1204 | uint8_t result = 0xff; | |
1205 | ||
1206 | if (denali->buf.head < denali->buf.tail) | |
ce082596 | 1207 | result = denali->buf.buf[denali->buf.head++]; |
ce082596 | 1208 | |
ce082596 JR |
1209 | return result; |
1210 | } | |
1211 | ||
1212 | static void denali_select_chip(struct mtd_info *mtd, int chip) | |
1213 | { | |
1214 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
7cfffac0 | 1215 | |
ce082596 JR |
1216 | spin_lock_irq(&denali->irq_lock); |
1217 | denali->flash_bank = chip; | |
1218 | spin_unlock_irq(&denali->irq_lock); | |
1219 | } | |
1220 | ||
1221 | static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip) | |
1222 | { | |
1223 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1224 | int status = denali->status; | |
1225 | denali->status = 0; | |
1226 | ||
ce082596 JR |
1227 | return status; |
1228 | } | |
1229 | ||
1230 | static void denali_erase(struct mtd_info *mtd, int page) | |
1231 | { | |
1232 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1233 | ||
1234 | uint32_t cmd = 0x0, irq_status = 0; | |
1235 | ||
ce082596 | 1236 | /* clear interrupts */ |
5bac3acf | 1237 | clear_interrupts(denali); |
ce082596 JR |
1238 | |
1239 | /* setup page read request for access type */ | |
1240 | cmd = MODE_10 | BANK(denali->flash_bank) | page; | |
1241 | index_addr(denali, (uint32_t)cmd, 0x1); | |
1242 | ||
1243 | /* wait for erase to complete or failure to occur */ | |
9589bf5b JI |
1244 | irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP | |
1245 | INTR_STATUS__ERASE_FAIL); | |
ce082596 | 1246 | |
9589bf5b | 1247 | denali->status = (irq_status & INTR_STATUS__ERASE_FAIL) ? |
bdca6dae | 1248 | NAND_STATUS_FAIL : PASS; |
ce082596 JR |
1249 | } |
1250 | ||
5bac3acf | 1251 | static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, |
ce082596 JR |
1252 | int page) |
1253 | { | |
1254 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
ef41e1bb CD |
1255 | uint32_t addr, id; |
1256 | int i; | |
ce082596 | 1257 | |
345b1d3b | 1258 | switch (cmd) { |
a99d1796 CD |
1259 | case NAND_CMD_PAGEPROG: |
1260 | break; | |
1261 | case NAND_CMD_STATUS: | |
1262 | read_status(denali); | |
1263 | break; | |
1264 | case NAND_CMD_READID: | |
42af8b58 | 1265 | case NAND_CMD_PARAM: |
a99d1796 | 1266 | reset_buf(denali); |
ef41e1bb CD |
1267 | /*sometimes ManufactureId read from register is not right |
1268 | * e.g. some of Micron MT29F32G08QAA MLC NAND chips | |
1269 | * So here we send READID cmd to NAND insteand | |
1270 | * */ | |
1271 | addr = (uint32_t)MODE_11 | BANK(denali->flash_bank); | |
1272 | index_addr(denali, (uint32_t)addr | 0, 0x90); | |
1273 | index_addr(denali, (uint32_t)addr | 1, 0); | |
1274 | for (i = 0; i < 5; i++) { | |
1275 | index_addr_read_data(denali, | |
1276 | (uint32_t)addr | 2, | |
1277 | &id); | |
1278 | write_byte_to_buf(denali, id); | |
a99d1796 CD |
1279 | } |
1280 | break; | |
1281 | case NAND_CMD_READ0: | |
1282 | case NAND_CMD_SEQIN: | |
1283 | denali->page = page; | |
1284 | break; | |
1285 | case NAND_CMD_RESET: | |
1286 | reset_bank(denali); | |
1287 | break; | |
1288 | case NAND_CMD_READOOB: | |
1289 | /* TODO: Read OOB data */ | |
1290 | break; | |
1291 | default: | |
1292 | printk(KERN_ERR ": unsupported command" | |
1293 | " received 0x%x\n", cmd); | |
1294 | break; | |
ce082596 JR |
1295 | } |
1296 | } | |
1297 | ||
1298 | /* stubs for ECC functions not used by the NAND core */ | |
5bac3acf | 1299 | static int denali_ecc_calculate(struct mtd_info *mtd, const uint8_t *data, |
ce082596 JR |
1300 | uint8_t *ecc_code) |
1301 | { | |
7cfffac0 | 1302 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
84457949 | 1303 | dev_err(denali->dev, |
7cfffac0 | 1304 | "denali_ecc_calculate called unexpectedly\n"); |
ce082596 JR |
1305 | BUG(); |
1306 | return -EIO; | |
1307 | } | |
1308 | ||
5bac3acf | 1309 | static int denali_ecc_correct(struct mtd_info *mtd, uint8_t *data, |
ce082596 JR |
1310 | uint8_t *read_ecc, uint8_t *calc_ecc) |
1311 | { | |
7cfffac0 | 1312 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
84457949 | 1313 | dev_err(denali->dev, |
7cfffac0 | 1314 | "denali_ecc_correct called unexpectedly\n"); |
ce082596 JR |
1315 | BUG(); |
1316 | return -EIO; | |
1317 | } | |
1318 | ||
1319 | static void denali_ecc_hwctl(struct mtd_info *mtd, int mode) | |
1320 | { | |
7cfffac0 | 1321 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
84457949 | 1322 | dev_err(denali->dev, |
7cfffac0 | 1323 | "denali_ecc_hwctl called unexpectedly\n"); |
ce082596 JR |
1324 | BUG(); |
1325 | } | |
1326 | /* end NAND core entry points */ | |
1327 | ||
1328 | /* Initialization code to bring the device up to a known good state */ | |
1329 | static void denali_hw_init(struct denali_nand_info *denali) | |
1330 | { | |
db9a3210 CD |
1331 | /* tell driver how many bit controller will skip before |
1332 | * writing ECC code in OOB, this register may be already | |
1333 | * set by firmware. So we read this value out. | |
1334 | * if this value is 0, just let it be. | |
1335 | * */ | |
1336 | denali->bbtskipbytes = ioread32(denali->flash_reg + | |
1337 | SPARE_AREA_SKIP_BYTES); | |
eda936ef | 1338 | denali_nand_reset(denali); |
24c3fa36 CD |
1339 | iowrite32(0x0F, denali->flash_reg + RB_PIN_ENABLED); |
1340 | iowrite32(CHIP_EN_DONT_CARE__FLAG, | |
bdca6dae | 1341 | denali->flash_reg + CHIP_ENABLE_DONT_CARE); |
ce082596 | 1342 | |
24c3fa36 | 1343 | iowrite32(0xffff, denali->flash_reg + SPARE_AREA_MARKER); |
ce082596 JR |
1344 | |
1345 | /* Should set value for these registers when init */ | |
24c3fa36 CD |
1346 | iowrite32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES); |
1347 | iowrite32(1, denali->flash_reg + ECC_ENABLE); | |
5eab6aaa CD |
1348 | denali_nand_timing_set(denali); |
1349 | denali_irq_init(denali); | |
ce082596 JR |
1350 | } |
1351 | ||
db9a3210 CD |
1352 | /* Althogh controller spec said SLC ECC is forceb to be 4bit, |
1353 | * but denali controller in MRST only support 15bit and 8bit ECC | |
1354 | * correction | |
1355 | * */ | |
1356 | #define ECC_8BITS 14 | |
1357 | static struct nand_ecclayout nand_8bit_oob = { | |
1358 | .eccbytes = 14, | |
ce082596 JR |
1359 | }; |
1360 | ||
db9a3210 CD |
1361 | #define ECC_15BITS 26 |
1362 | static struct nand_ecclayout nand_15bit_oob = { | |
1363 | .eccbytes = 26, | |
ce082596 JR |
1364 | }; |
1365 | ||
1366 | static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' }; | |
1367 | static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' }; | |
1368 | ||
1369 | static struct nand_bbt_descr bbt_main_descr = { | |
1370 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
1371 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
1372 | .offs = 8, | |
1373 | .len = 4, | |
1374 | .veroffs = 12, | |
1375 | .maxblocks = 4, | |
1376 | .pattern = bbt_pattern, | |
1377 | }; | |
1378 | ||
1379 | static struct nand_bbt_descr bbt_mirror_descr = { | |
1380 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
1381 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
1382 | .offs = 8, | |
1383 | .len = 4, | |
1384 | .veroffs = 12, | |
1385 | .maxblocks = 4, | |
1386 | .pattern = mirror_pattern, | |
1387 | }; | |
1388 | ||
421f91d2 | 1389 | /* initialize driver data structures */ |
ce082596 JR |
1390 | void denali_drv_init(struct denali_nand_info *denali) |
1391 | { | |
1392 | denali->idx = 0; | |
1393 | ||
1394 | /* setup interrupt handler */ | |
5bac3acf | 1395 | /* the completion object will be used to notify |
ce082596 JR |
1396 | * the callee that the interrupt is done */ |
1397 | init_completion(&denali->complete); | |
1398 | ||
1399 | /* the spinlock will be used to synchronize the ISR | |
5bac3acf | 1400 | * with any element that might be access shared |
ce082596 JR |
1401 | * data (interrupt status) */ |
1402 | spin_lock_init(&denali->irq_lock); | |
1403 | ||
1404 | /* indicate that MTD has not selected a valid bank yet */ | |
1405 | denali->flash_bank = CHIP_SELECT_INVALID; | |
1406 | ||
1407 | /* initialize our irq_status variable to indicate no interrupts */ | |
1408 | denali->irq_status = 0; | |
1409 | } | |
1410 | ||
1411 | /* driver entry point */ | |
1412 | static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) | |
1413 | { | |
1414 | int ret = -ENODEV; | |
1415 | resource_size_t csr_base, mem_base; | |
1416 | unsigned long csr_len, mem_len; | |
1417 | struct denali_nand_info *denali; | |
1418 | ||
ce082596 JR |
1419 | denali = kzalloc(sizeof(*denali), GFP_KERNEL); |
1420 | if (!denali) | |
1421 | return -ENOMEM; | |
1422 | ||
1423 | ret = pci_enable_device(dev); | |
1424 | if (ret) { | |
1425 | printk(KERN_ERR "Spectra: pci_enable_device failed.\n"); | |
5c0eb900 | 1426 | goto failed_alloc_memery; |
ce082596 JR |
1427 | } |
1428 | ||
1429 | if (id->driver_data == INTEL_CE4100) { | |
5bac3acf C |
1430 | /* Due to a silicon limitation, we can only support |
1431 | * ONFI timing mode 1 and below. | |
1432 | */ | |
345b1d3b | 1433 | if (onfi_timing_mode < -1 || onfi_timing_mode > 1) { |
bdca6dae CD |
1434 | printk(KERN_ERR "Intel CE4100 only supports" |
1435 | " ONFI timing mode 1 or below\n"); | |
ce082596 | 1436 | ret = -EINVAL; |
5c0eb900 | 1437 | goto failed_enable_dev; |
ce082596 JR |
1438 | } |
1439 | denali->platform = INTEL_CE4100; | |
1440 | mem_base = pci_resource_start(dev, 0); | |
1441 | mem_len = pci_resource_len(dev, 1); | |
1442 | csr_base = pci_resource_start(dev, 1); | |
1443 | csr_len = pci_resource_len(dev, 1); | |
1444 | } else { | |
1445 | denali->platform = INTEL_MRST; | |
1446 | csr_base = pci_resource_start(dev, 0); | |
5c0eb900 | 1447 | csr_len = pci_resource_len(dev, 0); |
ce082596 JR |
1448 | mem_base = pci_resource_start(dev, 1); |
1449 | mem_len = pci_resource_len(dev, 1); | |
1450 | if (!mem_len) { | |
1451 | mem_base = csr_base + csr_len; | |
1452 | mem_len = csr_len; | |
ce082596 JR |
1453 | } |
1454 | } | |
1455 | ||
1456 | /* Is 32-bit DMA supported? */ | |
84457949 | 1457 | ret = dma_set_mask(&dev->dev, DMA_BIT_MASK(32)); |
345b1d3b | 1458 | if (ret) { |
ce082596 | 1459 | printk(KERN_ERR "Spectra: no usable DMA configuration\n"); |
5c0eb900 | 1460 | goto failed_enable_dev; |
ce082596 | 1461 | } |
84457949 JI |
1462 | denali->buf.dma_buf = dma_map_single(&dev->dev, denali->buf.buf, |
1463 | DENALI_BUF_SIZE, | |
1464 | DMA_BIDIRECTIONAL); | |
ce082596 | 1465 | |
84457949 | 1466 | if (dma_mapping_error(&dev->dev, denali->buf.dma_buf)) { |
7cfffac0 | 1467 | dev_err(&dev->dev, "Spectra: failed to map DMA buffer\n"); |
5c0eb900 | 1468 | goto failed_enable_dev; |
ce082596 JR |
1469 | } |
1470 | ||
1471 | pci_set_master(dev); | |
84457949 | 1472 | denali->dev = &dev->dev; |
5eab6aaa | 1473 | denali->mtd.dev.parent = &dev->dev; |
ce082596 JR |
1474 | |
1475 | ret = pci_request_regions(dev, DENALI_NAND_NAME); | |
1476 | if (ret) { | |
1477 | printk(KERN_ERR "Spectra: Unable to request memory regions\n"); | |
5c0eb900 | 1478 | goto failed_dma_map; |
ce082596 JR |
1479 | } |
1480 | ||
1481 | denali->flash_reg = ioremap_nocache(csr_base, csr_len); | |
1482 | if (!denali->flash_reg) { | |
1483 | printk(KERN_ERR "Spectra: Unable to remap memory region\n"); | |
1484 | ret = -ENOMEM; | |
5c0eb900 | 1485 | goto failed_req_regions; |
ce082596 | 1486 | } |
ce082596 JR |
1487 | |
1488 | denali->flash_mem = ioremap_nocache(mem_base, mem_len); | |
1489 | if (!denali->flash_mem) { | |
1490 | printk(KERN_ERR "Spectra: ioremap_nocache failed!"); | |
ce082596 | 1491 | ret = -ENOMEM; |
5c0eb900 | 1492 | goto failed_remap_reg; |
ce082596 JR |
1493 | } |
1494 | ||
ce082596 JR |
1495 | denali_hw_init(denali); |
1496 | denali_drv_init(denali); | |
1497 | ||
5eab6aaa CD |
1498 | /* denali_isr register is done after all the hardware |
1499 | * initilization is finished*/ | |
ce082596 JR |
1500 | if (request_irq(dev->irq, denali_isr, IRQF_SHARED, |
1501 | DENALI_NAND_NAME, denali)) { | |
1502 | printk(KERN_ERR "Spectra: Unable to allocate IRQ\n"); | |
1503 | ret = -ENODEV; | |
5c0eb900 | 1504 | goto failed_remap_mem; |
ce082596 JR |
1505 | } |
1506 | ||
1507 | /* now that our ISR is registered, we can enable interrupts */ | |
eda936ef | 1508 | denali_set_intr_modes(denali, true); |
ce082596 JR |
1509 | |
1510 | pci_set_drvdata(dev, denali); | |
1511 | ||
5eab6aaa | 1512 | denali->mtd.name = "denali-nand"; |
ce082596 JR |
1513 | denali->mtd.owner = THIS_MODULE; |
1514 | denali->mtd.priv = &denali->nand; | |
1515 | ||
1516 | /* register the driver with the NAND core subsystem */ | |
1517 | denali->nand.select_chip = denali_select_chip; | |
1518 | denali->nand.cmdfunc = denali_cmdfunc; | |
1519 | denali->nand.read_byte = denali_read_byte; | |
1520 | denali->nand.waitfunc = denali_waitfunc; | |
1521 | ||
5bac3acf | 1522 | /* scan for NAND devices attached to the controller |
ce082596 | 1523 | * this is the first stage in a two step process to register |
5bac3acf | 1524 | * with the nand subsystem */ |
345b1d3b | 1525 | if (nand_scan_ident(&denali->mtd, LLD_MAX_FLASH_BANKS, NULL)) { |
ce082596 | 1526 | ret = -ENXIO; |
5c0eb900 | 1527 | goto failed_req_irq; |
ce082596 | 1528 | } |
5bac3acf | 1529 | |
66406524 CD |
1530 | /* MTD supported page sizes vary by kernel. We validate our |
1531 | * kernel supports the device here. | |
1532 | */ | |
1533 | if (denali->mtd.writesize > NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE) { | |
1534 | ret = -ENODEV; | |
1535 | printk(KERN_ERR "Spectra: device size not supported by this " | |
1536 | "version of MTD."); | |
5c0eb900 | 1537 | goto failed_req_irq; |
66406524 CD |
1538 | } |
1539 | ||
08b9ab99 CD |
1540 | /* support for multi nand |
1541 | * MTD known nothing about multi nand, | |
1542 | * so we should tell it the real pagesize | |
1543 | * and anything necessery | |
1544 | */ | |
1545 | denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED); | |
1546 | denali->nand.chipsize <<= (denali->devnum - 1); | |
1547 | denali->nand.page_shift += (denali->devnum - 1); | |
1548 | denali->nand.pagemask = (denali->nand.chipsize >> | |
1549 | denali->nand.page_shift) - 1; | |
1550 | denali->nand.bbt_erase_shift += (denali->devnum - 1); | |
1551 | denali->nand.phys_erase_shift = denali->nand.bbt_erase_shift; | |
1552 | denali->nand.chip_shift += (denali->devnum - 1); | |
1553 | denali->mtd.writesize <<= (denali->devnum - 1); | |
1554 | denali->mtd.oobsize <<= (denali->devnum - 1); | |
1555 | denali->mtd.erasesize <<= (denali->devnum - 1); | |
1556 | denali->mtd.size = denali->nand.numchips * denali->nand.chipsize; | |
1557 | denali->bbtskipbytes *= denali->devnum; | |
1558 | ||
5bac3acf C |
1559 | /* second stage of the NAND scan |
1560 | * this stage requires information regarding ECC and | |
1561 | * bad block management. */ | |
ce082596 JR |
1562 | |
1563 | /* Bad block management */ | |
1564 | denali->nand.bbt_td = &bbt_main_descr; | |
1565 | denali->nand.bbt_md = &bbt_mirror_descr; | |
1566 | ||
1567 | /* skip the scan for now until we have OOB read and write support */ | |
1568 | denali->nand.options |= NAND_USE_FLASH_BBT | NAND_SKIP_BBTSCAN; | |
1569 | denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME; | |
1570 | ||
db9a3210 CD |
1571 | /* Denali Controller only support 15bit and 8bit ECC in MRST, |
1572 | * so just let controller do 15bit ECC for MLC and 8bit ECC for | |
1573 | * SLC if possible. | |
1574 | * */ | |
1575 | if (denali->nand.cellinfo & 0xc && | |
1576 | (denali->mtd.oobsize > (denali->bbtskipbytes + | |
1577 | ECC_15BITS * (denali->mtd.writesize / | |
1578 | ECC_SECTOR_SIZE)))) { | |
1579 | /* if MLC OOB size is large enough, use 15bit ECC*/ | |
1580 | denali->nand.ecc.layout = &nand_15bit_oob; | |
1581 | denali->nand.ecc.bytes = ECC_15BITS; | |
24c3fa36 | 1582 | iowrite32(15, denali->flash_reg + ECC_CORRECTION); |
db9a3210 CD |
1583 | } else if (denali->mtd.oobsize < (denali->bbtskipbytes + |
1584 | ECC_8BITS * (denali->mtd.writesize / | |
1585 | ECC_SECTOR_SIZE))) { | |
1586 | printk(KERN_ERR "Your NAND chip OOB is not large enough to" | |
1587 | " contain 8bit ECC correction codes"); | |
5c0eb900 | 1588 | goto failed_req_irq; |
db9a3210 CD |
1589 | } else { |
1590 | denali->nand.ecc.layout = &nand_8bit_oob; | |
1591 | denali->nand.ecc.bytes = ECC_8BITS; | |
24c3fa36 | 1592 | iowrite32(8, denali->flash_reg + ECC_CORRECTION); |
ce082596 JR |
1593 | } |
1594 | ||
08b9ab99 | 1595 | denali->nand.ecc.bytes *= denali->devnum; |
db9a3210 CD |
1596 | denali->nand.ecc.layout->eccbytes *= |
1597 | denali->mtd.writesize / ECC_SECTOR_SIZE; | |
1598 | denali->nand.ecc.layout->oobfree[0].offset = | |
1599 | denali->bbtskipbytes + denali->nand.ecc.layout->eccbytes; | |
1600 | denali->nand.ecc.layout->oobfree[0].length = | |
1601 | denali->mtd.oobsize - denali->nand.ecc.layout->eccbytes - | |
1602 | denali->bbtskipbytes; | |
1603 | ||
66406524 CD |
1604 | /* Let driver know the total blocks number and |
1605 | * how many blocks contained by each nand chip. | |
1606 | * blksperchip will help driver to know how many | |
1607 | * blocks is taken by FW. | |
1608 | * */ | |
1609 | denali->totalblks = denali->mtd.size >> | |
1610 | denali->nand.phys_erase_shift; | |
1611 | denali->blksperchip = denali->totalblks / denali->nand.numchips; | |
1612 | ||
5bac3acf C |
1613 | /* These functions are required by the NAND core framework, otherwise, |
1614 | * the NAND core will assert. However, we don't need them, so we'll stub | |
1615 | * them out. */ | |
ce082596 JR |
1616 | denali->nand.ecc.calculate = denali_ecc_calculate; |
1617 | denali->nand.ecc.correct = denali_ecc_correct; | |
1618 | denali->nand.ecc.hwctl = denali_ecc_hwctl; | |
1619 | ||
1620 | /* override the default read operations */ | |
08b9ab99 | 1621 | denali->nand.ecc.size = ECC_SECTOR_SIZE * denali->devnum; |
ce082596 JR |
1622 | denali->nand.ecc.read_page = denali_read_page; |
1623 | denali->nand.ecc.read_page_raw = denali_read_page_raw; | |
1624 | denali->nand.ecc.write_page = denali_write_page; | |
1625 | denali->nand.ecc.write_page_raw = denali_write_page_raw; | |
1626 | denali->nand.ecc.read_oob = denali_read_oob; | |
1627 | denali->nand.ecc.write_oob = denali_write_oob; | |
1628 | denali->nand.erase_cmd = denali_erase; | |
1629 | ||
345b1d3b | 1630 | if (nand_scan_tail(&denali->mtd)) { |
ce082596 | 1631 | ret = -ENXIO; |
5c0eb900 | 1632 | goto failed_req_irq; |
ce082596 JR |
1633 | } |
1634 | ||
1635 | ret = add_mtd_device(&denali->mtd); | |
1636 | if (ret) { | |
7cfffac0 CD |
1637 | dev_err(&dev->dev, "Spectra: Failed to register MTD: %d\n", |
1638 | ret); | |
5c0eb900 | 1639 | goto failed_req_irq; |
ce082596 JR |
1640 | } |
1641 | return 0; | |
1642 | ||
5c0eb900 | 1643 | failed_req_irq: |
ce082596 | 1644 | denali_irq_cleanup(dev->irq, denali); |
5c0eb900 | 1645 | failed_remap_mem: |
ce082596 | 1646 | iounmap(denali->flash_mem); |
5c0eb900 CD |
1647 | failed_remap_reg: |
1648 | iounmap(denali->flash_reg); | |
1649 | failed_req_regions: | |
ce082596 | 1650 | pci_release_regions(dev); |
5c0eb900 | 1651 | failed_dma_map: |
84457949 JI |
1652 | dma_unmap_single(&dev->dev, denali->buf.dma_buf, DENALI_BUF_SIZE, |
1653 | DMA_BIDIRECTIONAL); | |
5c0eb900 CD |
1654 | failed_enable_dev: |
1655 | pci_disable_device(dev); | |
1656 | failed_alloc_memery: | |
ce082596 JR |
1657 | kfree(denali); |
1658 | return ret; | |
1659 | } | |
1660 | ||
1661 | /* driver exit point */ | |
1662 | static void denali_pci_remove(struct pci_dev *dev) | |
1663 | { | |
1664 | struct denali_nand_info *denali = pci_get_drvdata(dev); | |
1665 | ||
ce082596 JR |
1666 | nand_release(&denali->mtd); |
1667 | del_mtd_device(&denali->mtd); | |
1668 | ||
1669 | denali_irq_cleanup(dev->irq, denali); | |
1670 | ||
1671 | iounmap(denali->flash_reg); | |
1672 | iounmap(denali->flash_mem); | |
1673 | pci_release_regions(dev); | |
1674 | pci_disable_device(dev); | |
84457949 JI |
1675 | dma_unmap_single(&dev->dev, denali->buf.dma_buf, DENALI_BUF_SIZE, |
1676 | DMA_BIDIRECTIONAL); | |
ce082596 JR |
1677 | pci_set_drvdata(dev, NULL); |
1678 | kfree(denali); | |
1679 | } | |
1680 | ||
1681 | MODULE_DEVICE_TABLE(pci, denali_pci_ids); | |
1682 | ||
1683 | static struct pci_driver denali_pci_driver = { | |
1684 | .name = DENALI_NAND_NAME, | |
1685 | .id_table = denali_pci_ids, | |
1686 | .probe = denali_pci_probe, | |
1687 | .remove = denali_pci_remove, | |
1688 | }; | |
1689 | ||
1690 | static int __devinit denali_init(void) | |
1691 | { | |
9b5705a2 | 1692 | printk(KERN_INFO "Spectra MTD driver\n"); |
ce082596 JR |
1693 | return pci_register_driver(&denali_pci_driver); |
1694 | } | |
1695 | ||
1696 | /* Free memory */ | |
1697 | static void __devexit denali_exit(void) | |
1698 | { | |
1699 | pci_unregister_driver(&denali_pci_driver); | |
1700 | } | |
1701 | ||
1702 | module_init(denali_init); | |
1703 | module_exit(denali_exit); |