Commit | Line | Data |
---|---|---|
76b10467 SW |
1 | /* Freescale Enhanced Local Bus Controller NAND driver |
2 | * | |
3ab8f2a2 | 3 | * Copyright © 2006-2007, 2010 Freescale Semiconductor |
76b10467 SW |
4 | * |
5 | * Authors: Nick Spence <nick.spence@freescale.com>, | |
6 | * Scott Wood <scottwood@freescale.com> | |
3ab8f2a2 RZ |
7 | * Jack Lan <jack.lan@freescale.com> |
8 | * Roy Zang <tie-fei.zang@freescale.com> | |
76b10467 SW |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #include <linux/module.h> | |
26 | #include <linux/types.h> | |
27 | #include <linux/init.h> | |
28 | #include <linux/kernel.h> | |
29 | #include <linux/string.h> | |
30 | #include <linux/ioport.h> | |
5af50730 | 31 | #include <linux/of_address.h> |
76b10467 | 32 | #include <linux/of_platform.h> |
3ab8f2a2 | 33 | #include <linux/platform_device.h> |
76b10467 SW |
34 | #include <linux/slab.h> |
35 | #include <linux/interrupt.h> | |
36 | ||
37 | #include <linux/mtd/mtd.h> | |
38 | #include <linux/mtd/nand.h> | |
39 | #include <linux/mtd/nand_ecc.h> | |
40 | #include <linux/mtd/partitions.h> | |
41 | ||
42 | #include <asm/io.h> | |
d4a32fe4 | 43 | #include <asm/fsl_lbc.h> |
76b10467 SW |
44 | |
45 | #define MAX_BANKS 8 | |
46 | #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */ | |
47 | #define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */ | |
48 | ||
76b10467 SW |
49 | /* mtd information per set */ |
50 | ||
51 | struct fsl_elbc_mtd { | |
52 | struct mtd_info mtd; | |
53 | struct nand_chip chip; | |
3ab8f2a2 | 54 | struct fsl_lbc_ctrl *ctrl; |
76b10467 SW |
55 | |
56 | struct device *dev; | |
57 | int bank; /* Chip select bank number */ | |
58 | u8 __iomem *vbase; /* Chip select base virtual address */ | |
59 | int page_size; /* NAND page size (0=512, 1=2048) */ | |
60 | unsigned int fmr; /* FCM Flash Mode Register value */ | |
61 | }; | |
62 | ||
25985edc | 63 | /* Freescale eLBC FCM controller information */ |
76b10467 | 64 | |
3ab8f2a2 | 65 | struct fsl_elbc_fcm_ctrl { |
76b10467 SW |
66 | struct nand_hw_control controller; |
67 | struct fsl_elbc_mtd *chips[MAX_BANKS]; | |
68 | ||
76b10467 SW |
69 | u8 __iomem *addr; /* Address of assigned FCM buffer */ |
70 | unsigned int page; /* Last page written to / read from */ | |
71 | unsigned int read_bytes; /* Number of bytes read during command */ | |
72 | unsigned int column; /* Saved column from SEQIN */ | |
73 | unsigned int index; /* Pointer to next byte to 'read' */ | |
74 | unsigned int status; /* status read from LTESR after last op */ | |
75 | unsigned int mdr; /* UPM/FCM Data Register value */ | |
76 | unsigned int use_mdr; /* Non zero if the MDR is to be set */ | |
77 | unsigned int oob; /* Non zero if operating on OOB data */ | |
3ab8f2a2 | 78 | unsigned int counter; /* counter for the initializations */ |
3f91e94f | 79 | unsigned int max_bitflips; /* Saved during READ0 cmd */ |
76b10467 SW |
80 | }; |
81 | ||
82 | /* These map to the positions used by the FCM hardware ECC generator */ | |
83 | ||
84 | /* Small Page FLASH with FMR[ECCM] = 0 */ | |
85 | static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = { | |
86 | .eccbytes = 3, | |
87 | .eccpos = {6, 7, 8}, | |
88 | .oobfree = { {0, 5}, {9, 7} }, | |
76b10467 SW |
89 | }; |
90 | ||
91 | /* Small Page FLASH with FMR[ECCM] = 1 */ | |
92 | static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = { | |
93 | .eccbytes = 3, | |
94 | .eccpos = {8, 9, 10}, | |
95 | .oobfree = { {0, 5}, {6, 2}, {11, 5} }, | |
76b10467 SW |
96 | }; |
97 | ||
98 | /* Large Page FLASH with FMR[ECCM] = 0 */ | |
99 | static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = { | |
100 | .eccbytes = 12, | |
101 | .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56}, | |
102 | .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} }, | |
76b10467 SW |
103 | }; |
104 | ||
105 | /* Large Page FLASH with FMR[ECCM] = 1 */ | |
106 | static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = { | |
107 | .eccbytes = 12, | |
108 | .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58}, | |
109 | .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} }, | |
76b10467 SW |
110 | }; |
111 | ||
ec6e0ea3 AV |
112 | /* |
113 | * ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt, | |
114 | * interfere with ECC positions, that's why we implement our own descriptors. | |
115 | * OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0. | |
116 | */ | |
117 | static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; | |
118 | static u8 mirror_pattern[] = {'1', 't', 'b', 'B' }; | |
119 | ||
120 | static struct nand_bbt_descr bbt_main_descr = { | |
121 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | | |
122 | NAND_BBT_2BIT | NAND_BBT_VERSION, | |
123 | .offs = 11, | |
124 | .len = 4, | |
125 | .veroffs = 15, | |
126 | .maxblocks = 4, | |
127 | .pattern = bbt_pattern, | |
128 | }; | |
129 | ||
130 | static struct nand_bbt_descr bbt_mirror_descr = { | |
131 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | | |
132 | NAND_BBT_2BIT | NAND_BBT_VERSION, | |
133 | .offs = 11, | |
134 | .len = 4, | |
135 | .veroffs = 15, | |
136 | .maxblocks = 4, | |
137 | .pattern = mirror_pattern, | |
138 | }; | |
139 | ||
76b10467 SW |
140 | /*=================================*/ |
141 | ||
142 | /* | |
143 | * Set up the FCM hardware block and page address fields, and the fcm | |
144 | * structure addr field to point to the correct FCM buffer in memory | |
145 | */ | |
146 | static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) | |
147 | { | |
148 | struct nand_chip *chip = mtd->priv; | |
149 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 | 150 | struct fsl_lbc_ctrl *ctrl = priv->ctrl; |
d4a32fe4 | 151 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
3ab8f2a2 | 152 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; |
76b10467 SW |
153 | int buf_num; |
154 | ||
3ab8f2a2 | 155 | elbc_fcm_ctrl->page = page_addr; |
76b10467 | 156 | |
76b10467 | 157 | if (priv->page_size) { |
9ae84fe8 LS |
158 | /* |
159 | * large page size chip : FPAR[PI] save the lowest 6 bits, | |
160 | * FBAR[BLK] save the other bits. | |
161 | */ | |
162 | out_be32(&lbc->fbar, page_addr >> 6); | |
76b10467 SW |
163 | out_be32(&lbc->fpar, |
164 | ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) | | |
165 | (oob ? FPAR_LP_MS : 0) | column); | |
166 | buf_num = (page_addr & 1) << 2; | |
167 | } else { | |
9ae84fe8 LS |
168 | /* |
169 | * small page size chip : FPAR[PI] save the lowest 5 bits, | |
170 | * FBAR[BLK] save the other bits. | |
171 | */ | |
172 | out_be32(&lbc->fbar, page_addr >> 5); | |
76b10467 SW |
173 | out_be32(&lbc->fpar, |
174 | ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) | | |
175 | (oob ? FPAR_SP_MS : 0) | column); | |
176 | buf_num = page_addr & 7; | |
177 | } | |
178 | ||
3ab8f2a2 RZ |
179 | elbc_fcm_ctrl->addr = priv->vbase + buf_num * 1024; |
180 | elbc_fcm_ctrl->index = column; | |
76b10467 SW |
181 | |
182 | /* for OOB data point to the second half of the buffer */ | |
183 | if (oob) | |
3ab8f2a2 | 184 | elbc_fcm_ctrl->index += priv->page_size ? 2048 : 512; |
76b10467 | 185 | |
3ab8f2a2 RZ |
186 | dev_vdbg(priv->dev, "set_addr: bank=%d, " |
187 | "elbc_fcm_ctrl->addr=0x%p (0x%p), " | |
76b10467 | 188 | "index %x, pes %d ps %d\n", |
3ab8f2a2 RZ |
189 | buf_num, elbc_fcm_ctrl->addr, priv->vbase, |
190 | elbc_fcm_ctrl->index, | |
76b10467 SW |
191 | chip->phys_erase_shift, chip->page_shift); |
192 | } | |
193 | ||
194 | /* | |
195 | * execute FCM command and wait for it to complete | |
196 | */ | |
197 | static int fsl_elbc_run_command(struct mtd_info *mtd) | |
198 | { | |
199 | struct nand_chip *chip = mtd->priv; | |
200 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 RZ |
201 | struct fsl_lbc_ctrl *ctrl = priv->ctrl; |
202 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; | |
d4a32fe4 | 203 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
76b10467 SW |
204 | |
205 | /* Setup the FMR[OP] to execute without write protection */ | |
206 | out_be32(&lbc->fmr, priv->fmr | 3); | |
3ab8f2a2 RZ |
207 | if (elbc_fcm_ctrl->use_mdr) |
208 | out_be32(&lbc->mdr, elbc_fcm_ctrl->mdr); | |
76b10467 | 209 | |
3ab8f2a2 | 210 | dev_vdbg(priv->dev, |
76b10467 SW |
211 | "fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n", |
212 | in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr)); | |
3ab8f2a2 | 213 | dev_vdbg(priv->dev, |
76b10467 SW |
214 | "fsl_elbc_run_command: fbar=%08x fpar=%08x " |
215 | "fbcr=%08x bank=%d\n", | |
216 | in_be32(&lbc->fbar), in_be32(&lbc->fpar), | |
217 | in_be32(&lbc->fbcr), priv->bank); | |
218 | ||
1938de46 | 219 | ctrl->irq_status = 0; |
76b10467 SW |
220 | /* execute special operation */ |
221 | out_be32(&lbc->lsor, priv->bank); | |
222 | ||
223 | /* wait for FCM complete flag or timeout */ | |
76b10467 SW |
224 | wait_event_timeout(ctrl->irq_wait, ctrl->irq_status, |
225 | FCM_TIMEOUT_MSECS * HZ/1000); | |
3ab8f2a2 | 226 | elbc_fcm_ctrl->status = ctrl->irq_status; |
76b10467 | 227 | /* store mdr value in case it was needed */ |
3ab8f2a2 RZ |
228 | if (elbc_fcm_ctrl->use_mdr) |
229 | elbc_fcm_ctrl->mdr = in_be32(&lbc->mdr); | |
76b10467 | 230 | |
3ab8f2a2 | 231 | elbc_fcm_ctrl->use_mdr = 0; |
76b10467 | 232 | |
3ab8f2a2 RZ |
233 | if (elbc_fcm_ctrl->status != LTESR_CC) { |
234 | dev_info(priv->dev, | |
c1317f71 SW |
235 | "command failed: fir %x fcr %x status %x mdr %x\n", |
236 | in_be32(&lbc->fir), in_be32(&lbc->fcr), | |
3ab8f2a2 | 237 | elbc_fcm_ctrl->status, elbc_fcm_ctrl->mdr); |
c1317f71 SW |
238 | return -EIO; |
239 | } | |
76b10467 | 240 | |
f975c6bc MH |
241 | if (chip->ecc.mode != NAND_ECC_HW) |
242 | return 0; | |
243 | ||
3f91e94f MD |
244 | elbc_fcm_ctrl->max_bitflips = 0; |
245 | ||
f975c6bc MH |
246 | if (elbc_fcm_ctrl->read_bytes == mtd->writesize + mtd->oobsize) { |
247 | uint32_t lteccr = in_be32(&lbc->lteccr); | |
248 | /* | |
249 | * if command was a full page read and the ELBC | |
250 | * has the LTECCR register, then bits 12-15 (ppc order) of | |
251 | * LTECCR indicates which 512 byte sub-pages had fixed errors. | |
252 | * bits 28-31 are uncorrectable errors, marked elsewhere. | |
253 | * for small page nand only 1 bit is used. | |
254 | * if the ELBC doesn't have the lteccr register it reads 0 | |
3f91e94f MD |
255 | * FIXME: 4 bits can be corrected on NANDs with 2k pages, so |
256 | * count the number of sub-pages with bitflips and update | |
257 | * ecc_stats.corrected accordingly. | |
f975c6bc MH |
258 | */ |
259 | if (lteccr & 0x000F000F) | |
260 | out_be32(&lbc->lteccr, 0x000F000F); /* clear lteccr */ | |
3f91e94f | 261 | if (lteccr & 0x000F0000) { |
f975c6bc | 262 | mtd->ecc_stats.corrected++; |
3f91e94f MD |
263 | elbc_fcm_ctrl->max_bitflips = 1; |
264 | } | |
f975c6bc MH |
265 | } |
266 | ||
c1317f71 | 267 | return 0; |
76b10467 SW |
268 | } |
269 | ||
270 | static void fsl_elbc_do_read(struct nand_chip *chip, int oob) | |
271 | { | |
272 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 | 273 | struct fsl_lbc_ctrl *ctrl = priv->ctrl; |
d4a32fe4 | 274 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
76b10467 SW |
275 | |
276 | if (priv->page_size) { | |
277 | out_be32(&lbc->fir, | |
476459a6 | 278 | (FIR_OP_CM0 << FIR_OP0_SHIFT) | |
76b10467 SW |
279 | (FIR_OP_CA << FIR_OP1_SHIFT) | |
280 | (FIR_OP_PA << FIR_OP2_SHIFT) | | |
476459a6 | 281 | (FIR_OP_CM1 << FIR_OP3_SHIFT) | |
76b10467 SW |
282 | (FIR_OP_RBW << FIR_OP4_SHIFT)); |
283 | ||
284 | out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) | | |
285 | (NAND_CMD_READSTART << FCR_CMD1_SHIFT)); | |
286 | } else { | |
287 | out_be32(&lbc->fir, | |
476459a6 | 288 | (FIR_OP_CM0 << FIR_OP0_SHIFT) | |
76b10467 SW |
289 | (FIR_OP_CA << FIR_OP1_SHIFT) | |
290 | (FIR_OP_PA << FIR_OP2_SHIFT) | | |
291 | (FIR_OP_RBW << FIR_OP3_SHIFT)); | |
292 | ||
293 | if (oob) | |
294 | out_be32(&lbc->fcr, NAND_CMD_READOOB << FCR_CMD0_SHIFT); | |
295 | else | |
296 | out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT); | |
297 | } | |
298 | } | |
299 | ||
300 | /* cmdfunc send commands to the FCM */ | |
301 | static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command, | |
302 | int column, int page_addr) | |
303 | { | |
304 | struct nand_chip *chip = mtd->priv; | |
305 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 RZ |
306 | struct fsl_lbc_ctrl *ctrl = priv->ctrl; |
307 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; | |
d4a32fe4 | 308 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
76b10467 | 309 | |
3ab8f2a2 | 310 | elbc_fcm_ctrl->use_mdr = 0; |
76b10467 SW |
311 | |
312 | /* clear the read buffer */ | |
3ab8f2a2 | 313 | elbc_fcm_ctrl->read_bytes = 0; |
76b10467 | 314 | if (command != NAND_CMD_PAGEPROG) |
3ab8f2a2 | 315 | elbc_fcm_ctrl->index = 0; |
76b10467 SW |
316 | |
317 | switch (command) { | |
318 | /* READ0 and READ1 read the entire buffer to use hardware ECC. */ | |
319 | case NAND_CMD_READ1: | |
320 | column += 256; | |
321 | ||
322 | /* fall-through */ | |
323 | case NAND_CMD_READ0: | |
3ab8f2a2 | 324 | dev_dbg(priv->dev, |
76b10467 SW |
325 | "fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:" |
326 | " 0x%x, column: 0x%x.\n", page_addr, column); | |
327 | ||
328 | ||
329 | out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */ | |
330 | set_addr(mtd, 0, page_addr, 0); | |
331 | ||
3ab8f2a2 RZ |
332 | elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize; |
333 | elbc_fcm_ctrl->index += column; | |
76b10467 SW |
334 | |
335 | fsl_elbc_do_read(chip, 0); | |
336 | fsl_elbc_run_command(mtd); | |
337 | return; | |
338 | ||
339 | /* READOOB reads only the OOB because no ECC is performed. */ | |
340 | case NAND_CMD_READOOB: | |
3ab8f2a2 | 341 | dev_vdbg(priv->dev, |
76b10467 SW |
342 | "fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:" |
343 | " 0x%x, column: 0x%x.\n", page_addr, column); | |
344 | ||
345 | out_be32(&lbc->fbcr, mtd->oobsize - column); | |
346 | set_addr(mtd, column, page_addr, 1); | |
347 | ||
3ab8f2a2 | 348 | elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize; |
76b10467 SW |
349 | |
350 | fsl_elbc_do_read(chip, 1); | |
351 | fsl_elbc_run_command(mtd); | |
352 | return; | |
353 | ||
76b10467 | 354 | case NAND_CMD_READID: |
f57eb5cc SL |
355 | case NAND_CMD_PARAM: |
356 | dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD %x\n", command); | |
76b10467 | 357 | |
476459a6 | 358 | out_be32(&lbc->fir, (FIR_OP_CM0 << FIR_OP0_SHIFT) | |
76b10467 SW |
359 | (FIR_OP_UA << FIR_OP1_SHIFT) | |
360 | (FIR_OP_RBW << FIR_OP2_SHIFT)); | |
f57eb5cc SL |
361 | out_be32(&lbc->fcr, command << FCR_CMD0_SHIFT); |
362 | /* | |
363 | * although currently it's 8 bytes for READID, we always read | |
364 | * the maximum 256 bytes(for PARAM) | |
365 | */ | |
366 | out_be32(&lbc->fbcr, 256); | |
367 | elbc_fcm_ctrl->read_bytes = 256; | |
3ab8f2a2 | 368 | elbc_fcm_ctrl->use_mdr = 1; |
f57eb5cc | 369 | elbc_fcm_ctrl->mdr = column; |
76b10467 SW |
370 | set_addr(mtd, 0, 0, 0); |
371 | fsl_elbc_run_command(mtd); | |
372 | return; | |
373 | ||
374 | /* ERASE1 stores the block and page address */ | |
375 | case NAND_CMD_ERASE1: | |
3ab8f2a2 | 376 | dev_vdbg(priv->dev, |
76b10467 SW |
377 | "fsl_elbc_cmdfunc: NAND_CMD_ERASE1, " |
378 | "page_addr: 0x%x.\n", page_addr); | |
379 | set_addr(mtd, 0, page_addr, 0); | |
380 | return; | |
381 | ||
382 | /* ERASE2 uses the block and page address from ERASE1 */ | |
383 | case NAND_CMD_ERASE2: | |
3ab8f2a2 | 384 | dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n"); |
76b10467 SW |
385 | |
386 | out_be32(&lbc->fir, | |
476459a6 | 387 | (FIR_OP_CM0 << FIR_OP0_SHIFT) | |
76b10467 | 388 | (FIR_OP_PA << FIR_OP1_SHIFT) | |
476459a6 SW |
389 | (FIR_OP_CM2 << FIR_OP2_SHIFT) | |
390 | (FIR_OP_CW1 << FIR_OP3_SHIFT) | | |
391 | (FIR_OP_RS << FIR_OP4_SHIFT)); | |
76b10467 SW |
392 | |
393 | out_be32(&lbc->fcr, | |
394 | (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) | | |
476459a6 SW |
395 | (NAND_CMD_STATUS << FCR_CMD1_SHIFT) | |
396 | (NAND_CMD_ERASE2 << FCR_CMD2_SHIFT)); | |
76b10467 SW |
397 | |
398 | out_be32(&lbc->fbcr, 0); | |
3ab8f2a2 RZ |
399 | elbc_fcm_ctrl->read_bytes = 0; |
400 | elbc_fcm_ctrl->use_mdr = 1; | |
76b10467 SW |
401 | |
402 | fsl_elbc_run_command(mtd); | |
403 | return; | |
404 | ||
405 | /* SEQIN sets up the addr buffer and all registers except the length */ | |
406 | case NAND_CMD_SEQIN: { | |
407 | __be32 fcr; | |
3ab8f2a2 RZ |
408 | dev_vdbg(priv->dev, |
409 | "fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, " | |
76b10467 SW |
410 | "page_addr: 0x%x, column: 0x%x.\n", |
411 | page_addr, column); | |
412 | ||
eeda667a | 413 | elbc_fcm_ctrl->column = column; |
3ab8f2a2 | 414 | elbc_fcm_ctrl->use_mdr = 1; |
76b10467 | 415 | |
a9a552f0 LS |
416 | if (column >= mtd->writesize) { |
417 | /* OOB area */ | |
418 | column -= mtd->writesize; | |
419 | elbc_fcm_ctrl->oob = 1; | |
420 | } else { | |
421 | WARN_ON(column != 0); | |
422 | elbc_fcm_ctrl->oob = 0; | |
423 | } | |
424 | ||
476459a6 SW |
425 | fcr = (NAND_CMD_STATUS << FCR_CMD1_SHIFT) | |
426 | (NAND_CMD_SEQIN << FCR_CMD2_SHIFT) | | |
427 | (NAND_CMD_PAGEPROG << FCR_CMD3_SHIFT); | |
57650664 | 428 | |
476459a6 | 429 | if (priv->page_size) { |
76b10467 | 430 | out_be32(&lbc->fir, |
476459a6 | 431 | (FIR_OP_CM2 << FIR_OP0_SHIFT) | |
76b10467 SW |
432 | (FIR_OP_CA << FIR_OP1_SHIFT) | |
433 | (FIR_OP_PA << FIR_OP2_SHIFT) | | |
434 | (FIR_OP_WB << FIR_OP3_SHIFT) | | |
476459a6 SW |
435 | (FIR_OP_CM3 << FIR_OP4_SHIFT) | |
436 | (FIR_OP_CW1 << FIR_OP5_SHIFT) | | |
437 | (FIR_OP_RS << FIR_OP6_SHIFT)); | |
76b10467 SW |
438 | } else { |
439 | out_be32(&lbc->fir, | |
476459a6 | 440 | (FIR_OP_CM0 << FIR_OP0_SHIFT) | |
76b10467 SW |
441 | (FIR_OP_CM2 << FIR_OP1_SHIFT) | |
442 | (FIR_OP_CA << FIR_OP2_SHIFT) | | |
443 | (FIR_OP_PA << FIR_OP3_SHIFT) | | |
444 | (FIR_OP_WB << FIR_OP4_SHIFT) | | |
476459a6 SW |
445 | (FIR_OP_CM3 << FIR_OP5_SHIFT) | |
446 | (FIR_OP_CW1 << FIR_OP6_SHIFT) | | |
447 | (FIR_OP_RS << FIR_OP7_SHIFT)); | |
76b10467 | 448 | |
a9a552f0 | 449 | if (elbc_fcm_ctrl->oob) |
76b10467 | 450 | /* OOB area --> READOOB */ |
76b10467 | 451 | fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT; |
a9a552f0 | 452 | else |
76b10467 SW |
453 | /* First 256 bytes --> READ0 */ |
454 | fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT; | |
76b10467 SW |
455 | } |
456 | ||
457 | out_be32(&lbc->fcr, fcr); | |
3ab8f2a2 | 458 | set_addr(mtd, column, page_addr, elbc_fcm_ctrl->oob); |
76b10467 SW |
459 | return; |
460 | } | |
461 | ||
462 | /* PAGEPROG reuses all of the setup from SEQIN and adds the length */ | |
463 | case NAND_CMD_PAGEPROG: { | |
3ab8f2a2 | 464 | dev_vdbg(priv->dev, |
76b10467 | 465 | "fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG " |
3ab8f2a2 | 466 | "writing %d bytes.\n", elbc_fcm_ctrl->index); |
76b10467 SW |
467 | |
468 | /* if the write did not start at 0 or is not a full page | |
469 | * then set the exact length, otherwise use a full page | |
470 | * write so the HW generates the ECC. | |
471 | */ | |
3ab8f2a2 | 472 | if (elbc_fcm_ctrl->oob || elbc_fcm_ctrl->column != 0 || |
52a474de | 473 | elbc_fcm_ctrl->index != mtd->writesize + mtd->oobsize) |
e32de766 LS |
474 | out_be32(&lbc->fbcr, |
475 | elbc_fcm_ctrl->index - elbc_fcm_ctrl->column); | |
52a474de | 476 | else |
76b10467 | 477 | out_be32(&lbc->fbcr, 0); |
76b10467 SW |
478 | |
479 | fsl_elbc_run_command(mtd); | |
76b10467 SW |
480 | return; |
481 | } | |
482 | ||
483 | /* CMD_STATUS must read the status byte while CEB is active */ | |
484 | /* Note - it does not wait for the ready line */ | |
485 | case NAND_CMD_STATUS: | |
486 | out_be32(&lbc->fir, | |
487 | (FIR_OP_CM0 << FIR_OP0_SHIFT) | | |
488 | (FIR_OP_RBW << FIR_OP1_SHIFT)); | |
489 | out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT); | |
490 | out_be32(&lbc->fbcr, 1); | |
491 | set_addr(mtd, 0, 0, 0); | |
3ab8f2a2 | 492 | elbc_fcm_ctrl->read_bytes = 1; |
76b10467 SW |
493 | |
494 | fsl_elbc_run_command(mtd); | |
495 | ||
496 | /* The chip always seems to report that it is | |
497 | * write-protected, even when it is not. | |
498 | */ | |
3ab8f2a2 | 499 | setbits8(elbc_fcm_ctrl->addr, NAND_STATUS_WP); |
76b10467 SW |
500 | return; |
501 | ||
502 | /* RESET without waiting for the ready line */ | |
503 | case NAND_CMD_RESET: | |
3ab8f2a2 | 504 | dev_dbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_RESET.\n"); |
76b10467 SW |
505 | out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT); |
506 | out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT); | |
507 | fsl_elbc_run_command(mtd); | |
508 | return; | |
509 | ||
510 | default: | |
3ab8f2a2 | 511 | dev_err(priv->dev, |
76b10467 SW |
512 | "fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n", |
513 | command); | |
514 | } | |
515 | } | |
516 | ||
517 | static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip) | |
518 | { | |
519 | /* The hardware does not seem to support multiple | |
520 | * chips per bank. | |
521 | */ | |
522 | } | |
523 | ||
524 | /* | |
525 | * Write buf to the FCM Controller Data Buffer | |
526 | */ | |
527 | static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len) | |
528 | { | |
529 | struct nand_chip *chip = mtd->priv; | |
530 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 | 531 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; |
76b10467 SW |
532 | unsigned int bufsize = mtd->writesize + mtd->oobsize; |
533 | ||
0ff6631b | 534 | if (len <= 0) { |
3ab8f2a2 RZ |
535 | dev_err(priv->dev, "write_buf of %d bytes", len); |
536 | elbc_fcm_ctrl->status = 0; | |
76b10467 SW |
537 | return; |
538 | } | |
539 | ||
3ab8f2a2 RZ |
540 | if ((unsigned int)len > bufsize - elbc_fcm_ctrl->index) { |
541 | dev_err(priv->dev, | |
76b10467 SW |
542 | "write_buf beyond end of buffer " |
543 | "(%d requested, %u available)\n", | |
3ab8f2a2 RZ |
544 | len, bufsize - elbc_fcm_ctrl->index); |
545 | len = bufsize - elbc_fcm_ctrl->index; | |
76b10467 SW |
546 | } |
547 | ||
3ab8f2a2 | 548 | memcpy_toio(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], buf, len); |
0ff6631b AV |
549 | /* |
550 | * This is workaround for the weird elbc hangs during nand write, | |
551 | * Scott Wood says: "...perhaps difference in how long it takes a | |
552 | * write to make it through the localbus compared to a write to IMMR | |
553 | * is causing problems, and sync isn't helping for some reason." | |
554 | * Reading back the last byte helps though. | |
555 | */ | |
3ab8f2a2 | 556 | in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index] + len - 1); |
0ff6631b | 557 | |
3ab8f2a2 | 558 | elbc_fcm_ctrl->index += len; |
76b10467 SW |
559 | } |
560 | ||
561 | /* | |
562 | * read a byte from either the FCM hardware buffer if it has any data left | |
563 | * otherwise issue a command to read a single byte. | |
564 | */ | |
565 | static u8 fsl_elbc_read_byte(struct mtd_info *mtd) | |
566 | { | |
567 | struct nand_chip *chip = mtd->priv; | |
568 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 | 569 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; |
76b10467 SW |
570 | |
571 | /* If there are still bytes in the FCM, then use the next byte. */ | |
3ab8f2a2 RZ |
572 | if (elbc_fcm_ctrl->index < elbc_fcm_ctrl->read_bytes) |
573 | return in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index++]); | |
76b10467 | 574 | |
3ab8f2a2 | 575 | dev_err(priv->dev, "read_byte beyond end of buffer\n"); |
76b10467 SW |
576 | return ERR_BYTE; |
577 | } | |
578 | ||
579 | /* | |
580 | * Read from the FCM Controller Data Buffer | |
581 | */ | |
582 | static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len) | |
583 | { | |
584 | struct nand_chip *chip = mtd->priv; | |
585 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 | 586 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; |
76b10467 SW |
587 | int avail; |
588 | ||
589 | if (len < 0) | |
590 | return; | |
591 | ||
3ab8f2a2 RZ |
592 | avail = min((unsigned int)len, |
593 | elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index); | |
594 | memcpy_fromio(buf, &elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], avail); | |
595 | elbc_fcm_ctrl->index += avail; | |
76b10467 SW |
596 | |
597 | if (len > avail) | |
3ab8f2a2 | 598 | dev_err(priv->dev, |
76b10467 SW |
599 | "read_buf beyond end of buffer " |
600 | "(%d requested, %d available)\n", | |
601 | len, avail); | |
602 | } | |
603 | ||
76b10467 SW |
604 | /* This function is called after Program and Erase Operations to |
605 | * check for success or failure. | |
606 | */ | |
607 | static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip) | |
608 | { | |
609 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 | 610 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; |
76b10467 | 611 | |
3ab8f2a2 | 612 | if (elbc_fcm_ctrl->status != LTESR_CC) |
76b10467 SW |
613 | return NAND_STATUS_FAIL; |
614 | ||
615 | /* The chip always seems to report that it is | |
616 | * write-protected, even when it is not. | |
617 | */ | |
3ab8f2a2 | 618 | return (elbc_fcm_ctrl->mdr & 0xff) | NAND_STATUS_WP; |
76b10467 SW |
619 | } |
620 | ||
621 | static int fsl_elbc_chip_init_tail(struct mtd_info *mtd) | |
622 | { | |
623 | struct nand_chip *chip = mtd->priv; | |
624 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 | 625 | struct fsl_lbc_ctrl *ctrl = priv->ctrl; |
d4a32fe4 | 626 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
76b10467 SW |
627 | unsigned int al; |
628 | ||
629 | /* calculate FMR Address Length field */ | |
630 | al = 0; | |
631 | if (chip->pagemask & 0xffff0000) | |
632 | al++; | |
633 | if (chip->pagemask & 0xff000000) | |
634 | al++; | |
635 | ||
d8251108 | 636 | priv->fmr |= al << FMR_AL_SHIFT; |
76b10467 | 637 | |
3ab8f2a2 | 638 | dev_dbg(priv->dev, "fsl_elbc_init: nand->numchips = %d\n", |
76b10467 | 639 | chip->numchips); |
3ab8f2a2 | 640 | dev_dbg(priv->dev, "fsl_elbc_init: nand->chipsize = %lld\n", |
76b10467 | 641 | chip->chipsize); |
3ab8f2a2 | 642 | dev_dbg(priv->dev, "fsl_elbc_init: nand->pagemask = %8x\n", |
76b10467 | 643 | chip->pagemask); |
3ab8f2a2 | 644 | dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_delay = %d\n", |
76b10467 | 645 | chip->chip_delay); |
3ab8f2a2 | 646 | dev_dbg(priv->dev, "fsl_elbc_init: nand->badblockpos = %d\n", |
76b10467 | 647 | chip->badblockpos); |
3ab8f2a2 | 648 | dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_shift = %d\n", |
76b10467 | 649 | chip->chip_shift); |
3ab8f2a2 | 650 | dev_dbg(priv->dev, "fsl_elbc_init: nand->page_shift = %d\n", |
76b10467 | 651 | chip->page_shift); |
3ab8f2a2 | 652 | dev_dbg(priv->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n", |
76b10467 | 653 | chip->phys_erase_shift); |
3ab8f2a2 | 654 | dev_dbg(priv->dev, "fsl_elbc_init: nand->ecclayout = %p\n", |
76b10467 | 655 | chip->ecclayout); |
3ab8f2a2 | 656 | dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.mode = %d\n", |
76b10467 | 657 | chip->ecc.mode); |
3ab8f2a2 | 658 | dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.steps = %d\n", |
76b10467 | 659 | chip->ecc.steps); |
3ab8f2a2 | 660 | dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n", |
76b10467 | 661 | chip->ecc.bytes); |
3ab8f2a2 | 662 | dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.total = %d\n", |
76b10467 | 663 | chip->ecc.total); |
3ab8f2a2 | 664 | dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.layout = %p\n", |
76b10467 | 665 | chip->ecc.layout); |
3ab8f2a2 RZ |
666 | dev_dbg(priv->dev, "fsl_elbc_init: mtd->flags = %08x\n", mtd->flags); |
667 | dev_dbg(priv->dev, "fsl_elbc_init: mtd->size = %lld\n", mtd->size); | |
668 | dev_dbg(priv->dev, "fsl_elbc_init: mtd->erasesize = %d\n", | |
76b10467 | 669 | mtd->erasesize); |
3ab8f2a2 | 670 | dev_dbg(priv->dev, "fsl_elbc_init: mtd->writesize = %d\n", |
76b10467 | 671 | mtd->writesize); |
3ab8f2a2 | 672 | dev_dbg(priv->dev, "fsl_elbc_init: mtd->oobsize = %d\n", |
76b10467 SW |
673 | mtd->oobsize); |
674 | ||
675 | /* adjust Option Register and ECC to match Flash page size */ | |
676 | if (mtd->writesize == 512) { | |
677 | priv->page_size = 0; | |
1938de46 | 678 | clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS); |
76b10467 SW |
679 | } else if (mtd->writesize == 2048) { |
680 | priv->page_size = 1; | |
681 | setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS); | |
682 | /* adjust ecc setup if needed */ | |
683 | if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) == | |
684 | BR_DECC_CHK_GEN) { | |
685 | chip->ecc.size = 512; | |
686 | chip->ecc.layout = (priv->fmr & FMR_ECCM) ? | |
687 | &fsl_elbc_oob_lp_eccm1 : | |
688 | &fsl_elbc_oob_lp_eccm0; | |
76b10467 SW |
689 | } |
690 | } else { | |
3ab8f2a2 | 691 | dev_err(priv->dev, |
76b10467 SW |
692 | "fsl_elbc_init: page size %d is not supported\n", |
693 | mtd->writesize); | |
694 | return -1; | |
695 | } | |
696 | ||
76b10467 SW |
697 | return 0; |
698 | } | |
699 | ||
1fbb938d BN |
700 | static int fsl_elbc_read_page(struct mtd_info *mtd, struct nand_chip *chip, |
701 | uint8_t *buf, int oob_required, int page) | |
76b10467 | 702 | { |
3f91e94f MD |
703 | struct fsl_elbc_mtd *priv = chip->priv; |
704 | struct fsl_lbc_ctrl *ctrl = priv->ctrl; | |
705 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; | |
706 | ||
76b10467 | 707 | fsl_elbc_read_buf(mtd, buf, mtd->writesize); |
d112dc7f BN |
708 | if (oob_required) |
709 | fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
76b10467 SW |
710 | |
711 | if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL) | |
712 | mtd->ecc_stats.failed++; | |
713 | ||
3f91e94f | 714 | return elbc_fcm_ctrl->max_bitflips; |
76b10467 SW |
715 | } |
716 | ||
717 | /* ECC will be calculated automatically, and errors will be detected in | |
718 | * waitfunc. | |
719 | */ | |
fdbad98d | 720 | static int fsl_elbc_write_page(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 721 | const uint8_t *buf, int oob_required) |
76b10467 | 722 | { |
76b10467 SW |
723 | fsl_elbc_write_buf(mtd, buf, mtd->writesize); |
724 | fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
fdbad98d JW |
725 | |
726 | return 0; | |
76b10467 SW |
727 | } |
728 | ||
729 | static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv) | |
730 | { | |
3ab8f2a2 | 731 | struct fsl_lbc_ctrl *ctrl = priv->ctrl; |
d4a32fe4 | 732 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
3ab8f2a2 | 733 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; |
76b10467 SW |
734 | struct nand_chip *chip = &priv->chip; |
735 | ||
736 | dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank); | |
737 | ||
738 | /* Fill in fsl_elbc_mtd structure */ | |
739 | priv->mtd.priv = chip; | |
740 | priv->mtd.owner = THIS_MODULE; | |
03ed1078 | 741 | |
d8251108 SL |
742 | /* set timeout to maximum */ |
743 | priv->fmr = 15 << FMR_CWTO_SHIFT; | |
744 | if (in_be32(&lbc->bank[priv->bank].or) & OR_FCM_PGS) | |
745 | priv->fmr |= FMR_ECCM; | |
76b10467 SW |
746 | |
747 | /* fill in nand_chip structure */ | |
748 | /* set up function call table */ | |
749 | chip->read_byte = fsl_elbc_read_byte; | |
750 | chip->write_buf = fsl_elbc_write_buf; | |
751 | chip->read_buf = fsl_elbc_read_buf; | |
76b10467 SW |
752 | chip->select_chip = fsl_elbc_select_chip; |
753 | chip->cmdfunc = fsl_elbc_cmdfunc; | |
754 | chip->waitfunc = fsl_elbc_wait; | |
755 | ||
ec6e0ea3 AV |
756 | chip->bbt_td = &bbt_main_descr; |
757 | chip->bbt_md = &bbt_mirror_descr; | |
758 | ||
76b10467 | 759 | /* set up nand options */ |
bb9ebd4e | 760 | chip->bbt_options = NAND_BBT_USE_FLASH; |
76b10467 | 761 | |
3ab8f2a2 | 762 | chip->controller = &elbc_fcm_ctrl->controller; |
76b10467 SW |
763 | chip->priv = priv; |
764 | ||
765 | chip->ecc.read_page = fsl_elbc_read_page; | |
766 | chip->ecc.write_page = fsl_elbc_write_page; | |
767 | ||
768 | /* If CS Base Register selects full hardware ECC then use it */ | |
769 | if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) == | |
770 | BR_DECC_CHK_GEN) { | |
771 | chip->ecc.mode = NAND_ECC_HW; | |
772 | /* put in small page settings and adjust later if needed */ | |
773 | chip->ecc.layout = (priv->fmr & FMR_ECCM) ? | |
774 | &fsl_elbc_oob_sp_eccm1 : &fsl_elbc_oob_sp_eccm0; | |
775 | chip->ecc.size = 512; | |
776 | chip->ecc.bytes = 3; | |
6a918bad | 777 | chip->ecc.strength = 1; |
76b10467 SW |
778 | } else { |
779 | /* otherwise fall back to default software ECC */ | |
780 | chip->ecc.mode = NAND_ECC_SOFT; | |
781 | } | |
782 | ||
783 | return 0; | |
784 | } | |
785 | ||
786 | static int fsl_elbc_chip_remove(struct fsl_elbc_mtd *priv) | |
787 | { | |
3ab8f2a2 | 788 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; |
76b10467 SW |
789 | nand_release(&priv->mtd); |
790 | ||
9ebed3e6 AV |
791 | kfree(priv->mtd.name); |
792 | ||
76b10467 SW |
793 | if (priv->vbase) |
794 | iounmap(priv->vbase); | |
795 | ||
3ab8f2a2 | 796 | elbc_fcm_ctrl->chips[priv->bank] = NULL; |
76b10467 | 797 | kfree(priv); |
76b10467 SW |
798 | return 0; |
799 | } | |
800 | ||
3ab8f2a2 RZ |
801 | static DEFINE_MUTEX(fsl_elbc_nand_mutex); |
802 | ||
06f25510 | 803 | static int fsl_elbc_nand_probe(struct platform_device *pdev) |
76b10467 | 804 | { |
3ab8f2a2 | 805 | struct fsl_lbc_regs __iomem *lbc; |
76b10467 SW |
806 | struct fsl_elbc_mtd *priv; |
807 | struct resource res; | |
3ab8f2a2 | 808 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl; |
76b10467 | 809 | static const char *part_probe_types[] |
b6b0fae7 | 810 | = { "cmdlinepart", "RedBoot", "ofpart", NULL }; |
76b10467 SW |
811 | int ret; |
812 | int bank; | |
3ab8f2a2 RZ |
813 | struct device *dev; |
814 | struct device_node *node = pdev->dev.of_node; | |
b6b0fae7 | 815 | struct mtd_part_parser_data ppdata; |
3ab8f2a2 | 816 | |
b6b0fae7 | 817 | ppdata.of_node = pdev->dev.of_node; |
3ab8f2a2 RZ |
818 | if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs) |
819 | return -ENODEV; | |
820 | lbc = fsl_lbc_ctrl_dev->regs; | |
821 | dev = fsl_lbc_ctrl_dev->dev; | |
76b10467 SW |
822 | |
823 | /* get, allocate and map the memory resource */ | |
824 | ret = of_address_to_resource(node, 0, &res); | |
825 | if (ret) { | |
3ab8f2a2 | 826 | dev_err(dev, "failed to get resource\n"); |
76b10467 SW |
827 | return ret; |
828 | } | |
829 | ||
830 | /* find which chip select it is connected to */ | |
831 | for (bank = 0; bank < MAX_BANKS; bank++) | |
832 | if ((in_be32(&lbc->bank[bank].br) & BR_V) && | |
833 | (in_be32(&lbc->bank[bank].br) & BR_MSEL) == BR_MS_FCM && | |
834 | (in_be32(&lbc->bank[bank].br) & | |
835 | in_be32(&lbc->bank[bank].or) & BR_BA) | |
0b824d2b | 836 | == fsl_lbc_addr(res.start)) |
76b10467 SW |
837 | break; |
838 | ||
839 | if (bank >= MAX_BANKS) { | |
3ab8f2a2 | 840 | dev_err(dev, "address did not match any chip selects\n"); |
76b10467 SW |
841 | return -ENODEV; |
842 | } | |
843 | ||
844 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
845 | if (!priv) | |
846 | return -ENOMEM; | |
847 | ||
3ab8f2a2 RZ |
848 | mutex_lock(&fsl_elbc_nand_mutex); |
849 | if (!fsl_lbc_ctrl_dev->nand) { | |
850 | elbc_fcm_ctrl = kzalloc(sizeof(*elbc_fcm_ctrl), GFP_KERNEL); | |
851 | if (!elbc_fcm_ctrl) { | |
852 | dev_err(dev, "failed to allocate memory\n"); | |
853 | mutex_unlock(&fsl_elbc_nand_mutex); | |
854 | ret = -ENOMEM; | |
855 | goto err; | |
856 | } | |
857 | elbc_fcm_ctrl->counter++; | |
858 | ||
859 | spin_lock_init(&elbc_fcm_ctrl->controller.lock); | |
860 | init_waitqueue_head(&elbc_fcm_ctrl->controller.wq); | |
861 | fsl_lbc_ctrl_dev->nand = elbc_fcm_ctrl; | |
862 | } else { | |
863 | elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand; | |
864 | } | |
865 | mutex_unlock(&fsl_elbc_nand_mutex); | |
866 | ||
867 | elbc_fcm_ctrl->chips[bank] = priv; | |
76b10467 | 868 | priv->bank = bank; |
3ab8f2a2 | 869 | priv->ctrl = fsl_lbc_ctrl_dev; |
874d72c4 SW |
870 | priv->dev = &pdev->dev; |
871 | dev_set_drvdata(priv->dev, priv); | |
76b10467 | 872 | |
8a19b558 | 873 | priv->vbase = ioremap(res.start, resource_size(&res)); |
76b10467 | 874 | if (!priv->vbase) { |
3ab8f2a2 | 875 | dev_err(dev, "failed to map chip region\n"); |
76b10467 SW |
876 | ret = -ENOMEM; |
877 | goto err; | |
878 | } | |
879 | ||
650da9d0 | 880 | priv->mtd.name = kasprintf(GFP_KERNEL, "%x.flash", (unsigned)res.start); |
9ebed3e6 AV |
881 | if (!priv->mtd.name) { |
882 | ret = -ENOMEM; | |
883 | goto err; | |
884 | } | |
885 | ||
76b10467 SW |
886 | ret = fsl_elbc_chip_init(priv); |
887 | if (ret) | |
888 | goto err; | |
889 | ||
5e81e88a | 890 | ret = nand_scan_ident(&priv->mtd, 1, NULL); |
76b10467 SW |
891 | if (ret) |
892 | goto err; | |
893 | ||
894 | ret = fsl_elbc_chip_init_tail(&priv->mtd); | |
895 | if (ret) | |
896 | goto err; | |
897 | ||
898 | ret = nand_scan_tail(&priv->mtd); | |
899 | if (ret) | |
900 | goto err; | |
901 | ||
76b10467 SW |
902 | /* First look for RedBoot table or partitions on the command |
903 | * line, these take precedence over device tree information */ | |
99add422 DES |
904 | mtd_device_parse_register(&priv->mtd, part_probe_types, &ppdata, |
905 | NULL, 0); | |
76b10467 | 906 | |
4712fff9 SR |
907 | printk(KERN_INFO "eLBC NAND device at 0x%llx, bank %d\n", |
908 | (unsigned long long)res.start, priv->bank); | |
76b10467 SW |
909 | return 0; |
910 | ||
911 | err: | |
912 | fsl_elbc_chip_remove(priv); | |
913 | return ret; | |
914 | } | |
915 | ||
3ab8f2a2 | 916 | static int fsl_elbc_nand_remove(struct platform_device *pdev) |
76b10467 | 917 | { |
3ab8f2a2 | 918 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand; |
874d72c4 SW |
919 | struct fsl_elbc_mtd *priv = dev_get_drvdata(&pdev->dev); |
920 | ||
921 | fsl_elbc_chip_remove(priv); | |
3ab8f2a2 RZ |
922 | |
923 | mutex_lock(&fsl_elbc_nand_mutex); | |
924 | elbc_fcm_ctrl->counter--; | |
925 | if (!elbc_fcm_ctrl->counter) { | |
926 | fsl_lbc_ctrl_dev->nand = NULL; | |
927 | kfree(elbc_fcm_ctrl); | |
76b10467 | 928 | } |
3ab8f2a2 | 929 | mutex_unlock(&fsl_elbc_nand_mutex); |
76b10467 SW |
930 | |
931 | return 0; | |
932 | ||
76b10467 SW |
933 | } |
934 | ||
3ab8f2a2 RZ |
935 | static const struct of_device_id fsl_elbc_nand_match[] = { |
936 | { .compatible = "fsl,elbc-fcm-nand", }, | |
76b10467 SW |
937 | {} |
938 | }; | |
939 | ||
3ab8f2a2 | 940 | static struct platform_driver fsl_elbc_nand_driver = { |
76b10467 | 941 | .driver = { |
3ab8f2a2 | 942 | .name = "fsl,elbc-fcm-nand", |
4018294b | 943 | .owner = THIS_MODULE, |
3ab8f2a2 | 944 | .of_match_table = fsl_elbc_nand_match, |
76b10467 | 945 | }, |
3ab8f2a2 RZ |
946 | .probe = fsl_elbc_nand_probe, |
947 | .remove = fsl_elbc_nand_remove, | |
76b10467 SW |
948 | }; |
949 | ||
f99640de | 950 | module_platform_driver(fsl_elbc_nand_driver); |
76b10467 SW |
951 | |
952 | MODULE_LICENSE("GPL"); | |
953 | MODULE_AUTHOR("Freescale"); | |
954 | MODULE_DESCRIPTION("Freescale Enhanced Local Bus Controller MTD NAND driver"); |