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76b10467 SW |
1 | /* Freescale Enhanced Local Bus Controller NAND driver |
2 | * | |
3 | * Copyright (c) 2006-2007 Freescale Semiconductor | |
4 | * | |
5 | * Authors: Nick Spence <nick.spence@freescale.com>, | |
6 | * Scott Wood <scottwood@freescale.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #include <linux/module.h> | |
24 | #include <linux/types.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/kernel.h> | |
27 | #include <linux/string.h> | |
28 | #include <linux/ioport.h> | |
29 | #include <linux/of_platform.h> | |
30 | #include <linux/slab.h> | |
31 | #include <linux/interrupt.h> | |
32 | ||
33 | #include <linux/mtd/mtd.h> | |
34 | #include <linux/mtd/nand.h> | |
35 | #include <linux/mtd/nand_ecc.h> | |
36 | #include <linux/mtd/partitions.h> | |
37 | ||
38 | #include <asm/io.h> | |
d4a32fe4 | 39 | #include <asm/fsl_lbc.h> |
76b10467 SW |
40 | |
41 | #define MAX_BANKS 8 | |
42 | #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */ | |
43 | #define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */ | |
44 | ||
76b10467 SW |
45 | struct fsl_elbc_ctrl; |
46 | ||
47 | /* mtd information per set */ | |
48 | ||
49 | struct fsl_elbc_mtd { | |
50 | struct mtd_info mtd; | |
51 | struct nand_chip chip; | |
52 | struct fsl_elbc_ctrl *ctrl; | |
53 | ||
54 | struct device *dev; | |
55 | int bank; /* Chip select bank number */ | |
56 | u8 __iomem *vbase; /* Chip select base virtual address */ | |
57 | int page_size; /* NAND page size (0=512, 1=2048) */ | |
58 | unsigned int fmr; /* FCM Flash Mode Register value */ | |
59 | }; | |
60 | ||
61 | /* overview of the fsl elbc controller */ | |
62 | ||
63 | struct fsl_elbc_ctrl { | |
64 | struct nand_hw_control controller; | |
65 | struct fsl_elbc_mtd *chips[MAX_BANKS]; | |
66 | ||
67 | /* device info */ | |
68 | struct device *dev; | |
d4a32fe4 | 69 | struct fsl_lbc_regs __iomem *regs; |
76b10467 SW |
70 | int irq; |
71 | wait_queue_head_t irq_wait; | |
72 | unsigned int irq_status; /* status read from LTESR by irq handler */ | |
73 | u8 __iomem *addr; /* Address of assigned FCM buffer */ | |
74 | unsigned int page; /* Last page written to / read from */ | |
75 | unsigned int read_bytes; /* Number of bytes read during command */ | |
76 | unsigned int column; /* Saved column from SEQIN */ | |
77 | unsigned int index; /* Pointer to next byte to 'read' */ | |
78 | unsigned int status; /* status read from LTESR after last op */ | |
79 | unsigned int mdr; /* UPM/FCM Data Register value */ | |
80 | unsigned int use_mdr; /* Non zero if the MDR is to be set */ | |
81 | unsigned int oob; /* Non zero if operating on OOB data */ | |
82 | char *oob_poi; /* Place to write ECC after read back */ | |
83 | }; | |
84 | ||
85 | /* These map to the positions used by the FCM hardware ECC generator */ | |
86 | ||
87 | /* Small Page FLASH with FMR[ECCM] = 0 */ | |
88 | static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = { | |
89 | .eccbytes = 3, | |
90 | .eccpos = {6, 7, 8}, | |
91 | .oobfree = { {0, 5}, {9, 7} }, | |
92 | .oobavail = 12, | |
93 | }; | |
94 | ||
95 | /* Small Page FLASH with FMR[ECCM] = 1 */ | |
96 | static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = { | |
97 | .eccbytes = 3, | |
98 | .eccpos = {8, 9, 10}, | |
99 | .oobfree = { {0, 5}, {6, 2}, {11, 5} }, | |
100 | .oobavail = 12, | |
101 | }; | |
102 | ||
103 | /* Large Page FLASH with FMR[ECCM] = 0 */ | |
104 | static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = { | |
105 | .eccbytes = 12, | |
106 | .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56}, | |
107 | .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} }, | |
108 | .oobavail = 48, | |
109 | }; | |
110 | ||
111 | /* Large Page FLASH with FMR[ECCM] = 1 */ | |
112 | static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = { | |
113 | .eccbytes = 12, | |
114 | .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58}, | |
115 | .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} }, | |
116 | .oobavail = 48, | |
117 | }; | |
118 | ||
119 | /*=================================*/ | |
120 | ||
121 | /* | |
122 | * Set up the FCM hardware block and page address fields, and the fcm | |
123 | * structure addr field to point to the correct FCM buffer in memory | |
124 | */ | |
125 | static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) | |
126 | { | |
127 | struct nand_chip *chip = mtd->priv; | |
128 | struct fsl_elbc_mtd *priv = chip->priv; | |
129 | struct fsl_elbc_ctrl *ctrl = priv->ctrl; | |
d4a32fe4 | 130 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
76b10467 SW |
131 | int buf_num; |
132 | ||
133 | ctrl->page = page_addr; | |
134 | ||
135 | out_be32(&lbc->fbar, | |
136 | page_addr >> (chip->phys_erase_shift - chip->page_shift)); | |
137 | ||
138 | if (priv->page_size) { | |
139 | out_be32(&lbc->fpar, | |
140 | ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) | | |
141 | (oob ? FPAR_LP_MS : 0) | column); | |
142 | buf_num = (page_addr & 1) << 2; | |
143 | } else { | |
144 | out_be32(&lbc->fpar, | |
145 | ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) | | |
146 | (oob ? FPAR_SP_MS : 0) | column); | |
147 | buf_num = page_addr & 7; | |
148 | } | |
149 | ||
150 | ctrl->addr = priv->vbase + buf_num * 1024; | |
151 | ctrl->index = column; | |
152 | ||
153 | /* for OOB data point to the second half of the buffer */ | |
154 | if (oob) | |
155 | ctrl->index += priv->page_size ? 2048 : 512; | |
156 | ||
157 | dev_vdbg(ctrl->dev, "set_addr: bank=%d, ctrl->addr=0x%p (0x%p), " | |
158 | "index %x, pes %d ps %d\n", | |
159 | buf_num, ctrl->addr, priv->vbase, ctrl->index, | |
160 | chip->phys_erase_shift, chip->page_shift); | |
161 | } | |
162 | ||
163 | /* | |
164 | * execute FCM command and wait for it to complete | |
165 | */ | |
166 | static int fsl_elbc_run_command(struct mtd_info *mtd) | |
167 | { | |
168 | struct nand_chip *chip = mtd->priv; | |
169 | struct fsl_elbc_mtd *priv = chip->priv; | |
170 | struct fsl_elbc_ctrl *ctrl = priv->ctrl; | |
d4a32fe4 | 171 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
76b10467 SW |
172 | |
173 | /* Setup the FMR[OP] to execute without write protection */ | |
174 | out_be32(&lbc->fmr, priv->fmr | 3); | |
175 | if (ctrl->use_mdr) | |
176 | out_be32(&lbc->mdr, ctrl->mdr); | |
177 | ||
178 | dev_vdbg(ctrl->dev, | |
179 | "fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n", | |
180 | in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr)); | |
181 | dev_vdbg(ctrl->dev, | |
182 | "fsl_elbc_run_command: fbar=%08x fpar=%08x " | |
183 | "fbcr=%08x bank=%d\n", | |
184 | in_be32(&lbc->fbar), in_be32(&lbc->fpar), | |
185 | in_be32(&lbc->fbcr), priv->bank); | |
186 | ||
187 | /* execute special operation */ | |
188 | out_be32(&lbc->lsor, priv->bank); | |
189 | ||
190 | /* wait for FCM complete flag or timeout */ | |
191 | ctrl->irq_status = 0; | |
192 | wait_event_timeout(ctrl->irq_wait, ctrl->irq_status, | |
193 | FCM_TIMEOUT_MSECS * HZ/1000); | |
194 | ctrl->status = ctrl->irq_status; | |
195 | ||
196 | /* store mdr value in case it was needed */ | |
197 | if (ctrl->use_mdr) | |
198 | ctrl->mdr = in_be32(&lbc->mdr); | |
199 | ||
200 | ctrl->use_mdr = 0; | |
201 | ||
202 | dev_vdbg(ctrl->dev, | |
203 | "fsl_elbc_run_command: stat=%08x mdr=%08x fmr=%08x\n", | |
204 | ctrl->status, ctrl->mdr, in_be32(&lbc->fmr)); | |
205 | ||
206 | /* returns 0 on success otherwise non-zero) */ | |
207 | return ctrl->status == LTESR_CC ? 0 : -EIO; | |
208 | } | |
209 | ||
210 | static void fsl_elbc_do_read(struct nand_chip *chip, int oob) | |
211 | { | |
212 | struct fsl_elbc_mtd *priv = chip->priv; | |
213 | struct fsl_elbc_ctrl *ctrl = priv->ctrl; | |
d4a32fe4 | 214 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
76b10467 SW |
215 | |
216 | if (priv->page_size) { | |
217 | out_be32(&lbc->fir, | |
218 | (FIR_OP_CW0 << FIR_OP0_SHIFT) | | |
219 | (FIR_OP_CA << FIR_OP1_SHIFT) | | |
220 | (FIR_OP_PA << FIR_OP2_SHIFT) | | |
221 | (FIR_OP_CW1 << FIR_OP3_SHIFT) | | |
222 | (FIR_OP_RBW << FIR_OP4_SHIFT)); | |
223 | ||
224 | out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) | | |
225 | (NAND_CMD_READSTART << FCR_CMD1_SHIFT)); | |
226 | } else { | |
227 | out_be32(&lbc->fir, | |
228 | (FIR_OP_CW0 << FIR_OP0_SHIFT) | | |
229 | (FIR_OP_CA << FIR_OP1_SHIFT) | | |
230 | (FIR_OP_PA << FIR_OP2_SHIFT) | | |
231 | (FIR_OP_RBW << FIR_OP3_SHIFT)); | |
232 | ||
233 | if (oob) | |
234 | out_be32(&lbc->fcr, NAND_CMD_READOOB << FCR_CMD0_SHIFT); | |
235 | else | |
236 | out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT); | |
237 | } | |
238 | } | |
239 | ||
240 | /* cmdfunc send commands to the FCM */ | |
241 | static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command, | |
242 | int column, int page_addr) | |
243 | { | |
244 | struct nand_chip *chip = mtd->priv; | |
245 | struct fsl_elbc_mtd *priv = chip->priv; | |
246 | struct fsl_elbc_ctrl *ctrl = priv->ctrl; | |
d4a32fe4 | 247 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
76b10467 SW |
248 | |
249 | ctrl->use_mdr = 0; | |
250 | ||
251 | /* clear the read buffer */ | |
252 | ctrl->read_bytes = 0; | |
253 | if (command != NAND_CMD_PAGEPROG) | |
254 | ctrl->index = 0; | |
255 | ||
256 | switch (command) { | |
257 | /* READ0 and READ1 read the entire buffer to use hardware ECC. */ | |
258 | case NAND_CMD_READ1: | |
259 | column += 256; | |
260 | ||
261 | /* fall-through */ | |
262 | case NAND_CMD_READ0: | |
263 | dev_dbg(ctrl->dev, | |
264 | "fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:" | |
265 | " 0x%x, column: 0x%x.\n", page_addr, column); | |
266 | ||
267 | ||
268 | out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */ | |
269 | set_addr(mtd, 0, page_addr, 0); | |
270 | ||
271 | ctrl->read_bytes = mtd->writesize + mtd->oobsize; | |
272 | ctrl->index += column; | |
273 | ||
274 | fsl_elbc_do_read(chip, 0); | |
275 | fsl_elbc_run_command(mtd); | |
276 | return; | |
277 | ||
278 | /* READOOB reads only the OOB because no ECC is performed. */ | |
279 | case NAND_CMD_READOOB: | |
280 | dev_vdbg(ctrl->dev, | |
281 | "fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:" | |
282 | " 0x%x, column: 0x%x.\n", page_addr, column); | |
283 | ||
284 | out_be32(&lbc->fbcr, mtd->oobsize - column); | |
285 | set_addr(mtd, column, page_addr, 1); | |
286 | ||
287 | ctrl->read_bytes = mtd->writesize + mtd->oobsize; | |
288 | ||
289 | fsl_elbc_do_read(chip, 1); | |
290 | fsl_elbc_run_command(mtd); | |
291 | return; | |
292 | ||
293 | /* READID must read all 5 possible bytes while CEB is active */ | |
294 | case NAND_CMD_READID: | |
295 | dev_vdbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_READID.\n"); | |
296 | ||
297 | out_be32(&lbc->fir, (FIR_OP_CW0 << FIR_OP0_SHIFT) | | |
298 | (FIR_OP_UA << FIR_OP1_SHIFT) | | |
299 | (FIR_OP_RBW << FIR_OP2_SHIFT)); | |
300 | out_be32(&lbc->fcr, NAND_CMD_READID << FCR_CMD0_SHIFT); | |
301 | /* 5 bytes for manuf, device and exts */ | |
302 | out_be32(&lbc->fbcr, 5); | |
303 | ctrl->read_bytes = 5; | |
304 | ctrl->use_mdr = 1; | |
305 | ctrl->mdr = 0; | |
306 | ||
307 | set_addr(mtd, 0, 0, 0); | |
308 | fsl_elbc_run_command(mtd); | |
309 | return; | |
310 | ||
311 | /* ERASE1 stores the block and page address */ | |
312 | case NAND_CMD_ERASE1: | |
313 | dev_vdbg(ctrl->dev, | |
314 | "fsl_elbc_cmdfunc: NAND_CMD_ERASE1, " | |
315 | "page_addr: 0x%x.\n", page_addr); | |
316 | set_addr(mtd, 0, page_addr, 0); | |
317 | return; | |
318 | ||
319 | /* ERASE2 uses the block and page address from ERASE1 */ | |
320 | case NAND_CMD_ERASE2: | |
321 | dev_vdbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n"); | |
322 | ||
323 | out_be32(&lbc->fir, | |
324 | (FIR_OP_CW0 << FIR_OP0_SHIFT) | | |
325 | (FIR_OP_PA << FIR_OP1_SHIFT) | | |
326 | (FIR_OP_CM1 << FIR_OP2_SHIFT)); | |
327 | ||
328 | out_be32(&lbc->fcr, | |
329 | (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) | | |
330 | (NAND_CMD_ERASE2 << FCR_CMD1_SHIFT)); | |
331 | ||
332 | out_be32(&lbc->fbcr, 0); | |
333 | ctrl->read_bytes = 0; | |
334 | ||
335 | fsl_elbc_run_command(mtd); | |
336 | return; | |
337 | ||
338 | /* SEQIN sets up the addr buffer and all registers except the length */ | |
339 | case NAND_CMD_SEQIN: { | |
340 | __be32 fcr; | |
341 | dev_vdbg(ctrl->dev, | |
342 | "fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, " | |
343 | "page_addr: 0x%x, column: 0x%x.\n", | |
344 | page_addr, column); | |
345 | ||
346 | ctrl->column = column; | |
347 | ctrl->oob = 0; | |
348 | ||
76b10467 | 349 | if (priv->page_size) { |
57650664 SW |
350 | fcr = (NAND_CMD_SEQIN << FCR_CMD0_SHIFT) | |
351 | (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT); | |
352 | ||
76b10467 SW |
353 | out_be32(&lbc->fir, |
354 | (FIR_OP_CW0 << FIR_OP0_SHIFT) | | |
355 | (FIR_OP_CA << FIR_OP1_SHIFT) | | |
356 | (FIR_OP_PA << FIR_OP2_SHIFT) | | |
357 | (FIR_OP_WB << FIR_OP3_SHIFT) | | |
358 | (FIR_OP_CW1 << FIR_OP4_SHIFT)); | |
76b10467 | 359 | } else { |
57650664 SW |
360 | fcr = (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT) | |
361 | (NAND_CMD_SEQIN << FCR_CMD2_SHIFT); | |
362 | ||
76b10467 SW |
363 | out_be32(&lbc->fir, |
364 | (FIR_OP_CW0 << FIR_OP0_SHIFT) | | |
365 | (FIR_OP_CM2 << FIR_OP1_SHIFT) | | |
366 | (FIR_OP_CA << FIR_OP2_SHIFT) | | |
367 | (FIR_OP_PA << FIR_OP3_SHIFT) | | |
368 | (FIR_OP_WB << FIR_OP4_SHIFT) | | |
369 | (FIR_OP_CW1 << FIR_OP5_SHIFT)); | |
370 | ||
371 | if (column >= mtd->writesize) { | |
372 | /* OOB area --> READOOB */ | |
373 | column -= mtd->writesize; | |
374 | fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT; | |
375 | ctrl->oob = 1; | |
376 | } else if (column < 256) { | |
377 | /* First 256 bytes --> READ0 */ | |
378 | fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT; | |
379 | } else { | |
380 | /* Second 256 bytes --> READ1 */ | |
381 | fcr |= NAND_CMD_READ1 << FCR_CMD0_SHIFT; | |
382 | } | |
383 | } | |
384 | ||
385 | out_be32(&lbc->fcr, fcr); | |
386 | set_addr(mtd, column, page_addr, ctrl->oob); | |
387 | return; | |
388 | } | |
389 | ||
390 | /* PAGEPROG reuses all of the setup from SEQIN and adds the length */ | |
391 | case NAND_CMD_PAGEPROG: { | |
392 | int full_page; | |
393 | dev_vdbg(ctrl->dev, | |
394 | "fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG " | |
395 | "writing %d bytes.\n", ctrl->index); | |
396 | ||
397 | /* if the write did not start at 0 or is not a full page | |
398 | * then set the exact length, otherwise use a full page | |
399 | * write so the HW generates the ECC. | |
400 | */ | |
401 | if (ctrl->oob || ctrl->column != 0 || | |
402 | ctrl->index != mtd->writesize + mtd->oobsize) { | |
403 | out_be32(&lbc->fbcr, ctrl->index); | |
404 | full_page = 0; | |
405 | } else { | |
406 | out_be32(&lbc->fbcr, 0); | |
407 | full_page = 1; | |
408 | } | |
409 | ||
410 | fsl_elbc_run_command(mtd); | |
411 | ||
412 | /* Read back the page in order to fill in the ECC for the | |
413 | * caller. Is this really needed? | |
414 | */ | |
415 | if (full_page && ctrl->oob_poi) { | |
416 | out_be32(&lbc->fbcr, 3); | |
417 | set_addr(mtd, 6, page_addr, 1); | |
418 | ||
419 | ctrl->read_bytes = mtd->writesize + 9; | |
420 | ||
421 | fsl_elbc_do_read(chip, 1); | |
422 | fsl_elbc_run_command(mtd); | |
423 | ||
424 | memcpy_fromio(ctrl->oob_poi + 6, | |
425 | &ctrl->addr[ctrl->index], 3); | |
426 | ctrl->index += 3; | |
427 | } | |
428 | ||
429 | ctrl->oob_poi = NULL; | |
430 | return; | |
431 | } | |
432 | ||
433 | /* CMD_STATUS must read the status byte while CEB is active */ | |
434 | /* Note - it does not wait for the ready line */ | |
435 | case NAND_CMD_STATUS: | |
436 | out_be32(&lbc->fir, | |
437 | (FIR_OP_CM0 << FIR_OP0_SHIFT) | | |
438 | (FIR_OP_RBW << FIR_OP1_SHIFT)); | |
439 | out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT); | |
440 | out_be32(&lbc->fbcr, 1); | |
441 | set_addr(mtd, 0, 0, 0); | |
442 | ctrl->read_bytes = 1; | |
443 | ||
444 | fsl_elbc_run_command(mtd); | |
445 | ||
446 | /* The chip always seems to report that it is | |
447 | * write-protected, even when it is not. | |
448 | */ | |
449 | setbits8(ctrl->addr, NAND_STATUS_WP); | |
450 | return; | |
451 | ||
452 | /* RESET without waiting for the ready line */ | |
453 | case NAND_CMD_RESET: | |
454 | dev_dbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_RESET.\n"); | |
455 | out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT); | |
456 | out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT); | |
457 | fsl_elbc_run_command(mtd); | |
458 | return; | |
459 | ||
460 | default: | |
461 | dev_err(ctrl->dev, | |
462 | "fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n", | |
463 | command); | |
464 | } | |
465 | } | |
466 | ||
467 | static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip) | |
468 | { | |
469 | /* The hardware does not seem to support multiple | |
470 | * chips per bank. | |
471 | */ | |
472 | } | |
473 | ||
474 | /* | |
475 | * Write buf to the FCM Controller Data Buffer | |
476 | */ | |
477 | static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len) | |
478 | { | |
479 | struct nand_chip *chip = mtd->priv; | |
480 | struct fsl_elbc_mtd *priv = chip->priv; | |
481 | struct fsl_elbc_ctrl *ctrl = priv->ctrl; | |
482 | unsigned int bufsize = mtd->writesize + mtd->oobsize; | |
483 | ||
484 | if (len < 0) { | |
485 | dev_err(ctrl->dev, "write_buf of %d bytes", len); | |
486 | ctrl->status = 0; | |
487 | return; | |
488 | } | |
489 | ||
490 | if ((unsigned int)len > bufsize - ctrl->index) { | |
491 | dev_err(ctrl->dev, | |
492 | "write_buf beyond end of buffer " | |
493 | "(%d requested, %u available)\n", | |
494 | len, bufsize - ctrl->index); | |
495 | len = bufsize - ctrl->index; | |
496 | } | |
497 | ||
498 | memcpy_toio(&ctrl->addr[ctrl->index], buf, len); | |
499 | ctrl->index += len; | |
500 | } | |
501 | ||
502 | /* | |
503 | * read a byte from either the FCM hardware buffer if it has any data left | |
504 | * otherwise issue a command to read a single byte. | |
505 | */ | |
506 | static u8 fsl_elbc_read_byte(struct mtd_info *mtd) | |
507 | { | |
508 | struct nand_chip *chip = mtd->priv; | |
509 | struct fsl_elbc_mtd *priv = chip->priv; | |
510 | struct fsl_elbc_ctrl *ctrl = priv->ctrl; | |
511 | ||
512 | /* If there are still bytes in the FCM, then use the next byte. */ | |
513 | if (ctrl->index < ctrl->read_bytes) | |
514 | return in_8(&ctrl->addr[ctrl->index++]); | |
515 | ||
516 | dev_err(ctrl->dev, "read_byte beyond end of buffer\n"); | |
517 | return ERR_BYTE; | |
518 | } | |
519 | ||
520 | /* | |
521 | * Read from the FCM Controller Data Buffer | |
522 | */ | |
523 | static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len) | |
524 | { | |
525 | struct nand_chip *chip = mtd->priv; | |
526 | struct fsl_elbc_mtd *priv = chip->priv; | |
527 | struct fsl_elbc_ctrl *ctrl = priv->ctrl; | |
528 | int avail; | |
529 | ||
530 | if (len < 0) | |
531 | return; | |
532 | ||
533 | avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index); | |
534 | memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail); | |
535 | ctrl->index += avail; | |
536 | ||
537 | if (len > avail) | |
538 | dev_err(ctrl->dev, | |
539 | "read_buf beyond end of buffer " | |
540 | "(%d requested, %d available)\n", | |
541 | len, avail); | |
542 | } | |
543 | ||
544 | /* | |
545 | * Verify buffer against the FCM Controller Data Buffer | |
546 | */ | |
547 | static int fsl_elbc_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) | |
548 | { | |
549 | struct nand_chip *chip = mtd->priv; | |
550 | struct fsl_elbc_mtd *priv = chip->priv; | |
551 | struct fsl_elbc_ctrl *ctrl = priv->ctrl; | |
552 | int i; | |
553 | ||
554 | if (len < 0) { | |
555 | dev_err(ctrl->dev, "write_buf of %d bytes", len); | |
556 | return -EINVAL; | |
557 | } | |
558 | ||
559 | if ((unsigned int)len > ctrl->read_bytes - ctrl->index) { | |
560 | dev_err(ctrl->dev, | |
561 | "verify_buf beyond end of buffer " | |
562 | "(%d requested, %u available)\n", | |
563 | len, ctrl->read_bytes - ctrl->index); | |
564 | ||
565 | ctrl->index = ctrl->read_bytes; | |
566 | return -EINVAL; | |
567 | } | |
568 | ||
569 | for (i = 0; i < len; i++) | |
570 | if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i]) | |
571 | break; | |
572 | ||
573 | ctrl->index += len; | |
574 | return i == len && ctrl->status == LTESR_CC ? 0 : -EIO; | |
575 | } | |
576 | ||
577 | /* This function is called after Program and Erase Operations to | |
578 | * check for success or failure. | |
579 | */ | |
580 | static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip) | |
581 | { | |
582 | struct fsl_elbc_mtd *priv = chip->priv; | |
583 | struct fsl_elbc_ctrl *ctrl = priv->ctrl; | |
d4a32fe4 | 584 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
76b10467 SW |
585 | |
586 | if (ctrl->status != LTESR_CC) | |
587 | return NAND_STATUS_FAIL; | |
588 | ||
589 | /* Use READ_STATUS command, but wait for the device to be ready */ | |
590 | ctrl->use_mdr = 0; | |
591 | out_be32(&lbc->fir, | |
592 | (FIR_OP_CW0 << FIR_OP0_SHIFT) | | |
593 | (FIR_OP_RBW << FIR_OP1_SHIFT)); | |
594 | out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT); | |
595 | out_be32(&lbc->fbcr, 1); | |
596 | set_addr(mtd, 0, 0, 0); | |
597 | ctrl->read_bytes = 1; | |
598 | ||
599 | fsl_elbc_run_command(mtd); | |
600 | ||
601 | if (ctrl->status != LTESR_CC) | |
602 | return NAND_STATUS_FAIL; | |
603 | ||
604 | /* The chip always seems to report that it is | |
605 | * write-protected, even when it is not. | |
606 | */ | |
607 | setbits8(ctrl->addr, NAND_STATUS_WP); | |
608 | return fsl_elbc_read_byte(mtd); | |
609 | } | |
610 | ||
611 | static int fsl_elbc_chip_init_tail(struct mtd_info *mtd) | |
612 | { | |
613 | struct nand_chip *chip = mtd->priv; | |
614 | struct fsl_elbc_mtd *priv = chip->priv; | |
615 | struct fsl_elbc_ctrl *ctrl = priv->ctrl; | |
d4a32fe4 | 616 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
76b10467 SW |
617 | unsigned int al; |
618 | ||
619 | /* calculate FMR Address Length field */ | |
620 | al = 0; | |
621 | if (chip->pagemask & 0xffff0000) | |
622 | al++; | |
623 | if (chip->pagemask & 0xff000000) | |
624 | al++; | |
625 | ||
626 | /* add to ECCM mode set in fsl_elbc_init */ | |
627 | priv->fmr |= (12 << FMR_CWTO_SHIFT) | /* Timeout > 12 ms */ | |
628 | (al << FMR_AL_SHIFT); | |
629 | ||
630 | dev_dbg(ctrl->dev, "fsl_elbc_init: nand->numchips = %d\n", | |
631 | chip->numchips); | |
632 | dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chipsize = %ld\n", | |
633 | chip->chipsize); | |
634 | dev_dbg(ctrl->dev, "fsl_elbc_init: nand->pagemask = %8x\n", | |
635 | chip->pagemask); | |
636 | dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chip_delay = %d\n", | |
637 | chip->chip_delay); | |
638 | dev_dbg(ctrl->dev, "fsl_elbc_init: nand->badblockpos = %d\n", | |
639 | chip->badblockpos); | |
640 | dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chip_shift = %d\n", | |
641 | chip->chip_shift); | |
642 | dev_dbg(ctrl->dev, "fsl_elbc_init: nand->page_shift = %d\n", | |
643 | chip->page_shift); | |
644 | dev_dbg(ctrl->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n", | |
645 | chip->phys_erase_shift); | |
646 | dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecclayout = %p\n", | |
647 | chip->ecclayout); | |
648 | dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.mode = %d\n", | |
649 | chip->ecc.mode); | |
650 | dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.steps = %d\n", | |
651 | chip->ecc.steps); | |
652 | dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n", | |
653 | chip->ecc.bytes); | |
654 | dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.total = %d\n", | |
655 | chip->ecc.total); | |
656 | dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.layout = %p\n", | |
657 | chip->ecc.layout); | |
658 | dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->flags = %08x\n", mtd->flags); | |
659 | dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->size = %d\n", mtd->size); | |
660 | dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->erasesize = %d\n", | |
661 | mtd->erasesize); | |
662 | dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->writesize = %d\n", | |
663 | mtd->writesize); | |
664 | dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->oobsize = %d\n", | |
665 | mtd->oobsize); | |
666 | ||
667 | /* adjust Option Register and ECC to match Flash page size */ | |
668 | if (mtd->writesize == 512) { | |
669 | priv->page_size = 0; | |
670 | clrbits32(&lbc->bank[priv->bank].or, ~OR_FCM_PGS); | |
671 | } else if (mtd->writesize == 2048) { | |
672 | priv->page_size = 1; | |
673 | setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS); | |
674 | /* adjust ecc setup if needed */ | |
675 | if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) == | |
676 | BR_DECC_CHK_GEN) { | |
677 | chip->ecc.size = 512; | |
678 | chip->ecc.layout = (priv->fmr & FMR_ECCM) ? | |
679 | &fsl_elbc_oob_lp_eccm1 : | |
680 | &fsl_elbc_oob_lp_eccm0; | |
681 | mtd->ecclayout = chip->ecc.layout; | |
682 | mtd->oobavail = chip->ecc.layout->oobavail; | |
683 | } | |
684 | } else { | |
685 | dev_err(ctrl->dev, | |
686 | "fsl_elbc_init: page size %d is not supported\n", | |
687 | mtd->writesize); | |
688 | return -1; | |
689 | } | |
690 | ||
691 | /* The default u-boot configuration on MPC8313ERDB causes errors; | |
692 | * more delay is needed. This should be safe for other boards | |
693 | * as well. | |
694 | */ | |
695 | setbits32(&lbc->bank[priv->bank].or, 0x70); | |
696 | return 0; | |
697 | } | |
698 | ||
699 | static int fsl_elbc_read_page(struct mtd_info *mtd, | |
700 | struct nand_chip *chip, | |
701 | uint8_t *buf) | |
702 | { | |
703 | fsl_elbc_read_buf(mtd, buf, mtd->writesize); | |
704 | fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
705 | ||
706 | if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL) | |
707 | mtd->ecc_stats.failed++; | |
708 | ||
709 | return 0; | |
710 | } | |
711 | ||
712 | /* ECC will be calculated automatically, and errors will be detected in | |
713 | * waitfunc. | |
714 | */ | |
715 | static void fsl_elbc_write_page(struct mtd_info *mtd, | |
716 | struct nand_chip *chip, | |
717 | const uint8_t *buf) | |
718 | { | |
719 | struct fsl_elbc_mtd *priv = chip->priv; | |
720 | struct fsl_elbc_ctrl *ctrl = priv->ctrl; | |
721 | ||
722 | fsl_elbc_write_buf(mtd, buf, mtd->writesize); | |
723 | fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
724 | ||
725 | ctrl->oob_poi = chip->oob_poi; | |
726 | } | |
727 | ||
728 | static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv) | |
729 | { | |
730 | struct fsl_elbc_ctrl *ctrl = priv->ctrl; | |
d4a32fe4 | 731 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
76b10467 SW |
732 | struct nand_chip *chip = &priv->chip; |
733 | ||
734 | dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank); | |
735 | ||
736 | /* Fill in fsl_elbc_mtd structure */ | |
737 | priv->mtd.priv = chip; | |
738 | priv->mtd.owner = THIS_MODULE; | |
739 | priv->fmr = 0; /* rest filled in later */ | |
740 | ||
741 | /* fill in nand_chip structure */ | |
742 | /* set up function call table */ | |
743 | chip->read_byte = fsl_elbc_read_byte; | |
744 | chip->write_buf = fsl_elbc_write_buf; | |
745 | chip->read_buf = fsl_elbc_read_buf; | |
746 | chip->verify_buf = fsl_elbc_verify_buf; | |
747 | chip->select_chip = fsl_elbc_select_chip; | |
748 | chip->cmdfunc = fsl_elbc_cmdfunc; | |
749 | chip->waitfunc = fsl_elbc_wait; | |
750 | ||
751 | /* set up nand options */ | |
752 | chip->options = NAND_NO_READRDY | NAND_NO_AUTOINCR; | |
753 | ||
754 | chip->controller = &ctrl->controller; | |
755 | chip->priv = priv; | |
756 | ||
757 | chip->ecc.read_page = fsl_elbc_read_page; | |
758 | chip->ecc.write_page = fsl_elbc_write_page; | |
759 | ||
760 | /* If CS Base Register selects full hardware ECC then use it */ | |
761 | if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) == | |
762 | BR_DECC_CHK_GEN) { | |
763 | chip->ecc.mode = NAND_ECC_HW; | |
764 | /* put in small page settings and adjust later if needed */ | |
765 | chip->ecc.layout = (priv->fmr & FMR_ECCM) ? | |
766 | &fsl_elbc_oob_sp_eccm1 : &fsl_elbc_oob_sp_eccm0; | |
767 | chip->ecc.size = 512; | |
768 | chip->ecc.bytes = 3; | |
769 | } else { | |
770 | /* otherwise fall back to default software ECC */ | |
771 | chip->ecc.mode = NAND_ECC_SOFT; | |
772 | } | |
773 | ||
774 | return 0; | |
775 | } | |
776 | ||
777 | static int fsl_elbc_chip_remove(struct fsl_elbc_mtd *priv) | |
778 | { | |
779 | struct fsl_elbc_ctrl *ctrl = priv->ctrl; | |
780 | ||
781 | nand_release(&priv->mtd); | |
782 | ||
783 | if (priv->vbase) | |
784 | iounmap(priv->vbase); | |
785 | ||
786 | ctrl->chips[priv->bank] = NULL; | |
787 | kfree(priv); | |
788 | ||
789 | return 0; | |
790 | } | |
791 | ||
792 | static int fsl_elbc_chip_probe(struct fsl_elbc_ctrl *ctrl, | |
793 | struct device_node *node) | |
794 | { | |
d4a32fe4 | 795 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
76b10467 SW |
796 | struct fsl_elbc_mtd *priv; |
797 | struct resource res; | |
798 | #ifdef CONFIG_MTD_PARTITIONS | |
799 | static const char *part_probe_types[] | |
800 | = { "cmdlinepart", "RedBoot", NULL }; | |
801 | struct mtd_partition *parts; | |
802 | #endif | |
803 | int ret; | |
804 | int bank; | |
805 | ||
806 | /* get, allocate and map the memory resource */ | |
807 | ret = of_address_to_resource(node, 0, &res); | |
808 | if (ret) { | |
809 | dev_err(ctrl->dev, "failed to get resource\n"); | |
810 | return ret; | |
811 | } | |
812 | ||
813 | /* find which chip select it is connected to */ | |
814 | for (bank = 0; bank < MAX_BANKS; bank++) | |
815 | if ((in_be32(&lbc->bank[bank].br) & BR_V) && | |
816 | (in_be32(&lbc->bank[bank].br) & BR_MSEL) == BR_MS_FCM && | |
817 | (in_be32(&lbc->bank[bank].br) & | |
818 | in_be32(&lbc->bank[bank].or) & BR_BA) | |
819 | == res.start) | |
820 | break; | |
821 | ||
822 | if (bank >= MAX_BANKS) { | |
823 | dev_err(ctrl->dev, "address did not match any chip selects\n"); | |
824 | return -ENODEV; | |
825 | } | |
826 | ||
827 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
828 | if (!priv) | |
829 | return -ENOMEM; | |
830 | ||
831 | ctrl->chips[bank] = priv; | |
832 | priv->bank = bank; | |
833 | priv->ctrl = ctrl; | |
834 | priv->dev = ctrl->dev; | |
835 | ||
836 | priv->vbase = ioremap(res.start, res.end - res.start + 1); | |
837 | if (!priv->vbase) { | |
838 | dev_err(ctrl->dev, "failed to map chip region\n"); | |
839 | ret = -ENOMEM; | |
840 | goto err; | |
841 | } | |
842 | ||
843 | ret = fsl_elbc_chip_init(priv); | |
844 | if (ret) | |
845 | goto err; | |
846 | ||
847 | ret = nand_scan_ident(&priv->mtd, 1); | |
848 | if (ret) | |
849 | goto err; | |
850 | ||
851 | ret = fsl_elbc_chip_init_tail(&priv->mtd); | |
852 | if (ret) | |
853 | goto err; | |
854 | ||
855 | ret = nand_scan_tail(&priv->mtd); | |
856 | if (ret) | |
857 | goto err; | |
858 | ||
859 | #ifdef CONFIG_MTD_PARTITIONS | |
860 | /* First look for RedBoot table or partitions on the command | |
861 | * line, these take precedence over device tree information */ | |
862 | ret = parse_mtd_partitions(&priv->mtd, part_probe_types, &parts, 0); | |
863 | if (ret < 0) | |
864 | goto err; | |
865 | ||
866 | #ifdef CONFIG_MTD_OF_PARTS | |
867 | if (ret == 0) { | |
868 | ret = of_mtd_parse_partitions(priv->dev, &priv->mtd, | |
869 | node, &parts); | |
870 | if (ret < 0) | |
871 | goto err; | |
872 | } | |
873 | #endif | |
874 | ||
875 | if (ret > 0) | |
876 | add_mtd_partitions(&priv->mtd, parts, ret); | |
877 | else | |
878 | #endif | |
879 | add_mtd_device(&priv->mtd); | |
880 | ||
881 | printk(KERN_INFO "eLBC NAND device at 0x%zx, bank %d\n", | |
882 | res.start, priv->bank); | |
883 | return 0; | |
884 | ||
885 | err: | |
886 | fsl_elbc_chip_remove(priv); | |
887 | return ret; | |
888 | } | |
889 | ||
890 | static int __devinit fsl_elbc_ctrl_init(struct fsl_elbc_ctrl *ctrl) | |
891 | { | |
d4a32fe4 | 892 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
76b10467 SW |
893 | |
894 | /* clear event registers */ | |
895 | setbits32(&lbc->ltesr, LTESR_NAND_MASK); | |
896 | out_be32(&lbc->lteatr, 0); | |
897 | ||
898 | /* Enable interrupts for any detected events */ | |
899 | out_be32(&lbc->lteir, LTESR_NAND_MASK); | |
900 | ||
901 | ctrl->read_bytes = 0; | |
902 | ctrl->index = 0; | |
903 | ctrl->addr = NULL; | |
904 | ||
905 | return 0; | |
906 | } | |
907 | ||
908 | static int __devexit fsl_elbc_ctrl_remove(struct of_device *ofdev) | |
909 | { | |
910 | struct fsl_elbc_ctrl *ctrl = dev_get_drvdata(&ofdev->dev); | |
911 | int i; | |
912 | ||
913 | for (i = 0; i < MAX_BANKS; i++) | |
914 | if (ctrl->chips[i]) | |
915 | fsl_elbc_chip_remove(ctrl->chips[i]); | |
916 | ||
917 | if (ctrl->irq) | |
918 | free_irq(ctrl->irq, ctrl); | |
919 | ||
920 | if (ctrl->regs) | |
921 | iounmap(ctrl->regs); | |
922 | ||
923 | dev_set_drvdata(&ofdev->dev, NULL); | |
924 | kfree(ctrl); | |
925 | return 0; | |
926 | } | |
927 | ||
928 | /* NOTE: This interrupt is also used to report other localbus events, | |
929 | * such as transaction errors on other chipselects. If we want to | |
930 | * capture those, we'll need to move the IRQ code into a shared | |
931 | * LBC driver. | |
932 | */ | |
933 | ||
934 | static irqreturn_t fsl_elbc_ctrl_irq(int irqno, void *data) | |
935 | { | |
936 | struct fsl_elbc_ctrl *ctrl = data; | |
d4a32fe4 | 937 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
76b10467 SW |
938 | __be32 status = in_be32(&lbc->ltesr) & LTESR_NAND_MASK; |
939 | ||
940 | if (status) { | |
941 | out_be32(&lbc->ltesr, status); | |
942 | out_be32(&lbc->lteatr, 0); | |
943 | ||
944 | ctrl->irq_status = status; | |
945 | smp_wmb(); | |
946 | wake_up(&ctrl->irq_wait); | |
947 | ||
948 | return IRQ_HANDLED; | |
949 | } | |
950 | ||
951 | return IRQ_NONE; | |
952 | } | |
953 | ||
954 | /* fsl_elbc_ctrl_probe | |
955 | * | |
956 | * called by device layer when it finds a device matching | |
957 | * one our driver can handled. This code allocates all of | |
958 | * the resources needed for the controller only. The | |
959 | * resources for the NAND banks themselves are allocated | |
960 | * in the chip probe function. | |
961 | */ | |
962 | ||
963 | static int __devinit fsl_elbc_ctrl_probe(struct of_device *ofdev, | |
964 | const struct of_device_id *match) | |
965 | { | |
966 | struct device_node *child; | |
967 | struct fsl_elbc_ctrl *ctrl; | |
968 | int ret; | |
969 | ||
970 | ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); | |
971 | if (!ctrl) | |
972 | return -ENOMEM; | |
973 | ||
974 | dev_set_drvdata(&ofdev->dev, ctrl); | |
975 | ||
976 | spin_lock_init(&ctrl->controller.lock); | |
977 | init_waitqueue_head(&ctrl->controller.wq); | |
978 | init_waitqueue_head(&ctrl->irq_wait); | |
979 | ||
980 | ctrl->regs = of_iomap(ofdev->node, 0); | |
981 | if (!ctrl->regs) { | |
982 | dev_err(&ofdev->dev, "failed to get memory region\n"); | |
983 | ret = -ENODEV; | |
984 | goto err; | |
985 | } | |
986 | ||
987 | ctrl->irq = of_irq_to_resource(ofdev->node, 0, NULL); | |
988 | if (ctrl->irq == NO_IRQ) { | |
989 | dev_err(&ofdev->dev, "failed to get irq resource\n"); | |
990 | ret = -ENODEV; | |
991 | goto err; | |
992 | } | |
993 | ||
994 | ctrl->dev = &ofdev->dev; | |
995 | ||
996 | ret = fsl_elbc_ctrl_init(ctrl); | |
997 | if (ret < 0) | |
998 | goto err; | |
999 | ||
1000 | ret = request_irq(ctrl->irq, fsl_elbc_ctrl_irq, 0, "fsl-elbc", ctrl); | |
1001 | if (ret != 0) { | |
1002 | dev_err(&ofdev->dev, "failed to install irq (%d)\n", | |
1003 | ctrl->irq); | |
1004 | ret = ctrl->irq; | |
1005 | goto err; | |
1006 | } | |
1007 | ||
1008 | for_each_child_of_node(ofdev->node, child) | |
1009 | if (of_device_is_compatible(child, "fsl,elbc-fcm-nand")) | |
1010 | fsl_elbc_chip_probe(ctrl, child); | |
1011 | ||
1012 | return 0; | |
1013 | ||
1014 | err: | |
1015 | fsl_elbc_ctrl_remove(ofdev); | |
1016 | return ret; | |
1017 | } | |
1018 | ||
1019 | static const struct of_device_id fsl_elbc_match[] = { | |
1020 | { | |
1021 | .compatible = "fsl,elbc", | |
1022 | }, | |
1023 | {} | |
1024 | }; | |
1025 | ||
1026 | static struct of_platform_driver fsl_elbc_ctrl_driver = { | |
1027 | .driver = { | |
1028 | .name = "fsl-elbc", | |
1029 | }, | |
1030 | .match_table = fsl_elbc_match, | |
1031 | .probe = fsl_elbc_ctrl_probe, | |
1032 | .remove = __devexit_p(fsl_elbc_ctrl_remove), | |
1033 | }; | |
1034 | ||
1035 | static int __init fsl_elbc_init(void) | |
1036 | { | |
1037 | return of_register_platform_driver(&fsl_elbc_ctrl_driver); | |
1038 | } | |
1039 | ||
1040 | static void __exit fsl_elbc_exit(void) | |
1041 | { | |
1042 | of_unregister_platform_driver(&fsl_elbc_ctrl_driver); | |
1043 | } | |
1044 | ||
1045 | module_init(fsl_elbc_init); | |
1046 | module_exit(fsl_elbc_exit); | |
1047 | ||
1048 | MODULE_LICENSE("GPL"); | |
1049 | MODULE_AUTHOR("Freescale"); | |
1050 | MODULE_DESCRIPTION("Freescale Enhanced Local Bus Controller MTD NAND driver"); |