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82771882 PK |
1 | /* |
2 | * Freescale Integrated Flash Controller NAND driver | |
3 | * | |
4 | * Copyright 2011-2012 Freescale Semiconductor, Inc | |
5 | * | |
6 | * Author: Dipen Dudhat <Dipen.Dudhat@freescale.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #include <linux/module.h> | |
24 | #include <linux/types.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/kernel.h> | |
27 | #include <linux/slab.h> | |
28 | #include <linux/mtd/mtd.h> | |
29 | #include <linux/mtd/nand.h> | |
30 | #include <linux/mtd/partitions.h> | |
31 | #include <linux/mtd/nand_ecc.h> | |
32 | #include <asm/fsl_ifc.h> | |
33 | ||
10bfa766 | 34 | #define FSL_IFC_V1_1_0 0x01010000 |
82771882 PK |
35 | #define ERR_BYTE 0xFF /* Value returned for read |
36 | bytes when read failed */ | |
37 | #define IFC_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait | |
38 | for IFC NAND Machine */ | |
39 | ||
40 | struct fsl_ifc_ctrl; | |
41 | ||
42 | /* mtd information per set */ | |
43 | struct fsl_ifc_mtd { | |
44 | struct mtd_info mtd; | |
45 | struct nand_chip chip; | |
46 | struct fsl_ifc_ctrl *ctrl; | |
47 | ||
48 | struct device *dev; | |
49 | int bank; /* Chip select bank number */ | |
50 | unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */ | |
51 | u8 __iomem *vbase; /* Chip select base virtual address */ | |
52 | }; | |
53 | ||
54 | /* overview of the fsl ifc controller */ | |
55 | struct fsl_ifc_nand_ctrl { | |
56 | struct nand_hw_control controller; | |
57 | struct fsl_ifc_mtd *chips[FSL_IFC_BANK_COUNT]; | |
58 | ||
59 | u8 __iomem *addr; /* Address of assigned IFC buffer */ | |
60 | unsigned int page; /* Last page written to / read from */ | |
61 | unsigned int read_bytes;/* Number of bytes read during command */ | |
62 | unsigned int column; /* Saved column from SEQIN */ | |
63 | unsigned int index; /* Pointer to next byte to 'read' */ | |
64 | unsigned int oob; /* Non zero if operating on OOB data */ | |
65 | unsigned int eccread; /* Non zero for a full-page ECC read */ | |
66 | unsigned int counter; /* counter for the initializations */ | |
3f91e94f | 67 | unsigned int max_bitflips; /* Saved during READ0 cmd */ |
82771882 PK |
68 | }; |
69 | ||
70 | static struct fsl_ifc_nand_ctrl *ifc_nand_ctrl; | |
71 | ||
72 | /* 512-byte page with 4-bit ECC, 8-bit */ | |
73 | static struct nand_ecclayout oob_512_8bit_ecc4 = { | |
74 | .eccbytes = 8, | |
75 | .eccpos = {8, 9, 10, 11, 12, 13, 14, 15}, | |
76 | .oobfree = { {0, 5}, {6, 2} }, | |
77 | }; | |
78 | ||
79 | /* 512-byte page with 4-bit ECC, 16-bit */ | |
80 | static struct nand_ecclayout oob_512_16bit_ecc4 = { | |
81 | .eccbytes = 8, | |
82 | .eccpos = {8, 9, 10, 11, 12, 13, 14, 15}, | |
83 | .oobfree = { {2, 6}, }, | |
84 | }; | |
85 | ||
86 | /* 2048-byte page size with 4-bit ECC */ | |
87 | static struct nand_ecclayout oob_2048_ecc4 = { | |
88 | .eccbytes = 32, | |
89 | .eccpos = { | |
90 | 8, 9, 10, 11, 12, 13, 14, 15, | |
91 | 16, 17, 18, 19, 20, 21, 22, 23, | |
92 | 24, 25, 26, 27, 28, 29, 30, 31, | |
93 | 32, 33, 34, 35, 36, 37, 38, 39, | |
94 | }, | |
95 | .oobfree = { {2, 6}, {40, 24} }, | |
96 | }; | |
97 | ||
98 | /* 4096-byte page size with 4-bit ECC */ | |
99 | static struct nand_ecclayout oob_4096_ecc4 = { | |
100 | .eccbytes = 64, | |
101 | .eccpos = { | |
102 | 8, 9, 10, 11, 12, 13, 14, 15, | |
103 | 16, 17, 18, 19, 20, 21, 22, 23, | |
104 | 24, 25, 26, 27, 28, 29, 30, 31, | |
105 | 32, 33, 34, 35, 36, 37, 38, 39, | |
106 | 40, 41, 42, 43, 44, 45, 46, 47, | |
107 | 48, 49, 50, 51, 52, 53, 54, 55, | |
108 | 56, 57, 58, 59, 60, 61, 62, 63, | |
109 | 64, 65, 66, 67, 68, 69, 70, 71, | |
110 | }, | |
111 | .oobfree = { {2, 6}, {72, 56} }, | |
112 | }; | |
113 | ||
114 | /* 4096-byte page size with 8-bit ECC -- requires 218-byte OOB */ | |
115 | static struct nand_ecclayout oob_4096_ecc8 = { | |
116 | .eccbytes = 128, | |
117 | .eccpos = { | |
118 | 8, 9, 10, 11, 12, 13, 14, 15, | |
119 | 16, 17, 18, 19, 20, 21, 22, 23, | |
120 | 24, 25, 26, 27, 28, 29, 30, 31, | |
121 | 32, 33, 34, 35, 36, 37, 38, 39, | |
122 | 40, 41, 42, 43, 44, 45, 46, 47, | |
123 | 48, 49, 50, 51, 52, 53, 54, 55, | |
124 | 56, 57, 58, 59, 60, 61, 62, 63, | |
125 | 64, 65, 66, 67, 68, 69, 70, 71, | |
126 | 72, 73, 74, 75, 76, 77, 78, 79, | |
127 | 80, 81, 82, 83, 84, 85, 86, 87, | |
128 | 88, 89, 90, 91, 92, 93, 94, 95, | |
129 | 96, 97, 98, 99, 100, 101, 102, 103, | |
130 | 104, 105, 106, 107, 108, 109, 110, 111, | |
131 | 112, 113, 114, 115, 116, 117, 118, 119, | |
132 | 120, 121, 122, 123, 124, 125, 126, 127, | |
133 | 128, 129, 130, 131, 132, 133, 134, 135, | |
134 | }, | |
135 | .oobfree = { {2, 6}, {136, 82} }, | |
136 | }; | |
137 | ||
138 | ||
139 | /* | |
140 | * Generic flash bbt descriptors | |
141 | */ | |
142 | static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; | |
143 | static u8 mirror_pattern[] = {'1', 't', 'b', 'B' }; | |
144 | ||
145 | static struct nand_bbt_descr bbt_main_descr = { | |
146 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | | |
147 | NAND_BBT_2BIT | NAND_BBT_VERSION, | |
148 | .offs = 2, /* 0 on 8-bit small page */ | |
149 | .len = 4, | |
150 | .veroffs = 6, | |
151 | .maxblocks = 4, | |
152 | .pattern = bbt_pattern, | |
153 | }; | |
154 | ||
155 | static struct nand_bbt_descr bbt_mirror_descr = { | |
156 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | | |
157 | NAND_BBT_2BIT | NAND_BBT_VERSION, | |
158 | .offs = 2, /* 0 on 8-bit small page */ | |
159 | .len = 4, | |
160 | .veroffs = 6, | |
161 | .maxblocks = 4, | |
162 | .pattern = mirror_pattern, | |
163 | }; | |
164 | ||
165 | /* | |
166 | * Set up the IFC hardware block and page address fields, and the ifc nand | |
167 | * structure addr field to point to the correct IFC buffer in memory | |
168 | */ | |
169 | static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) | |
170 | { | |
171 | struct nand_chip *chip = mtd->priv; | |
172 | struct fsl_ifc_mtd *priv = chip->priv; | |
173 | struct fsl_ifc_ctrl *ctrl = priv->ctrl; | |
174 | struct fsl_ifc_regs __iomem *ifc = ctrl->regs; | |
175 | int buf_num; | |
176 | ||
177 | ifc_nand_ctrl->page = page_addr; | |
178 | /* Program ROW0/COL0 */ | |
0c69fb03 KP |
179 | iowrite32be(page_addr, &ifc->ifc_nand.row0); |
180 | iowrite32be((oob ? IFC_NAND_COL_MS : 0) | column, &ifc->ifc_nand.col0); | |
82771882 PK |
181 | |
182 | buf_num = page_addr & priv->bufnum_mask; | |
183 | ||
184 | ifc_nand_ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2); | |
185 | ifc_nand_ctrl->index = column; | |
186 | ||
187 | /* for OOB data point to the second half of the buffer */ | |
188 | if (oob) | |
189 | ifc_nand_ctrl->index += mtd->writesize; | |
190 | } | |
191 | ||
192 | static int is_blank(struct mtd_info *mtd, unsigned int bufnum) | |
193 | { | |
194 | struct nand_chip *chip = mtd->priv; | |
195 | struct fsl_ifc_mtd *priv = chip->priv; | |
196 | u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2); | |
2caf87a4 | 197 | u32 __iomem *mainarea = (u32 __iomem *)addr; |
82771882 PK |
198 | u8 __iomem *oob = addr + mtd->writesize; |
199 | int i; | |
200 | ||
201 | for (i = 0; i < mtd->writesize / 4; i++) { | |
202 | if (__raw_readl(&mainarea[i]) != 0xffffffff) | |
203 | return 0; | |
204 | } | |
205 | ||
206 | for (i = 0; i < chip->ecc.layout->eccbytes; i++) { | |
207 | int pos = chip->ecc.layout->eccpos[i]; | |
208 | ||
209 | if (__raw_readb(&oob[pos]) != 0xff) | |
210 | return 0; | |
211 | } | |
212 | ||
213 | return 1; | |
214 | } | |
215 | ||
216 | /* returns nonzero if entire page is blank */ | |
217 | static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl, | |
218 | u32 *eccstat, unsigned int bufnum) | |
219 | { | |
220 | u32 reg = eccstat[bufnum / 4]; | |
221 | int errors; | |
222 | ||
223 | errors = (reg >> ((3 - bufnum % 4) * 8)) & 15; | |
224 | ||
225 | return errors; | |
226 | } | |
227 | ||
228 | /* | |
229 | * execute IFC NAND command and wait for it to complete | |
230 | */ | |
231 | static void fsl_ifc_run_command(struct mtd_info *mtd) | |
232 | { | |
233 | struct nand_chip *chip = mtd->priv; | |
234 | struct fsl_ifc_mtd *priv = chip->priv; | |
235 | struct fsl_ifc_ctrl *ctrl = priv->ctrl; | |
236 | struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl; | |
237 | struct fsl_ifc_regs __iomem *ifc = ctrl->regs; | |
238 | u32 eccstat[4]; | |
239 | int i; | |
240 | ||
241 | /* set the chip select for NAND Transaction */ | |
0c69fb03 KP |
242 | iowrite32be(priv->bank << IFC_NAND_CSEL_SHIFT, |
243 | &ifc->ifc_nand.nand_csel); | |
82771882 PK |
244 | |
245 | dev_vdbg(priv->dev, | |
246 | "%s: fir0=%08x fcr0=%08x\n", | |
247 | __func__, | |
0c69fb03 KP |
248 | ioread32be(&ifc->ifc_nand.nand_fir0), |
249 | ioread32be(&ifc->ifc_nand.nand_fcr0)); | |
82771882 PK |
250 | |
251 | ctrl->nand_stat = 0; | |
252 | ||
253 | /* start read/write seq */ | |
0c69fb03 | 254 | iowrite32be(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt); |
82771882 PK |
255 | |
256 | /* wait for command complete flag or timeout */ | |
257 | wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat, | |
258 | IFC_TIMEOUT_MSECS * HZ/1000); | |
259 | ||
260 | /* ctrl->nand_stat will be updated from IRQ context */ | |
261 | if (!ctrl->nand_stat) | |
262 | dev_err(priv->dev, "Controller is not responding\n"); | |
263 | if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_FTOER) | |
264 | dev_err(priv->dev, "NAND Flash Timeout Error\n"); | |
265 | if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_WPER) | |
266 | dev_err(priv->dev, "NAND Flash Write Protect Error\n"); | |
267 | ||
3f91e94f MD |
268 | nctrl->max_bitflips = 0; |
269 | ||
82771882 PK |
270 | if (nctrl->eccread) { |
271 | int errors; | |
272 | int bufnum = nctrl->page & priv->bufnum_mask; | |
273 | int sector = bufnum * chip->ecc.steps; | |
274 | int sector_end = sector + chip->ecc.steps - 1; | |
275 | ||
276 | for (i = sector / 4; i <= sector_end / 4; i++) | |
0c69fb03 | 277 | eccstat[i] = ioread32be(&ifc->ifc_nand.nand_eccstat[i]); |
82771882 PK |
278 | |
279 | for (i = sector; i <= sector_end; i++) { | |
280 | errors = check_read_ecc(mtd, ctrl, eccstat, i); | |
281 | ||
282 | if (errors == 15) { | |
283 | /* | |
284 | * Uncorrectable error. | |
285 | * OK only if the whole page is blank. | |
286 | * | |
287 | * We disable ECCER reporting due to... | |
288 | * erratum IFC-A002770 -- so report it now if we | |
289 | * see an uncorrectable error in ECCSTAT. | |
290 | */ | |
291 | if (!is_blank(mtd, bufnum)) | |
292 | ctrl->nand_stat |= | |
293 | IFC_NAND_EVTER_STAT_ECCER; | |
294 | break; | |
295 | } | |
296 | ||
297 | mtd->ecc_stats.corrected += errors; | |
3f91e94f MD |
298 | nctrl->max_bitflips = max_t(unsigned int, |
299 | nctrl->max_bitflips, | |
300 | errors); | |
82771882 PK |
301 | } |
302 | ||
303 | nctrl->eccread = 0; | |
304 | } | |
305 | } | |
306 | ||
307 | static void fsl_ifc_do_read(struct nand_chip *chip, | |
308 | int oob, | |
309 | struct mtd_info *mtd) | |
310 | { | |
311 | struct fsl_ifc_mtd *priv = chip->priv; | |
312 | struct fsl_ifc_ctrl *ctrl = priv->ctrl; | |
313 | struct fsl_ifc_regs __iomem *ifc = ctrl->regs; | |
314 | ||
315 | /* Program FIR/IFC_NAND_FCR0 for Small/Large page */ | |
316 | if (mtd->writesize > 512) { | |
0c69fb03 KP |
317 | iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | |
318 | (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | | |
319 | (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | | |
320 | (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) | | |
321 | (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT), | |
322 | &ifc->ifc_nand.nand_fir0); | |
323 | iowrite32be(0x0, &ifc->ifc_nand.nand_fir1); | |
324 | ||
325 | iowrite32be((NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) | | |
326 | (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT), | |
327 | &ifc->ifc_nand.nand_fcr0); | |
82771882 | 328 | } else { |
0c69fb03 KP |
329 | iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | |
330 | (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | | |
331 | (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | | |
332 | (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT), | |
333 | &ifc->ifc_nand.nand_fir0); | |
334 | iowrite32be(0x0, &ifc->ifc_nand.nand_fir1); | |
82771882 PK |
335 | |
336 | if (oob) | |
0c69fb03 KP |
337 | iowrite32be(NAND_CMD_READOOB << |
338 | IFC_NAND_FCR0_CMD0_SHIFT, | |
339 | &ifc->ifc_nand.nand_fcr0); | |
82771882 | 340 | else |
0c69fb03 KP |
341 | iowrite32be(NAND_CMD_READ0 << |
342 | IFC_NAND_FCR0_CMD0_SHIFT, | |
343 | &ifc->ifc_nand.nand_fcr0); | |
82771882 PK |
344 | } |
345 | } | |
346 | ||
347 | /* cmdfunc send commands to the IFC NAND Machine */ | |
348 | static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, | |
349 | int column, int page_addr) { | |
350 | struct nand_chip *chip = mtd->priv; | |
351 | struct fsl_ifc_mtd *priv = chip->priv; | |
352 | struct fsl_ifc_ctrl *ctrl = priv->ctrl; | |
353 | struct fsl_ifc_regs __iomem *ifc = ctrl->regs; | |
354 | ||
355 | /* clear the read buffer */ | |
356 | ifc_nand_ctrl->read_bytes = 0; | |
357 | if (command != NAND_CMD_PAGEPROG) | |
358 | ifc_nand_ctrl->index = 0; | |
359 | ||
360 | switch (command) { | |
361 | /* READ0 read the entire buffer to use hardware ECC. */ | |
362 | case NAND_CMD_READ0: | |
0c69fb03 | 363 | iowrite32be(0, &ifc->ifc_nand.nand_fbcr); |
82771882 PK |
364 | set_addr(mtd, 0, page_addr, 0); |
365 | ||
366 | ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize; | |
367 | ifc_nand_ctrl->index += column; | |
368 | ||
369 | if (chip->ecc.mode == NAND_ECC_HW) | |
370 | ifc_nand_ctrl->eccread = 1; | |
371 | ||
372 | fsl_ifc_do_read(chip, 0, mtd); | |
373 | fsl_ifc_run_command(mtd); | |
374 | return; | |
375 | ||
376 | /* READOOB reads only the OOB because no ECC is performed. */ | |
377 | case NAND_CMD_READOOB: | |
0c69fb03 | 378 | iowrite32be(mtd->oobsize - column, &ifc->ifc_nand.nand_fbcr); |
82771882 PK |
379 | set_addr(mtd, column, page_addr, 1); |
380 | ||
381 | ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize; | |
382 | ||
383 | fsl_ifc_do_read(chip, 1, mtd); | |
384 | fsl_ifc_run_command(mtd); | |
385 | ||
386 | return; | |
387 | ||
82771882 | 388 | case NAND_CMD_READID: |
59fdd5b9 PK |
389 | case NAND_CMD_PARAM: { |
390 | int timing = IFC_FIR_OP_RB; | |
391 | if (command == NAND_CMD_PARAM) | |
392 | timing = IFC_FIR_OP_RBCD; | |
393 | ||
0c69fb03 KP |
394 | iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | |
395 | (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | | |
396 | (timing << IFC_NAND_FIR0_OP2_SHIFT), | |
397 | &ifc->ifc_nand.nand_fir0); | |
398 | iowrite32be(command << IFC_NAND_FCR0_CMD0_SHIFT, | |
399 | &ifc->ifc_nand.nand_fcr0); | |
400 | iowrite32be(column, &ifc->ifc_nand.row3); | |
59fdd5b9 PK |
401 | |
402 | /* | |
403 | * although currently it's 8 bytes for READID, we always read | |
404 | * the maximum 256 bytes(for PARAM) | |
405 | */ | |
0c69fb03 | 406 | iowrite32be(256, &ifc->ifc_nand.nand_fbcr); |
59fdd5b9 | 407 | ifc_nand_ctrl->read_bytes = 256; |
82771882 PK |
408 | |
409 | set_addr(mtd, 0, 0, 0); | |
410 | fsl_ifc_run_command(mtd); | |
411 | return; | |
59fdd5b9 | 412 | } |
82771882 PK |
413 | |
414 | /* ERASE1 stores the block and page address */ | |
415 | case NAND_CMD_ERASE1: | |
416 | set_addr(mtd, 0, page_addr, 0); | |
417 | return; | |
418 | ||
419 | /* ERASE2 uses the block and page address from ERASE1 */ | |
420 | case NAND_CMD_ERASE2: | |
0c69fb03 KP |
421 | iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | |
422 | (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) | | |
423 | (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT), | |
424 | &ifc->ifc_nand.nand_fir0); | |
82771882 | 425 | |
0c69fb03 KP |
426 | iowrite32be((NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) | |
427 | (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT), | |
428 | &ifc->ifc_nand.nand_fcr0); | |
82771882 | 429 | |
0c69fb03 | 430 | iowrite32be(0, &ifc->ifc_nand.nand_fbcr); |
82771882 PK |
431 | ifc_nand_ctrl->read_bytes = 0; |
432 | fsl_ifc_run_command(mtd); | |
433 | return; | |
434 | ||
435 | /* SEQIN sets up the addr buffer and all registers except the length */ | |
436 | case NAND_CMD_SEQIN: { | |
437 | u32 nand_fcr0; | |
438 | ifc_nand_ctrl->column = column; | |
439 | ifc_nand_ctrl->oob = 0; | |
440 | ||
441 | if (mtd->writesize > 512) { | |
442 | nand_fcr0 = | |
443 | (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) | | |
444 | (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD1_SHIFT); | |
445 | ||
0c69fb03 KP |
446 | iowrite32be( |
447 | (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | | |
448 | (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | | |
449 | (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | | |
450 | (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) | | |
451 | (IFC_FIR_OP_CW1 << IFC_NAND_FIR0_OP4_SHIFT), | |
452 | &ifc->ifc_nand.nand_fir0); | |
82771882 PK |
453 | } else { |
454 | nand_fcr0 = ((NAND_CMD_PAGEPROG << | |
455 | IFC_NAND_FCR0_CMD1_SHIFT) | | |
456 | (NAND_CMD_SEQIN << | |
457 | IFC_NAND_FCR0_CMD2_SHIFT)); | |
458 | ||
0c69fb03 KP |
459 | iowrite32be( |
460 | (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | | |
461 | (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) | | |
462 | (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) | | |
463 | (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) | | |
464 | (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT), | |
465 | &ifc->ifc_nand.nand_fir0); | |
466 | iowrite32be(IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT, | |
467 | &ifc->ifc_nand.nand_fir1); | |
82771882 PK |
468 | |
469 | if (column >= mtd->writesize) | |
470 | nand_fcr0 |= | |
471 | NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT; | |
472 | else | |
473 | nand_fcr0 |= | |
474 | NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT; | |
475 | } | |
476 | ||
477 | if (column >= mtd->writesize) { | |
478 | /* OOB area --> READOOB */ | |
479 | column -= mtd->writesize; | |
480 | ifc_nand_ctrl->oob = 1; | |
481 | } | |
0c69fb03 | 482 | iowrite32be(nand_fcr0, &ifc->ifc_nand.nand_fcr0); |
82771882 PK |
483 | set_addr(mtd, column, page_addr, ifc_nand_ctrl->oob); |
484 | return; | |
485 | } | |
486 | ||
487 | /* PAGEPROG reuses all of the setup from SEQIN and adds the length */ | |
488 | case NAND_CMD_PAGEPROG: { | |
489 | if (ifc_nand_ctrl->oob) { | |
0c69fb03 KP |
490 | iowrite32be(ifc_nand_ctrl->index - |
491 | ifc_nand_ctrl->column, | |
492 | &ifc->ifc_nand.nand_fbcr); | |
82771882 | 493 | } else { |
0c69fb03 | 494 | iowrite32be(0, &ifc->ifc_nand.nand_fbcr); |
82771882 PK |
495 | } |
496 | ||
497 | fsl_ifc_run_command(mtd); | |
498 | return; | |
499 | } | |
500 | ||
501 | case NAND_CMD_STATUS: | |
0c69fb03 KP |
502 | iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | |
503 | (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT), | |
504 | &ifc->ifc_nand.nand_fir0); | |
505 | iowrite32be(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT, | |
506 | &ifc->ifc_nand.nand_fcr0); | |
507 | iowrite32be(1, &ifc->ifc_nand.nand_fbcr); | |
82771882 PK |
508 | set_addr(mtd, 0, 0, 0); |
509 | ifc_nand_ctrl->read_bytes = 1; | |
510 | ||
511 | fsl_ifc_run_command(mtd); | |
512 | ||
513 | /* | |
514 | * The chip always seems to report that it is | |
515 | * write-protected, even when it is not. | |
516 | */ | |
517 | setbits8(ifc_nand_ctrl->addr, NAND_STATUS_WP); | |
518 | return; | |
519 | ||
520 | case NAND_CMD_RESET: | |
0c69fb03 KP |
521 | iowrite32be(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT, |
522 | &ifc->ifc_nand.nand_fir0); | |
523 | iowrite32be(NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT, | |
524 | &ifc->ifc_nand.nand_fcr0); | |
82771882 PK |
525 | fsl_ifc_run_command(mtd); |
526 | return; | |
527 | ||
528 | default: | |
529 | dev_err(priv->dev, "%s: error, unsupported command 0x%x.\n", | |
530 | __func__, command); | |
531 | } | |
532 | } | |
533 | ||
534 | static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip) | |
535 | { | |
536 | /* The hardware does not seem to support multiple | |
537 | * chips per bank. | |
538 | */ | |
539 | } | |
540 | ||
541 | /* | |
542 | * Write buf to the IFC NAND Controller Data Buffer | |
543 | */ | |
544 | static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len) | |
545 | { | |
546 | struct nand_chip *chip = mtd->priv; | |
547 | struct fsl_ifc_mtd *priv = chip->priv; | |
548 | unsigned int bufsize = mtd->writesize + mtd->oobsize; | |
549 | ||
550 | if (len <= 0) { | |
551 | dev_err(priv->dev, "%s: len %d bytes", __func__, len); | |
552 | return; | |
553 | } | |
554 | ||
555 | if ((unsigned int)len > bufsize - ifc_nand_ctrl->index) { | |
556 | dev_err(priv->dev, | |
557 | "%s: beyond end of buffer (%d requested, %u available)\n", | |
558 | __func__, len, bufsize - ifc_nand_ctrl->index); | |
559 | len = bufsize - ifc_nand_ctrl->index; | |
560 | } | |
561 | ||
562 | memcpy_toio(&ifc_nand_ctrl->addr[ifc_nand_ctrl->index], buf, len); | |
563 | ifc_nand_ctrl->index += len; | |
564 | } | |
565 | ||
566 | /* | |
567 | * Read a byte from either the IFC hardware buffer | |
568 | * read function for 8-bit buswidth | |
569 | */ | |
570 | static uint8_t fsl_ifc_read_byte(struct mtd_info *mtd) | |
571 | { | |
572 | struct nand_chip *chip = mtd->priv; | |
573 | struct fsl_ifc_mtd *priv = chip->priv; | |
574 | ||
575 | /* | |
576 | * If there are still bytes in the IFC buffer, then use the | |
577 | * next byte. | |
578 | */ | |
579 | if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) | |
580 | return in_8(&ifc_nand_ctrl->addr[ifc_nand_ctrl->index++]); | |
581 | ||
582 | dev_err(priv->dev, "%s: beyond end of buffer\n", __func__); | |
583 | return ERR_BYTE; | |
584 | } | |
585 | ||
586 | /* | |
587 | * Read two bytes from the IFC hardware buffer | |
588 | * read function for 16-bit buswith | |
589 | */ | |
590 | static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd) | |
591 | { | |
592 | struct nand_chip *chip = mtd->priv; | |
593 | struct fsl_ifc_mtd *priv = chip->priv; | |
594 | uint16_t data; | |
595 | ||
596 | /* | |
597 | * If there are still bytes in the IFC buffer, then use the | |
598 | * next byte. | |
599 | */ | |
600 | if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) { | |
2caf87a4 KP |
601 | data = in_be16((uint16_t __iomem *)&ifc_nand_ctrl-> |
602 | addr[ifc_nand_ctrl->index]); | |
82771882 PK |
603 | ifc_nand_ctrl->index += 2; |
604 | return (uint8_t) data; | |
605 | } | |
606 | ||
607 | dev_err(priv->dev, "%s: beyond end of buffer\n", __func__); | |
608 | return ERR_BYTE; | |
609 | } | |
610 | ||
611 | /* | |
612 | * Read from the IFC Controller Data Buffer | |
613 | */ | |
614 | static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len) | |
615 | { | |
616 | struct nand_chip *chip = mtd->priv; | |
617 | struct fsl_ifc_mtd *priv = chip->priv; | |
618 | int avail; | |
619 | ||
620 | if (len < 0) { | |
621 | dev_err(priv->dev, "%s: len %d bytes", __func__, len); | |
622 | return; | |
623 | } | |
624 | ||
625 | avail = min((unsigned int)len, | |
626 | ifc_nand_ctrl->read_bytes - ifc_nand_ctrl->index); | |
627 | memcpy_fromio(buf, &ifc_nand_ctrl->addr[ifc_nand_ctrl->index], avail); | |
628 | ifc_nand_ctrl->index += avail; | |
629 | ||
630 | if (len > avail) | |
631 | dev_err(priv->dev, | |
632 | "%s: beyond end of buffer (%d requested, %d available)\n", | |
633 | __func__, len, avail); | |
634 | } | |
635 | ||
82771882 PK |
636 | /* |
637 | * This function is called after Program and Erase Operations to | |
638 | * check for success or failure. | |
639 | */ | |
640 | static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip) | |
641 | { | |
642 | struct fsl_ifc_mtd *priv = chip->priv; | |
643 | struct fsl_ifc_ctrl *ctrl = priv->ctrl; | |
644 | struct fsl_ifc_regs __iomem *ifc = ctrl->regs; | |
645 | u32 nand_fsr; | |
646 | ||
647 | /* Use READ_STATUS command, but wait for the device to be ready */ | |
0c69fb03 KP |
648 | iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | |
649 | (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT), | |
650 | &ifc->ifc_nand.nand_fir0); | |
651 | iowrite32be(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT, | |
652 | &ifc->ifc_nand.nand_fcr0); | |
653 | iowrite32be(1, &ifc->ifc_nand.nand_fbcr); | |
82771882 PK |
654 | set_addr(mtd, 0, 0, 0); |
655 | ifc_nand_ctrl->read_bytes = 1; | |
656 | ||
657 | fsl_ifc_run_command(mtd); | |
658 | ||
0c69fb03 | 659 | nand_fsr = ioread32be(&ifc->ifc_nand.nand_fsr); |
82771882 PK |
660 | |
661 | /* | |
662 | * The chip always seems to report that it is | |
663 | * write-protected, even when it is not. | |
664 | */ | |
665 | return nand_fsr | NAND_STATUS_WP; | |
666 | } | |
667 | ||
1fbb938d BN |
668 | static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip, |
669 | uint8_t *buf, int oob_required, int page) | |
82771882 PK |
670 | { |
671 | struct fsl_ifc_mtd *priv = chip->priv; | |
672 | struct fsl_ifc_ctrl *ctrl = priv->ctrl; | |
3f91e94f | 673 | struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl; |
82771882 PK |
674 | |
675 | fsl_ifc_read_buf(mtd, buf, mtd->writesize); | |
a6976cdf BN |
676 | if (oob_required) |
677 | fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
82771882 PK |
678 | |
679 | if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_ECCER) | |
680 | dev_err(priv->dev, "NAND Flash ECC Uncorrectable Error\n"); | |
681 | ||
682 | if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC) | |
683 | mtd->ecc_stats.failed++; | |
684 | ||
3f91e94f | 685 | return nctrl->max_bitflips; |
82771882 PK |
686 | } |
687 | ||
688 | /* ECC will be calculated automatically, and errors will be detected in | |
689 | * waitfunc. | |
690 | */ | |
fdbad98d | 691 | static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 692 | const uint8_t *buf, int oob_required) |
82771882 PK |
693 | { |
694 | fsl_ifc_write_buf(mtd, buf, mtd->writesize); | |
695 | fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
fdbad98d JW |
696 | |
697 | return 0; | |
82771882 PK |
698 | } |
699 | ||
700 | static int fsl_ifc_chip_init_tail(struct mtd_info *mtd) | |
701 | { | |
702 | struct nand_chip *chip = mtd->priv; | |
703 | struct fsl_ifc_mtd *priv = chip->priv; | |
704 | ||
705 | dev_dbg(priv->dev, "%s: nand->numchips = %d\n", __func__, | |
706 | chip->numchips); | |
707 | dev_dbg(priv->dev, "%s: nand->chipsize = %lld\n", __func__, | |
708 | chip->chipsize); | |
709 | dev_dbg(priv->dev, "%s: nand->pagemask = %8x\n", __func__, | |
710 | chip->pagemask); | |
711 | dev_dbg(priv->dev, "%s: nand->chip_delay = %d\n", __func__, | |
712 | chip->chip_delay); | |
713 | dev_dbg(priv->dev, "%s: nand->badblockpos = %d\n", __func__, | |
714 | chip->badblockpos); | |
715 | dev_dbg(priv->dev, "%s: nand->chip_shift = %d\n", __func__, | |
716 | chip->chip_shift); | |
717 | dev_dbg(priv->dev, "%s: nand->page_shift = %d\n", __func__, | |
718 | chip->page_shift); | |
719 | dev_dbg(priv->dev, "%s: nand->phys_erase_shift = %d\n", __func__, | |
720 | chip->phys_erase_shift); | |
721 | dev_dbg(priv->dev, "%s: nand->ecclayout = %p\n", __func__, | |
722 | chip->ecclayout); | |
723 | dev_dbg(priv->dev, "%s: nand->ecc.mode = %d\n", __func__, | |
724 | chip->ecc.mode); | |
725 | dev_dbg(priv->dev, "%s: nand->ecc.steps = %d\n", __func__, | |
726 | chip->ecc.steps); | |
727 | dev_dbg(priv->dev, "%s: nand->ecc.bytes = %d\n", __func__, | |
728 | chip->ecc.bytes); | |
729 | dev_dbg(priv->dev, "%s: nand->ecc.total = %d\n", __func__, | |
730 | chip->ecc.total); | |
731 | dev_dbg(priv->dev, "%s: nand->ecc.layout = %p\n", __func__, | |
732 | chip->ecc.layout); | |
733 | dev_dbg(priv->dev, "%s: mtd->flags = %08x\n", __func__, mtd->flags); | |
734 | dev_dbg(priv->dev, "%s: mtd->size = %lld\n", __func__, mtd->size); | |
735 | dev_dbg(priv->dev, "%s: mtd->erasesize = %d\n", __func__, | |
736 | mtd->erasesize); | |
737 | dev_dbg(priv->dev, "%s: mtd->writesize = %d\n", __func__, | |
738 | mtd->writesize); | |
739 | dev_dbg(priv->dev, "%s: mtd->oobsize = %d\n", __func__, | |
740 | mtd->oobsize); | |
741 | ||
742 | return 0; | |
743 | } | |
744 | ||
10bfa766 PK |
745 | static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv) |
746 | { | |
747 | struct fsl_ifc_ctrl *ctrl = priv->ctrl; | |
748 | struct fsl_ifc_regs __iomem *ifc = ctrl->regs; | |
749 | uint32_t csor = 0, csor_8k = 0, csor_ext = 0; | |
750 | uint32_t cs = priv->bank; | |
751 | ||
752 | /* Save CSOR and CSOR_ext */ | |
0c69fb03 KP |
753 | csor = ioread32be(&ifc->csor_cs[cs].csor); |
754 | csor_ext = ioread32be(&ifc->csor_cs[cs].csor_ext); | |
10bfa766 PK |
755 | |
756 | /* chage PageSize 8K and SpareSize 1K*/ | |
757 | csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000; | |
0c69fb03 KP |
758 | iowrite32be(csor_8k, &ifc->csor_cs[cs].csor); |
759 | iowrite32be(0x0000400, &ifc->csor_cs[cs].csor_ext); | |
10bfa766 PK |
760 | |
761 | /* READID */ | |
0c69fb03 KP |
762 | iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | |
763 | (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | | |
764 | (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT), | |
765 | &ifc->ifc_nand.nand_fir0); | |
766 | iowrite32be(NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT, | |
767 | &ifc->ifc_nand.nand_fcr0); | |
768 | iowrite32be(0x0, &ifc->ifc_nand.row3); | |
10bfa766 | 769 | |
0c69fb03 | 770 | iowrite32be(0x0, &ifc->ifc_nand.nand_fbcr); |
10bfa766 PK |
771 | |
772 | /* Program ROW0/COL0 */ | |
0c69fb03 KP |
773 | iowrite32be(0x0, &ifc->ifc_nand.row0); |
774 | iowrite32be(0x0, &ifc->ifc_nand.col0); | |
10bfa766 PK |
775 | |
776 | /* set the chip select for NAND Transaction */ | |
0c69fb03 | 777 | iowrite32be(cs << IFC_NAND_CSEL_SHIFT, &ifc->ifc_nand.nand_csel); |
10bfa766 PK |
778 | |
779 | /* start read seq */ | |
0c69fb03 | 780 | iowrite32be(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt); |
10bfa766 PK |
781 | |
782 | /* wait for command complete flag or timeout */ | |
783 | wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat, | |
784 | IFC_TIMEOUT_MSECS * HZ/1000); | |
785 | ||
786 | if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC) | |
787 | printk(KERN_ERR "fsl-ifc: Failed to Initialise SRAM\n"); | |
788 | ||
789 | /* Restore CSOR and CSOR_ext */ | |
0c69fb03 KP |
790 | iowrite32be(csor, &ifc->csor_cs[cs].csor); |
791 | iowrite32be(csor_ext, &ifc->csor_cs[cs].csor_ext); | |
10bfa766 PK |
792 | } |
793 | ||
82771882 PK |
794 | static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv) |
795 | { | |
796 | struct fsl_ifc_ctrl *ctrl = priv->ctrl; | |
797 | struct fsl_ifc_regs __iomem *ifc = ctrl->regs; | |
798 | struct nand_chip *chip = &priv->chip; | |
799 | struct nand_ecclayout *layout; | |
10bfa766 | 800 | u32 csor, ver; |
82771882 PK |
801 | |
802 | /* Fill in fsl_ifc_mtd structure */ | |
803 | priv->mtd.priv = chip; | |
804 | priv->mtd.owner = THIS_MODULE; | |
805 | ||
806 | /* fill in nand_chip structure */ | |
807 | /* set up function call table */ | |
0c69fb03 | 808 | if ((ioread32be(&ifc->cspr_cs[priv->bank].cspr)) & CSPR_PORT_SIZE_16) |
82771882 PK |
809 | chip->read_byte = fsl_ifc_read_byte16; |
810 | else | |
811 | chip->read_byte = fsl_ifc_read_byte; | |
812 | ||
813 | chip->write_buf = fsl_ifc_write_buf; | |
814 | chip->read_buf = fsl_ifc_read_buf; | |
82771882 PK |
815 | chip->select_chip = fsl_ifc_select_chip; |
816 | chip->cmdfunc = fsl_ifc_cmdfunc; | |
817 | chip->waitfunc = fsl_ifc_wait; | |
818 | ||
819 | chip->bbt_td = &bbt_main_descr; | |
820 | chip->bbt_md = &bbt_mirror_descr; | |
821 | ||
0c69fb03 | 822 | iowrite32be(0x0, &ifc->ifc_nand.ncfgr); |
82771882 PK |
823 | |
824 | /* set up nand options */ | |
82771882 | 825 | chip->bbt_options = NAND_BBT_USE_FLASH; |
20cd0008 | 826 | chip->options = NAND_NO_SUBPAGE_WRITE; |
82771882 | 827 | |
0c69fb03 | 828 | if (ioread32be(&ifc->cspr_cs[priv->bank].cspr) & CSPR_PORT_SIZE_16) { |
82771882 PK |
829 | chip->read_byte = fsl_ifc_read_byte16; |
830 | chip->options |= NAND_BUSWIDTH_16; | |
831 | } else { | |
832 | chip->read_byte = fsl_ifc_read_byte; | |
833 | } | |
834 | ||
835 | chip->controller = &ifc_nand_ctrl->controller; | |
836 | chip->priv = priv; | |
837 | ||
838 | chip->ecc.read_page = fsl_ifc_read_page; | |
839 | chip->ecc.write_page = fsl_ifc_write_page; | |
840 | ||
0c69fb03 | 841 | csor = ioread32be(&ifc->csor_cs[priv->bank].csor); |
82771882 PK |
842 | |
843 | /* Hardware generates ECC per 512 Bytes */ | |
844 | chip->ecc.size = 512; | |
845 | chip->ecc.bytes = 8; | |
44df4d11 | 846 | chip->ecc.strength = 4; |
82771882 PK |
847 | |
848 | switch (csor & CSOR_NAND_PGS_MASK) { | |
849 | case CSOR_NAND_PGS_512: | |
850 | if (chip->options & NAND_BUSWIDTH_16) { | |
851 | layout = &oob_512_16bit_ecc4; | |
852 | } else { | |
853 | layout = &oob_512_8bit_ecc4; | |
854 | ||
855 | /* Avoid conflict with bad block marker */ | |
856 | bbt_main_descr.offs = 0; | |
857 | bbt_mirror_descr.offs = 0; | |
858 | } | |
859 | ||
860 | priv->bufnum_mask = 15; | |
861 | break; | |
862 | ||
863 | case CSOR_NAND_PGS_2K: | |
864 | layout = &oob_2048_ecc4; | |
865 | priv->bufnum_mask = 3; | |
866 | break; | |
867 | ||
868 | case CSOR_NAND_PGS_4K: | |
869 | if ((csor & CSOR_NAND_ECC_MODE_MASK) == | |
870 | CSOR_NAND_ECC_MODE_4) { | |
871 | layout = &oob_4096_ecc4; | |
872 | } else { | |
873 | layout = &oob_4096_ecc8; | |
874 | chip->ecc.bytes = 16; | |
875 | } | |
876 | ||
877 | priv->bufnum_mask = 1; | |
878 | break; | |
879 | ||
880 | default: | |
881 | dev_err(priv->dev, "bad csor %#x: bad page size\n", csor); | |
882 | return -ENODEV; | |
883 | } | |
884 | ||
885 | /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */ | |
886 | if (csor & CSOR_NAND_ECC_DEC_EN) { | |
887 | chip->ecc.mode = NAND_ECC_HW; | |
888 | chip->ecc.layout = layout; | |
889 | } else { | |
890 | chip->ecc.mode = NAND_ECC_SOFT; | |
891 | } | |
892 | ||
0c69fb03 | 893 | ver = ioread32be(&ifc->ifc_rev); |
10bfa766 PK |
894 | if (ver == FSL_IFC_V1_1_0) |
895 | fsl_ifc_sram_init(priv); | |
896 | ||
82771882 PK |
897 | return 0; |
898 | } | |
899 | ||
900 | static int fsl_ifc_chip_remove(struct fsl_ifc_mtd *priv) | |
901 | { | |
902 | nand_release(&priv->mtd); | |
903 | ||
904 | kfree(priv->mtd.name); | |
905 | ||
906 | if (priv->vbase) | |
907 | iounmap(priv->vbase); | |
908 | ||
909 | ifc_nand_ctrl->chips[priv->bank] = NULL; | |
910 | dev_set_drvdata(priv->dev, NULL); | |
82771882 PK |
911 | |
912 | return 0; | |
913 | } | |
914 | ||
915 | static int match_bank(struct fsl_ifc_regs __iomem *ifc, int bank, | |
916 | phys_addr_t addr) | |
917 | { | |
0c69fb03 | 918 | u32 cspr = ioread32be(&ifc->cspr_cs[bank].cspr); |
82771882 PK |
919 | |
920 | if (!(cspr & CSPR_V)) | |
921 | return 0; | |
922 | if ((cspr & CSPR_MSEL) != CSPR_MSEL_NAND) | |
923 | return 0; | |
924 | ||
925 | return (cspr & CSPR_BA) == convert_ifc_address(addr); | |
926 | } | |
927 | ||
928 | static DEFINE_MUTEX(fsl_ifc_nand_mutex); | |
929 | ||
06f25510 | 930 | static int fsl_ifc_nand_probe(struct platform_device *dev) |
82771882 PK |
931 | { |
932 | struct fsl_ifc_regs __iomem *ifc; | |
933 | struct fsl_ifc_mtd *priv; | |
934 | struct resource res; | |
935 | static const char *part_probe_types[] | |
936 | = { "cmdlinepart", "RedBoot", "ofpart", NULL }; | |
937 | int ret; | |
938 | int bank; | |
939 | struct device_node *node = dev->dev.of_node; | |
940 | struct mtd_part_parser_data ppdata; | |
941 | ||
942 | ppdata.of_node = dev->dev.of_node; | |
943 | if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->regs) | |
944 | return -ENODEV; | |
945 | ifc = fsl_ifc_ctrl_dev->regs; | |
946 | ||
947 | /* get, allocate and map the memory resource */ | |
948 | ret = of_address_to_resource(node, 0, &res); | |
949 | if (ret) { | |
950 | dev_err(&dev->dev, "%s: failed to get resource\n", __func__); | |
951 | return ret; | |
952 | } | |
953 | ||
954 | /* find which chip select it is connected to */ | |
955 | for (bank = 0; bank < FSL_IFC_BANK_COUNT; bank++) { | |
956 | if (match_bank(ifc, bank, res.start)) | |
957 | break; | |
958 | } | |
959 | ||
960 | if (bank >= FSL_IFC_BANK_COUNT) { | |
961 | dev_err(&dev->dev, "%s: address did not match any chip selects\n", | |
962 | __func__); | |
963 | return -ENODEV; | |
964 | } | |
965 | ||
966 | priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL); | |
967 | if (!priv) | |
968 | return -ENOMEM; | |
969 | ||
970 | mutex_lock(&fsl_ifc_nand_mutex); | |
971 | if (!fsl_ifc_ctrl_dev->nand) { | |
972 | ifc_nand_ctrl = kzalloc(sizeof(*ifc_nand_ctrl), GFP_KERNEL); | |
973 | if (!ifc_nand_ctrl) { | |
974 | dev_err(&dev->dev, "failed to allocate memory\n"); | |
975 | mutex_unlock(&fsl_ifc_nand_mutex); | |
976 | return -ENOMEM; | |
977 | } | |
978 | ||
979 | ifc_nand_ctrl->read_bytes = 0; | |
980 | ifc_nand_ctrl->index = 0; | |
981 | ifc_nand_ctrl->addr = NULL; | |
982 | fsl_ifc_ctrl_dev->nand = ifc_nand_ctrl; | |
983 | ||
984 | spin_lock_init(&ifc_nand_ctrl->controller.lock); | |
985 | init_waitqueue_head(&ifc_nand_ctrl->controller.wq); | |
986 | } else { | |
987 | ifc_nand_ctrl = fsl_ifc_ctrl_dev->nand; | |
988 | } | |
989 | mutex_unlock(&fsl_ifc_nand_mutex); | |
990 | ||
991 | ifc_nand_ctrl->chips[bank] = priv; | |
992 | priv->bank = bank; | |
993 | priv->ctrl = fsl_ifc_ctrl_dev; | |
994 | priv->dev = &dev->dev; | |
995 | ||
996 | priv->vbase = ioremap(res.start, resource_size(&res)); | |
997 | if (!priv->vbase) { | |
998 | dev_err(priv->dev, "%s: failed to map chip region\n", __func__); | |
999 | ret = -ENOMEM; | |
1000 | goto err; | |
1001 | } | |
1002 | ||
1003 | dev_set_drvdata(priv->dev, priv); | |
1004 | ||
0c69fb03 KP |
1005 | iowrite32be(IFC_NAND_EVTER_EN_OPC_EN | |
1006 | IFC_NAND_EVTER_EN_FTOER_EN | | |
1007 | IFC_NAND_EVTER_EN_WPER_EN, | |
1008 | &ifc->ifc_nand.nand_evter_en); | |
82771882 PK |
1009 | |
1010 | /* enable NAND Machine Interrupts */ | |
0c69fb03 KP |
1011 | iowrite32be(IFC_NAND_EVTER_INTR_OPCIR_EN | |
1012 | IFC_NAND_EVTER_INTR_FTOERIR_EN | | |
1013 | IFC_NAND_EVTER_INTR_WPERIR_EN, | |
1014 | &ifc->ifc_nand.nand_evter_intr_en); | |
82771882 PK |
1015 | priv->mtd.name = kasprintf(GFP_KERNEL, "%x.flash", (unsigned)res.start); |
1016 | if (!priv->mtd.name) { | |
1017 | ret = -ENOMEM; | |
1018 | goto err; | |
1019 | } | |
1020 | ||
1021 | ret = fsl_ifc_chip_init(priv); | |
1022 | if (ret) | |
1023 | goto err; | |
1024 | ||
1025 | ret = nand_scan_ident(&priv->mtd, 1, NULL); | |
1026 | if (ret) | |
1027 | goto err; | |
1028 | ||
1029 | ret = fsl_ifc_chip_init_tail(&priv->mtd); | |
1030 | if (ret) | |
1031 | goto err; | |
1032 | ||
1033 | ret = nand_scan_tail(&priv->mtd); | |
1034 | if (ret) | |
1035 | goto err; | |
1036 | ||
1037 | /* First look for RedBoot table or partitions on the command | |
1038 | * line, these take precedence over device tree information */ | |
1039 | mtd_device_parse_register(&priv->mtd, part_probe_types, &ppdata, | |
1040 | NULL, 0); | |
1041 | ||
1042 | dev_info(priv->dev, "IFC NAND device at 0x%llx, bank %d\n", | |
1043 | (unsigned long long)res.start, priv->bank); | |
1044 | return 0; | |
1045 | ||
1046 | err: | |
1047 | fsl_ifc_chip_remove(priv); | |
1048 | return ret; | |
1049 | } | |
1050 | ||
1051 | static int fsl_ifc_nand_remove(struct platform_device *dev) | |
1052 | { | |
1053 | struct fsl_ifc_mtd *priv = dev_get_drvdata(&dev->dev); | |
1054 | ||
1055 | fsl_ifc_chip_remove(priv); | |
1056 | ||
1057 | mutex_lock(&fsl_ifc_nand_mutex); | |
1058 | ifc_nand_ctrl->counter--; | |
1059 | if (!ifc_nand_ctrl->counter) { | |
1060 | fsl_ifc_ctrl_dev->nand = NULL; | |
1061 | kfree(ifc_nand_ctrl); | |
1062 | } | |
1063 | mutex_unlock(&fsl_ifc_nand_mutex); | |
1064 | ||
1065 | return 0; | |
1066 | } | |
1067 | ||
1068 | static const struct of_device_id fsl_ifc_nand_match[] = { | |
1069 | { | |
1070 | .compatible = "fsl,ifc-nand", | |
1071 | }, | |
1072 | {} | |
1073 | }; | |
1074 | ||
1075 | static struct platform_driver fsl_ifc_nand_driver = { | |
1076 | .driver = { | |
1077 | .name = "fsl,ifc-nand", | |
1078 | .owner = THIS_MODULE, | |
1079 | .of_match_table = fsl_ifc_nand_match, | |
1080 | }, | |
1081 | .probe = fsl_ifc_nand_probe, | |
1082 | .remove = fsl_ifc_nand_remove, | |
1083 | }; | |
1084 | ||
1085 | static int __init fsl_ifc_nand_init(void) | |
1086 | { | |
1087 | int ret; | |
1088 | ||
1089 | ret = platform_driver_register(&fsl_ifc_nand_driver); | |
1090 | if (ret) | |
1091 | printk(KERN_ERR "fsl-ifc: Failed to register platform" | |
1092 | "driver\n"); | |
1093 | ||
1094 | return ret; | |
1095 | } | |
1096 | ||
1097 | static void __exit fsl_ifc_nand_exit(void) | |
1098 | { | |
1099 | platform_driver_unregister(&fsl_ifc_nand_driver); | |
1100 | } | |
1101 | ||
1102 | module_init(fsl_ifc_nand_init); | |
1103 | module_exit(fsl_ifc_nand_exit); | |
1104 | ||
1105 | MODULE_LICENSE("GPL"); | |
1106 | MODULE_AUTHOR("Freescale"); | |
1107 | MODULE_DESCRIPTION("Freescale Integrated Flash Controller MTD NAND driver"); |