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drivers: clean-up prom.h implicit includes
[deliverable/linux.git] / drivers / mtd / nand / fsl_ifc_nand.c
CommitLineData
82771882
PK		 1/*
2 * Freescale Integrated Flash Controller NAND driver
3 *
4 * Copyright 2011-2012 Freescale Semiconductor, Inc
5 *
6 * Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <linux/module.h>
24#include <linux/types.h>
25#include <linux/init.h>
26#include <linux/kernel.h>
5af50730 27#include <linux/of_address.h>
82771882
PK		 28#include <linux/slab.h>
29#include <linux/mtd/mtd.h>
30#include <linux/mtd/nand.h>
31#include <linux/mtd/partitions.h>
32#include <linux/mtd/nand_ecc.h>
33#include <asm/fsl_ifc.h>
34
10bfa766 35#define FSL_IFC_V1_1_0 0x01010000
82771882
PK		 36#define ERR_BYTE 0xFF /* Value returned for read
37 bytes when read failed */
38#define IFC_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait
39 for IFC NAND Machine */
40
41struct fsl_ifc_ctrl;
42
43/* mtd information per set */
44struct fsl_ifc_mtd {
45 struct mtd_info mtd;
46 struct nand_chip chip;
47 struct fsl_ifc_ctrl *ctrl;
48
49 struct device *dev;
50 int bank; /* Chip select bank number */
51 unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
52 u8 __iomem *vbase; /* Chip select base virtual address */
53};
54
55/* overview of the fsl ifc controller */
56struct fsl_ifc_nand_ctrl {
57 struct nand_hw_control controller;
58 struct fsl_ifc_mtd *chips[FSL_IFC_BANK_COUNT];
59
60 u8 __iomem *addr; /* Address of assigned IFC buffer */
61 unsigned int page; /* Last page written to / read from */
62 unsigned int read_bytes;/* Number of bytes read during command */
63 unsigned int column; /* Saved column from SEQIN */
64 unsigned int index; /* Pointer to next byte to 'read' */
65 unsigned int oob; /* Non zero if operating on OOB data */
66 unsigned int eccread; /* Non zero for a full-page ECC read */
67 unsigned int counter; /* counter for the initializations */
3f91e94f 68 unsigned int max_bitflips; /* Saved during READ0 cmd */
82771882
PK		 69};
70
71static struct fsl_ifc_nand_ctrl *ifc_nand_ctrl;
72
73/* 512-byte page with 4-bit ECC, 8-bit */
74static struct nand_ecclayout oob_512_8bit_ecc4 = {
75 .eccbytes = 8,
76 .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
77 .oobfree = { {0, 5}, {6, 2} },
78};
79
80/* 512-byte page with 4-bit ECC, 16-bit */
81static struct nand_ecclayout oob_512_16bit_ecc4 = {
82 .eccbytes = 8,
83 .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
84 .oobfree = { {2, 6}, },
85};
86
87/* 2048-byte page size with 4-bit ECC */
88static struct nand_ecclayout oob_2048_ecc4 = {
89 .eccbytes = 32,
90 .eccpos = {
91 8, 9, 10, 11, 12, 13, 14, 15,
92 16, 17, 18, 19, 20, 21, 22, 23,
93 24, 25, 26, 27, 28, 29, 30, 31,
94 32, 33, 34, 35, 36, 37, 38, 39,
95 },
96 .oobfree = { {2, 6}, {40, 24} },
97};
98
99/* 4096-byte page size with 4-bit ECC */
100static struct nand_ecclayout oob_4096_ecc4 = {
101 .eccbytes = 64,
102 .eccpos = {
103 8, 9, 10, 11, 12, 13, 14, 15,
104 16, 17, 18, 19, 20, 21, 22, 23,
105 24, 25, 26, 27, 28, 29, 30, 31,
106 32, 33, 34, 35, 36, 37, 38, 39,
107 40, 41, 42, 43, 44, 45, 46, 47,
108 48, 49, 50, 51, 52, 53, 54, 55,
109 56, 57, 58, 59, 60, 61, 62, 63,
110 64, 65, 66, 67, 68, 69, 70, 71,
111 },
112 .oobfree = { {2, 6}, {72, 56} },
113};
114
115/* 4096-byte page size with 8-bit ECC -- requires 218-byte OOB */
116static struct nand_ecclayout oob_4096_ecc8 = {
117 .eccbytes = 128,
118 .eccpos = {
119 8, 9, 10, 11, 12, 13, 14, 15,
120 16, 17, 18, 19, 20, 21, 22, 23,
121 24, 25, 26, 27, 28, 29, 30, 31,
122 32, 33, 34, 35, 36, 37, 38, 39,
123 40, 41, 42, 43, 44, 45, 46, 47,
124 48, 49, 50, 51, 52, 53, 54, 55,
125 56, 57, 58, 59, 60, 61, 62, 63,
126 64, 65, 66, 67, 68, 69, 70, 71,
127 72, 73, 74, 75, 76, 77, 78, 79,
128 80, 81, 82, 83, 84, 85, 86, 87,
129 88, 89, 90, 91, 92, 93, 94, 95,
130 96, 97, 98, 99, 100, 101, 102, 103,
131 104, 105, 106, 107, 108, 109, 110, 111,
132 112, 113, 114, 115, 116, 117, 118, 119,
133 120, 121, 122, 123, 124, 125, 126, 127,
134 128, 129, 130, 131, 132, 133, 134, 135,
135 },
136 .oobfree = { {2, 6}, {136, 82} },
137};
138
139
140/*
141 * Generic flash bbt descriptors
142 */
143static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
144static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
145
146static struct nand_bbt_descr bbt_main_descr = {
147 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
148 NAND_BBT_2BIT | NAND_BBT_VERSION,
149 .offs = 2, /* 0 on 8-bit small page */
150 .len = 4,
151 .veroffs = 6,
152 .maxblocks = 4,
153 .pattern = bbt_pattern,
154};
155
156static struct nand_bbt_descr bbt_mirror_descr = {
157 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
158 NAND_BBT_2BIT | NAND_BBT_VERSION,
159 .offs = 2, /* 0 on 8-bit small page */
160 .len = 4,
161 .veroffs = 6,
162 .maxblocks = 4,
163 .pattern = mirror_pattern,
164};
165
166/*
167 * Set up the IFC hardware block and page address fields, and the ifc nand
168 * structure addr field to point to the correct IFC buffer in memory
169 */
170static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
171{
172 struct nand_chip *chip = mtd->priv;
173 struct fsl_ifc_mtd *priv = chip->priv;
174 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
175 struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
176 int buf_num;
177
178 ifc_nand_ctrl->page = page_addr;
179 /* Program ROW0/COL0 */
0c69fb03
KP		 180 iowrite32be(page_addr, &ifc->ifc_nand.row0);
181 iowrite32be((oob ? IFC_NAND_COL_MS : 0) | column, &ifc->ifc_nand.col0);
82771882
PK		 182
183 buf_num = page_addr & priv->bufnum_mask;
184
185 ifc_nand_ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
186 ifc_nand_ctrl->index = column;
187
188 /* for OOB data point to the second half of the buffer */
189 if (oob)
190 ifc_nand_ctrl->index += mtd->writesize;
191}
192
193static int is_blank(struct mtd_info *mtd, unsigned int bufnum)
194{
195 struct nand_chip *chip = mtd->priv;
196 struct fsl_ifc_mtd *priv = chip->priv;
197 u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2);
2caf87a4 198 u32 __iomem *mainarea = (u32 __iomem *)addr;
82771882
PK		 199 u8 __iomem *oob = addr + mtd->writesize;
200 int i;
201
202 for (i = 0; i < mtd->writesize / 4; i++) {
203 if (__raw_readl(&mainarea[i]) != 0xffffffff)
204 return 0;
205 }
206
207 for (i = 0; i < chip->ecc.layout->eccbytes; i++) {
208 int pos = chip->ecc.layout->eccpos[i];
209
210 if (__raw_readb(&oob[pos]) != 0xff)
211 return 0;
212 }
213
214 return 1;
215}
216
217/* returns nonzero if entire page is blank */
218static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
219 u32 *eccstat, unsigned int bufnum)
220{
221 u32 reg = eccstat[bufnum / 4];
222 int errors;
223
224 errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
225
226 return errors;
227}
228
229/*
230 * execute IFC NAND command and wait for it to complete
231 */
232static void fsl_ifc_run_command(struct mtd_info *mtd)
233{
234 struct nand_chip *chip = mtd->priv;
235 struct fsl_ifc_mtd *priv = chip->priv;
236 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
237 struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
238 struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
239 u32 eccstat[4];
240 int i;
241
242 /* set the chip select for NAND Transaction */
0c69fb03
KP		 243 iowrite32be(priv->bank << IFC_NAND_CSEL_SHIFT,
244 &ifc->ifc_nand.nand_csel);
82771882
PK		 245
246 dev_vdbg(priv->dev,
247 "%s: fir0=%08x fcr0=%08x\n",
248 __func__,
0c69fb03
KP		 249 ioread32be(&ifc->ifc_nand.nand_fir0),
250 ioread32be(&ifc->ifc_nand.nand_fcr0));
82771882
PK		 251
252 ctrl->nand_stat = 0;
253
254 /* start read/write seq */
0c69fb03 255 iowrite32be(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
82771882
PK		 256
257 /* wait for command complete flag or timeout */
258 wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
259 IFC_TIMEOUT_MSECS * HZ/1000);
260
261 /* ctrl->nand_stat will be updated from IRQ context */
262 if (!ctrl->nand_stat)
263 dev_err(priv->dev, "Controller is not responding\n");
264 if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_FTOER)
265 dev_err(priv->dev, "NAND Flash Timeout Error\n");
266 if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_WPER)
267 dev_err(priv->dev, "NAND Flash Write Protect Error\n");
268
3f91e94f
MD		 269 nctrl->max_bitflips = 0;
270
82771882
PK		 271 if (nctrl->eccread) {
272 int errors;
273 int bufnum = nctrl->page & priv->bufnum_mask;
274 int sector = bufnum * chip->ecc.steps;
275 int sector_end = sector + chip->ecc.steps - 1;
276
277 for (i = sector / 4; i <= sector_end / 4; i++)
0c69fb03 278 eccstat[i] = ioread32be(&ifc->ifc_nand.nand_eccstat[i]);
82771882
PK		 279
280 for (i = sector; i <= sector_end; i++) {
281 errors = check_read_ecc(mtd, ctrl, eccstat, i);
282
283 if (errors == 15) {
284 /*
285 * Uncorrectable error.
286 * OK only if the whole page is blank.
287 *
288 * We disable ECCER reporting due to...
289 * erratum IFC-A002770 -- so report it now if we
290 * see an uncorrectable error in ECCSTAT.
291 */
292 if (!is_blank(mtd, bufnum))
293 ctrl->nand_stat |=
294 IFC_NAND_EVTER_STAT_ECCER;
295 break;
296 }
297
298 mtd->ecc_stats.corrected += errors;
3f91e94f
MD		 299 nctrl->max_bitflips = max_t(unsigned int,
300 nctrl->max_bitflips,
301 errors);
82771882
PK		 302 }
303
304 nctrl->eccread = 0;
305 }
306}
307
308static void fsl_ifc_do_read(struct nand_chip *chip,
309 int oob,
310 struct mtd_info *mtd)
311{
312 struct fsl_ifc_mtd *priv = chip->priv;
313 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
314 struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
315
316 /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
317 if (mtd->writesize > 512) {
0c69fb03
KP		 318 iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
319 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
320 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
321 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
322 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT),
323 &ifc->ifc_nand.nand_fir0);
324 iowrite32be(0x0, &ifc->ifc_nand.nand_fir1);
325
326 iowrite32be((NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
327 (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT),
328 &ifc->ifc_nand.nand_fcr0);
82771882 329 } else {
0c69fb03
KP		 330 iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
331 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
332 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
333 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT),
334 &ifc->ifc_nand.nand_fir0);
335 iowrite32be(0x0, &ifc->ifc_nand.nand_fir1);
82771882
PK		 336
337 if (oob)
0c69fb03
KP		 338 iowrite32be(NAND_CMD_READOOB <<
339 IFC_NAND_FCR0_CMD0_SHIFT,
340 &ifc->ifc_nand.nand_fcr0);
82771882 341 else
0c69fb03
KP		 342 iowrite32be(NAND_CMD_READ0 <<
343 IFC_NAND_FCR0_CMD0_SHIFT,
344 &ifc->ifc_nand.nand_fcr0);
82771882
PK		 345 }
346}
347
348/* cmdfunc send commands to the IFC NAND Machine */
349static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
350 int column, int page_addr) {
351 struct nand_chip *chip = mtd->priv;
352 struct fsl_ifc_mtd *priv = chip->priv;
353 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
354 struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
355
356 /* clear the read buffer */
357 ifc_nand_ctrl->read_bytes = 0;
358 if (command != NAND_CMD_PAGEPROG)
359 ifc_nand_ctrl->index = 0;
360
361 switch (command) {
362 /* READ0 read the entire buffer to use hardware ECC. */
363 case NAND_CMD_READ0:
0c69fb03 364 iowrite32be(0, &ifc->ifc_nand.nand_fbcr);
82771882
PK		 365 set_addr(mtd, 0, page_addr, 0);
366
367 ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
368 ifc_nand_ctrl->index += column;
369
370 if (chip->ecc.mode == NAND_ECC_HW)
371 ifc_nand_ctrl->eccread = 1;
372
373 fsl_ifc_do_read(chip, 0, mtd);
374 fsl_ifc_run_command(mtd);
375 return;
376
377 /* READOOB reads only the OOB because no ECC is performed. */
378 case NAND_CMD_READOOB:
0c69fb03 379 iowrite32be(mtd->oobsize - column, &ifc->ifc_nand.nand_fbcr);
82771882
PK		 380 set_addr(mtd, column, page_addr, 1);
381
382 ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
383
384 fsl_ifc_do_read(chip, 1, mtd);
385 fsl_ifc_run_command(mtd);
386
387 return;
388
82771882 389 case NAND_CMD_READID:
59fdd5b9
PK		 390 case NAND_CMD_PARAM: {
391 int timing = IFC_FIR_OP_RB;
392 if (command == NAND_CMD_PARAM)
393 timing = IFC_FIR_OP_RBCD;
394
0c69fb03
KP		 395 iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
396 (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
397 (timing << IFC_NAND_FIR0_OP2_SHIFT),
398 &ifc->ifc_nand.nand_fir0);
399 iowrite32be(command << IFC_NAND_FCR0_CMD0_SHIFT,
400 &ifc->ifc_nand.nand_fcr0);
401 iowrite32be(column, &ifc->ifc_nand.row3);
59fdd5b9
PK		 402
403 /*
404 * although currently it's 8 bytes for READID, we always read
405 * the maximum 256 bytes(for PARAM)
406 */
0c69fb03 407 iowrite32be(256, &ifc->ifc_nand.nand_fbcr);
59fdd5b9 408 ifc_nand_ctrl->read_bytes = 256;
82771882
PK		 409
410 set_addr(mtd, 0, 0, 0);
411 fsl_ifc_run_command(mtd);
412 return;
59fdd5b9 413 }
82771882
PK		 414
415 /* ERASE1 stores the block and page address */
416 case NAND_CMD_ERASE1:
417 set_addr(mtd, 0, page_addr, 0);
418 return;
419
420 /* ERASE2 uses the block and page address from ERASE1 */
421 case NAND_CMD_ERASE2:
0c69fb03
KP		 422 iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
423 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
424 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT),
425 &ifc->ifc_nand.nand_fir0);
82771882 426
0c69fb03
KP		 427 iowrite32be((NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
428 (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT),
429 &ifc->ifc_nand.nand_fcr0);
82771882 430
0c69fb03 431 iowrite32be(0, &ifc->ifc_nand.nand_fbcr);
82771882
PK		 432 ifc_nand_ctrl->read_bytes = 0;
433 fsl_ifc_run_command(mtd);
434 return;
435
436 /* SEQIN sets up the addr buffer and all registers except the length */
437 case NAND_CMD_SEQIN: {
438 u32 nand_fcr0;
439 ifc_nand_ctrl->column = column;
440 ifc_nand_ctrl->oob = 0;
441
442 if (mtd->writesize > 512) {
443 nand_fcr0 =
444 (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
445 (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD1_SHIFT);
446
0c69fb03
KP		 447 iowrite32be(
448 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
449 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
450 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
451 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) |
452 (IFC_FIR_OP_CW1 << IFC_NAND_FIR0_OP4_SHIFT),
453 &ifc->ifc_nand.nand_fir0);
82771882
PK		 454 } else {
455 nand_fcr0 = ((NAND_CMD_PAGEPROG <<
456 IFC_NAND_FCR0_CMD1_SHIFT) |
457 (NAND_CMD_SEQIN <<
458 IFC_NAND_FCR0_CMD2_SHIFT));
459
0c69fb03
KP		 460 iowrite32be(
461 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
462 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
463 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
464 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
465 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT),
466 &ifc->ifc_nand.nand_fir0);
467 iowrite32be(IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT,
468 &ifc->ifc_nand.nand_fir1);
82771882
PK		 469
470 if (column >= mtd->writesize)
471 nand_fcr0 |=
472 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
473 else
474 nand_fcr0 |=
475 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
476 }
477
478 if (column >= mtd->writesize) {
479 /* OOB area --> READOOB */
480 column -= mtd->writesize;
481 ifc_nand_ctrl->oob = 1;
482 }
0c69fb03 483 iowrite32be(nand_fcr0, &ifc->ifc_nand.nand_fcr0);
82771882
PK		 484 set_addr(mtd, column, page_addr, ifc_nand_ctrl->oob);
485 return;
486 }
487
488 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
489 case NAND_CMD_PAGEPROG: {
490 if (ifc_nand_ctrl->oob) {
0c69fb03
KP		 491 iowrite32be(ifc_nand_ctrl->index -
492 ifc_nand_ctrl->column,
493 &ifc->ifc_nand.nand_fbcr);
82771882 494 } else {
0c69fb03 495 iowrite32be(0, &ifc->ifc_nand.nand_fbcr);
82771882
PK		 496 }
497
498 fsl_ifc_run_command(mtd);
499 return;
500 }
501
502 case NAND_CMD_STATUS:
0c69fb03
KP		 503 iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
504 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT),
505 &ifc->ifc_nand.nand_fir0);
506 iowrite32be(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
507 &ifc->ifc_nand.nand_fcr0);
508 iowrite32be(1, &ifc->ifc_nand.nand_fbcr);
82771882
PK		 509 set_addr(mtd, 0, 0, 0);
510 ifc_nand_ctrl->read_bytes = 1;
511
512 fsl_ifc_run_command(mtd);
513
514 /*
515 * The chip always seems to report that it is
516 * write-protected, even when it is not.
517 */
518 setbits8(ifc_nand_ctrl->addr, NAND_STATUS_WP);
519 return;
520
521 case NAND_CMD_RESET:
0c69fb03
KP		 522 iowrite32be(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT,
523 &ifc->ifc_nand.nand_fir0);
524 iowrite32be(NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT,
525 &ifc->ifc_nand.nand_fcr0);
82771882
PK		 526 fsl_ifc_run_command(mtd);
527 return;
528
529 default:
530 dev_err(priv->dev, "%s: error, unsupported command 0x%x.\n",
531 __func__, command);
532 }
533}
534
535static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
536{
537 /* The hardware does not seem to support multiple
538 * chips per bank.
539 */
540}
541
542/*
543 * Write buf to the IFC NAND Controller Data Buffer
544 */
545static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
546{
547 struct nand_chip *chip = mtd->priv;
548 struct fsl_ifc_mtd *priv = chip->priv;
549 unsigned int bufsize = mtd->writesize + mtd->oobsize;
550
551 if (len <= 0) {
552 dev_err(priv->dev, "%s: len %d bytes", __func__, len);
553 return;
554 }
555
556 if ((unsigned int)len > bufsize - ifc_nand_ctrl->index) {
557 dev_err(priv->dev,
558 "%s: beyond end of buffer (%d requested, %u available)\n",
559 __func__, len, bufsize - ifc_nand_ctrl->index);
560 len = bufsize - ifc_nand_ctrl->index;
561 }
562
563 memcpy_toio(&ifc_nand_ctrl->addr[ifc_nand_ctrl->index], buf, len);
564 ifc_nand_ctrl->index += len;
565}
566
567/*
568 * Read a byte from either the IFC hardware buffer
569 * read function for 8-bit buswidth
570 */
571static uint8_t fsl_ifc_read_byte(struct mtd_info *mtd)
572{
573 struct nand_chip *chip = mtd->priv;
574 struct fsl_ifc_mtd *priv = chip->priv;
575
576 /*
577 * If there are still bytes in the IFC buffer, then use the
578 * next byte.
579 */
580 if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes)
581 return in_8(&ifc_nand_ctrl->addr[ifc_nand_ctrl->index++]);
582
583 dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
584 return ERR_BYTE;
585}
586
587/*
588 * Read two bytes from the IFC hardware buffer
589 * read function for 16-bit buswith
590 */
591static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
592{
593 struct nand_chip *chip = mtd->priv;
594 struct fsl_ifc_mtd *priv = chip->priv;
595 uint16_t data;
596
597 /*
598 * If there are still bytes in the IFC buffer, then use the
599 * next byte.
600 */
601 if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
2caf87a4
KP		 602 data = in_be16((uint16_t __iomem *)&ifc_nand_ctrl->
603 addr[ifc_nand_ctrl->index]);
82771882
PK		 604 ifc_nand_ctrl->index += 2;
605 return (uint8_t) data;
606 }
607
608 dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
609 return ERR_BYTE;
610}
611
612/*
613 * Read from the IFC Controller Data Buffer
614 */
615static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
616{
617 struct nand_chip *chip = mtd->priv;
618 struct fsl_ifc_mtd *priv = chip->priv;
619 int avail;
620
621 if (len < 0) {
622 dev_err(priv->dev, "%s: len %d bytes", __func__, len);
623 return;
624 }
625
626 avail = min((unsigned int)len,
627 ifc_nand_ctrl->read_bytes - ifc_nand_ctrl->index);
628 memcpy_fromio(buf, &ifc_nand_ctrl->addr[ifc_nand_ctrl->index], avail);
629 ifc_nand_ctrl->index += avail;
630
631 if (len > avail)
632 dev_err(priv->dev,
633 "%s: beyond end of buffer (%d requested, %d available)\n",
634 __func__, len, avail);
635}
636
82771882
PK		 637/*
638 * This function is called after Program and Erase Operations to
639 * check for success or failure.
640 */
641static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
642{
643 struct fsl_ifc_mtd *priv = chip->priv;
644 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
645 struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
646 u32 nand_fsr;
647
648 /* Use READ_STATUS command, but wait for the device to be ready */
0c69fb03
KP		 649 iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
650 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT),
651 &ifc->ifc_nand.nand_fir0);
652 iowrite32be(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
653 &ifc->ifc_nand.nand_fcr0);
654 iowrite32be(1, &ifc->ifc_nand.nand_fbcr);
82771882
PK		 655 set_addr(mtd, 0, 0, 0);
656 ifc_nand_ctrl->read_bytes = 1;
657
658 fsl_ifc_run_command(mtd);
659
0c69fb03 660 nand_fsr = ioread32be(&ifc->ifc_nand.nand_fsr);
82771882
PK		 661
662 /*
663 * The chip always seems to report that it is
664 * write-protected, even when it is not.
665 */
666 return nand_fsr | NAND_STATUS_WP;
667}
668
1fbb938d
BN		 669static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
670 uint8_t *buf, int oob_required, int page)
82771882
PK		 671{
672 struct fsl_ifc_mtd *priv = chip->priv;
673 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
3f91e94f 674 struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
82771882
PK		 675
676 fsl_ifc_read_buf(mtd, buf, mtd->writesize);
a6976cdf
BN		 677 if (oob_required)
678 fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
82771882
PK		 679
680 if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_ECCER)
681 dev_err(priv->dev, "NAND Flash ECC Uncorrectable Error\n");
682
683 if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
684 mtd->ecc_stats.failed++;
685
3f91e94f 686 return nctrl->max_bitflips;
82771882
PK		 687}
688
689/* ECC will be calculated automatically, and errors will be detected in
690 * waitfunc.
691 */
fdbad98d 692static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 693 const uint8_t *buf, int oob_required)
82771882
PK		 694{
695 fsl_ifc_write_buf(mtd, buf, mtd->writesize);
696 fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
fdbad98d
JW		 697
698 return 0;
82771882
PK		 699}
700
701static int fsl_ifc_chip_init_tail(struct mtd_info *mtd)
702{
703 struct nand_chip *chip = mtd->priv;
704 struct fsl_ifc_mtd *priv = chip->priv;
705
706 dev_dbg(priv->dev, "%s: nand->numchips = %d\n", __func__,
707 chip->numchips);
708 dev_dbg(priv->dev, "%s: nand->chipsize = %lld\n", __func__,
709 chip->chipsize);
710 dev_dbg(priv->dev, "%s: nand->pagemask = %8x\n", __func__,
711 chip->pagemask);
712 dev_dbg(priv->dev, "%s: nand->chip_delay = %d\n", __func__,
713 chip->chip_delay);
714 dev_dbg(priv->dev, "%s: nand->badblockpos = %d\n", __func__,
715 chip->badblockpos);
716 dev_dbg(priv->dev, "%s: nand->chip_shift = %d\n", __func__,
717 chip->chip_shift);
718 dev_dbg(priv->dev, "%s: nand->page_shift = %d\n", __func__,
719 chip->page_shift);
720 dev_dbg(priv->dev, "%s: nand->phys_erase_shift = %d\n", __func__,
721 chip->phys_erase_shift);
722 dev_dbg(priv->dev, "%s: nand->ecclayout = %p\n", __func__,
723 chip->ecclayout);
724 dev_dbg(priv->dev, "%s: nand->ecc.mode = %d\n", __func__,
725 chip->ecc.mode);
726 dev_dbg(priv->dev, "%s: nand->ecc.steps = %d\n", __func__,
727 chip->ecc.steps);
728 dev_dbg(priv->dev, "%s: nand->ecc.bytes = %d\n", __func__,
729 chip->ecc.bytes);
730 dev_dbg(priv->dev, "%s: nand->ecc.total = %d\n", __func__,
731 chip->ecc.total);
732 dev_dbg(priv->dev, "%s: nand->ecc.layout = %p\n", __func__,
733 chip->ecc.layout);
734 dev_dbg(priv->dev, "%s: mtd->flags = %08x\n", __func__, mtd->flags);
735 dev_dbg(priv->dev, "%s: mtd->size = %lld\n", __func__, mtd->size);
736 dev_dbg(priv->dev, "%s: mtd->erasesize = %d\n", __func__,
737 mtd->erasesize);
738 dev_dbg(priv->dev, "%s: mtd->writesize = %d\n", __func__,
739 mtd->writesize);
740 dev_dbg(priv->dev, "%s: mtd->oobsize = %d\n", __func__,
741 mtd->oobsize);
742
743 return 0;
744}
745
10bfa766
PK		 746static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
747{
748 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
749 struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
750 uint32_t csor = 0, csor_8k = 0, csor_ext = 0;
751 uint32_t cs = priv->bank;
752
753 /* Save CSOR and CSOR_ext */
0c69fb03
KP		 754 csor = ioread32be(&ifc->csor_cs[cs].csor);
755 csor_ext = ioread32be(&ifc->csor_cs[cs].csor_ext);
10bfa766
PK		 756
757 /* chage PageSize 8K and SpareSize 1K*/
758 csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
0c69fb03
KP		 759 iowrite32be(csor_8k, &ifc->csor_cs[cs].csor);
760 iowrite32be(0x0000400, &ifc->csor_cs[cs].csor_ext);
10bfa766
PK		 761
762 /* READID */
0c69fb03
KP		 763 iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
764 (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
765 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT),
766 &ifc->ifc_nand.nand_fir0);
767 iowrite32be(NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT,
768 &ifc->ifc_nand.nand_fcr0);
769 iowrite32be(0x0, &ifc->ifc_nand.row3);
10bfa766 770
0c69fb03 771 iowrite32be(0x0, &ifc->ifc_nand.nand_fbcr);
10bfa766
PK		 772
773 /* Program ROW0/COL0 */
0c69fb03
KP		 774 iowrite32be(0x0, &ifc->ifc_nand.row0);
775 iowrite32be(0x0, &ifc->ifc_nand.col0);
10bfa766
PK		 776
777 /* set the chip select for NAND Transaction */
0c69fb03 778 iowrite32be(cs << IFC_NAND_CSEL_SHIFT, &ifc->ifc_nand.nand_csel);
10bfa766
PK		 779
780 /* start read seq */
0c69fb03 781 iowrite32be(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
10bfa766
PK		 782
783 /* wait for command complete flag or timeout */
784 wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
785 IFC_TIMEOUT_MSECS * HZ/1000);
786
787 if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
788 printk(KERN_ERR "fsl-ifc: Failed to Initialise SRAM\n");
789
790 /* Restore CSOR and CSOR_ext */
0c69fb03
KP		 791 iowrite32be(csor, &ifc->csor_cs[cs].csor);
792 iowrite32be(csor_ext, &ifc->csor_cs[cs].csor_ext);
10bfa766
PK		 793}
794
82771882
PK		 795static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
796{
797 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
798 struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
799 struct nand_chip *chip = &priv->chip;
800 struct nand_ecclayout *layout;
10bfa766 801 u32 csor, ver;
82771882
PK		 802
803 /* Fill in fsl_ifc_mtd structure */
804 priv->mtd.priv = chip;
805 priv->mtd.owner = THIS_MODULE;
806
807 /* fill in nand_chip structure */
808 /* set up function call table */
0c69fb03 809 if ((ioread32be(&ifc->cspr_cs[priv->bank].cspr)) & CSPR_PORT_SIZE_16)
82771882
PK		 810 chip->read_byte = fsl_ifc_read_byte16;
811 else
812 chip->read_byte = fsl_ifc_read_byte;
813
814 chip->write_buf = fsl_ifc_write_buf;
815 chip->read_buf = fsl_ifc_read_buf;
82771882
PK		 816 chip->select_chip = fsl_ifc_select_chip;
817 chip->cmdfunc = fsl_ifc_cmdfunc;
818 chip->waitfunc = fsl_ifc_wait;
819
820 chip->bbt_td = &bbt_main_descr;
821 chip->bbt_md = &bbt_mirror_descr;
822
0c69fb03 823 iowrite32be(0x0, &ifc->ifc_nand.ncfgr);
82771882
PK		 824
825 /* set up nand options */
82771882 826 chip->bbt_options = NAND_BBT_USE_FLASH;
20cd0008 827 chip->options = NAND_NO_SUBPAGE_WRITE;
82771882 828
0c69fb03 829 if (ioread32be(&ifc->cspr_cs[priv->bank].cspr) & CSPR_PORT_SIZE_16) {
82771882
PK		 830 chip->read_byte = fsl_ifc_read_byte16;
831 chip->options |= NAND_BUSWIDTH_16;
832 } else {
833 chip->read_byte = fsl_ifc_read_byte;
834 }
835
836 chip->controller = &ifc_nand_ctrl->controller;
837 chip->priv = priv;
838
839 chip->ecc.read_page = fsl_ifc_read_page;
840 chip->ecc.write_page = fsl_ifc_write_page;
841
0c69fb03 842 csor = ioread32be(&ifc->csor_cs[priv->bank].csor);
82771882
PK		 843
844 /* Hardware generates ECC per 512 Bytes */
845 chip->ecc.size = 512;
846 chip->ecc.bytes = 8;
44df4d11 847 chip->ecc.strength = 4;
82771882
PK		 848
849 switch (csor & CSOR_NAND_PGS_MASK) {
850 case CSOR_NAND_PGS_512:
851 if (chip->options & NAND_BUSWIDTH_16) {
852 layout = &oob_512_16bit_ecc4;
853 } else {
854 layout = &oob_512_8bit_ecc4;
855
856 /* Avoid conflict with bad block marker */
857 bbt_main_descr.offs = 0;
858 bbt_mirror_descr.offs = 0;
859 }
860
861 priv->bufnum_mask = 15;
862 break;
863
864 case CSOR_NAND_PGS_2K:
865 layout = &oob_2048_ecc4;
866 priv->bufnum_mask = 3;
867 break;
868
869 case CSOR_NAND_PGS_4K:
870 if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
871 CSOR_NAND_ECC_MODE_4) {
872 layout = &oob_4096_ecc4;
873 } else {
874 layout = &oob_4096_ecc8;
875 chip->ecc.bytes = 16;
876 }
877
878 priv->bufnum_mask = 1;
879 break;
880
881 default:
882 dev_err(priv->dev, "bad csor %#x: bad page size\n", csor);
883 return -ENODEV;
884 }
885
886 /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
887 if (csor & CSOR_NAND_ECC_DEC_EN) {
888 chip->ecc.mode = NAND_ECC_HW;
889 chip->ecc.layout = layout;
890 } else {
891 chip->ecc.mode = NAND_ECC_SOFT;
892 }
893
0c69fb03 894 ver = ioread32be(&ifc->ifc_rev);
10bfa766
PK		 895 if (ver == FSL_IFC_V1_1_0)
896 fsl_ifc_sram_init(priv);
897
82771882
PK		 898 return 0;
899}
900
901static int fsl_ifc_chip_remove(struct fsl_ifc_mtd *priv)
902{
903 nand_release(&priv->mtd);
904
905 kfree(priv->mtd.name);
906
907 if (priv->vbase)
908 iounmap(priv->vbase);
909
910 ifc_nand_ctrl->chips[priv->bank] = NULL;
911 dev_set_drvdata(priv->dev, NULL);
82771882
PK		 912
913 return 0;
914}
915
916static int match_bank(struct fsl_ifc_regs __iomem *ifc, int bank,
917 phys_addr_t addr)
918{
0c69fb03 919 u32 cspr = ioread32be(&ifc->cspr_cs[bank].cspr);
82771882
PK		 920
921 if (!(cspr & CSPR_V))
922 return 0;
923 if ((cspr & CSPR_MSEL) != CSPR_MSEL_NAND)
924 return 0;
925
926 return (cspr & CSPR_BA) == convert_ifc_address(addr);
927}
928
929static DEFINE_MUTEX(fsl_ifc_nand_mutex);
930
06f25510 931static int fsl_ifc_nand_probe(struct platform_device *dev)
82771882
PK		 932{
933 struct fsl_ifc_regs __iomem *ifc;
934 struct fsl_ifc_mtd *priv;
935 struct resource res;
936 static const char *part_probe_types[]
937 = { "cmdlinepart", "RedBoot", "ofpart", NULL };
938 int ret;
939 int bank;
940 struct device_node *node = dev->dev.of_node;
941 struct mtd_part_parser_data ppdata;
942
943 ppdata.of_node = dev->dev.of_node;
944 if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->regs)
945 return -ENODEV;
946 ifc = fsl_ifc_ctrl_dev->regs;
947
948 /* get, allocate and map the memory resource */
949 ret = of_address_to_resource(node, 0, &res);
950 if (ret) {
951 dev_err(&dev->dev, "%s: failed to get resource\n", __func__);
952 return ret;
953 }
954
955 /* find which chip select it is connected to */
956 for (bank = 0; bank < FSL_IFC_BANK_COUNT; bank++) {
957 if (match_bank(ifc, bank, res.start))
958 break;
959 }
960
961 if (bank >= FSL_IFC_BANK_COUNT) {
962 dev_err(&dev->dev, "%s: address did not match any chip selects\n",
963 __func__);
964 return -ENODEV;
965 }
966
967 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
968 if (!priv)
969 return -ENOMEM;
970
971 mutex_lock(&fsl_ifc_nand_mutex);
972 if (!fsl_ifc_ctrl_dev->nand) {
973 ifc_nand_ctrl = kzalloc(sizeof(*ifc_nand_ctrl), GFP_KERNEL);
974 if (!ifc_nand_ctrl) {
975 dev_err(&dev->dev, "failed to allocate memory\n");
976 mutex_unlock(&fsl_ifc_nand_mutex);
977 return -ENOMEM;
978 }
979
980 ifc_nand_ctrl->read_bytes = 0;
981 ifc_nand_ctrl->index = 0;
982 ifc_nand_ctrl->addr = NULL;
983 fsl_ifc_ctrl_dev->nand = ifc_nand_ctrl;
984
985 spin_lock_init(&ifc_nand_ctrl->controller.lock);
986 init_waitqueue_head(&ifc_nand_ctrl->controller.wq);
987 } else {
988 ifc_nand_ctrl = fsl_ifc_ctrl_dev->nand;
989 }
990 mutex_unlock(&fsl_ifc_nand_mutex);
991
992 ifc_nand_ctrl->chips[bank] = priv;
993 priv->bank = bank;
994 priv->ctrl = fsl_ifc_ctrl_dev;
995 priv->dev = &dev->dev;
996
997 priv->vbase = ioremap(res.start, resource_size(&res));
998 if (!priv->vbase) {
999 dev_err(priv->dev, "%s: failed to map chip region\n", __func__);
1000 ret = -ENOMEM;
1001 goto err;
1002 }
1003
1004 dev_set_drvdata(priv->dev, priv);
1005
0c69fb03
KP		 1006 iowrite32be(IFC_NAND_EVTER_EN_OPC_EN |
1007 IFC_NAND_EVTER_EN_FTOER_EN |
1008 IFC_NAND_EVTER_EN_WPER_EN,
1009 &ifc->ifc_nand.nand_evter_en);
82771882
PK		 1010
1011 /* enable NAND Machine Interrupts */
0c69fb03
KP		 1012 iowrite32be(IFC_NAND_EVTER_INTR_OPCIR_EN |
1013 IFC_NAND_EVTER_INTR_FTOERIR_EN |
1014 IFC_NAND_EVTER_INTR_WPERIR_EN,
1015 &ifc->ifc_nand.nand_evter_intr_en);
82771882
PK		 1016 priv->mtd.name = kasprintf(GFP_KERNEL, "%x.flash", (unsigned)res.start);
1017 if (!priv->mtd.name) {
1018 ret = -ENOMEM;
1019 goto err;
1020 }
1021
1022 ret = fsl_ifc_chip_init(priv);
1023 if (ret)
1024 goto err;
1025
1026 ret = nand_scan_ident(&priv->mtd, 1, NULL);
1027 if (ret)
1028 goto err;
1029
1030 ret = fsl_ifc_chip_init_tail(&priv->mtd);
1031 if (ret)
1032 goto err;
1033
1034 ret = nand_scan_tail(&priv->mtd);
1035 if (ret)
1036 goto err;
1037
1038 /* First look for RedBoot table or partitions on the command
1039 * line, these take precedence over device tree information */
1040 mtd_device_parse_register(&priv->mtd, part_probe_types, &ppdata,
1041 NULL, 0);
1042
1043 dev_info(priv->dev, "IFC NAND device at 0x%llx, bank %d\n",
1044 (unsigned long long)res.start, priv->bank);
1045 return 0;
1046
1047err:
1048 fsl_ifc_chip_remove(priv);
1049 return ret;
1050}
1051
1052static int fsl_ifc_nand_remove(struct platform_device *dev)
1053{
1054 struct fsl_ifc_mtd *priv = dev_get_drvdata(&dev->dev);
1055
1056 fsl_ifc_chip_remove(priv);
1057
1058 mutex_lock(&fsl_ifc_nand_mutex);
1059 ifc_nand_ctrl->counter--;
1060 if (!ifc_nand_ctrl->counter) {
1061 fsl_ifc_ctrl_dev->nand = NULL;
1062 kfree(ifc_nand_ctrl);
1063 }
1064 mutex_unlock(&fsl_ifc_nand_mutex);
1065
1066 return 0;
1067}
1068
1069static const struct of_device_id fsl_ifc_nand_match[] = {
1070 {
1071 .compatible = "fsl,ifc-nand",
1072 },
1073 {}
1074};
1075
1076static struct platform_driver fsl_ifc_nand_driver = {
1077 .driver = {
1078 .name = "fsl,ifc-nand",
1079 .owner = THIS_MODULE,
1080 .of_match_table = fsl_ifc_nand_match,
1081 },
1082 .probe = fsl_ifc_nand_probe,
1083 .remove = fsl_ifc_nand_remove,
1084};
1085
1086static int __init fsl_ifc_nand_init(void)
1087{
1088 int ret;
1089
1090 ret = platform_driver_register(&fsl_ifc_nand_driver);
1091 if (ret)
1092 printk(KERN_ERR "fsl-ifc: Failed to register platform"
1093 "driver\n");
1094
1095 return ret;
1096}
1097
1098static void __exit fsl_ifc_nand_exit(void)
1099{
1100 platform_driver_unregister(&fsl_ifc_nand_driver);
1101}
1102
1103module_init(fsl_ifc_nand_init);
1104module_exit(fsl_ifc_nand_exit);
1105
1106MODULE_LICENSE("GPL");
1107MODULE_AUTHOR("Freescale");
1108MODULE_DESCRIPTION("Freescale Integrated Flash Controller MTD NAND driver");
Linux kernel - Deliverables
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