[deliverable/linux.git] / drivers / mtd / nand / fsl_upm.c

/*
 * Freescale UPM NAND driver.
 *
 * Copyright © 2007-2008  MontaVista Software, Inc.
 *
 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/mtd.h>
#include <linux/of_platform.h>
#include <linux/of_gpio.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <asm/fsl_lbc.h>

#define FSL_UPM_WAIT_RUN_PATTERN  0x1
#define FSL_UPM_WAIT_WRITE_BYTE   0x2
#define FSL_UPM_WAIT_WRITE_BUFFER 0x4

struct fsl_upm_nand {
	struct device *dev;
	struct mtd_info mtd;
	struct nand_chip chip;
	int last_ctrl;
	struct mtd_partition *parts;
	struct fsl_upm upm;
	uint8_t upm_addr_offset;
	uint8_t upm_cmd_offset;
	void __iomem *io_base;
	int rnb_gpio[NAND_MAX_CHIPS];
	uint32_t mchip_offsets[NAND_MAX_CHIPS];
	uint32_t mchip_count;
	uint32_t mchip_number;
	int chip_delay;
	uint32_t wait_flags;
};

static inline struct fsl_upm_nand *to_fsl_upm_nand(struct mtd_info *mtdinfo)
{
	return container_of(mtdinfo, struct fsl_upm_nand, mtd);
}

static int fun_chip_ready(struct mtd_info *mtd)
{
	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);

	if (gpio_get_value(fun->rnb_gpio[fun->mchip_number]))
		return 1;

	dev_vdbg(fun->dev, "busy\n");
	return 0;
}

static void fun_wait_rnb(struct fsl_upm_nand *fun)
{
	if (fun->rnb_gpio[fun->mchip_number] >= 0) {
		int cnt = 1000000;

		while (--cnt && !fun_chip_ready(&fun->mtd))
			cpu_relax();
		if (!cnt)
			dev_err(fun->dev, "tired waiting for RNB\n");
	} else {
		ndelay(100);
	}
}

static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
	struct nand_chip *chip = mtd->priv;
	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
	u32 mar;

	if (!(ctrl & fun->last_ctrl)) {
		fsl_upm_end_pattern(&fun->upm);

		if (cmd == NAND_CMD_NONE)
			return;

		fun->last_ctrl = ctrl & (NAND_ALE | NAND_CLE);
	}

	if (ctrl & NAND_CTRL_CHANGE) {
		if (ctrl & NAND_ALE)
			fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
		else if (ctrl & NAND_CLE)
			fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
	}

	mar = (cmd << (32 - fun->upm.width)) |
		fun->mchip_offsets[fun->mchip_number];
	fsl_upm_run_pattern(&fun->upm, chip->IO_ADDR_R, mar);

	if (fun->wait_flags & FSL_UPM_WAIT_RUN_PATTERN)
		fun_wait_rnb(fun);
}

static void fun_select_chip(struct mtd_info *mtd, int mchip_nr)
{
	struct nand_chip *chip = mtd->priv;
	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);

	if (mchip_nr == -1) {
		chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
	} else if (mchip_nr >= 0 && mchip_nr < NAND_MAX_CHIPS) {
		fun->mchip_number = mchip_nr;
		chip->IO_ADDR_R = fun->io_base + fun->mchip_offsets[mchip_nr];
		chip->IO_ADDR_W = chip->IO_ADDR_R;
	} else {
		BUG();
	}
}

static uint8_t fun_read_byte(struct mtd_info *mtd)
{
	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);

	return in_8(fun->chip.IO_ADDR_R);
}

static void fun_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
{
	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
	int i;

	for (i = 0; i < len; i++)
		buf[i] = in_8(fun->chip.IO_ADDR_R);
}

static void fun_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
{
	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
	int i;

	for (i = 0; i < len; i++) {
		out_8(fun->chip.IO_ADDR_W, buf[i]);
		if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BYTE)
			fun_wait_rnb(fun);
	}
	if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BUFFER)
		fun_wait_rnb(fun);
}

static int fun_chip_init(struct fsl_upm_nand *fun,
			 const struct device_node *upm_np,
			 const struct resource *io_res)
{
	int ret;
	struct device_node *flash_np;
	struct mtd_part_parser_data ppdata;

	fun->chip.IO_ADDR_R = fun->io_base;
	fun->chip.IO_ADDR_W = fun->io_base;
	fun->chip.cmd_ctrl = fun_cmd_ctrl;
	fun->chip.chip_delay = fun->chip_delay;
	fun->chip.read_byte = fun_read_byte;
	fun->chip.read_buf = fun_read_buf;
	fun->chip.write_buf = fun_write_buf;
	fun->chip.ecc.mode = NAND_ECC_SOFT;
	if (fun->mchip_count > 1)
		fun->chip.select_chip = fun_select_chip;

	if (fun->rnb_gpio[0] >= 0)
		fun->chip.dev_ready = fun_chip_ready;

	fun->mtd.priv = &fun->chip;
	fun->mtd.owner = THIS_MODULE;

	flash_np = of_get_next_child(upm_np, NULL);
	if (!flash_np)
		return -ENODEV;

	fun->mtd.name = kasprintf(GFP_KERNEL, "0x%llx.%s", (u64)io_res->start,
				  flash_np->name);
	if (!fun->mtd.name) {
		ret = -ENOMEM;
		goto err;
	}

	ret = nand_scan(&fun->mtd, fun->mchip_count);
	if (ret)
		goto err;

	ppdata.of_node = flash_np;
	ret = mtd_device_parse_register(&fun->mtd, NULL, &ppdata, NULL, 0);
err:
	of_node_put(flash_np);
	if (ret)
		kfree(fun->mtd.name);
	return ret;
}

static int fun_probe(struct platform_device *ofdev)
{
	struct fsl_upm_nand *fun;
	struct resource io_res;
	const __be32 *prop;
	int rnb_gpio;
	int ret;
	int size;
	int i;

	fun = kzalloc(sizeof(*fun), GFP_KERNEL);
	if (!fun)
		return -ENOMEM;

	ret = of_address_to_resource(ofdev->dev.of_node, 0, &io_res);
	if (ret) {
		dev_err(&ofdev->dev, "can't get IO base\n");
		goto err1;
	}

	ret = fsl_upm_find(io_res.start, &fun->upm);
	if (ret) {
		dev_err(&ofdev->dev, "can't find UPM\n");
		goto err1;
	}

	prop = of_get_property(ofdev->dev.of_node, "fsl,upm-addr-offset",
			       &size);
	if (!prop || size != sizeof(uint32_t)) {
		dev_err(&ofdev->dev, "can't get UPM address offset\n");
		ret = -EINVAL;
		goto err1;
	}
	fun->upm_addr_offset = *prop;

	prop = of_get_property(ofdev->dev.of_node, "fsl,upm-cmd-offset", &size);
	if (!prop || size != sizeof(uint32_t)) {
		dev_err(&ofdev->dev, "can't get UPM command offset\n");
		ret = -EINVAL;
		goto err1;
	}
	fun->upm_cmd_offset = *prop;

	prop = of_get_property(ofdev->dev.of_node,
			       "fsl,upm-addr-line-cs-offsets", &size);
	if (prop && (size / sizeof(uint32_t)) > 0) {
		fun->mchip_count = size / sizeof(uint32_t);
		if (fun->mchip_count >= NAND_MAX_CHIPS) {
			dev_err(&ofdev->dev, "too much multiple chips\n");
			goto err1;
		}
		for (i = 0; i < fun->mchip_count; i++)
			fun->mchip_offsets[i] = be32_to_cpu(prop[i]);
	} else {
		fun->mchip_count = 1;
	}

	for (i = 0; i < fun->mchip_count; i++) {
		fun->rnb_gpio[i] = -1;
		rnb_gpio = of_get_gpio(ofdev->dev.of_node, i);
		if (rnb_gpio >= 0) {
			ret = gpio_request(rnb_gpio, dev_name(&ofdev->dev));
			if (ret) {
				dev_err(&ofdev->dev,
					"can't request RNB gpio #%d\n", i);
				goto err2;
			}
			gpio_direction_input(rnb_gpio);
			fun->rnb_gpio[i] = rnb_gpio;
		} else if (rnb_gpio == -EINVAL) {
			dev_err(&ofdev->dev, "RNB gpio #%d is invalid\n", i);
			goto err2;
		}
	}

	prop = of_get_property(ofdev->dev.of_node, "chip-delay", NULL);
	if (prop)
		fun->chip_delay = be32_to_cpup(prop);
	else
		fun->chip_delay = 50;

	prop = of_get_property(ofdev->dev.of_node, "fsl,upm-wait-flags", &size);
	if (prop && size == sizeof(uint32_t))
		fun->wait_flags = be32_to_cpup(prop);
	else
		fun->wait_flags = FSL_UPM_WAIT_RUN_PATTERN |
				  FSL_UPM_WAIT_WRITE_BYTE;

	fun->io_base = devm_ioremap_nocache(&ofdev->dev, io_res.start,
					    resource_size(&io_res));
	if (!fun->io_base) {
		ret = -ENOMEM;
		goto err2;
	}

	fun->dev = &ofdev->dev;
	fun->last_ctrl = NAND_CLE;

	ret = fun_chip_init(fun, ofdev->dev.of_node, &io_res);
	if (ret)
		goto err2;

	dev_set_drvdata(&ofdev->dev, fun);

	return 0;
err2:
	for (i = 0; i < fun->mchip_count; i++) {
		if (fun->rnb_gpio[i] < 0)
			break;
		gpio_free(fun->rnb_gpio[i]);
	}
err1:
	kfree(fun);

	return ret;
}

static int fun_remove(struct platform_device *ofdev)
{
	struct fsl_upm_nand *fun = dev_get_drvdata(&ofdev->dev);
	int i;

	nand_release(&fun->mtd);
	kfree(fun->mtd.name);

	for (i = 0; i < fun->mchip_count; i++) {
		if (fun->rnb_gpio[i] < 0)
			break;
		gpio_free(fun->rnb_gpio[i]);
	}

	kfree(fun);

	return 0;
}

static const struct of_device_id of_fun_match[] = {
	{ .compatible = "fsl,upm-nand" },
	{},
};
MODULE_DEVICE_TABLE(of, of_fun_match);

static struct platform_driver of_fun_driver = {
	.driver = {
		.name = "fsl,upm-nand",
		.owner = THIS_MODULE,
		.of_match_table = of_fun_match,
	},
	.probe		= fun_probe,
	.remove		= fun_remove,
};

module_platform_driver(of_fun_driver);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Anton Vorontsov <avorontsov@ru.mvista.com>");
MODULE_DESCRIPTION("Driver for NAND chips working through Freescale "
		   "LocalBus User-Programmable Machine");
Commit	Line	Data
5c249c5a AV	1	/*
	2	* Freescale UPM NAND driver.
	3	*
	4	* Copyright © 2007-2008 MontaVista Software, Inc.
	5	*
	6	* Author: Anton Vorontsov <avorontsov@ru.mvista.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/module.h>
13f53697	16	#include <linux/delay.h>
5c249c5a AV	17	#include <linux/mtd/nand.h>
	18	#include <linux/mtd/nand_ecc.h>
	19	#include <linux/mtd/partitions.h>
	20	#include <linux/mtd/mtd.h>
	21	#include <linux/of_platform.h>
	22	#include <linux/of_gpio.h>
	23	#include <linux/io.h>
5a0e3ad6	24	#include <linux/slab.h>
5c249c5a AV	25	#include <asm/fsl_lbc.h>
5c249c5a AV	26
ade92a63 WG	27	#define FSL_UPM_WAIT_RUN_PATTERN 0x1
	28	#define FSL_UPM_WAIT_WRITE_BYTE 0x2
	29	#define FSL_UPM_WAIT_WRITE_BUFFER 0x4
	30
5c249c5a AV	31	struct fsl_upm_nand {
	32	struct device *dev;
	33	struct mtd_info mtd;
	34	struct nand_chip chip;
	35	int last_ctrl;
5c249c5a	36	struct mtd_partition *parts;
5c249c5a AV	37	struct fsl_upm upm;
	38	uint8_t upm_addr_offset;
	39	uint8_t upm_cmd_offset;
	40	void __iomem *io_base;
b6e0e8c0 WG	41	int rnb_gpio[NAND_MAX_CHIPS];
	42	uint32_t mchip_offsets[NAND_MAX_CHIPS];
	43	uint32_t mchip_count;
	44	uint32_t mchip_number;
13f53697	45	int chip_delay;
ade92a63	46	uint32_t wait_flags;
5c249c5a AV	47	};
5c249c5a AV	48
b92b5c41 FW	49	static inline struct fsl_upm_nand to_fsl_upm_nand(struct mtd_info mtdinfo)
	50	{
	51	return container_of(mtdinfo, struct fsl_upm_nand, mtd);
	52	}
5c249c5a AV	53
	54	static int fun_chip_ready(struct mtd_info *mtd)
	55	{
	56	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
	57
b6e0e8c0	58	if (gpio_get_value(fun->rnb_gpio[fun->mchip_number]))
5c249c5a AV	59	return 1;
	60
	61	dev_vdbg(fun->dev, "busy\n");
	62	return 0;
	63	}
	64
	65	static void fun_wait_rnb(struct fsl_upm_nand *fun)
	66	{
b6e0e8c0 WG	67	if (fun->rnb_gpio[fun->mchip_number] >= 0) {
b6e0e8c0 WG	68	int cnt = 1000000;
5c249c5a	69
5c249c5a AV	70	while (--cnt && !fun_chip_ready(&fun->mtd))
5c249c5a AV	71	cpu_relax();
13f53697 WG	72	if (!cnt)
	73	dev_err(fun->dev, "tired waiting for RNB\n");
	74	} else {
	75	ndelay(100);
5c249c5a	76	}
5c249c5a AV	77	}
	78
	79	static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
	80	{
b6e0e8c0	81	struct nand_chip *chip = mtd->priv;
5c249c5a	82	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
b6e0e8c0	83	u32 mar;
5c249c5a AV	84
	85	if (!(ctrl & fun->last_ctrl)) {
	86	fsl_upm_end_pattern(&fun->upm);
	87
	88	if (cmd == NAND_CMD_NONE)
	89	return;
	90
	91	fun->last_ctrl = ctrl & (NAND_ALE \| NAND_CLE);
	92	}
	93
	94	if (ctrl & NAND_CTRL_CHANGE) {
	95	if (ctrl & NAND_ALE)
	96	fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
	97	else if (ctrl & NAND_CLE)
	98	fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
	99	}
	100
b6e0e8c0 WG	101	mar = (cmd << (32 - fun->upm.width)) \|
	102	fun->mchip_offsets[fun->mchip_number];
	103	fsl_upm_run_pattern(&fun->upm, chip->IO_ADDR_R, mar);
5c249c5a	104
ade92a63 WG	105	if (fun->wait_flags & FSL_UPM_WAIT_RUN_PATTERN)
ade92a63 WG	106	fun_wait_rnb(fun);
5c249c5a AV	107	}
5c249c5a AV	108
b6e0e8c0 WG	109	static void fun_select_chip(struct mtd_info *mtd, int mchip_nr)
	110	{
	111	struct nand_chip *chip = mtd->priv;
	112	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
	113
	114	if (mchip_nr == -1) {
	115	chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 \| NAND_CTRL_CHANGE);
35016dd7	116	} else if (mchip_nr >= 0 && mchip_nr < NAND_MAX_CHIPS) {
b6e0e8c0 WG	117	fun->mchip_number = mchip_nr;
	118	chip->IO_ADDR_R = fun->io_base + fun->mchip_offsets[mchip_nr];
	119	chip->IO_ADDR_W = chip->IO_ADDR_R;
	120	} else {
	121	BUG();
	122	}
	123	}
	124
5c249c5a AV	125	static uint8_t fun_read_byte(struct mtd_info *mtd)
	126	{
	127	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
	128
	129	return in_8(fun->chip.IO_ADDR_R);
	130	}
	131
	132	static void fun_read_buf(struct mtd_info mtd, uint8_t buf, int len)
	133	{
	134	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
	135	int i;
	136
	137	for (i = 0; i < len; i++)
	138	buf[i] = in_8(fun->chip.IO_ADDR_R);
	139	}
	140
	141	static void fun_write_buf(struct mtd_info mtd, const uint8_t buf, int len)
	142	{
	143	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
	144	int i;
	145
	146	for (i = 0; i < len; i++) {
	147	out_8(fun->chip.IO_ADDR_W, buf[i]);
ade92a63 WG	148	if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BYTE)
ade92a63 WG	149	fun_wait_rnb(fun);
5c249c5a	150	}
ade92a63 WG	151	if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BUFFER)
ade92a63 WG	152	fun_wait_rnb(fun);
5c249c5a AV	153	}
5c249c5a AV	154
06f25510	155	static int fun_chip_init(struct fsl_upm_nand *fun,
d8929942 GKH	156	const struct device_node *upm_np,
d8929942 GKH	157	const struct resource *io_res)
5c249c5a AV	158	{
5c249c5a AV	159	int ret;
95ebffd7	160	struct device_node *flash_np;
a454a296	161	struct mtd_part_parser_data ppdata;
5c249c5a AV	162
	163	fun->chip.IO_ADDR_R = fun->io_base;
	164	fun->chip.IO_ADDR_W = fun->io_base;
	165	fun->chip.cmd_ctrl = fun_cmd_ctrl;
13f53697	166	fun->chip.chip_delay = fun->chip_delay;
5c249c5a AV	167	fun->chip.read_byte = fun_read_byte;
	168	fun->chip.read_buf = fun_read_buf;
	169	fun->chip.write_buf = fun_write_buf;
	170	fun->chip.ecc.mode = NAND_ECC_SOFT;
b6e0e8c0 WG	171	if (fun->mchip_count > 1)
b6e0e8c0 WG	172	fun->chip.select_chip = fun_select_chip;
5c249c5a	173
b6e0e8c0	174	if (fun->rnb_gpio[0] >= 0)
5c249c5a AV	175	fun->chip.dev_ready = fun_chip_ready;
	176
	177	fun->mtd.priv = &fun->chip;
	178	fun->mtd.owner = THIS_MODULE;
	179
95ebffd7 AV	180	flash_np = of_get_next_child(upm_np, NULL);
	181	if (!flash_np)
	182	return -ENODEV;
	183
0eecf4b2	184	fun->mtd.name = kasprintf(GFP_KERNEL, "0x%llx.%s", (u64)io_res->start,
95ebffd7 AV	185	flash_np->name);
	186	if (!fun->mtd.name) {
	187	ret = -ENOMEM;
	188	goto err;
	189	}
	190
b6e0e8c0	191	ret = nand_scan(&fun->mtd, fun->mchip_count);
5c249c5a	192	if (ret)
95ebffd7	193	goto err;
5c249c5a	194
a454a296	195	ppdata.of_node = flash_np;
73f36b3e	196	ret = mtd_device_parse_register(&fun->mtd, NULL, &ppdata, NULL, 0);
95ebffd7 AV	197	err:
95ebffd7 AV	198	of_node_put(flash_np);
a751d315 AL	199	if (ret)
a751d315 AL	200	kfree(fun->mtd.name);
95ebffd7	201	return ret;
5c249c5a AV	202	}
5c249c5a AV	203
06f25510	204	static int fun_probe(struct platform_device *ofdev)
5c249c5a AV	205	{
	206	struct fsl_upm_nand *fun;
	207	struct resource io_res;
766f271a	208	const __be32 *prop;
b6e0e8c0	209	int rnb_gpio;
5c249c5a AV	210	int ret;
5c249c5a AV	211	int size;
b6e0e8c0	212	int i;
5c249c5a AV	213
	214	fun = kzalloc(sizeof(*fun), GFP_KERNEL);
	215	if (!fun)
	216	return -ENOMEM;
	217
c8a4d0fd	218	ret = of_address_to_resource(ofdev->dev.of_node, 0, &io_res);
5c249c5a AV	219	if (ret) {
	220	dev_err(&ofdev->dev, "can't get IO base\n");
	221	goto err1;
	222	}
	223
	224	ret = fsl_upm_find(io_res.start, &fun->upm);
	225	if (ret) {
	226	dev_err(&ofdev->dev, "can't find UPM\n");
	227	goto err1;
	228	}
	229
c8a4d0fd AG	230	prop = of_get_property(ofdev->dev.of_node, "fsl,upm-addr-offset",
c8a4d0fd AG	231	&size);
5c249c5a AV	232	if (!prop \|\| size != sizeof(uint32_t)) {
	233	dev_err(&ofdev->dev, "can't get UPM address offset\n");
	234	ret = -EINVAL;
b6e0e8c0	235	goto err1;
5c249c5a AV	236	}
	237	fun->upm_addr_offset = *prop;
	238
c8a4d0fd	239	prop = of_get_property(ofdev->dev.of_node, "fsl,upm-cmd-offset", &size);
5c249c5a AV	240	if (!prop \|\| size != sizeof(uint32_t)) {
	241	dev_err(&ofdev->dev, "can't get UPM command offset\n");
	242	ret = -EINVAL;
b6e0e8c0	243	goto err1;
5c249c5a AV	244	}
	245	fun->upm_cmd_offset = *prop;
	246
c8a4d0fd	247	prop = of_get_property(ofdev->dev.of_node,
b6e0e8c0 WG	248	"fsl,upm-addr-line-cs-offsets", &size);
	249	if (prop && (size / sizeof(uint32_t)) > 0) {
	250	fun->mchip_count = size / sizeof(uint32_t);
	251	if (fun->mchip_count >= NAND_MAX_CHIPS) {
	252	dev_err(&ofdev->dev, "too much multiple chips\n");
	253	goto err1;
	254	}
	255	for (i = 0; i < fun->mchip_count; i++)
766f271a	256	fun->mchip_offsets[i] = be32_to_cpu(prop[i]);
b6e0e8c0 WG	257	} else {
	258	fun->mchip_count = 1;
	259	}
	260
	261	for (i = 0; i < fun->mchip_count; i++) {
	262	fun->rnb_gpio[i] = -1;
c8a4d0fd	263	rnb_gpio = of_get_gpio(ofdev->dev.of_node, i);
b6e0e8c0 WG	264	if (rnb_gpio >= 0) {
	265	ret = gpio_request(rnb_gpio, dev_name(&ofdev->dev));
	266	if (ret) {
	267	dev_err(&ofdev->dev,
	268	"can't request RNB gpio #%d\n", i);
	269	goto err2;
	270	}
	271	gpio_direction_input(rnb_gpio);
	272	fun->rnb_gpio[i] = rnb_gpio;
	273	} else if (rnb_gpio == -EINVAL) {
	274	dev_err(&ofdev->dev, "RNB gpio #%d is invalid\n", i);
5c249c5a AV	275	goto err2;
5c249c5a AV	276	}
5c249c5a AV	277	}
5c249c5a AV	278
c8a4d0fd	279	prop = of_get_property(ofdev->dev.of_node, "chip-delay", NULL);
13f53697	280	if (prop)
766f271a	281	fun->chip_delay = be32_to_cpup(prop);
13f53697 WG	282	else
	283	fun->chip_delay = 50;
	284
c8a4d0fd	285	prop = of_get_property(ofdev->dev.of_node, "fsl,upm-wait-flags", &size);
ade92a63	286	if (prop && size == sizeof(uint32_t))
766f271a	287	fun->wait_flags = be32_to_cpup(prop);
ade92a63 WG	288	else
	289	fun->wait_flags = FSL_UPM_WAIT_RUN_PATTERN \|
	290	FSL_UPM_WAIT_WRITE_BYTE;
	291
5c249c5a	292	fun->io_base = devm_ioremap_nocache(&ofdev->dev, io_res.start,
58e6a84d	293	resource_size(&io_res));
5c249c5a AV	294	if (!fun->io_base) {
	295	ret = -ENOMEM;
	296	goto err2;
	297	}
	298
	299	fun->dev = &ofdev->dev;
	300	fun->last_ctrl = NAND_CLE;
5c249c5a	301
c8a4d0fd	302	ret = fun_chip_init(fun, ofdev->dev.of_node, &io_res);
5c249c5a AV	303	if (ret)
	304	goto err2;
	305
	306	dev_set_drvdata(&ofdev->dev, fun);
	307
	308	return 0;
	309	err2:
b6e0e8c0 WG	310	for (i = 0; i < fun->mchip_count; i++) {
	311	if (fun->rnb_gpio[i] < 0)
	312	break;
	313	gpio_free(fun->rnb_gpio[i]);
	314	}
5c249c5a AV	315	err1:
	316	kfree(fun);
	317
	318	return ret;
	319	}
	320
810b7e06	321	static int fun_remove(struct platform_device *ofdev)
5c249c5a AV	322	{
5c249c5a AV	323	struct fsl_upm_nand *fun = dev_get_drvdata(&ofdev->dev);
b6e0e8c0	324	int i;
5c249c5a AV	325
5c249c5a AV	326	nand_release(&fun->mtd);
95ebffd7	327	kfree(fun->mtd.name);
5c249c5a	328
b6e0e8c0 WG	329	for (i = 0; i < fun->mchip_count; i++) {
	330	if (fun->rnb_gpio[i] < 0)
	331	break;
	332	gpio_free(fun->rnb_gpio[i]);
	333	}
5c249c5a AV	334
	335	kfree(fun);
	336
	337	return 0;
	338	}
	339
b2d4fbab	340	static const struct of_device_id of_fun_match[] = {
5c249c5a AV	341	{ .compatible = "fsl,upm-nand" },
	342	{},
	343	};
	344	MODULE_DEVICE_TABLE(of, of_fun_match);
	345
1c48a5c9	346	static struct platform_driver of_fun_driver = {
4018294b GL	347	.driver = {
	348	.name = "fsl,upm-nand",
	349	.owner = THIS_MODULE,
	350	.of_match_table = of_fun_match,
	351	},
5c249c5a	352	.probe = fun_probe,
5153b88c	353	.remove = fun_remove,
5c249c5a AV	354	};
5c249c5a AV	355
f99640de	356	module_platform_driver(of_fun_driver);
5c249c5a AV	357
	358	MODULE_LICENSE("GPL");
	359	MODULE_AUTHOR("Anton Vorontsov <avorontsov@ru.mvista.com>");
	360	MODULE_DESCRIPTION("Driver for NAND chips working through Freescale "
	361	"LocalBus User-Programmable Machine");