Commit | Line | Data |
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5c249c5a AV |
1 | /* |
2 | * Freescale UPM NAND driver. | |
3 | * | |
4 | * Copyright © 2007-2008 MontaVista Software, Inc. | |
5 | * | |
6 | * Author: Anton Vorontsov <avorontsov@ru.mvista.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/module.h> | |
13f53697 | 16 | #include <linux/delay.h> |
5c249c5a AV |
17 | #include <linux/mtd/nand.h> |
18 | #include <linux/mtd/nand_ecc.h> | |
19 | #include <linux/mtd/partitions.h> | |
20 | #include <linux/mtd/mtd.h> | |
21 | #include <linux/of_platform.h> | |
22 | #include <linux/of_gpio.h> | |
23 | #include <linux/io.h> | |
5a0e3ad6 | 24 | #include <linux/slab.h> |
5c249c5a AV |
25 | #include <asm/fsl_lbc.h> |
26 | ||
ade92a63 WG |
27 | #define FSL_UPM_WAIT_RUN_PATTERN 0x1 |
28 | #define FSL_UPM_WAIT_WRITE_BYTE 0x2 | |
29 | #define FSL_UPM_WAIT_WRITE_BUFFER 0x4 | |
30 | ||
5c249c5a AV |
31 | struct fsl_upm_nand { |
32 | struct device *dev; | |
33 | struct mtd_info mtd; | |
34 | struct nand_chip chip; | |
35 | int last_ctrl; | |
5c249c5a | 36 | struct mtd_partition *parts; |
5c249c5a AV |
37 | struct fsl_upm upm; |
38 | uint8_t upm_addr_offset; | |
39 | uint8_t upm_cmd_offset; | |
40 | void __iomem *io_base; | |
b6e0e8c0 WG |
41 | int rnb_gpio[NAND_MAX_CHIPS]; |
42 | uint32_t mchip_offsets[NAND_MAX_CHIPS]; | |
43 | uint32_t mchip_count; | |
44 | uint32_t mchip_number; | |
13f53697 | 45 | int chip_delay; |
ade92a63 | 46 | uint32_t wait_flags; |
5c249c5a AV |
47 | }; |
48 | ||
b92b5c41 FW |
49 | static inline struct fsl_upm_nand *to_fsl_upm_nand(struct mtd_info *mtdinfo) |
50 | { | |
51 | return container_of(mtdinfo, struct fsl_upm_nand, mtd); | |
52 | } | |
5c249c5a AV |
53 | |
54 | static int fun_chip_ready(struct mtd_info *mtd) | |
55 | { | |
56 | struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd); | |
57 | ||
b6e0e8c0 | 58 | if (gpio_get_value(fun->rnb_gpio[fun->mchip_number])) |
5c249c5a AV |
59 | return 1; |
60 | ||
61 | dev_vdbg(fun->dev, "busy\n"); | |
62 | return 0; | |
63 | } | |
64 | ||
65 | static void fun_wait_rnb(struct fsl_upm_nand *fun) | |
66 | { | |
b6e0e8c0 WG |
67 | if (fun->rnb_gpio[fun->mchip_number] >= 0) { |
68 | int cnt = 1000000; | |
5c249c5a | 69 | |
5c249c5a AV |
70 | while (--cnt && !fun_chip_ready(&fun->mtd)) |
71 | cpu_relax(); | |
13f53697 WG |
72 | if (!cnt) |
73 | dev_err(fun->dev, "tired waiting for RNB\n"); | |
74 | } else { | |
75 | ndelay(100); | |
5c249c5a | 76 | } |
5c249c5a AV |
77 | } |
78 | ||
79 | static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) | |
80 | { | |
b6e0e8c0 | 81 | struct nand_chip *chip = mtd->priv; |
5c249c5a | 82 | struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd); |
b6e0e8c0 | 83 | u32 mar; |
5c249c5a AV |
84 | |
85 | if (!(ctrl & fun->last_ctrl)) { | |
86 | fsl_upm_end_pattern(&fun->upm); | |
87 | ||
88 | if (cmd == NAND_CMD_NONE) | |
89 | return; | |
90 | ||
91 | fun->last_ctrl = ctrl & (NAND_ALE | NAND_CLE); | |
92 | } | |
93 | ||
94 | if (ctrl & NAND_CTRL_CHANGE) { | |
95 | if (ctrl & NAND_ALE) | |
96 | fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset); | |
97 | else if (ctrl & NAND_CLE) | |
98 | fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset); | |
99 | } | |
100 | ||
b6e0e8c0 WG |
101 | mar = (cmd << (32 - fun->upm.width)) | |
102 | fun->mchip_offsets[fun->mchip_number]; | |
103 | fsl_upm_run_pattern(&fun->upm, chip->IO_ADDR_R, mar); | |
5c249c5a | 104 | |
ade92a63 WG |
105 | if (fun->wait_flags & FSL_UPM_WAIT_RUN_PATTERN) |
106 | fun_wait_rnb(fun); | |
5c249c5a AV |
107 | } |
108 | ||
b6e0e8c0 WG |
109 | static void fun_select_chip(struct mtd_info *mtd, int mchip_nr) |
110 | { | |
111 | struct nand_chip *chip = mtd->priv; | |
112 | struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd); | |
113 | ||
114 | if (mchip_nr == -1) { | |
115 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); | |
35016dd7 | 116 | } else if (mchip_nr >= 0 && mchip_nr < NAND_MAX_CHIPS) { |
b6e0e8c0 WG |
117 | fun->mchip_number = mchip_nr; |
118 | chip->IO_ADDR_R = fun->io_base + fun->mchip_offsets[mchip_nr]; | |
119 | chip->IO_ADDR_W = chip->IO_ADDR_R; | |
120 | } else { | |
121 | BUG(); | |
122 | } | |
123 | } | |
124 | ||
5c249c5a AV |
125 | static uint8_t fun_read_byte(struct mtd_info *mtd) |
126 | { | |
127 | struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd); | |
128 | ||
129 | return in_8(fun->chip.IO_ADDR_R); | |
130 | } | |
131 | ||
132 | static void fun_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) | |
133 | { | |
134 | struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd); | |
135 | int i; | |
136 | ||
137 | for (i = 0; i < len; i++) | |
138 | buf[i] = in_8(fun->chip.IO_ADDR_R); | |
139 | } | |
140 | ||
141 | static void fun_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) | |
142 | { | |
143 | struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd); | |
144 | int i; | |
145 | ||
146 | for (i = 0; i < len; i++) { | |
147 | out_8(fun->chip.IO_ADDR_W, buf[i]); | |
ade92a63 WG |
148 | if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BYTE) |
149 | fun_wait_rnb(fun); | |
5c249c5a | 150 | } |
ade92a63 WG |
151 | if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BUFFER) |
152 | fun_wait_rnb(fun); | |
5c249c5a AV |
153 | } |
154 | ||
95ebffd7 AV |
155 | static int __devinit fun_chip_init(struct fsl_upm_nand *fun, |
156 | const struct device_node *upm_np, | |
157 | const struct resource *io_res) | |
5c249c5a AV |
158 | { |
159 | int ret; | |
95ebffd7 | 160 | struct device_node *flash_np; |
5c249c5a | 161 | static const char *part_types[] = { "cmdlinepart", NULL, }; |
5c249c5a AV |
162 | |
163 | fun->chip.IO_ADDR_R = fun->io_base; | |
164 | fun->chip.IO_ADDR_W = fun->io_base; | |
165 | fun->chip.cmd_ctrl = fun_cmd_ctrl; | |
13f53697 | 166 | fun->chip.chip_delay = fun->chip_delay; |
5c249c5a AV |
167 | fun->chip.read_byte = fun_read_byte; |
168 | fun->chip.read_buf = fun_read_buf; | |
169 | fun->chip.write_buf = fun_write_buf; | |
170 | fun->chip.ecc.mode = NAND_ECC_SOFT; | |
b6e0e8c0 WG |
171 | if (fun->mchip_count > 1) |
172 | fun->chip.select_chip = fun_select_chip; | |
5c249c5a | 173 | |
b6e0e8c0 | 174 | if (fun->rnb_gpio[0] >= 0) |
5c249c5a AV |
175 | fun->chip.dev_ready = fun_chip_ready; |
176 | ||
177 | fun->mtd.priv = &fun->chip; | |
178 | fun->mtd.owner = THIS_MODULE; | |
179 | ||
95ebffd7 AV |
180 | flash_np = of_get_next_child(upm_np, NULL); |
181 | if (!flash_np) | |
182 | return -ENODEV; | |
183 | ||
0eecf4b2 | 184 | fun->mtd.name = kasprintf(GFP_KERNEL, "0x%llx.%s", (u64)io_res->start, |
95ebffd7 AV |
185 | flash_np->name); |
186 | if (!fun->mtd.name) { | |
187 | ret = -ENOMEM; | |
188 | goto err; | |
189 | } | |
190 | ||
b6e0e8c0 | 191 | ret = nand_scan(&fun->mtd, fun->mchip_count); |
5c249c5a | 192 | if (ret) |
95ebffd7 | 193 | goto err; |
5c249c5a | 194 | |
5c249c5a | 195 | ret = parse_mtd_partitions(&fun->mtd, part_types, &fun->parts, 0); |
95ebffd7 AV |
196 | |
197 | #ifdef CONFIG_MTD_OF_PARTS | |
29b65861 WG |
198 | if (ret == 0) { |
199 | ret = of_mtd_parse_partitions(fun->dev, flash_np, &fun->parts); | |
200 | if (ret < 0) | |
201 | goto err; | |
202 | } | |
95ebffd7 | 203 | #endif |
13c41db9 | 204 | ret = mtd_device_register(&fun->mtd, fun->parts, ret); |
95ebffd7 AV |
205 | err: |
206 | of_node_put(flash_np); | |
207 | return ret; | |
5c249c5a AV |
208 | } |
209 | ||
1c48a5c9 | 210 | static int __devinit fun_probe(struct platform_device *ofdev) |
5c249c5a AV |
211 | { |
212 | struct fsl_upm_nand *fun; | |
213 | struct resource io_res; | |
766f271a | 214 | const __be32 *prop; |
b6e0e8c0 | 215 | int rnb_gpio; |
5c249c5a AV |
216 | int ret; |
217 | int size; | |
b6e0e8c0 | 218 | int i; |
5c249c5a AV |
219 | |
220 | fun = kzalloc(sizeof(*fun), GFP_KERNEL); | |
221 | if (!fun) | |
222 | return -ENOMEM; | |
223 | ||
c8a4d0fd | 224 | ret = of_address_to_resource(ofdev->dev.of_node, 0, &io_res); |
5c249c5a AV |
225 | if (ret) { |
226 | dev_err(&ofdev->dev, "can't get IO base\n"); | |
227 | goto err1; | |
228 | } | |
229 | ||
230 | ret = fsl_upm_find(io_res.start, &fun->upm); | |
231 | if (ret) { | |
232 | dev_err(&ofdev->dev, "can't find UPM\n"); | |
233 | goto err1; | |
234 | } | |
235 | ||
c8a4d0fd AG |
236 | prop = of_get_property(ofdev->dev.of_node, "fsl,upm-addr-offset", |
237 | &size); | |
5c249c5a AV |
238 | if (!prop || size != sizeof(uint32_t)) { |
239 | dev_err(&ofdev->dev, "can't get UPM address offset\n"); | |
240 | ret = -EINVAL; | |
b6e0e8c0 | 241 | goto err1; |
5c249c5a AV |
242 | } |
243 | fun->upm_addr_offset = *prop; | |
244 | ||
c8a4d0fd | 245 | prop = of_get_property(ofdev->dev.of_node, "fsl,upm-cmd-offset", &size); |
5c249c5a AV |
246 | if (!prop || size != sizeof(uint32_t)) { |
247 | dev_err(&ofdev->dev, "can't get UPM command offset\n"); | |
248 | ret = -EINVAL; | |
b6e0e8c0 | 249 | goto err1; |
5c249c5a AV |
250 | } |
251 | fun->upm_cmd_offset = *prop; | |
252 | ||
c8a4d0fd | 253 | prop = of_get_property(ofdev->dev.of_node, |
b6e0e8c0 WG |
254 | "fsl,upm-addr-line-cs-offsets", &size); |
255 | if (prop && (size / sizeof(uint32_t)) > 0) { | |
256 | fun->mchip_count = size / sizeof(uint32_t); | |
257 | if (fun->mchip_count >= NAND_MAX_CHIPS) { | |
258 | dev_err(&ofdev->dev, "too much multiple chips\n"); | |
259 | goto err1; | |
260 | } | |
261 | for (i = 0; i < fun->mchip_count; i++) | |
766f271a | 262 | fun->mchip_offsets[i] = be32_to_cpu(prop[i]); |
b6e0e8c0 WG |
263 | } else { |
264 | fun->mchip_count = 1; | |
265 | } | |
266 | ||
267 | for (i = 0; i < fun->mchip_count; i++) { | |
268 | fun->rnb_gpio[i] = -1; | |
c8a4d0fd | 269 | rnb_gpio = of_get_gpio(ofdev->dev.of_node, i); |
b6e0e8c0 WG |
270 | if (rnb_gpio >= 0) { |
271 | ret = gpio_request(rnb_gpio, dev_name(&ofdev->dev)); | |
272 | if (ret) { | |
273 | dev_err(&ofdev->dev, | |
274 | "can't request RNB gpio #%d\n", i); | |
275 | goto err2; | |
276 | } | |
277 | gpio_direction_input(rnb_gpio); | |
278 | fun->rnb_gpio[i] = rnb_gpio; | |
279 | } else if (rnb_gpio == -EINVAL) { | |
280 | dev_err(&ofdev->dev, "RNB gpio #%d is invalid\n", i); | |
5c249c5a AV |
281 | goto err2; |
282 | } | |
5c249c5a AV |
283 | } |
284 | ||
c8a4d0fd | 285 | prop = of_get_property(ofdev->dev.of_node, "chip-delay", NULL); |
13f53697 | 286 | if (prop) |
766f271a | 287 | fun->chip_delay = be32_to_cpup(prop); |
13f53697 WG |
288 | else |
289 | fun->chip_delay = 50; | |
290 | ||
c8a4d0fd | 291 | prop = of_get_property(ofdev->dev.of_node, "fsl,upm-wait-flags", &size); |
ade92a63 | 292 | if (prop && size == sizeof(uint32_t)) |
766f271a | 293 | fun->wait_flags = be32_to_cpup(prop); |
ade92a63 WG |
294 | else |
295 | fun->wait_flags = FSL_UPM_WAIT_RUN_PATTERN | | |
296 | FSL_UPM_WAIT_WRITE_BYTE; | |
297 | ||
5c249c5a | 298 | fun->io_base = devm_ioremap_nocache(&ofdev->dev, io_res.start, |
58e6a84d | 299 | resource_size(&io_res)); |
5c249c5a AV |
300 | if (!fun->io_base) { |
301 | ret = -ENOMEM; | |
302 | goto err2; | |
303 | } | |
304 | ||
305 | fun->dev = &ofdev->dev; | |
306 | fun->last_ctrl = NAND_CLE; | |
5c249c5a | 307 | |
c8a4d0fd | 308 | ret = fun_chip_init(fun, ofdev->dev.of_node, &io_res); |
5c249c5a AV |
309 | if (ret) |
310 | goto err2; | |
311 | ||
312 | dev_set_drvdata(&ofdev->dev, fun); | |
313 | ||
314 | return 0; | |
315 | err2: | |
b6e0e8c0 WG |
316 | for (i = 0; i < fun->mchip_count; i++) { |
317 | if (fun->rnb_gpio[i] < 0) | |
318 | break; | |
319 | gpio_free(fun->rnb_gpio[i]); | |
320 | } | |
5c249c5a AV |
321 | err1: |
322 | kfree(fun); | |
323 | ||
324 | return ret; | |
325 | } | |
326 | ||
2dc11581 | 327 | static int __devexit fun_remove(struct platform_device *ofdev) |
5c249c5a AV |
328 | { |
329 | struct fsl_upm_nand *fun = dev_get_drvdata(&ofdev->dev); | |
b6e0e8c0 | 330 | int i; |
5c249c5a AV |
331 | |
332 | nand_release(&fun->mtd); | |
95ebffd7 | 333 | kfree(fun->mtd.name); |
5c249c5a | 334 | |
b6e0e8c0 WG |
335 | for (i = 0; i < fun->mchip_count; i++) { |
336 | if (fun->rnb_gpio[i] < 0) | |
337 | break; | |
338 | gpio_free(fun->rnb_gpio[i]); | |
339 | } | |
5c249c5a AV |
340 | |
341 | kfree(fun); | |
342 | ||
343 | return 0; | |
344 | } | |
345 | ||
b2d4fbab | 346 | static const struct of_device_id of_fun_match[] = { |
5c249c5a AV |
347 | { .compatible = "fsl,upm-nand" }, |
348 | {}, | |
349 | }; | |
350 | MODULE_DEVICE_TABLE(of, of_fun_match); | |
351 | ||
1c48a5c9 | 352 | static struct platform_driver of_fun_driver = { |
4018294b GL |
353 | .driver = { |
354 | .name = "fsl,upm-nand", | |
355 | .owner = THIS_MODULE, | |
356 | .of_match_table = of_fun_match, | |
357 | }, | |
5c249c5a AV |
358 | .probe = fun_probe, |
359 | .remove = __devexit_p(fun_remove), | |
360 | }; | |
361 | ||
362 | static int __init fun_module_init(void) | |
363 | { | |
1c48a5c9 | 364 | return platform_driver_register(&of_fun_driver); |
5c249c5a AV |
365 | } |
366 | module_init(fun_module_init); | |
367 | ||
368 | static void __exit fun_module_exit(void) | |
369 | { | |
1c48a5c9 | 370 | platform_driver_unregister(&of_fun_driver); |
5c249c5a AV |
371 | } |
372 | module_exit(fun_module_exit); | |
373 | ||
374 | MODULE_LICENSE("GPL"); | |
375 | MODULE_AUTHOR("Anton Vorontsov <avorontsov@ru.mvista.com>"); | |
376 | MODULE_DESCRIPTION("Driver for NAND chips working through Freescale " | |
377 | "LocalBus User-Programmable Machine"); |