[deliverable/linux.git] / drivers / mtd / nand / fsl_upm.c

/*
 * Freescale UPM NAND driver.
 *
 * Copyright © 2007-2008  MontaVista Software, Inc.
 *
 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/mtd.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/of_gpio.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <asm/fsl_lbc.h>

#define FSL_UPM_WAIT_RUN_PATTERN  0x1
#define FSL_UPM_WAIT_WRITE_BYTE   0x2
#define FSL_UPM_WAIT_WRITE_BUFFER 0x4

struct fsl_upm_nand {
	struct device *dev;
	struct nand_chip chip;
	int last_ctrl;
	struct mtd_partition *parts;
	struct fsl_upm upm;
	uint8_t upm_addr_offset;
	uint8_t upm_cmd_offset;
	void __iomem *io_base;
	int rnb_gpio[NAND_MAX_CHIPS];
	uint32_t mchip_offsets[NAND_MAX_CHIPS];
	uint32_t mchip_count;
	uint32_t mchip_number;
	int chip_delay;
	uint32_t wait_flags;
};

static inline struct fsl_upm_nand *to_fsl_upm_nand(struct mtd_info *mtdinfo)
{
	return container_of(mtd_to_nand(mtdinfo), struct fsl_upm_nand,
			    chip);
}

static int fun_chip_ready(struct mtd_info *mtd)
{
	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);

	if (gpio_get_value(fun->rnb_gpio[fun->mchip_number]))
		return 1;

	dev_vdbg(fun->dev, "busy\n");
	return 0;
}

static void fun_wait_rnb(struct fsl_upm_nand *fun)
{
	if (fun->rnb_gpio[fun->mchip_number] >= 0) {
		struct mtd_info *mtd = nand_to_mtd(&fun->chip);
		int cnt = 1000000;

		while (--cnt && !fun_chip_ready(mtd))
			cpu_relax();
		if (!cnt)
			dev_err(fun->dev, "tired waiting for RNB\n");
	} else {
		ndelay(100);
	}
}

static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
	struct nand_chip *chip = mtd_to_nand(mtd);
	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
	u32 mar;

	if (!(ctrl & fun->last_ctrl)) {
		fsl_upm_end_pattern(&fun->upm);

		if (cmd == NAND_CMD_NONE)
			return;

		fun->last_ctrl = ctrl & (NAND_ALE | NAND_CLE);
	}

	if (ctrl & NAND_CTRL_CHANGE) {
		if (ctrl & NAND_ALE)
			fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
		else if (ctrl & NAND_CLE)
			fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
	}

	mar = (cmd << (32 - fun->upm.width)) |
		fun->mchip_offsets[fun->mchip_number];
	fsl_upm_run_pattern(&fun->upm, chip->IO_ADDR_R, mar);

	if (fun->wait_flags & FSL_UPM_WAIT_RUN_PATTERN)
		fun_wait_rnb(fun);
}

static void fun_select_chip(struct mtd_info *mtd, int mchip_nr)
{
	struct nand_chip *chip = mtd_to_nand(mtd);
	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);

	if (mchip_nr == -1) {
		chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
	} else if (mchip_nr >= 0 && mchip_nr < NAND_MAX_CHIPS) {
		fun->mchip_number = mchip_nr;
		chip->IO_ADDR_R = fun->io_base + fun->mchip_offsets[mchip_nr];
		chip->IO_ADDR_W = chip->IO_ADDR_R;
	} else {
		BUG();
	}
}

static uint8_t fun_read_byte(struct mtd_info *mtd)
{
	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);

	return in_8(fun->chip.IO_ADDR_R);
}

static void fun_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
{
	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
	int i;

	for (i = 0; i < len; i++)
		buf[i] = in_8(fun->chip.IO_ADDR_R);
}

static void fun_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
{
	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
	int i;

	for (i = 0; i < len; i++) {
		out_8(fun->chip.IO_ADDR_W, buf[i]);
		if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BYTE)
			fun_wait_rnb(fun);
	}
	if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BUFFER)
		fun_wait_rnb(fun);
}

static int fun_chip_init(struct fsl_upm_nand *fun,
			 const struct device_node *upm_np,
			 const struct resource *io_res)
{
	struct mtd_info *mtd = nand_to_mtd(&fun->chip);
	int ret;
	struct device_node *flash_np;

	fun->chip.IO_ADDR_R = fun->io_base;
	fun->chip.IO_ADDR_W = fun->io_base;
	fun->chip.cmd_ctrl = fun_cmd_ctrl;
	fun->chip.chip_delay = fun->chip_delay;
	fun->chip.read_byte = fun_read_byte;
	fun->chip.read_buf = fun_read_buf;
	fun->chip.write_buf = fun_write_buf;
	fun->chip.ecc.mode = NAND_ECC_SOFT;
	fun->chip.ecc.algo = NAND_ECC_HAMMING;
	if (fun->mchip_count > 1)
		fun->chip.select_chip = fun_select_chip;

	if (fun->rnb_gpio[0] >= 0)
		fun->chip.dev_ready = fun_chip_ready;

	mtd->dev.parent = fun->dev;

	flash_np = of_get_next_child(upm_np, NULL);
	if (!flash_np)
		return -ENODEV;

	nand_set_flash_node(&fun->chip, flash_np);
	mtd->name = kasprintf(GFP_KERNEL, "0x%llx.%s", (u64)io_res->start,
			      flash_np->name);
	if (!mtd->name) {
		ret = -ENOMEM;
		goto err;
	}

	ret = nand_scan(mtd, fun->mchip_count);
	if (ret)
		goto err;

	ret = mtd_device_register(mtd, NULL, 0);
err:
	of_node_put(flash_np);
	if (ret)
		kfree(mtd->name);
	return ret;
}

static int fun_probe(struct platform_device *ofdev)
{
	struct fsl_upm_nand *fun;
	struct resource io_res;
	const __be32 *prop;
	int rnb_gpio;
	int ret;
	int size;
	int i;

	fun = kzalloc(sizeof(*fun), GFP_KERNEL);
	if (!fun)
		return -ENOMEM;

	ret = of_address_to_resource(ofdev->dev.of_node, 0, &io_res);
	if (ret) {
		dev_err(&ofdev->dev, "can't get IO base\n");
		goto err1;
	}

	ret = fsl_upm_find(io_res.start, &fun->upm);
	if (ret) {
		dev_err(&ofdev->dev, "can't find UPM\n");
		goto err1;
	}

	prop = of_get_property(ofdev->dev.of_node, "fsl,upm-addr-offset",
			       &size);
	if (!prop || size != sizeof(uint32_t)) {
		dev_err(&ofdev->dev, "can't get UPM address offset\n");
		ret = -EINVAL;
		goto err1;
	}
	fun->upm_addr_offset = *prop;

	prop = of_get_property(ofdev->dev.of_node, "fsl,upm-cmd-offset", &size);
	if (!prop || size != sizeof(uint32_t)) {
		dev_err(&ofdev->dev, "can't get UPM command offset\n");
		ret = -EINVAL;
		goto err1;
	}
	fun->upm_cmd_offset = *prop;

	prop = of_get_property(ofdev->dev.of_node,
			       "fsl,upm-addr-line-cs-offsets", &size);
	if (prop && (size / sizeof(uint32_t)) > 0) {
		fun->mchip_count = size / sizeof(uint32_t);
		if (fun->mchip_count >= NAND_MAX_CHIPS) {
			dev_err(&ofdev->dev, "too much multiple chips\n");
			goto err1;
		}
		for (i = 0; i < fun->mchip_count; i++)
			fun->mchip_offsets[i] = be32_to_cpu(prop[i]);
	} else {
		fun->mchip_count = 1;
	}

	for (i = 0; i < fun->mchip_count; i++) {
		fun->rnb_gpio[i] = -1;
		rnb_gpio = of_get_gpio(ofdev->dev.of_node, i);
		if (rnb_gpio >= 0) {
			ret = gpio_request(rnb_gpio, dev_name(&ofdev->dev));
			if (ret) {
				dev_err(&ofdev->dev,
					"can't request RNB gpio #%d\n", i);
				goto err2;
			}
			gpio_direction_input(rnb_gpio);
			fun->rnb_gpio[i] = rnb_gpio;
		} else if (rnb_gpio == -EINVAL) {
			dev_err(&ofdev->dev, "RNB gpio #%d is invalid\n", i);
			goto err2;
		}
	}

	prop = of_get_property(ofdev->dev.of_node, "chip-delay", NULL);
	if (prop)
		fun->chip_delay = be32_to_cpup(prop);
	else
		fun->chip_delay = 50;

	prop = of_get_property(ofdev->dev.of_node, "fsl,upm-wait-flags", &size);
	if (prop && size == sizeof(uint32_t))
		fun->wait_flags = be32_to_cpup(prop);
	else
		fun->wait_flags = FSL_UPM_WAIT_RUN_PATTERN |
				  FSL_UPM_WAIT_WRITE_BYTE;

	fun->io_base = devm_ioremap_nocache(&ofdev->dev, io_res.start,
					    resource_size(&io_res));
	if (!fun->io_base) {
		ret = -ENOMEM;
		goto err2;
	}

	fun->dev = &ofdev->dev;
	fun->last_ctrl = NAND_CLE;

	ret = fun_chip_init(fun, ofdev->dev.of_node, &io_res);
	if (ret)
		goto err2;

	dev_set_drvdata(&ofdev->dev, fun);

	return 0;
err2:
	for (i = 0; i < fun->mchip_count; i++) {
		if (fun->rnb_gpio[i] < 0)
			break;
		gpio_free(fun->rnb_gpio[i]);
	}
err1:
	kfree(fun);

	return ret;
}

static int fun_remove(struct platform_device *ofdev)
{
	struct fsl_upm_nand *fun = dev_get_drvdata(&ofdev->dev);
	struct mtd_info *mtd = nand_to_mtd(&fun->chip);
	int i;

	nand_release(mtd);
	kfree(mtd->name);

	for (i = 0; i < fun->mchip_count; i++) {
		if (fun->rnb_gpio[i] < 0)
			break;
		gpio_free(fun->rnb_gpio[i]);
	}

	kfree(fun);

	return 0;
}

static const struct of_device_id of_fun_match[] = {
	{ .compatible = "fsl,upm-nand" },
	{},
};
MODULE_DEVICE_TABLE(of, of_fun_match);

static struct platform_driver of_fun_driver = {
	.driver = {
		.name = "fsl,upm-nand",
		.of_match_table = of_fun_match,
	},
	.probe		= fun_probe,
	.remove		= fun_remove,
};

module_platform_driver(of_fun_driver);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Anton Vorontsov <avorontsov@ru.mvista.com>");
MODULE_DESCRIPTION("Driver for NAND chips working through Freescale "
		   "LocalBus User-Programmable Machine");
Commit	Line	Data
5c249c5a AV	1	/*
	2	* Freescale UPM NAND driver.
	3	*
	4	* Copyright © 2007-2008 MontaVista Software, Inc.
	5	*
	6	* Author: Anton Vorontsov <avorontsov@ru.mvista.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/module.h>
13f53697	16	#include <linux/delay.h>
5c249c5a AV	17	#include <linux/mtd/nand.h>
	18	#include <linux/mtd/nand_ecc.h>
	19	#include <linux/mtd/partitions.h>
	20	#include <linux/mtd/mtd.h>
5af50730	21	#include <linux/of_address.h>
5c249c5a AV	22	#include <linux/of_platform.h>
	23	#include <linux/of_gpio.h>
	24	#include <linux/io.h>
5a0e3ad6	25	#include <linux/slab.h>
5c249c5a AV	26	#include <asm/fsl_lbc.h>
5c249c5a AV	27
ade92a63 WG	28	#define FSL_UPM_WAIT_RUN_PATTERN 0x1
	29	#define FSL_UPM_WAIT_WRITE_BYTE 0x2
	30	#define FSL_UPM_WAIT_WRITE_BUFFER 0x4
	31
5c249c5a AV	32	struct fsl_upm_nand {
5c249c5a AV	33	struct device *dev;
5c249c5a AV	34	struct nand_chip chip;
5c249c5a AV	35	int last_ctrl;
5c249c5a	36	struct mtd_partition *parts;
5c249c5a AV	37	struct fsl_upm upm;
	38	uint8_t upm_addr_offset;
	39	uint8_t upm_cmd_offset;
	40	void __iomem *io_base;
b6e0e8c0 WG	41	int rnb_gpio[NAND_MAX_CHIPS];
	42	uint32_t mchip_offsets[NAND_MAX_CHIPS];
	43	uint32_t mchip_count;
	44	uint32_t mchip_number;
13f53697	45	int chip_delay;
ade92a63	46	uint32_t wait_flags;
5c249c5a AV	47	};
5c249c5a AV	48
b92b5c41 FW	49	static inline struct fsl_upm_nand to_fsl_upm_nand(struct mtd_info mtdinfo)
b92b5c41 FW	50	{
478d51f0 BB	51	return container_of(mtd_to_nand(mtdinfo), struct fsl_upm_nand,
478d51f0 BB	52	chip);
b92b5c41	53	}
5c249c5a AV	54
	55	static int fun_chip_ready(struct mtd_info *mtd)
	56	{
	57	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
	58
b6e0e8c0	59	if (gpio_get_value(fun->rnb_gpio[fun->mchip_number]))
5c249c5a AV	60	return 1;
	61
	62	dev_vdbg(fun->dev, "busy\n");
	63	return 0;
	64	}
	65
	66	static void fun_wait_rnb(struct fsl_upm_nand *fun)
	67	{
b6e0e8c0	68	if (fun->rnb_gpio[fun->mchip_number] >= 0) {
478d51f0	69	struct mtd_info *mtd = nand_to_mtd(&fun->chip);
b6e0e8c0	70	int cnt = 1000000;
5c249c5a	71
478d51f0	72	while (--cnt && !fun_chip_ready(mtd))
5c249c5a	73	cpu_relax();
13f53697 WG	74	if (!cnt)
	75	dev_err(fun->dev, "tired waiting for RNB\n");
	76	} else {
	77	ndelay(100);
5c249c5a	78	}
5c249c5a AV	79	}
	80
	81	static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
	82	{
4bd4ebcc	83	struct nand_chip *chip = mtd_to_nand(mtd);
5c249c5a	84	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
b6e0e8c0	85	u32 mar;
5c249c5a AV	86
	87	if (!(ctrl & fun->last_ctrl)) {
	88	fsl_upm_end_pattern(&fun->upm);
	89
	90	if (cmd == NAND_CMD_NONE)
	91	return;
	92
	93	fun->last_ctrl = ctrl & (NAND_ALE \| NAND_CLE);
	94	}
	95
	96	if (ctrl & NAND_CTRL_CHANGE) {
	97	if (ctrl & NAND_ALE)
	98	fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
	99	else if (ctrl & NAND_CLE)
	100	fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
	101	}
	102
b6e0e8c0 WG	103	mar = (cmd << (32 - fun->upm.width)) \|
	104	fun->mchip_offsets[fun->mchip_number];
	105	fsl_upm_run_pattern(&fun->upm, chip->IO_ADDR_R, mar);
5c249c5a	106
ade92a63 WG	107	if (fun->wait_flags & FSL_UPM_WAIT_RUN_PATTERN)
ade92a63 WG	108	fun_wait_rnb(fun);
5c249c5a AV	109	}
5c249c5a AV	110
b6e0e8c0 WG	111	static void fun_select_chip(struct mtd_info *mtd, int mchip_nr)
b6e0e8c0 WG	112	{
4bd4ebcc	113	struct nand_chip *chip = mtd_to_nand(mtd);
b6e0e8c0 WG	114	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
	115
	116	if (mchip_nr == -1) {
	117	chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 \| NAND_CTRL_CHANGE);
35016dd7	118	} else if (mchip_nr >= 0 && mchip_nr < NAND_MAX_CHIPS) {
b6e0e8c0 WG	119	fun->mchip_number = mchip_nr;
	120	chip->IO_ADDR_R = fun->io_base + fun->mchip_offsets[mchip_nr];
	121	chip->IO_ADDR_W = chip->IO_ADDR_R;
	122	} else {
	123	BUG();
	124	}
	125	}
	126
5c249c5a AV	127	static uint8_t fun_read_byte(struct mtd_info *mtd)
	128	{
	129	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
	130
	131	return in_8(fun->chip.IO_ADDR_R);
	132	}
	133
	134	static void fun_read_buf(struct mtd_info mtd, uint8_t buf, int len)
	135	{
	136	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
	137	int i;
	138
	139	for (i = 0; i < len; i++)
	140	buf[i] = in_8(fun->chip.IO_ADDR_R);
	141	}
	142
	143	static void fun_write_buf(struct mtd_info mtd, const uint8_t buf, int len)
	144	{
	145	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
	146	int i;
	147
	148	for (i = 0; i < len; i++) {
	149	out_8(fun->chip.IO_ADDR_W, buf[i]);
ade92a63 WG	150	if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BYTE)
ade92a63 WG	151	fun_wait_rnb(fun);
5c249c5a	152	}
ade92a63 WG	153	if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BUFFER)
ade92a63 WG	154	fun_wait_rnb(fun);
5c249c5a AV	155	}
5c249c5a AV	156
06f25510	157	static int fun_chip_init(struct fsl_upm_nand *fun,
d8929942 GKH	158	const struct device_node *upm_np,
d8929942 GKH	159	const struct resource *io_res)
5c249c5a	160	{
478d51f0	161	struct mtd_info *mtd = nand_to_mtd(&fun->chip);
5c249c5a	162	int ret;
95ebffd7	163	struct device_node *flash_np;
5c249c5a AV	164
	165	fun->chip.IO_ADDR_R = fun->io_base;
	166	fun->chip.IO_ADDR_W = fun->io_base;
	167	fun->chip.cmd_ctrl = fun_cmd_ctrl;
13f53697	168	fun->chip.chip_delay = fun->chip_delay;
5c249c5a AV	169	fun->chip.read_byte = fun_read_byte;
	170	fun->chip.read_buf = fun_read_buf;
	171	fun->chip.write_buf = fun_write_buf;
	172	fun->chip.ecc.mode = NAND_ECC_SOFT;
ab2f5a80	173	fun->chip.ecc.algo = NAND_ECC_HAMMING;
b6e0e8c0 WG	174	if (fun->mchip_count > 1)
b6e0e8c0 WG	175	fun->chip.select_chip = fun_select_chip;
5c249c5a	176
b6e0e8c0	177	if (fun->rnb_gpio[0] >= 0)
5c249c5a AV	178	fun->chip.dev_ready = fun_chip_ready;
5c249c5a AV	179
478d51f0	180	mtd->dev.parent = fun->dev;
5c249c5a	181
95ebffd7 AV	182	flash_np = of_get_next_child(upm_np, NULL);
	183	if (!flash_np)
	184	return -ENODEV;
	185
a61ae81a	186	nand_set_flash_node(&fun->chip, flash_np);
478d51f0 BB	187	mtd->name = kasprintf(GFP_KERNEL, "0x%llx.%s", (u64)io_res->start,
	188	flash_np->name);
	189	if (!mtd->name) {
95ebffd7 AV	190	ret = -ENOMEM;
	191	goto err;
	192	}
	193
478d51f0	194	ret = nand_scan(mtd, fun->mchip_count);
5c249c5a	195	if (ret)
95ebffd7	196	goto err;
5c249c5a	197
478d51f0	198	ret = mtd_device_register(mtd, NULL, 0);
95ebffd7 AV	199	err:
95ebffd7 AV	200	of_node_put(flash_np);
a751d315	201	if (ret)
478d51f0	202	kfree(mtd->name);
95ebffd7	203	return ret;
5c249c5a AV	204	}
5c249c5a AV	205
06f25510	206	static int fun_probe(struct platform_device *ofdev)
5c249c5a AV	207	{
	208	struct fsl_upm_nand *fun;
	209	struct resource io_res;
766f271a	210	const __be32 *prop;
b6e0e8c0	211	int rnb_gpio;
5c249c5a AV	212	int ret;
5c249c5a AV	213	int size;
b6e0e8c0	214	int i;
5c249c5a AV	215
	216	fun = kzalloc(sizeof(*fun), GFP_KERNEL);
	217	if (!fun)
	218	return -ENOMEM;
	219
c8a4d0fd	220	ret = of_address_to_resource(ofdev->dev.of_node, 0, &io_res);
5c249c5a AV	221	if (ret) {
	222	dev_err(&ofdev->dev, "can't get IO base\n");
	223	goto err1;
	224	}
	225
	226	ret = fsl_upm_find(io_res.start, &fun->upm);
	227	if (ret) {
	228	dev_err(&ofdev->dev, "can't find UPM\n");
	229	goto err1;
	230	}
	231
c8a4d0fd AG	232	prop = of_get_property(ofdev->dev.of_node, "fsl,upm-addr-offset",
c8a4d0fd AG	233	&size);
5c249c5a AV	234	if (!prop \|\| size != sizeof(uint32_t)) {
	235	dev_err(&ofdev->dev, "can't get UPM address offset\n");
	236	ret = -EINVAL;
b6e0e8c0	237	goto err1;
5c249c5a AV	238	}
	239	fun->upm_addr_offset = *prop;
	240
c8a4d0fd	241	prop = of_get_property(ofdev->dev.of_node, "fsl,upm-cmd-offset", &size);
5c249c5a AV	242	if (!prop \|\| size != sizeof(uint32_t)) {
	243	dev_err(&ofdev->dev, "can't get UPM command offset\n");
	244	ret = -EINVAL;
b6e0e8c0	245	goto err1;
5c249c5a AV	246	}
	247	fun->upm_cmd_offset = *prop;
	248
c8a4d0fd	249	prop = of_get_property(ofdev->dev.of_node,
b6e0e8c0 WG	250	"fsl,upm-addr-line-cs-offsets", &size);
	251	if (prop && (size / sizeof(uint32_t)) > 0) {
	252	fun->mchip_count = size / sizeof(uint32_t);
	253	if (fun->mchip_count >= NAND_MAX_CHIPS) {
	254	dev_err(&ofdev->dev, "too much multiple chips\n");
	255	goto err1;
	256	}
	257	for (i = 0; i < fun->mchip_count; i++)
766f271a	258	fun->mchip_offsets[i] = be32_to_cpu(prop[i]);
b6e0e8c0 WG	259	} else {
	260	fun->mchip_count = 1;
	261	}
	262
	263	for (i = 0; i < fun->mchip_count; i++) {
	264	fun->rnb_gpio[i] = -1;
c8a4d0fd	265	rnb_gpio = of_get_gpio(ofdev->dev.of_node, i);
b6e0e8c0 WG	266	if (rnb_gpio >= 0) {
	267	ret = gpio_request(rnb_gpio, dev_name(&ofdev->dev));
	268	if (ret) {
	269	dev_err(&ofdev->dev,
	270	"can't request RNB gpio #%d\n", i);
	271	goto err2;
	272	}
	273	gpio_direction_input(rnb_gpio);
	274	fun->rnb_gpio[i] = rnb_gpio;
	275	} else if (rnb_gpio == -EINVAL) {
	276	dev_err(&ofdev->dev, "RNB gpio #%d is invalid\n", i);
5c249c5a AV	277	goto err2;
5c249c5a AV	278	}
5c249c5a AV	279	}
5c249c5a AV	280
c8a4d0fd	281	prop = of_get_property(ofdev->dev.of_node, "chip-delay", NULL);
13f53697	282	if (prop)
766f271a	283	fun->chip_delay = be32_to_cpup(prop);
13f53697 WG	284	else
	285	fun->chip_delay = 50;
	286
c8a4d0fd	287	prop = of_get_property(ofdev->dev.of_node, "fsl,upm-wait-flags", &size);
ade92a63	288	if (prop && size == sizeof(uint32_t))
766f271a	289	fun->wait_flags = be32_to_cpup(prop);
ade92a63 WG	290	else
	291	fun->wait_flags = FSL_UPM_WAIT_RUN_PATTERN \|
	292	FSL_UPM_WAIT_WRITE_BYTE;
	293
5c249c5a	294	fun->io_base = devm_ioremap_nocache(&ofdev->dev, io_res.start,
58e6a84d	295	resource_size(&io_res));
5c249c5a AV	296	if (!fun->io_base) {
	297	ret = -ENOMEM;
	298	goto err2;
	299	}
	300
	301	fun->dev = &ofdev->dev;
	302	fun->last_ctrl = NAND_CLE;
5c249c5a	303
c8a4d0fd	304	ret = fun_chip_init(fun, ofdev->dev.of_node, &io_res);
5c249c5a AV	305	if (ret)
	306	goto err2;
	307
	308	dev_set_drvdata(&ofdev->dev, fun);
	309
	310	return 0;
	311	err2:
b6e0e8c0 WG	312	for (i = 0; i < fun->mchip_count; i++) {
	313	if (fun->rnb_gpio[i] < 0)
	314	break;
	315	gpio_free(fun->rnb_gpio[i]);
	316	}
5c249c5a AV	317	err1:
	318	kfree(fun);
	319
	320	return ret;
	321	}
	322
810b7e06	323	static int fun_remove(struct platform_device *ofdev)
5c249c5a AV	324	{
5c249c5a AV	325	struct fsl_upm_nand *fun = dev_get_drvdata(&ofdev->dev);
478d51f0	326	struct mtd_info *mtd = nand_to_mtd(&fun->chip);
b6e0e8c0	327	int i;
5c249c5a	328
478d51f0 BB	329	nand_release(mtd);
478d51f0 BB	330	kfree(mtd->name);
5c249c5a	331
b6e0e8c0 WG	332	for (i = 0; i < fun->mchip_count; i++) {
	333	if (fun->rnb_gpio[i] < 0)
	334	break;
	335	gpio_free(fun->rnb_gpio[i]);
	336	}
5c249c5a AV	337
	338	kfree(fun);
	339
	340	return 0;
	341	}
	342
b2d4fbab	343	static const struct of_device_id of_fun_match[] = {
5c249c5a AV	344	{ .compatible = "fsl,upm-nand" },
	345	{},
	346	};
	347	MODULE_DEVICE_TABLE(of, of_fun_match);
	348
1c48a5c9	349	static struct platform_driver of_fun_driver = {
4018294b GL	350	.driver = {
4018294b GL	351	.name = "fsl,upm-nand",
4018294b GL	352	.of_match_table = of_fun_match,
4018294b GL	353	},
5c249c5a	354	.probe = fun_probe,
5153b88c	355	.remove = fun_remove,
5c249c5a AV	356	};
5c249c5a AV	357
f99640de	358	module_platform_driver(of_fun_driver);
5c249c5a AV	359
	360	MODULE_LICENSE("GPL");
	361	MODULE_AUTHOR("Anton Vorontsov <avorontsov@ru.mvista.com>");
	362	MODULE_DESCRIPTION("Driver for NAND chips working through Freescale "
	363	"LocalBus User-Programmable Machine");