[deliverable/linux.git] / drivers / mtd / nand / fsl_upm.c

/*
 * Freescale UPM NAND driver.
 *
 * Copyright © 2007-2008  MontaVista Software, Inc.
 *
 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/mtd.h>
#include <linux/of_platform.h>
#include <linux/of_gpio.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <asm/fsl_lbc.h>

#define FSL_UPM_WAIT_RUN_PATTERN  0x1
#define FSL_UPM_WAIT_WRITE_BYTE   0x2
#define FSL_UPM_WAIT_WRITE_BUFFER 0x4

struct fsl_upm_nand {
	struct device *dev;
	struct mtd_info mtd;
	struct nand_chip chip;
	int last_ctrl;
#ifdef CONFIG_MTD_PARTITIONS
	struct mtd_partition *parts;
#endif

	struct fsl_upm upm;
	uint8_t upm_addr_offset;
	uint8_t upm_cmd_offset;
	void __iomem *io_base;
	int rnb_gpio[NAND_MAX_CHIPS];
	uint32_t mchip_offsets[NAND_MAX_CHIPS];
	uint32_t mchip_count;
	uint32_t mchip_number;
	int chip_delay;
	uint32_t wait_flags;
};

static inline struct fsl_upm_nand *to_fsl_upm_nand(struct mtd_info *mtdinfo)
{
	return container_of(mtdinfo, struct fsl_upm_nand, mtd);
}

static int fun_chip_ready(struct mtd_info *mtd)
{
	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);

	if (gpio_get_value(fun->rnb_gpio[fun->mchip_number]))
		return 1;

	dev_vdbg(fun->dev, "busy\n");
	return 0;
}

static void fun_wait_rnb(struct fsl_upm_nand *fun)
{
	if (fun->rnb_gpio[fun->mchip_number] >= 0) {
		int cnt = 1000000;

		while (--cnt && !fun_chip_ready(&fun->mtd))
			cpu_relax();
		if (!cnt)
			dev_err(fun->dev, "tired waiting for RNB\n");
	} else {
		ndelay(100);
	}
}

static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
	struct nand_chip *chip = mtd->priv;
	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
	u32 mar;

	if (!(ctrl & fun->last_ctrl)) {
		fsl_upm_end_pattern(&fun->upm);

		if (cmd == NAND_CMD_NONE)
			return;

		fun->last_ctrl = ctrl & (NAND_ALE | NAND_CLE);
	}

	if (ctrl & NAND_CTRL_CHANGE) {
		if (ctrl & NAND_ALE)
			fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
		else if (ctrl & NAND_CLE)
			fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
	}

	mar = (cmd << (32 - fun->upm.width)) |
		fun->mchip_offsets[fun->mchip_number];
	fsl_upm_run_pattern(&fun->upm, chip->IO_ADDR_R, mar);

	if (fun->wait_flags & FSL_UPM_WAIT_RUN_PATTERN)
		fun_wait_rnb(fun);
}

static void fun_select_chip(struct mtd_info *mtd, int mchip_nr)
{
	struct nand_chip *chip = mtd->priv;
	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);

	if (mchip_nr == -1) {
		chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
	} else if (mchip_nr >= 0 && mchip_nr < NAND_MAX_CHIPS) {
		fun->mchip_number = mchip_nr;
		chip->IO_ADDR_R = fun->io_base + fun->mchip_offsets[mchip_nr];
		chip->IO_ADDR_W = chip->IO_ADDR_R;
	} else {
		BUG();
	}
}

static uint8_t fun_read_byte(struct mtd_info *mtd)
{
	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);

	return in_8(fun->chip.IO_ADDR_R);
}

static void fun_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
{
	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
	int i;

	for (i = 0; i < len; i++)
		buf[i] = in_8(fun->chip.IO_ADDR_R);
}

static void fun_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
{
	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
	int i;

	for (i = 0; i < len; i++) {
		out_8(fun->chip.IO_ADDR_W, buf[i]);
		if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BYTE)
			fun_wait_rnb(fun);
	}
	if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BUFFER)
		fun_wait_rnb(fun);
}

static int __devinit fun_chip_init(struct fsl_upm_nand *fun,
				   const struct device_node *upm_np,
				   const struct resource *io_res)
{
	int ret;
	struct device_node *flash_np;
#ifdef CONFIG_MTD_PARTITIONS
	static const char *part_types[] = { "cmdlinepart", NULL, };
#endif

	fun->chip.IO_ADDR_R = fun->io_base;
	fun->chip.IO_ADDR_W = fun->io_base;
	fun->chip.cmd_ctrl = fun_cmd_ctrl;
	fun->chip.chip_delay = fun->chip_delay;
	fun->chip.read_byte = fun_read_byte;
	fun->chip.read_buf = fun_read_buf;
	fun->chip.write_buf = fun_write_buf;
	fun->chip.ecc.mode = NAND_ECC_SOFT;
	if (fun->mchip_count > 1)
		fun->chip.select_chip = fun_select_chip;

	if (fun->rnb_gpio[0] >= 0)
		fun->chip.dev_ready = fun_chip_ready;

	fun->mtd.priv = &fun->chip;
	fun->mtd.owner = THIS_MODULE;

	flash_np = of_get_next_child(upm_np, NULL);
	if (!flash_np)
		return -ENODEV;

	fun->mtd.name = kasprintf(GFP_KERNEL, "0x%llx.%s", (u64)io_res->start,
				  flash_np->name);
	if (!fun->mtd.name) {
		ret = -ENOMEM;
		goto err;
	}

	ret = nand_scan(&fun->mtd, fun->mchip_count);
	if (ret)
		goto err;

#ifdef CONFIG_MTD_PARTITIONS
	ret = parse_mtd_partitions(&fun->mtd, part_types, &fun->parts, 0);

#ifdef CONFIG_MTD_OF_PARTS
	if (ret == 0) {
		ret = of_mtd_parse_partitions(fun->dev, flash_np, &fun->parts);
		if (ret < 0)
			goto err;
	}
#endif
	if (ret > 0)
		ret = add_mtd_partitions(&fun->mtd, fun->parts, ret);
	else
#endif
		ret = add_mtd_device(&fun->mtd);
err:
	of_node_put(flash_np);
	return ret;
}

static int __devinit fun_probe(struct platform_device *ofdev)
{
	struct fsl_upm_nand *fun;
	struct resource io_res;
	const __be32 *prop;
	int rnb_gpio;
	int ret;
	int size;
	int i;

	fun = kzalloc(sizeof(*fun), GFP_KERNEL);
	if (!fun)
		return -ENOMEM;

	ret = of_address_to_resource(ofdev->dev.of_node, 0, &io_res);
	if (ret) {
		dev_err(&ofdev->dev, "can't get IO base\n");
		goto err1;
	}

	ret = fsl_upm_find(io_res.start, &fun->upm);
	if (ret) {
		dev_err(&ofdev->dev, "can't find UPM\n");
		goto err1;
	}

	prop = of_get_property(ofdev->dev.of_node, "fsl,upm-addr-offset",
			       &size);
	if (!prop || size != sizeof(uint32_t)) {
		dev_err(&ofdev->dev, "can't get UPM address offset\n");
		ret = -EINVAL;
		goto err1;
	}
	fun->upm_addr_offset = *prop;

	prop = of_get_property(ofdev->dev.of_node, "fsl,upm-cmd-offset", &size);
	if (!prop || size != sizeof(uint32_t)) {
		dev_err(&ofdev->dev, "can't get UPM command offset\n");
		ret = -EINVAL;
		goto err1;
	}
	fun->upm_cmd_offset = *prop;

	prop = of_get_property(ofdev->dev.of_node,
			       "fsl,upm-addr-line-cs-offsets", &size);
	if (prop && (size / sizeof(uint32_t)) > 0) {
		fun->mchip_count = size / sizeof(uint32_t);
		if (fun->mchip_count >= NAND_MAX_CHIPS) {
			dev_err(&ofdev->dev, "too much multiple chips\n");
			goto err1;
		}
		for (i = 0; i < fun->mchip_count; i++)
			fun->mchip_offsets[i] = be32_to_cpu(prop[i]);
	} else {
		fun->mchip_count = 1;
	}

	for (i = 0; i < fun->mchip_count; i++) {
		fun->rnb_gpio[i] = -1;
		rnb_gpio = of_get_gpio(ofdev->dev.of_node, i);
		if (rnb_gpio >= 0) {
			ret = gpio_request(rnb_gpio, dev_name(&ofdev->dev));
			if (ret) {
				dev_err(&ofdev->dev,
					"can't request RNB gpio #%d\n", i);
				goto err2;
			}
			gpio_direction_input(rnb_gpio);
			fun->rnb_gpio[i] = rnb_gpio;
		} else if (rnb_gpio == -EINVAL) {
			dev_err(&ofdev->dev, "RNB gpio #%d is invalid\n", i);
			goto err2;
		}
	}

	prop = of_get_property(ofdev->dev.of_node, "chip-delay", NULL);
	if (prop)
		fun->chip_delay = be32_to_cpup(prop);
	else
		fun->chip_delay = 50;

	prop = of_get_property(ofdev->dev.of_node, "fsl,upm-wait-flags", &size);
	if (prop && size == sizeof(uint32_t))
		fun->wait_flags = be32_to_cpup(prop);
	else
		fun->wait_flags = FSL_UPM_WAIT_RUN_PATTERN |
				  FSL_UPM_WAIT_WRITE_BYTE;

	fun->io_base = devm_ioremap_nocache(&ofdev->dev, io_res.start,
					    resource_size(&io_res));
	if (!fun->io_base) {
		ret = -ENOMEM;
		goto err2;
	}

	fun->dev = &ofdev->dev;
	fun->last_ctrl = NAND_CLE;

	ret = fun_chip_init(fun, ofdev->dev.of_node, &io_res);
	if (ret)
		goto err2;

	dev_set_drvdata(&ofdev->dev, fun);

	return 0;
err2:
	for (i = 0; i < fun->mchip_count; i++) {
		if (fun->rnb_gpio[i] < 0)
			break;
		gpio_free(fun->rnb_gpio[i]);
	}
err1:
	kfree(fun);

	return ret;
}

static int __devexit fun_remove(struct platform_device *ofdev)
{
	struct fsl_upm_nand *fun = dev_get_drvdata(&ofdev->dev);
	int i;

	nand_release(&fun->mtd);
	kfree(fun->mtd.name);

	for (i = 0; i < fun->mchip_count; i++) {
		if (fun->rnb_gpio[i] < 0)
			break;
		gpio_free(fun->rnb_gpio[i]);
	}

	kfree(fun);

	return 0;
}

static const struct of_device_id of_fun_match[] = {
	{ .compatible = "fsl,upm-nand" },
	{},
};
MODULE_DEVICE_TABLE(of, of_fun_match);

static struct platform_driver of_fun_driver = {
	.driver = {
		.name = "fsl,upm-nand",
		.owner = THIS_MODULE,
		.of_match_table = of_fun_match,
	},
	.probe		= fun_probe,
	.remove		= __devexit_p(fun_remove),
};

static int __init fun_module_init(void)
{
	return platform_driver_register(&of_fun_driver);
}
module_init(fun_module_init);

static void __exit fun_module_exit(void)
{
	platform_driver_unregister(&of_fun_driver);
}
module_exit(fun_module_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Anton Vorontsov <avorontsov@ru.mvista.com>");
MODULE_DESCRIPTION("Driver for NAND chips working through Freescale "
		   "LocalBus User-Programmable Machine");
Commit	Line	Data
5c249c5a AV	1	/*
	2	* Freescale UPM NAND driver.
	3	*
	4	* Copyright © 2007-2008 MontaVista Software, Inc.
	5	*
	6	* Author: Anton Vorontsov <avorontsov@ru.mvista.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/module.h>
13f53697	16	#include <linux/delay.h>
5c249c5a AV	17	#include <linux/mtd/nand.h>
	18	#include <linux/mtd/nand_ecc.h>
	19	#include <linux/mtd/partitions.h>
	20	#include <linux/mtd/mtd.h>
	21	#include <linux/of_platform.h>
	22	#include <linux/of_gpio.h>
	23	#include <linux/io.h>
5a0e3ad6	24	#include <linux/slab.h>
5c249c5a AV	25	#include <asm/fsl_lbc.h>
5c249c5a AV	26
ade92a63 WG	27	#define FSL_UPM_WAIT_RUN_PATTERN 0x1
	28	#define FSL_UPM_WAIT_WRITE_BYTE 0x2
	29	#define FSL_UPM_WAIT_WRITE_BUFFER 0x4
	30
5c249c5a AV	31	struct fsl_upm_nand {
	32	struct device *dev;
	33	struct mtd_info mtd;
	34	struct nand_chip chip;
	35	int last_ctrl;
	36	#ifdef CONFIG_MTD_PARTITIONS
	37	struct mtd_partition *parts;
	38	#endif
	39
	40	struct fsl_upm upm;
	41	uint8_t upm_addr_offset;
	42	uint8_t upm_cmd_offset;
	43	void __iomem *io_base;
b6e0e8c0 WG	44	int rnb_gpio[NAND_MAX_CHIPS];
	45	uint32_t mchip_offsets[NAND_MAX_CHIPS];
	46	uint32_t mchip_count;
	47	uint32_t mchip_number;
13f53697	48	int chip_delay;
ade92a63	49	uint32_t wait_flags;
5c249c5a AV	50	};
5c249c5a AV	51
b92b5c41 FW	52	static inline struct fsl_upm_nand to_fsl_upm_nand(struct mtd_info mtdinfo)
	53	{
	54	return container_of(mtdinfo, struct fsl_upm_nand, mtd);
	55	}
5c249c5a AV	56
	57	static int fun_chip_ready(struct mtd_info *mtd)
	58	{
	59	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
	60
b6e0e8c0	61	if (gpio_get_value(fun->rnb_gpio[fun->mchip_number]))
5c249c5a AV	62	return 1;
	63
	64	dev_vdbg(fun->dev, "busy\n");
	65	return 0;
	66	}
	67
	68	static void fun_wait_rnb(struct fsl_upm_nand *fun)
	69	{
b6e0e8c0 WG	70	if (fun->rnb_gpio[fun->mchip_number] >= 0) {
b6e0e8c0 WG	71	int cnt = 1000000;
5c249c5a	72
5c249c5a AV	73	while (--cnt && !fun_chip_ready(&fun->mtd))
5c249c5a AV	74	cpu_relax();
13f53697 WG	75	if (!cnt)
	76	dev_err(fun->dev, "tired waiting for RNB\n");
	77	} else {
	78	ndelay(100);
5c249c5a	79	}
5c249c5a AV	80	}
	81
	82	static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
	83	{
b6e0e8c0	84	struct nand_chip *chip = mtd->priv;
5c249c5a	85	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
b6e0e8c0	86	u32 mar;
5c249c5a AV	87
	88	if (!(ctrl & fun->last_ctrl)) {
	89	fsl_upm_end_pattern(&fun->upm);
	90
	91	if (cmd == NAND_CMD_NONE)
	92	return;
	93
	94	fun->last_ctrl = ctrl & (NAND_ALE \| NAND_CLE);
	95	}
	96
	97	if (ctrl & NAND_CTRL_CHANGE) {
	98	if (ctrl & NAND_ALE)
	99	fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
	100	else if (ctrl & NAND_CLE)
	101	fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
	102	}
	103
b6e0e8c0 WG	104	mar = (cmd << (32 - fun->upm.width)) \|
	105	fun->mchip_offsets[fun->mchip_number];
	106	fsl_upm_run_pattern(&fun->upm, chip->IO_ADDR_R, mar);
5c249c5a	107
ade92a63 WG	108	if (fun->wait_flags & FSL_UPM_WAIT_RUN_PATTERN)
ade92a63 WG	109	fun_wait_rnb(fun);
5c249c5a AV	110	}
5c249c5a AV	111
b6e0e8c0 WG	112	static void fun_select_chip(struct mtd_info *mtd, int mchip_nr)
	113	{
	114	struct nand_chip *chip = mtd->priv;
	115	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
	116
	117	if (mchip_nr == -1) {
	118	chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 \| NAND_CTRL_CHANGE);
35016dd7	119	} else if (mchip_nr >= 0 && mchip_nr < NAND_MAX_CHIPS) {
b6e0e8c0 WG	120	fun->mchip_number = mchip_nr;
	121	chip->IO_ADDR_R = fun->io_base + fun->mchip_offsets[mchip_nr];
	122	chip->IO_ADDR_W = chip->IO_ADDR_R;
	123	} else {
	124	BUG();
	125	}
	126	}
	127
5c249c5a AV	128	static uint8_t fun_read_byte(struct mtd_info *mtd)
	129	{
	130	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
	131
	132	return in_8(fun->chip.IO_ADDR_R);
	133	}
	134
	135	static void fun_read_buf(struct mtd_info mtd, uint8_t buf, int len)
	136	{
	137	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
	138	int i;
	139
	140	for (i = 0; i < len; i++)
	141	buf[i] = in_8(fun->chip.IO_ADDR_R);
	142	}
	143
	144	static void fun_write_buf(struct mtd_info mtd, const uint8_t buf, int len)
	145	{
	146	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
	147	int i;
	148
	149	for (i = 0; i < len; i++) {
	150	out_8(fun->chip.IO_ADDR_W, buf[i]);
ade92a63 WG	151	if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BYTE)
ade92a63 WG	152	fun_wait_rnb(fun);
5c249c5a	153	}
ade92a63 WG	154	if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BUFFER)
ade92a63 WG	155	fun_wait_rnb(fun);
5c249c5a AV	156	}
5c249c5a AV	157
95ebffd7 AV	158	static int __devinit fun_chip_init(struct fsl_upm_nand *fun,
	159	const struct device_node *upm_np,
	160	const struct resource *io_res)
5c249c5a AV	161	{
5c249c5a AV	162	int ret;
95ebffd7	163	struct device_node *flash_np;
5c249c5a AV	164	#ifdef CONFIG_MTD_PARTITIONS
	165	static const char *part_types[] = { "cmdlinepart", NULL, };
	166	#endif
	167
	168	fun->chip.IO_ADDR_R = fun->io_base;
	169	fun->chip.IO_ADDR_W = fun->io_base;
	170	fun->chip.cmd_ctrl = fun_cmd_ctrl;
13f53697	171	fun->chip.chip_delay = fun->chip_delay;
5c249c5a AV	172	fun->chip.read_byte = fun_read_byte;
	173	fun->chip.read_buf = fun_read_buf;
	174	fun->chip.write_buf = fun_write_buf;
	175	fun->chip.ecc.mode = NAND_ECC_SOFT;
b6e0e8c0 WG	176	if (fun->mchip_count > 1)
b6e0e8c0 WG	177	fun->chip.select_chip = fun_select_chip;
5c249c5a	178
b6e0e8c0	179	if (fun->rnb_gpio[0] >= 0)
5c249c5a AV	180	fun->chip.dev_ready = fun_chip_ready;
	181
	182	fun->mtd.priv = &fun->chip;
	183	fun->mtd.owner = THIS_MODULE;
	184
95ebffd7 AV	185	flash_np = of_get_next_child(upm_np, NULL);
	186	if (!flash_np)
	187	return -ENODEV;
	188
0eecf4b2	189	fun->mtd.name = kasprintf(GFP_KERNEL, "0x%llx.%s", (u64)io_res->start,
95ebffd7 AV	190	flash_np->name);
	191	if (!fun->mtd.name) {
	192	ret = -ENOMEM;
	193	goto err;
	194	}
	195
b6e0e8c0	196	ret = nand_scan(&fun->mtd, fun->mchip_count);
5c249c5a	197	if (ret)
95ebffd7	198	goto err;
5c249c5a AV	199
	200	#ifdef CONFIG_MTD_PARTITIONS
	201	ret = parse_mtd_partitions(&fun->mtd, part_types, &fun->parts, 0);
95ebffd7 AV	202
95ebffd7 AV	203	#ifdef CONFIG_MTD_OF_PARTS
29b65861 WG	204	if (ret == 0) {
	205	ret = of_mtd_parse_partitions(fun->dev, flash_np, &fun->parts);
	206	if (ret < 0)
	207	goto err;
	208	}
95ebffd7	209	#endif
5c249c5a	210	if (ret > 0)
95ebffd7 AV	211	ret = add_mtd_partitions(&fun->mtd, fun->parts, ret);
95ebffd7 AV	212	else
5c249c5a	213	#endif
95ebffd7 AV	214	ret = add_mtd_device(&fun->mtd);
	215	err:
	216	of_node_put(flash_np);
	217	return ret;
5c249c5a AV	218	}
5c249c5a AV	219
1c48a5c9	220	static int __devinit fun_probe(struct platform_device *ofdev)
5c249c5a AV	221	{
	222	struct fsl_upm_nand *fun;
	223	struct resource io_res;
766f271a	224	const __be32 *prop;
b6e0e8c0	225	int rnb_gpio;
5c249c5a AV	226	int ret;
5c249c5a AV	227	int size;
b6e0e8c0	228	int i;
5c249c5a AV	229
	230	fun = kzalloc(sizeof(*fun), GFP_KERNEL);
	231	if (!fun)
	232	return -ENOMEM;
	233
c8a4d0fd	234	ret = of_address_to_resource(ofdev->dev.of_node, 0, &io_res);
5c249c5a AV	235	if (ret) {
	236	dev_err(&ofdev->dev, "can't get IO base\n");
	237	goto err1;
	238	}
	239
	240	ret = fsl_upm_find(io_res.start, &fun->upm);
	241	if (ret) {
	242	dev_err(&ofdev->dev, "can't find UPM\n");
	243	goto err1;
	244	}
	245
c8a4d0fd AG	246	prop = of_get_property(ofdev->dev.of_node, "fsl,upm-addr-offset",
c8a4d0fd AG	247	&size);
5c249c5a AV	248	if (!prop \|\| size != sizeof(uint32_t)) {
	249	dev_err(&ofdev->dev, "can't get UPM address offset\n");
	250	ret = -EINVAL;
b6e0e8c0	251	goto err1;
5c249c5a AV	252	}
	253	fun->upm_addr_offset = *prop;
	254
c8a4d0fd	255	prop = of_get_property(ofdev->dev.of_node, "fsl,upm-cmd-offset", &size);
5c249c5a AV	256	if (!prop \|\| size != sizeof(uint32_t)) {
	257	dev_err(&ofdev->dev, "can't get UPM command offset\n");
	258	ret = -EINVAL;
b6e0e8c0	259	goto err1;
5c249c5a AV	260	}
	261	fun->upm_cmd_offset = *prop;
	262
c8a4d0fd	263	prop = of_get_property(ofdev->dev.of_node,
b6e0e8c0 WG	264	"fsl,upm-addr-line-cs-offsets", &size);
	265	if (prop && (size / sizeof(uint32_t)) > 0) {
	266	fun->mchip_count = size / sizeof(uint32_t);
	267	if (fun->mchip_count >= NAND_MAX_CHIPS) {
	268	dev_err(&ofdev->dev, "too much multiple chips\n");
	269	goto err1;
	270	}
	271	for (i = 0; i < fun->mchip_count; i++)
766f271a	272	fun->mchip_offsets[i] = be32_to_cpu(prop[i]);
b6e0e8c0 WG	273	} else {
	274	fun->mchip_count = 1;
	275	}
	276
	277	for (i = 0; i < fun->mchip_count; i++) {
	278	fun->rnb_gpio[i] = -1;
c8a4d0fd	279	rnb_gpio = of_get_gpio(ofdev->dev.of_node, i);
b6e0e8c0 WG	280	if (rnb_gpio >= 0) {
	281	ret = gpio_request(rnb_gpio, dev_name(&ofdev->dev));
	282	if (ret) {
	283	dev_err(&ofdev->dev,
	284	"can't request RNB gpio #%d\n", i);
	285	goto err2;
	286	}
	287	gpio_direction_input(rnb_gpio);
	288	fun->rnb_gpio[i] = rnb_gpio;
	289	} else if (rnb_gpio == -EINVAL) {
	290	dev_err(&ofdev->dev, "RNB gpio #%d is invalid\n", i);
5c249c5a AV	291	goto err2;
5c249c5a AV	292	}
5c249c5a AV	293	}
5c249c5a AV	294
c8a4d0fd	295	prop = of_get_property(ofdev->dev.of_node, "chip-delay", NULL);
13f53697	296	if (prop)
766f271a	297	fun->chip_delay = be32_to_cpup(prop);
13f53697 WG	298	else
	299	fun->chip_delay = 50;
	300
c8a4d0fd	301	prop = of_get_property(ofdev->dev.of_node, "fsl,upm-wait-flags", &size);
ade92a63	302	if (prop && size == sizeof(uint32_t))
766f271a	303	fun->wait_flags = be32_to_cpup(prop);
ade92a63 WG	304	else
	305	fun->wait_flags = FSL_UPM_WAIT_RUN_PATTERN \|
	306	FSL_UPM_WAIT_WRITE_BYTE;
	307
5c249c5a	308	fun->io_base = devm_ioremap_nocache(&ofdev->dev, io_res.start,
58e6a84d	309	resource_size(&io_res));
5c249c5a AV	310	if (!fun->io_base) {
	311	ret = -ENOMEM;
	312	goto err2;
	313	}
	314
	315	fun->dev = &ofdev->dev;
	316	fun->last_ctrl = NAND_CLE;
5c249c5a	317
c8a4d0fd	318	ret = fun_chip_init(fun, ofdev->dev.of_node, &io_res);
5c249c5a AV	319	if (ret)
	320	goto err2;
	321
	322	dev_set_drvdata(&ofdev->dev, fun);
	323
	324	return 0;
	325	err2:
b6e0e8c0 WG	326	for (i = 0; i < fun->mchip_count; i++) {
	327	if (fun->rnb_gpio[i] < 0)
	328	break;
	329	gpio_free(fun->rnb_gpio[i]);
	330	}
5c249c5a AV	331	err1:
	332	kfree(fun);
	333
	334	return ret;
	335	}
	336
2dc11581	337	static int __devexit fun_remove(struct platform_device *ofdev)
5c249c5a AV	338	{
5c249c5a AV	339	struct fsl_upm_nand *fun = dev_get_drvdata(&ofdev->dev);
b6e0e8c0	340	int i;
5c249c5a AV	341
5c249c5a AV	342	nand_release(&fun->mtd);
95ebffd7	343	kfree(fun->mtd.name);
5c249c5a	344
b6e0e8c0 WG	345	for (i = 0; i < fun->mchip_count; i++) {
	346	if (fun->rnb_gpio[i] < 0)
	347	break;
	348	gpio_free(fun->rnb_gpio[i]);
	349	}
5c249c5a AV	350
	351	kfree(fun);
	352
	353	return 0;
	354	}
	355
b2d4fbab	356	static const struct of_device_id of_fun_match[] = {
5c249c5a AV	357	{ .compatible = "fsl,upm-nand" },
	358	{},
	359	};
	360	MODULE_DEVICE_TABLE(of, of_fun_match);
	361
1c48a5c9	362	static struct platform_driver of_fun_driver = {
4018294b GL	363	.driver = {
	364	.name = "fsl,upm-nand",
	365	.owner = THIS_MODULE,
	366	.of_match_table = of_fun_match,
	367	},
5c249c5a AV	368	.probe = fun_probe,
	369	.remove = __devexit_p(fun_remove),
	370	};
	371
	372	static int __init fun_module_init(void)
	373	{
1c48a5c9	374	return platform_driver_register(&of_fun_driver);
5c249c5a AV	375	}
	376	module_init(fun_module_init);
	377
	378	static void __exit fun_module_exit(void)
	379	{
1c48a5c9	380	platform_driver_unregister(&of_fun_driver);
5c249c5a AV	381	}
	382	module_exit(fun_module_exit);
	383
	384	MODULE_LICENSE("GPL");
	385	MODULE_AUTHOR("Anton Vorontsov <avorontsov@ru.mvista.com>");
	386	MODULE_DESCRIPTION("Driver for NAND chips working through Freescale "
	387	"LocalBus User-Programmable Machine");