[deliverable/linux.git] / drivers / mtd / nand / fsl_upm.c

/*
 * Freescale UPM NAND driver.
 *
 * Copyright © 2007-2008  MontaVista Software, Inc.
 *
 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/mtd.h>
#include <linux/of_platform.h>
#include <linux/of_gpio.h>
#include <linux/io.h>
#include <asm/fsl_lbc.h>

#define FSL_UPM_WAIT_RUN_PATTERN  0x1
#define FSL_UPM_WAIT_WRITE_BYTE   0x2
#define FSL_UPM_WAIT_WRITE_BUFFER 0x4

struct fsl_upm_nand {
	struct device *dev;
	struct mtd_info mtd;
	struct nand_chip chip;
	int last_ctrl;
#ifdef CONFIG_MTD_PARTITIONS
	struct mtd_partition *parts;
#endif

	struct fsl_upm upm;
	uint8_t upm_addr_offset;
	uint8_t upm_cmd_offset;
	void __iomem *io_base;
	int rnb_gpio[NAND_MAX_CHIPS];
	uint32_t mchip_offsets[NAND_MAX_CHIPS];
	uint32_t mchip_count;
	uint32_t mchip_number;
	int chip_delay;
	uint32_t wait_flags;
};

#define to_fsl_upm_nand(mtd) container_of(mtd, struct fsl_upm_nand, mtd)

static int fun_chip_ready(struct mtd_info *mtd)
{
	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);

	if (gpio_get_value(fun->rnb_gpio[fun->mchip_number]))
		return 1;

	dev_vdbg(fun->dev, "busy\n");
	return 0;
}

static void fun_wait_rnb(struct fsl_upm_nand *fun)
{
	if (fun->rnb_gpio[fun->mchip_number] >= 0) {
		int cnt = 1000000;

		while (--cnt && !fun_chip_ready(&fun->mtd))
			cpu_relax();
		if (!cnt)
			dev_err(fun->dev, "tired waiting for RNB\n");
	} else {
		ndelay(100);
	}
}

static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
	struct nand_chip *chip = mtd->priv;
	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
	u32 mar;

	if (!(ctrl & fun->last_ctrl)) {
		fsl_upm_end_pattern(&fun->upm);

		if (cmd == NAND_CMD_NONE)
			return;

		fun->last_ctrl = ctrl & (NAND_ALE | NAND_CLE);
	}

	if (ctrl & NAND_CTRL_CHANGE) {
		if (ctrl & NAND_ALE)
			fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
		else if (ctrl & NAND_CLE)
			fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
	}

	mar = (cmd << (32 - fun->upm.width)) |
		fun->mchip_offsets[fun->mchip_number];
	fsl_upm_run_pattern(&fun->upm, chip->IO_ADDR_R, mar);

	if (fun->wait_flags & FSL_UPM_WAIT_RUN_PATTERN)
		fun_wait_rnb(fun);
}

static void fun_select_chip(struct mtd_info *mtd, int mchip_nr)
{
	struct nand_chip *chip = mtd->priv;
	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);

	if (mchip_nr == -1) {
		chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
	} else if (mchip_nr >= 0 && mchip_nr < NAND_MAX_CHIPS) {
		fun->mchip_number = mchip_nr;
		chip->IO_ADDR_R = fun->io_base + fun->mchip_offsets[mchip_nr];
		chip->IO_ADDR_W = chip->IO_ADDR_R;
	} else {
		BUG();
	}
}

static uint8_t fun_read_byte(struct mtd_info *mtd)
{
	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);

	return in_8(fun->chip.IO_ADDR_R);
}

static void fun_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
{
	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
	int i;

	for (i = 0; i < len; i++)
		buf[i] = in_8(fun->chip.IO_ADDR_R);
}

static void fun_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
{
	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
	int i;

	for (i = 0; i < len; i++) {
		out_8(fun->chip.IO_ADDR_W, buf[i]);
		if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BYTE)
			fun_wait_rnb(fun);
	}
	if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BUFFER)
		fun_wait_rnb(fun);
}

static int __devinit fun_chip_init(struct fsl_upm_nand *fun,
				   const struct device_node *upm_np,
				   const struct resource *io_res)
{
	int ret;
	struct device_node *flash_np;
#ifdef CONFIG_MTD_PARTITIONS
	static const char *part_types[] = { "cmdlinepart", NULL, };
#endif

	fun->chip.IO_ADDR_R = fun->io_base;
	fun->chip.IO_ADDR_W = fun->io_base;
	fun->chip.cmd_ctrl = fun_cmd_ctrl;
	fun->chip.chip_delay = fun->chip_delay;
	fun->chip.read_byte = fun_read_byte;
	fun->chip.read_buf = fun_read_buf;
	fun->chip.write_buf = fun_write_buf;
	fun->chip.ecc.mode = NAND_ECC_SOFT;
	if (fun->mchip_count > 1)
		fun->chip.select_chip = fun_select_chip;

	if (fun->rnb_gpio[0] >= 0)
		fun->chip.dev_ready = fun_chip_ready;

	fun->mtd.priv = &fun->chip;
	fun->mtd.owner = THIS_MODULE;

	flash_np = of_get_next_child(upm_np, NULL);
	if (!flash_np)
		return -ENODEV;

	fun->mtd.name = kasprintf(GFP_KERNEL, "%x.%s", io_res->start,
				  flash_np->name);
	if (!fun->mtd.name) {
		ret = -ENOMEM;
		goto err;
	}

	ret = nand_scan(&fun->mtd, fun->mchip_count);
	if (ret)
		goto err;

#ifdef CONFIG_MTD_PARTITIONS
	ret = parse_mtd_partitions(&fun->mtd, part_types, &fun->parts, 0);

#ifdef CONFIG_MTD_OF_PARTS
	if (ret == 0) {
		ret = of_mtd_parse_partitions(fun->dev, flash_np, &fun->parts);
		if (ret < 0)
			goto err;
	}
#endif
	if (ret > 0)
		ret = add_mtd_partitions(&fun->mtd, fun->parts, ret);
	else
#endif
		ret = add_mtd_device(&fun->mtd);
err:
	of_node_put(flash_np);
	return ret;
}

static int __devinit fun_probe(struct of_device *ofdev,
			       const struct of_device_id *ofid)
{
	struct fsl_upm_nand *fun;
	struct resource io_res;
	const uint32_t *prop;
	int rnb_gpio;
	int ret;
	int size;
	int i;

	fun = kzalloc(sizeof(*fun), GFP_KERNEL);
	if (!fun)
		return -ENOMEM;

	ret = of_address_to_resource(ofdev->node, 0, &io_res);
	if (ret) {
		dev_err(&ofdev->dev, "can't get IO base\n");
		goto err1;
	}

	ret = fsl_upm_find(io_res.start, &fun->upm);
	if (ret) {
		dev_err(&ofdev->dev, "can't find UPM\n");
		goto err1;
	}

	prop = of_get_property(ofdev->node, "fsl,upm-addr-offset", &size);
	if (!prop || size != sizeof(uint32_t)) {
		dev_err(&ofdev->dev, "can't get UPM address offset\n");
		ret = -EINVAL;
		goto err1;
	}
	fun->upm_addr_offset = *prop;

	prop = of_get_property(ofdev->node, "fsl,upm-cmd-offset", &size);
	if (!prop || size != sizeof(uint32_t)) {
		dev_err(&ofdev->dev, "can't get UPM command offset\n");
		ret = -EINVAL;
		goto err1;
	}
	fun->upm_cmd_offset = *prop;

	prop = of_get_property(ofdev->node,
			       "fsl,upm-addr-line-cs-offsets", &size);
	if (prop && (size / sizeof(uint32_t)) > 0) {
		fun->mchip_count = size / sizeof(uint32_t);
		if (fun->mchip_count >= NAND_MAX_CHIPS) {
			dev_err(&ofdev->dev, "too much multiple chips\n");
			goto err1;
		}
		for (i = 0; i < fun->mchip_count; i++)
			fun->mchip_offsets[i] = prop[i];
	} else {
		fun->mchip_count = 1;
	}

	for (i = 0; i < fun->mchip_count; i++) {
		fun->rnb_gpio[i] = -1;
		rnb_gpio = of_get_gpio(ofdev->node, i);
		if (rnb_gpio >= 0) {
			ret = gpio_request(rnb_gpio, dev_name(&ofdev->dev));
			if (ret) {
				dev_err(&ofdev->dev,
					"can't request RNB gpio #%d\n", i);
				goto err2;
			}
			gpio_direction_input(rnb_gpio);
			fun->rnb_gpio[i] = rnb_gpio;
		} else if (rnb_gpio == -EINVAL) {
			dev_err(&ofdev->dev, "RNB gpio #%d is invalid\n", i);
			goto err2;
		}
	}

	prop = of_get_property(ofdev->node, "chip-delay", NULL);
	if (prop)
		fun->chip_delay = *prop;
	else
		fun->chip_delay = 50;

	prop = of_get_property(ofdev->node, "fsl,upm-wait-flags", &size);
	if (prop && size == sizeof(uint32_t))
		fun->wait_flags = *prop;
	else
		fun->wait_flags = FSL_UPM_WAIT_RUN_PATTERN |
				  FSL_UPM_WAIT_WRITE_BYTE;

	fun->io_base = devm_ioremap_nocache(&ofdev->dev, io_res.start,
					    io_res.end - io_res.start + 1);
	if (!fun->io_base) {
		ret = -ENOMEM;
		goto err2;
	}

	fun->dev = &ofdev->dev;
	fun->last_ctrl = NAND_CLE;

	ret = fun_chip_init(fun, ofdev->node, &io_res);
	if (ret)
		goto err2;

	dev_set_drvdata(&ofdev->dev, fun);

	return 0;
err2:
	for (i = 0; i < fun->mchip_count; i++) {
		if (fun->rnb_gpio[i] < 0)
			break;
		gpio_free(fun->rnb_gpio[i]);
	}
err1:
	kfree(fun);

	return ret;
}

static int __devexit fun_remove(struct of_device *ofdev)
{
	struct fsl_upm_nand *fun = dev_get_drvdata(&ofdev->dev);
	int i;

	nand_release(&fun->mtd);
	kfree(fun->mtd.name);

	for (i = 0; i < fun->mchip_count; i++) {
		if (fun->rnb_gpio[i] < 0)
			break;
		gpio_free(fun->rnb_gpio[i]);
	}

	kfree(fun);

	return 0;
}

static struct of_device_id of_fun_match[] = {
	{ .compatible = "fsl,upm-nand" },
	{},
};
MODULE_DEVICE_TABLE(of, of_fun_match);

static struct of_platform_driver of_fun_driver = {
	.name		= "fsl,upm-nand",
	.match_table	= of_fun_match,
	.probe		= fun_probe,
	.remove		= __devexit_p(fun_remove),
};

static int __init fun_module_init(void)
{
	return of_register_platform_driver(&of_fun_driver);
}
module_init(fun_module_init);

static void __exit fun_module_exit(void)
{
	of_unregister_platform_driver(&of_fun_driver);
}
module_exit(fun_module_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Anton Vorontsov <avorontsov@ru.mvista.com>");
MODULE_DESCRIPTION("Driver for NAND chips working through Freescale "
		   "LocalBus User-Programmable Machine");
Commit	Line	Data
5c249c5a AV	1	/*
	2	* Freescale UPM NAND driver.
	3	*
	4	* Copyright © 2007-2008 MontaVista Software, Inc.
	5	*
	6	* Author: Anton Vorontsov <avorontsov@ru.mvista.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/module.h>
13f53697	16	#include <linux/delay.h>
5c249c5a AV	17	#include <linux/mtd/nand.h>
	18	#include <linux/mtd/nand_ecc.h>
	19	#include <linux/mtd/partitions.h>
	20	#include <linux/mtd/mtd.h>
	21	#include <linux/of_platform.h>
	22	#include <linux/of_gpio.h>
	23	#include <linux/io.h>
	24	#include <asm/fsl_lbc.h>
	25
ade92a63 WG	26	#define FSL_UPM_WAIT_RUN_PATTERN 0x1
	27	#define FSL_UPM_WAIT_WRITE_BYTE 0x2
	28	#define FSL_UPM_WAIT_WRITE_BUFFER 0x4
	29
5c249c5a AV	30	struct fsl_upm_nand {
	31	struct device *dev;
	32	struct mtd_info mtd;
	33	struct nand_chip chip;
	34	int last_ctrl;
	35	#ifdef CONFIG_MTD_PARTITIONS
	36	struct mtd_partition *parts;
	37	#endif
	38
	39	struct fsl_upm upm;
	40	uint8_t upm_addr_offset;
	41	uint8_t upm_cmd_offset;
	42	void __iomem *io_base;
b6e0e8c0 WG	43	int rnb_gpio[NAND_MAX_CHIPS];
	44	uint32_t mchip_offsets[NAND_MAX_CHIPS];
	45	uint32_t mchip_count;
	46	uint32_t mchip_number;
13f53697	47	int chip_delay;
ade92a63	48	uint32_t wait_flags;
5c249c5a AV	49	};
	50
	51	#define to_fsl_upm_nand(mtd) container_of(mtd, struct fsl_upm_nand, mtd)
	52
	53	static int fun_chip_ready(struct mtd_info *mtd)
	54	{
	55	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
	56
b6e0e8c0	57	if (gpio_get_value(fun->rnb_gpio[fun->mchip_number]))
5c249c5a AV	58	return 1;
	59
	60	dev_vdbg(fun->dev, "busy\n");
	61	return 0;
	62	}
	63
	64	static void fun_wait_rnb(struct fsl_upm_nand *fun)
	65	{
b6e0e8c0 WG	66	if (fun->rnb_gpio[fun->mchip_number] >= 0) {
b6e0e8c0 WG	67	int cnt = 1000000;
5c249c5a	68
5c249c5a AV	69	while (--cnt && !fun_chip_ready(&fun->mtd))
5c249c5a AV	70	cpu_relax();
13f53697 WG	71	if (!cnt)
	72	dev_err(fun->dev, "tired waiting for RNB\n");
	73	} else {
	74	ndelay(100);
5c249c5a	75	}
5c249c5a AV	76	}
	77
	78	static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
	79	{
b6e0e8c0	80	struct nand_chip *chip = mtd->priv;
5c249c5a	81	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
b6e0e8c0	82	u32 mar;
5c249c5a AV	83
	84	if (!(ctrl & fun->last_ctrl)) {
	85	fsl_upm_end_pattern(&fun->upm);
	86
	87	if (cmd == NAND_CMD_NONE)
	88	return;
	89
	90	fun->last_ctrl = ctrl & (NAND_ALE \| NAND_CLE);
	91	}
	92
	93	if (ctrl & NAND_CTRL_CHANGE) {
	94	if (ctrl & NAND_ALE)
	95	fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
	96	else if (ctrl & NAND_CLE)
	97	fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
	98	}
	99
b6e0e8c0 WG	100	mar = (cmd << (32 - fun->upm.width)) \|
	101	fun->mchip_offsets[fun->mchip_number];
	102	fsl_upm_run_pattern(&fun->upm, chip->IO_ADDR_R, mar);
5c249c5a	103
ade92a63 WG	104	if (fun->wait_flags & FSL_UPM_WAIT_RUN_PATTERN)
ade92a63 WG	105	fun_wait_rnb(fun);
5c249c5a AV	106	}
5c249c5a AV	107
b6e0e8c0 WG	108	static void fun_select_chip(struct mtd_info *mtd, int mchip_nr)
	109	{
	110	struct nand_chip *chip = mtd->priv;
	111	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
	112
	113	if (mchip_nr == -1) {
	114	chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 \| NAND_CTRL_CHANGE);
35016dd7	115	} else if (mchip_nr >= 0 && mchip_nr < NAND_MAX_CHIPS) {
b6e0e8c0 WG	116	fun->mchip_number = mchip_nr;
	117	chip->IO_ADDR_R = fun->io_base + fun->mchip_offsets[mchip_nr];
	118	chip->IO_ADDR_W = chip->IO_ADDR_R;
	119	} else {
	120	BUG();
	121	}
	122	}
	123
5c249c5a AV	124	static uint8_t fun_read_byte(struct mtd_info *mtd)
	125	{
	126	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
	127
	128	return in_8(fun->chip.IO_ADDR_R);
	129	}
	130
	131	static void fun_read_buf(struct mtd_info mtd, uint8_t buf, int len)
	132	{
	133	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
	134	int i;
	135
	136	for (i = 0; i < len; i++)
	137	buf[i] = in_8(fun->chip.IO_ADDR_R);
	138	}
	139
	140	static void fun_write_buf(struct mtd_info mtd, const uint8_t buf, int len)
	141	{
	142	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
	143	int i;
	144
	145	for (i = 0; i < len; i++) {
	146	out_8(fun->chip.IO_ADDR_W, buf[i]);
ade92a63 WG	147	if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BYTE)
ade92a63 WG	148	fun_wait_rnb(fun);
5c249c5a	149	}
ade92a63 WG	150	if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BUFFER)
ade92a63 WG	151	fun_wait_rnb(fun);
5c249c5a AV	152	}
5c249c5a AV	153
95ebffd7 AV	154	static int __devinit fun_chip_init(struct fsl_upm_nand *fun,
	155	const struct device_node *upm_np,
	156	const struct resource *io_res)
5c249c5a AV	157	{
5c249c5a AV	158	int ret;
95ebffd7	159	struct device_node *flash_np;
5c249c5a AV	160	#ifdef CONFIG_MTD_PARTITIONS
	161	static const char *part_types[] = { "cmdlinepart", NULL, };
	162	#endif
	163
	164	fun->chip.IO_ADDR_R = fun->io_base;
	165	fun->chip.IO_ADDR_W = fun->io_base;
	166	fun->chip.cmd_ctrl = fun_cmd_ctrl;
13f53697	167	fun->chip.chip_delay = fun->chip_delay;
5c249c5a AV	168	fun->chip.read_byte = fun_read_byte;
	169	fun->chip.read_buf = fun_read_buf;
	170	fun->chip.write_buf = fun_write_buf;
	171	fun->chip.ecc.mode = NAND_ECC_SOFT;
b6e0e8c0 WG	172	if (fun->mchip_count > 1)
b6e0e8c0 WG	173	fun->chip.select_chip = fun_select_chip;
5c249c5a	174
b6e0e8c0	175	if (fun->rnb_gpio[0] >= 0)
5c249c5a AV	176	fun->chip.dev_ready = fun_chip_ready;
	177
	178	fun->mtd.priv = &fun->chip;
	179	fun->mtd.owner = THIS_MODULE;
	180
95ebffd7 AV	181	flash_np = of_get_next_child(upm_np, NULL);
	182	if (!flash_np)
	183	return -ENODEV;
	184
	185	fun->mtd.name = kasprintf(GFP_KERNEL, "%x.%s", io_res->start,
	186	flash_np->name);
	187	if (!fun->mtd.name) {
	188	ret = -ENOMEM;
	189	goto err;
	190	}
	191
b6e0e8c0	192	ret = nand_scan(&fun->mtd, fun->mchip_count);
5c249c5a	193	if (ret)
95ebffd7	194	goto err;
5c249c5a AV	195
	196	#ifdef CONFIG_MTD_PARTITIONS
	197	ret = parse_mtd_partitions(&fun->mtd, part_types, &fun->parts, 0);
95ebffd7 AV	198
95ebffd7 AV	199	#ifdef CONFIG_MTD_OF_PARTS
29b65861 WG	200	if (ret == 0) {
	201	ret = of_mtd_parse_partitions(fun->dev, flash_np, &fun->parts);
	202	if (ret < 0)
	203	goto err;
	204	}
95ebffd7	205	#endif
5c249c5a	206	if (ret > 0)
95ebffd7 AV	207	ret = add_mtd_partitions(&fun->mtd, fun->parts, ret);
95ebffd7 AV	208	else
5c249c5a	209	#endif
95ebffd7 AV	210	ret = add_mtd_device(&fun->mtd);
	211	err:
	212	of_node_put(flash_np);
	213	return ret;
5c249c5a AV	214	}
	215
	216	static int __devinit fun_probe(struct of_device *ofdev,
	217	const struct of_device_id *ofid)
	218	{
	219	struct fsl_upm_nand *fun;
	220	struct resource io_res;
	221	const uint32_t *prop;
b6e0e8c0	222	int rnb_gpio;
5c249c5a AV	223	int ret;
5c249c5a AV	224	int size;
b6e0e8c0	225	int i;
5c249c5a AV	226
	227	fun = kzalloc(sizeof(*fun), GFP_KERNEL);
	228	if (!fun)
	229	return -ENOMEM;
	230
	231	ret = of_address_to_resource(ofdev->node, 0, &io_res);
	232	if (ret) {
	233	dev_err(&ofdev->dev, "can't get IO base\n");
	234	goto err1;
	235	}
	236
	237	ret = fsl_upm_find(io_res.start, &fun->upm);
	238	if (ret) {
	239	dev_err(&ofdev->dev, "can't find UPM\n");
	240	goto err1;
	241	}
	242
	243	prop = of_get_property(ofdev->node, "fsl,upm-addr-offset", &size);
	244	if (!prop \|\| size != sizeof(uint32_t)) {
	245	dev_err(&ofdev->dev, "can't get UPM address offset\n");
	246	ret = -EINVAL;
b6e0e8c0	247	goto err1;
5c249c5a AV	248	}
	249	fun->upm_addr_offset = *prop;
	250
	251	prop = of_get_property(ofdev->node, "fsl,upm-cmd-offset", &size);
	252	if (!prop \|\| size != sizeof(uint32_t)) {
	253	dev_err(&ofdev->dev, "can't get UPM command offset\n");
	254	ret = -EINVAL;
b6e0e8c0	255	goto err1;
5c249c5a AV	256	}
	257	fun->upm_cmd_offset = *prop;
	258
b6e0e8c0 WG	259	prop = of_get_property(ofdev->node,
	260	"fsl,upm-addr-line-cs-offsets", &size);
	261	if (prop && (size / sizeof(uint32_t)) > 0) {
	262	fun->mchip_count = size / sizeof(uint32_t);
	263	if (fun->mchip_count >= NAND_MAX_CHIPS) {
	264	dev_err(&ofdev->dev, "too much multiple chips\n");
	265	goto err1;
	266	}
	267	for (i = 0; i < fun->mchip_count; i++)
	268	fun->mchip_offsets[i] = prop[i];
	269	} else {
	270	fun->mchip_count = 1;
	271	}
	272
	273	for (i = 0; i < fun->mchip_count; i++) {
	274	fun->rnb_gpio[i] = -1;
	275	rnb_gpio = of_get_gpio(ofdev->node, i);
	276	if (rnb_gpio >= 0) {
	277	ret = gpio_request(rnb_gpio, dev_name(&ofdev->dev));
	278	if (ret) {
	279	dev_err(&ofdev->dev,
	280	"can't request RNB gpio #%d\n", i);
	281	goto err2;
	282	}
	283	gpio_direction_input(rnb_gpio);
	284	fun->rnb_gpio[i] = rnb_gpio;
	285	} else if (rnb_gpio == -EINVAL) {
	286	dev_err(&ofdev->dev, "RNB gpio #%d is invalid\n", i);
5c249c5a AV	287	goto err2;
5c249c5a AV	288	}
5c249c5a AV	289	}
5c249c5a AV	290
13f53697 WG	291	prop = of_get_property(ofdev->node, "chip-delay", NULL);
	292	if (prop)
	293	fun->chip_delay = *prop;
	294	else
	295	fun->chip_delay = 50;
	296
ade92a63 WG	297	prop = of_get_property(ofdev->node, "fsl,upm-wait-flags", &size);
	298	if (prop && size == sizeof(uint32_t))
	299	fun->wait_flags = *prop;
	300	else
	301	fun->wait_flags = FSL_UPM_WAIT_RUN_PATTERN \|
	302	FSL_UPM_WAIT_WRITE_BYTE;
	303
5c249c5a	304	fun->io_base = devm_ioremap_nocache(&ofdev->dev, io_res.start,
b6e0e8c0	305	io_res.end - io_res.start + 1);
5c249c5a AV	306	if (!fun->io_base) {
	307	ret = -ENOMEM;
	308	goto err2;
	309	}
	310
	311	fun->dev = &ofdev->dev;
	312	fun->last_ctrl = NAND_CLE;
5c249c5a	313
95ebffd7	314	ret = fun_chip_init(fun, ofdev->node, &io_res);
5c249c5a AV	315	if (ret)
	316	goto err2;
	317
	318	dev_set_drvdata(&ofdev->dev, fun);
	319
	320	return 0;
	321	err2:
b6e0e8c0 WG	322	for (i = 0; i < fun->mchip_count; i++) {
	323	if (fun->rnb_gpio[i] < 0)
	324	break;
	325	gpio_free(fun->rnb_gpio[i]);
	326	}
5c249c5a AV	327	err1:
	328	kfree(fun);
	329
	330	return ret;
	331	}
	332
	333	static int __devexit fun_remove(struct of_device *ofdev)
	334	{
	335	struct fsl_upm_nand *fun = dev_get_drvdata(&ofdev->dev);
b6e0e8c0	336	int i;
5c249c5a AV	337
5c249c5a AV	338	nand_release(&fun->mtd);
95ebffd7	339	kfree(fun->mtd.name);
5c249c5a	340
b6e0e8c0 WG	341	for (i = 0; i < fun->mchip_count; i++) {
	342	if (fun->rnb_gpio[i] < 0)
	343	break;
	344	gpio_free(fun->rnb_gpio[i]);
	345	}
5c249c5a AV	346
	347	kfree(fun);
	348
	349	return 0;
	350	}
	351
	352	static struct of_device_id of_fun_match[] = {
	353	{ .compatible = "fsl,upm-nand" },
	354	{},
	355	};
	356	MODULE_DEVICE_TABLE(of, of_fun_match);
	357
	358	static struct of_platform_driver of_fun_driver = {
	359	.name = "fsl,upm-nand",
	360	.match_table = of_fun_match,
	361	.probe = fun_probe,
	362	.remove = __devexit_p(fun_remove),
	363	};
	364
	365	static int __init fun_module_init(void)
	366	{
	367	return of_register_platform_driver(&of_fun_driver);
	368	}
	369	module_init(fun_module_init);
	370
	371	static void __exit fun_module_exit(void)
	372	{
	373	of_unregister_platform_driver(&of_fun_driver);
	374	}
	375	module_exit(fun_module_exit);
	376
	377	MODULE_LICENSE("GPL");
	378	MODULE_AUTHOR("Anton Vorontsov <avorontsov@ru.mvista.com>");
	379	MODULE_DESCRIPTION("Driver for NAND chips working through Freescale "
	380	"LocalBus User-Programmable Machine");