[deliverable/linux.git] / drivers / mtd / nand / gpmi-nand / gpmi-nand.h

/*
 * Freescale GPMI NAND Flash Driver
 *
 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
 * Copyright (C) 2008 Embedded Alley Solutions, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
#ifndef __DRIVERS_MTD_NAND_GPMI_NAND_H
#define __DRIVERS_MTD_NAND_GPMI_NAND_H

#include <linux/mtd/nand.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>

#define GPMI_CLK_MAX 5 /* MX6Q needs five clocks */
struct resources {
	void __iomem  *gpmi_regs;
	void __iomem  *bch_regs;
	unsigned int  dma_low_channel;
	unsigned int  dma_high_channel;
	struct clk    *clock[GPMI_CLK_MAX];
};

/**
 * struct bch_geometry - BCH geometry description.
 * @gf_len:                   The length of Galois Field. (e.g., 13 or 14)
 * @ecc_strength:             A number that describes the strength of the ECC
 *                            algorithm.
 * @page_size:                The size, in bytes, of a physical page, including
 *                            both data and OOB.
 * @metadata_size:            The size, in bytes, of the metadata.
 * @ecc_chunk_size:           The size, in bytes, of a single ECC chunk. Note
 *                            the first chunk in the page includes both data and
 *                            metadata, so it's a bit larger than this value.
 * @ecc_chunk_count:          The number of ECC chunks in the page,
 * @payload_size:             The size, in bytes, of the payload buffer.
 * @auxiliary_size:           The size, in bytes, of the auxiliary buffer.
 * @auxiliary_status_offset:  The offset into the auxiliary buffer at which
 *                            the ECC status appears.
 * @block_mark_byte_offset:   The byte offset in the ECC-based page view at
 *                            which the underlying physical block mark appears.
 * @block_mark_bit_offset:    The bit offset into the ECC-based page view at
 *                            which the underlying physical block mark appears.
 */
struct bch_geometry {
	unsigned int  gf_len;
	unsigned int  ecc_strength;
	unsigned int  page_size;
	unsigned int  metadata_size;
	unsigned int  ecc_chunk_size;
	unsigned int  ecc_chunk_count;
	unsigned int  payload_size;
	unsigned int  auxiliary_size;
	unsigned int  auxiliary_status_offset;
	unsigned int  block_mark_byte_offset;
	unsigned int  block_mark_bit_offset;
};

/**
 * struct boot_rom_geometry - Boot ROM geometry description.
 * @stride_size_in_pages:        The size of a boot block stride, in pages.
 * @search_area_stride_exponent: The logarithm to base 2 of the size of a
 *                               search area in boot block strides.
 */
struct boot_rom_geometry {
	unsigned int  stride_size_in_pages;
	unsigned int  search_area_stride_exponent;
};

/* DMA operations types */
enum dma_ops_type {
	DMA_FOR_COMMAND = 1,
	DMA_FOR_READ_DATA,
	DMA_FOR_WRITE_DATA,
	DMA_FOR_READ_ECC_PAGE,
	DMA_FOR_WRITE_ECC_PAGE
};

/**
 * struct nand_timing - Fundamental timing attributes for NAND.
 * @data_setup_in_ns:         The data setup time, in nanoseconds. Usually the
 *                            maximum of tDS and tWP. A negative value
 *                            indicates this characteristic isn't known.
 * @data_hold_in_ns:          The data hold time, in nanoseconds. Usually the
 *                            maximum of tDH, tWH and tREH. A negative value
 *                            indicates this characteristic isn't known.
 * @address_setup_in_ns:      The address setup time, in nanoseconds. Usually
 *                            the maximum of tCLS, tCS and tALS. A negative
 *                            value indicates this characteristic isn't known.
 * @gpmi_sample_delay_in_ns:  A GPMI-specific timing parameter. A negative value
 *                            indicates this characteristic isn't known.
 * @tREA_in_ns:               tREA, in nanoseconds, from the data sheet. A
 *                            negative value indicates this characteristic isn't
 *                            known.
 * @tRLOH_in_ns:              tRLOH, in nanoseconds, from the data sheet. A
 *                            negative value indicates this characteristic isn't
 *                            known.
 * @tRHOH_in_ns:              tRHOH, in nanoseconds, from the data sheet. A
 *                            negative value indicates this characteristic isn't
 *                            known.
 */
struct nand_timing {
	int8_t  data_setup_in_ns;
	int8_t  data_hold_in_ns;
	int8_t  address_setup_in_ns;
	int8_t  gpmi_sample_delay_in_ns;
	int8_t  tREA_in_ns;
	int8_t  tRLOH_in_ns;
	int8_t  tRHOH_in_ns;
};

enum gpmi_type {
	IS_MX23,
	IS_MX28,
	IS_MX6Q,
	IS_MX6SX
};

struct gpmi_devdata {
	enum gpmi_type type;
	int bch_max_ecc_strength;
	int max_chain_delay; /* See the async EDO mode */
};

struct gpmi_nand_data {
	/* flags */
#define GPMI_ASYNC_EDO_ENABLED	(1 << 0)
#define GPMI_TIMING_INIT_OK	(1 << 1)
	int			flags;
	const struct gpmi_devdata *devdata;

	/* System Interface */
	struct device		*dev;
	struct platform_device	*pdev;

	/* Resources */
	struct resources	resources;

	/* Flash Hardware */
	struct nand_timing	timing;
	int			timing_mode;

	/* BCH */
	struct bch_geometry	bch_geometry;
	struct completion	bch_done;

	/* NAND Boot issue */
	bool			swap_block_mark;
	struct boot_rom_geometry rom_geometry;

	/* MTD / NAND */
	struct nand_chip	nand;

	/* General-use Variables */
	int			current_chip;
	unsigned int		command_length;

	/* passed from upper layer */
	uint8_t			*upper_buf;
	int			upper_len;

	/* for DMA operations */
	bool			direct_dma_map_ok;

	struct scatterlist	cmd_sgl;
	char			*cmd_buffer;

	struct scatterlist	data_sgl;
	char			*data_buffer_dma;

	void			*page_buffer_virt;
	dma_addr_t		page_buffer_phys;
	unsigned int		page_buffer_size;

	void			*payload_virt;
	dma_addr_t		payload_phys;

	void			*auxiliary_virt;
	dma_addr_t		auxiliary_phys;

	void			*raw_buffer;

	/* DMA channels */
#define DMA_CHANS		8
	struct dma_chan		*dma_chans[DMA_CHANS];
	enum dma_ops_type	last_dma_type;
	enum dma_ops_type	dma_type;
	struct completion	dma_done;

	/* private */
	void			*private;
};

/**
 * struct gpmi_nfc_hardware_timing - GPMI hardware timing parameters.
 * @data_setup_in_cycles:      The data setup time, in cycles.
 * @data_hold_in_cycles:       The data hold time, in cycles.
 * @address_setup_in_cycles:   The address setup time, in cycles.
 * @device_busy_timeout:       The timeout waiting for NAND Ready/Busy,
 *                             this value is the number of cycles multiplied
 *                             by 4096.
 * @use_half_periods:          Indicates the clock is running slowly, so the
 *                             NFC DLL should use half-periods.
 * @sample_delay_factor:       The sample delay factor.
 * @wrn_dly_sel:               The delay on the GPMI write strobe.
 */
struct gpmi_nfc_hardware_timing {
	/* for HW_GPMI_TIMING0 */
	uint8_t  data_setup_in_cycles;
	uint8_t  data_hold_in_cycles;
	uint8_t  address_setup_in_cycles;

	/* for HW_GPMI_TIMING1 */
	uint16_t device_busy_timeout;
#define GPMI_DEFAULT_BUSY_TIMEOUT	0x500 /* default busy timeout value.*/

	/* for HW_GPMI_CTRL1 */
	bool     use_half_periods;
	uint8_t  sample_delay_factor;
	uint8_t  wrn_dly_sel;
};

/**
 * struct timing_threshod - Timing threshold
 * @max_data_setup_cycles:       The maximum number of data setup cycles that
 *                               can be expressed in the hardware.
 * @internal_data_setup_in_ns:   The time, in ns, that the NFC hardware requires
 *                               for data read internal setup. In the Reference
 *                               Manual, see the chapter "High-Speed NAND
 *                               Timing" for more details.
 * @max_sample_delay_factor:     The maximum sample delay factor that can be
 *                               expressed in the hardware.
 * @max_dll_clock_period_in_ns:  The maximum period of the GPMI clock that the
 *                               sample delay DLL hardware can possibly work
 *                               with (the DLL is unusable with longer periods).
 *                               If the full-cycle period is greater than HALF
 *                               this value, the DLL must be configured to use
 *                               half-periods.
 * @max_dll_delay_in_ns:         The maximum amount of delay, in ns, that the
 *                               DLL can implement.
 * @clock_frequency_in_hz:       The clock frequency, in Hz, during the current
 *                               I/O transaction. If no I/O transaction is in
 *                               progress, this is the clock frequency during
 *                               the most recent I/O transaction.
 */
struct timing_threshod {
	const unsigned int      max_chip_count;
	const unsigned int      max_data_setup_cycles;
	const unsigned int      internal_data_setup_in_ns;
	const unsigned int      max_sample_delay_factor;
	const unsigned int      max_dll_clock_period_in_ns;
	const unsigned int      max_dll_delay_in_ns;
	unsigned long           clock_frequency_in_hz;

};

/* Common Services */
extern int common_nfc_set_geometry(struct gpmi_nand_data *);
extern struct dma_chan *get_dma_chan(struct gpmi_nand_data *);
extern void prepare_data_dma(struct gpmi_nand_data *,
				enum dma_data_direction dr);
extern int start_dma_without_bch_irq(struct gpmi_nand_data *,
				struct dma_async_tx_descriptor *);
extern int start_dma_with_bch_irq(struct gpmi_nand_data *,
				struct dma_async_tx_descriptor *);

/* GPMI-NAND helper function library */
extern int gpmi_init(struct gpmi_nand_data *);
extern int gpmi_extra_init(struct gpmi_nand_data *);
extern void gpmi_clear_bch(struct gpmi_nand_data *);
extern void gpmi_dump_info(struct gpmi_nand_data *);
extern int bch_set_geometry(struct gpmi_nand_data *);
extern int gpmi_is_ready(struct gpmi_nand_data *, unsigned chip);
extern int gpmi_send_command(struct gpmi_nand_data *);
extern void gpmi_begin(struct gpmi_nand_data *);
extern void gpmi_end(struct gpmi_nand_data *);
extern int gpmi_read_data(struct gpmi_nand_data *);
extern int gpmi_send_data(struct gpmi_nand_data *);
extern int gpmi_send_page(struct gpmi_nand_data *,
			dma_addr_t payload, dma_addr_t auxiliary);
extern int gpmi_read_page(struct gpmi_nand_data *,
			dma_addr_t payload, dma_addr_t auxiliary);

void gpmi_copy_bits(u8 *dst, size_t dst_bit_off,
		    const u8 *src, size_t src_bit_off,
		    size_t nbits);

/* BCH : Status Block Completion Codes */
#define STATUS_GOOD		0x00
#define STATUS_ERASED		0xff
#define STATUS_UNCORRECTABLE	0xfe

/* Use the devdata to distinguish different Archs. */
#define GPMI_IS_MX23(x)		((x)->devdata->type == IS_MX23)
#define GPMI_IS_MX28(x)		((x)->devdata->type == IS_MX28)
#define GPMI_IS_MX6Q(x)		((x)->devdata->type == IS_MX6Q)
#define GPMI_IS_MX6SX(x)	((x)->devdata->type == IS_MX6SX)

#define GPMI_IS_MX6(x)		(GPMI_IS_MX6Q(x) || GPMI_IS_MX6SX(x))
#endif
Commit	Line	Data
10a2bcae HS	1	/*
	2	* Freescale GPMI NAND Flash Driver
	3	*
	4	* Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
	5	* Copyright (C) 2008 Embedded Alley Solutions, Inc.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*/
	17	#ifndef __DRIVERS_MTD_NAND_GPMI_NAND_H
	18	#define __DRIVERS_MTD_NAND_GPMI_NAND_H
	19
	20	#include <linux/mtd/nand.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/dma-mapping.h>
5fac0e18	23	#include <linux/dmaengine.h>
10a2bcae	24
ff506172	25	#define GPMI_CLK_MAX 5 /* MX6Q needs five clocks */
10a2bcae	26	struct resources {
513d57e1 HS	27	void __iomem *gpmi_regs;
513d57e1 HS	28	void __iomem *bch_regs;
10a2bcae HS	29	unsigned int dma_low_channel;
10a2bcae HS	30	unsigned int dma_high_channel;
ff506172	31	struct clk *clock[GPMI_CLK_MAX];
10a2bcae HS	32	};
	33
	34	/**
	35	* struct bch_geometry - BCH geometry description.
	36	* @gf_len: The length of Galois Field. (e.g., 13 or 14)
	37	* @ecc_strength: A number that describes the strength of the ECC
	38	* algorithm.
	39	* @page_size: The size, in bytes, of a physical page, including
	40	* both data and OOB.
	41	* @metadata_size: The size, in bytes, of the metadata.
	42	* @ecc_chunk_size: The size, in bytes, of a single ECC chunk. Note
	43	* the first chunk in the page includes both data and
	44	* metadata, so it's a bit larger than this value.
	45	* @ecc_chunk_count: The number of ECC chunks in the page,
	46	* @payload_size: The size, in bytes, of the payload buffer.
	47	* @auxiliary_size: The size, in bytes, of the auxiliary buffer.
	48	* @auxiliary_status_offset: The offset into the auxiliary buffer at which
	49	* the ECC status appears.
	50	* @block_mark_byte_offset: The byte offset in the ECC-based page view at
	51	* which the underlying physical block mark appears.
	52	* @block_mark_bit_offset: The bit offset into the ECC-based page view at
	53	* which the underlying physical block mark appears.
	54	*/
	55	struct bch_geometry {
	56	unsigned int gf_len;
	57	unsigned int ecc_strength;
	58	unsigned int page_size;
	59	unsigned int metadata_size;
	60	unsigned int ecc_chunk_size;
	61	unsigned int ecc_chunk_count;
	62	unsigned int payload_size;
	63	unsigned int auxiliary_size;
	64	unsigned int auxiliary_status_offset;
	65	unsigned int block_mark_byte_offset;
	66	unsigned int block_mark_bit_offset;
	67	};
	68
	69	/**
	70	* struct boot_rom_geometry - Boot ROM geometry description.
	71	* @stride_size_in_pages: The size of a boot block stride, in pages.
	72	* @search_area_stride_exponent: The logarithm to base 2 of the size of a
	73	* search area in boot block strides.
	74	*/
	75	struct boot_rom_geometry {
	76	unsigned int stride_size_in_pages;
	77	unsigned int search_area_stride_exponent;
	78	};
	79
	80	/* DMA operations types */
	81	enum dma_ops_type {
	82	DMA_FOR_COMMAND = 1,
	83	DMA_FOR_READ_DATA,
	84	DMA_FOR_WRITE_DATA,
	85	DMA_FOR_READ_ECC_PAGE,
	86	DMA_FOR_WRITE_ECC_PAGE
	87	};
	88
	89	/**
	90	* struct nand_timing - Fundamental timing attributes for NAND.
	91	* @data_setup_in_ns: The data setup time, in nanoseconds. Usually the
	92	* maximum of tDS and tWP. A negative value
	93	* indicates this characteristic isn't known.
	94	* @data_hold_in_ns: The data hold time, in nanoseconds. Usually the
	95	* maximum of tDH, tWH and tREH. A negative value
96	* indicates this characteristic isn't known.
97	* @address_setup_in_ns: The address setup time, in nanoseconds. Usually
98	* the maximum of tCLS, tCS and tALS. A negative
99	* value indicates this characteristic isn't known.
100	* @gpmi_sample_delay_in_ns: A GPMI-specific timing parameter. A negative value
101	* indicates this characteristic isn't known.
102	* @tREA_in_ns: tREA, in nanoseconds, from the data sheet. A
103	* negative value indicates this characteristic isn't
104	* known.
105	* @tRLOH_in_ns: tRLOH, in nanoseconds, from the data sheet. A
106	* negative value indicates this characteristic isn't
107	* known.
108	* @tRHOH_in_ns: tRHOH, in nanoseconds, from the data sheet. A
109	* negative value indicates this characteristic isn't
110	* known.
111	*/
112	struct nand_timing {
113	int8_t data_setup_in_ns;
114	int8_t data_hold_in_ns;
115	int8_t address_setup_in_ns;
116	int8_t gpmi_sample_delay_in_ns;
117	int8_t tREA_in_ns;
118	int8_t tRLOH_in_ns;
119	int8_t tRHOH_in_ns;
120	};
121
6189cccb HS	122	enum gpmi_type {
	123	IS_MX23,
	124	IS_MX28,
91f5498e HS	125	IS_MX6Q,
91f5498e HS	126	IS_MX6SX
6189cccb HS	127	};
	128
	129	struct gpmi_devdata {
	130	enum gpmi_type type;
	131	int bch_max_ecc_strength;
	132	int max_chain_delay; /* See the async EDO mode */
	133	};
	134
10a2bcae	135	struct gpmi_nand_data {
995fbbf5 HS	136	/* flags */
995fbbf5 HS	137	#define GPMI_ASYNC_EDO_ENABLED (1 << 0)
9c95f11b	138	#define GPMI_TIMING_INIT_OK (1 << 1)
995fbbf5	139	int flags;
6189cccb	140	const struct gpmi_devdata *devdata;
995fbbf5	141
10a2bcae HS	142	/* System Interface */
	143	struct device *dev;
	144	struct platform_device *pdev;
10a2bcae HS	145
	146	/* Resources */
	147	struct resources resources;
	148
	149	/* Flash Hardware */
	150	struct nand_timing timing;
995fbbf5	151	int timing_mode;
10a2bcae HS	152
	153	/* BCH */
	154	struct bch_geometry bch_geometry;
	155	struct completion bch_done;
	156
	157	/* NAND Boot issue */
	158	bool swap_block_mark;
	159	struct boot_rom_geometry rom_geometry;
	160
	161	/* MTD / NAND */
	162	struct nand_chip nand;
10a2bcae HS	163
	164	/* General-use Variables */
	165	int current_chip;
	166	unsigned int command_length;
	167
	168	/* passed from upper layer */
	169	uint8_t *upper_buf;
	170	int upper_len;
	171
	172	/* for DMA operations */
	173	bool direct_dma_map_ok;
	174
	175	struct scatterlist cmd_sgl;
	176	char *cmd_buffer;
	177
	178	struct scatterlist data_sgl;
	179	char *data_buffer_dma;
	180
	181	void *page_buffer_virt;
	182	dma_addr_t page_buffer_phys;
	183	unsigned int page_buffer_size;
	184
	185	void *payload_virt;
	186	dma_addr_t payload_phys;
	187
	188	void *auxiliary_virt;
	189	dma_addr_t auxiliary_phys;
	190
da3bc42c BB	191	void *raw_buffer;
da3bc42c BB	192
10a2bcae HS	193	/* DMA channels */
	194	#define DMA_CHANS 8
	195	struct dma_chan *dma_chans[DMA_CHANS];
10a2bcae HS	196	enum dma_ops_type last_dma_type;
	197	enum dma_ops_type dma_type;
	198	struct completion dma_done;
	199
	200	/* private */
	201	void *private;
	202	};
	203
	204	/**
	205	* struct gpmi_nfc_hardware_timing - GPMI hardware timing parameters.
	206	* @data_setup_in_cycles: The data setup time, in cycles.
	207	* @data_hold_in_cycles: The data hold time, in cycles.
	208	* @address_setup_in_cycles: The address setup time, in cycles.
ddab3838 HS	209	* @device_busy_timeout: The timeout waiting for NAND Ready/Busy,
	210	* this value is the number of cycles multiplied
	211	* by 4096.
10a2bcae HS	212	* @use_half_periods: Indicates the clock is running slowly, so the
	213	* NFC DLL should use half-periods.
	214	* @sample_delay_factor: The sample delay factor.
d37e02d8	215	* @wrn_dly_sel: The delay on the GPMI write strobe.
10a2bcae HS	216	*/
10a2bcae HS	217	struct gpmi_nfc_hardware_timing {
ddab3838	218	/* for HW_GPMI_TIMING0 */
10a2bcae HS	219	uint8_t data_setup_in_cycles;
	220	uint8_t data_hold_in_cycles;
	221	uint8_t address_setup_in_cycles;
ddab3838 HS	222
	223	/* for HW_GPMI_TIMING1 */
	224	uint16_t device_busy_timeout;
	225	#define GPMI_DEFAULT_BUSY_TIMEOUT 0x500 /* default busy timeout value.*/
	226
	227	/* for HW_GPMI_CTRL1 */
10a2bcae HS	228	bool use_half_periods;
10a2bcae HS	229	uint8_t sample_delay_factor;
d37e02d8	230	uint8_t wrn_dly_sel;
10a2bcae HS	231	};
	232
	233	/**
	234	* struct timing_threshod - Timing threshold
	235	* @max_data_setup_cycles: The maximum number of data setup cycles that
	236	* can be expressed in the hardware.
	237	* @internal_data_setup_in_ns: The time, in ns, that the NFC hardware requires
	238	* for data read internal setup. In the Reference
	239	* Manual, see the chapter "High-Speed NAND
	240	* Timing" for more details.
	241	* @max_sample_delay_factor: The maximum sample delay factor that can be
	242	* expressed in the hardware.
	243	* @max_dll_clock_period_in_ns: The maximum period of the GPMI clock that the
	244	* sample delay DLL hardware can possibly work
	245	* with (the DLL is unusable with longer periods).
	246	* If the full-cycle period is greater than HALF
	247	* this value, the DLL must be configured to use
	248	* half-periods.
	249	* @max_dll_delay_in_ns: The maximum amount of delay, in ns, that the
	250	* DLL can implement.
	251	* @clock_frequency_in_hz: The clock frequency, in Hz, during the current
	252	* I/O transaction. If no I/O transaction is in
	253	* progress, this is the clock frequency during
	254	* the most recent I/O transaction.
	255	*/
	256	struct timing_threshod {
	257	const unsigned int max_chip_count;
	258	const unsigned int max_data_setup_cycles;
	259	const unsigned int internal_data_setup_in_ns;
	260	const unsigned int max_sample_delay_factor;
	261	const unsigned int max_dll_clock_period_in_ns;
	262	const unsigned int max_dll_delay_in_ns;
	263	unsigned long clock_frequency_in_hz;
	264
	265	};
	266
	267	/* Common Services */
	268	extern int common_nfc_set_geometry(struct gpmi_nand_data *);
	269	extern struct dma_chan get_dma_chan(struct gpmi_nand_data );
	270	extern void prepare_data_dma(struct gpmi_nand_data *,
	271	enum dma_data_direction dr);
	272	extern int start_dma_without_bch_irq(struct gpmi_nand_data *,
	273	struct dma_async_tx_descriptor *);
	274	extern int start_dma_with_bch_irq(struct gpmi_nand_data *,
	275	struct dma_async_tx_descriptor *);
	276
	277	/* GPMI-NAND helper function library */
	278	extern int gpmi_init(struct gpmi_nand_data *);
995fbbf5	279	extern int gpmi_extra_init(struct gpmi_nand_data *);
10a2bcae HS	280	extern void gpmi_clear_bch(struct gpmi_nand_data *);
	281	extern void gpmi_dump_info(struct gpmi_nand_data *);
	282	extern int bch_set_geometry(struct gpmi_nand_data *);
	283	extern int gpmi_is_ready(struct gpmi_nand_data *, unsigned chip);
	284	extern int gpmi_send_command(struct gpmi_nand_data *);
	285	extern void gpmi_begin(struct gpmi_nand_data *);
	286	extern void gpmi_end(struct gpmi_nand_data *);
	287	extern int gpmi_read_data(struct gpmi_nand_data *);
	288	extern int gpmi_send_data(struct gpmi_nand_data *);
	289	extern int gpmi_send_page(struct gpmi_nand_data *,
	290	dma_addr_t payload, dma_addr_t auxiliary);
	291	extern int gpmi_read_page(struct gpmi_nand_data *,
	292	dma_addr_t payload, dma_addr_t auxiliary);
	293
66de54a7 BB	294	void gpmi_copy_bits(u8 *dst, size_t dst_bit_off,
	295	const u8 *src, size_t src_bit_off,
	296	size_t nbits);
	297
10a2bcae HS	298	/* BCH : Status Block Completion Codes */
	299	#define STATUS_GOOD 0x00
	300	#define STATUS_ERASED 0xff
	301	#define STATUS_UNCORRECTABLE 0xfe
	302
6189cccb HS	303	/* Use the devdata to distinguish different Archs. */
	304	#define GPMI_IS_MX23(x) ((x)->devdata->type == IS_MX23)
	305	#define GPMI_IS_MX28(x) ((x)->devdata->type == IS_MX28)
	306	#define GPMI_IS_MX6Q(x) ((x)->devdata->type == IS_MX6Q)
91f5498e HS	307	#define GPMI_IS_MX6SX(x) ((x)->devdata->type == IS_MX6SX)
	308
	309	#define GPMI_IS_MX6(x) (GPMI_IS_MX6Q(x) \|\| GPMI_IS_MX6SX(x))
10a2bcae	310	#endif