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ba01d6ec LPC |
1 | /* |
2 | * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de> | |
3 | * JZ4740 SoC NAND controller driver | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License as published by the | |
7 | * Free Software Foundation; either version 2 of the License, or (at your | |
8 | * option) any later version. | |
9 | * | |
10 | * You should have received a copy of the GNU General Public License along | |
11 | * with this program; if not, write to the Free Software Foundation, Inc., | |
12 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
13 | * | |
14 | */ | |
15 | ||
16 | #include <linux/ioport.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/platform_device.h> | |
20 | #include <linux/slab.h> | |
21 | ||
22 | #include <linux/mtd/mtd.h> | |
23 | #include <linux/mtd/nand.h> | |
24 | #include <linux/mtd/partitions.h> | |
25 | ||
26 | #include <linux/gpio.h> | |
27 | ||
28 | #include <asm/mach-jz4740/jz4740_nand.h> | |
29 | ||
30 | #define JZ_REG_NAND_CTRL 0x50 | |
31 | #define JZ_REG_NAND_ECC_CTRL 0x100 | |
32 | #define JZ_REG_NAND_DATA 0x104 | |
33 | #define JZ_REG_NAND_PAR0 0x108 | |
34 | #define JZ_REG_NAND_PAR1 0x10C | |
35 | #define JZ_REG_NAND_PAR2 0x110 | |
36 | #define JZ_REG_NAND_IRQ_STAT 0x114 | |
37 | #define JZ_REG_NAND_IRQ_CTRL 0x118 | |
38 | #define JZ_REG_NAND_ERR(x) (0x11C + ((x) << 2)) | |
39 | ||
40 | #define JZ_NAND_ECC_CTRL_PAR_READY BIT(4) | |
41 | #define JZ_NAND_ECC_CTRL_ENCODING BIT(3) | |
42 | #define JZ_NAND_ECC_CTRL_RS BIT(2) | |
43 | #define JZ_NAND_ECC_CTRL_RESET BIT(1) | |
44 | #define JZ_NAND_ECC_CTRL_ENABLE BIT(0) | |
45 | ||
46 | #define JZ_NAND_STATUS_ERR_COUNT (BIT(31) | BIT(30) | BIT(29)) | |
47 | #define JZ_NAND_STATUS_PAD_FINISH BIT(4) | |
48 | #define JZ_NAND_STATUS_DEC_FINISH BIT(3) | |
49 | #define JZ_NAND_STATUS_ENC_FINISH BIT(2) | |
50 | #define JZ_NAND_STATUS_UNCOR_ERROR BIT(1) | |
51 | #define JZ_NAND_STATUS_ERROR BIT(0) | |
52 | ||
53 | #define JZ_NAND_CTRL_ENABLE_CHIP(x) BIT((x) << 1) | |
54 | #define JZ_NAND_CTRL_ASSERT_CHIP(x) BIT(((x) << 1) + 1) | |
55 | ||
56 | #define JZ_NAND_MEM_ADDR_OFFSET 0x10000 | |
57 | #define JZ_NAND_MEM_CMD_OFFSET 0x08000 | |
58 | ||
59 | struct jz_nand { | |
60 | struct mtd_info mtd; | |
61 | struct nand_chip chip; | |
62 | void __iomem *base; | |
63 | struct resource *mem; | |
64 | ||
65 | void __iomem *bank_base; | |
66 | struct resource *bank_mem; | |
67 | ||
68 | struct jz_nand_platform_data *pdata; | |
69 | bool is_reading; | |
70 | }; | |
71 | ||
72 | static inline struct jz_nand *mtd_to_jz_nand(struct mtd_info *mtd) | |
73 | { | |
74 | return container_of(mtd, struct jz_nand, mtd); | |
75 | } | |
76 | ||
77 | static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl) | |
78 | { | |
79 | struct jz_nand *nand = mtd_to_jz_nand(mtd); | |
80 | struct nand_chip *chip = mtd->priv; | |
81 | uint32_t reg; | |
82 | ||
83 | if (ctrl & NAND_CTRL_CHANGE) { | |
84 | BUG_ON((ctrl & NAND_ALE) && (ctrl & NAND_CLE)); | |
85 | if (ctrl & NAND_ALE) | |
86 | chip->IO_ADDR_W = nand->bank_base + JZ_NAND_MEM_ADDR_OFFSET; | |
87 | else if (ctrl & NAND_CLE) | |
88 | chip->IO_ADDR_W = nand->bank_base + JZ_NAND_MEM_CMD_OFFSET; | |
89 | else | |
90 | chip->IO_ADDR_W = nand->bank_base; | |
91 | ||
92 | reg = readl(nand->base + JZ_REG_NAND_CTRL); | |
93 | if (ctrl & NAND_NCE) | |
94 | reg |= JZ_NAND_CTRL_ASSERT_CHIP(0); | |
95 | else | |
96 | reg &= ~JZ_NAND_CTRL_ASSERT_CHIP(0); | |
97 | writel(reg, nand->base + JZ_REG_NAND_CTRL); | |
98 | } | |
99 | if (dat != NAND_CMD_NONE) | |
100 | writeb(dat, chip->IO_ADDR_W); | |
101 | } | |
102 | ||
103 | static int jz_nand_dev_ready(struct mtd_info *mtd) | |
104 | { | |
105 | struct jz_nand *nand = mtd_to_jz_nand(mtd); | |
106 | return gpio_get_value_cansleep(nand->pdata->busy_gpio); | |
107 | } | |
108 | ||
109 | static void jz_nand_hwctl(struct mtd_info *mtd, int mode) | |
110 | { | |
111 | struct jz_nand *nand = mtd_to_jz_nand(mtd); | |
112 | uint32_t reg; | |
113 | ||
114 | writel(0, nand->base + JZ_REG_NAND_IRQ_STAT); | |
115 | reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL); | |
116 | ||
117 | reg |= JZ_NAND_ECC_CTRL_RESET; | |
118 | reg |= JZ_NAND_ECC_CTRL_ENABLE; | |
119 | reg |= JZ_NAND_ECC_CTRL_RS; | |
120 | ||
121 | switch (mode) { | |
122 | case NAND_ECC_READ: | |
123 | reg &= ~JZ_NAND_ECC_CTRL_ENCODING; | |
124 | nand->is_reading = true; | |
125 | break; | |
126 | case NAND_ECC_WRITE: | |
127 | reg |= JZ_NAND_ECC_CTRL_ENCODING; | |
128 | nand->is_reading = false; | |
129 | break; | |
130 | default: | |
131 | break; | |
132 | } | |
133 | ||
134 | writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL); | |
135 | } | |
136 | ||
137 | static int jz_nand_calculate_ecc_rs(struct mtd_info *mtd, const uint8_t *dat, | |
138 | uint8_t *ecc_code) | |
139 | { | |
140 | struct jz_nand *nand = mtd_to_jz_nand(mtd); | |
141 | uint32_t reg, status; | |
142 | int i; | |
143 | unsigned int timeout = 1000; | |
144 | static uint8_t empty_block_ecc[] = {0xcd, 0x9d, 0x90, 0x58, 0xf4, | |
145 | 0x8b, 0xff, 0xb7, 0x6f}; | |
146 | ||
147 | if (nand->is_reading) | |
148 | return 0; | |
149 | ||
150 | do { | |
151 | status = readl(nand->base + JZ_REG_NAND_IRQ_STAT); | |
152 | } while (!(status & JZ_NAND_STATUS_ENC_FINISH) && --timeout); | |
153 | ||
154 | if (timeout == 0) | |
155 | return -1; | |
156 | ||
157 | reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL); | |
158 | reg &= ~JZ_NAND_ECC_CTRL_ENABLE; | |
159 | writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL); | |
160 | ||
161 | for (i = 0; i < 9; ++i) | |
162 | ecc_code[i] = readb(nand->base + JZ_REG_NAND_PAR0 + i); | |
163 | ||
164 | /* If the written data is completly 0xff, we also want to write 0xff as | |
165 | * ecc, otherwise we will get in trouble when doing subpage writes. */ | |
166 | if (memcmp(ecc_code, empty_block_ecc, 9) == 0) | |
167 | memset(ecc_code, 0xff, 9); | |
168 | ||
169 | return 0; | |
170 | } | |
171 | ||
172 | static void jz_nand_correct_data(uint8_t *dat, int index, int mask) | |
173 | { | |
174 | int offset = index & 0x7; | |
175 | uint16_t data; | |
176 | ||
177 | index += (index >> 3); | |
178 | ||
179 | data = dat[index]; | |
180 | data |= dat[index+1] << 8; | |
181 | ||
182 | mask ^= (data >> offset) & 0x1ff; | |
183 | data &= ~(0x1ff << offset); | |
184 | data |= (mask << offset); | |
185 | ||
186 | dat[index] = data & 0xff; | |
187 | dat[index+1] = (data >> 8) & 0xff; | |
188 | } | |
189 | ||
190 | static int jz_nand_correct_ecc_rs(struct mtd_info *mtd, uint8_t *dat, | |
191 | uint8_t *read_ecc, uint8_t *calc_ecc) | |
192 | { | |
193 | struct jz_nand *nand = mtd_to_jz_nand(mtd); | |
194 | int i, error_count, index; | |
195 | uint32_t reg, status, error; | |
196 | uint32_t t; | |
197 | unsigned int timeout = 1000; | |
198 | ||
199 | t = read_ecc[0]; | |
200 | ||
201 | if (t == 0xff) { | |
202 | for (i = 1; i < 9; ++i) | |
203 | t &= read_ecc[i]; | |
204 | ||
205 | t &= dat[0]; | |
206 | t &= dat[nand->chip.ecc.size / 2]; | |
207 | t &= dat[nand->chip.ecc.size - 1]; | |
208 | ||
209 | if (t == 0xff) { | |
210 | for (i = 1; i < nand->chip.ecc.size - 1; ++i) | |
211 | t &= dat[i]; | |
212 | if (t == 0xff) | |
213 | return 0; | |
214 | } | |
215 | } | |
216 | ||
217 | for (i = 0; i < 9; ++i) | |
218 | writeb(read_ecc[i], nand->base + JZ_REG_NAND_PAR0 + i); | |
219 | ||
220 | reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL); | |
221 | reg |= JZ_NAND_ECC_CTRL_PAR_READY; | |
222 | writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL); | |
223 | ||
224 | do { | |
225 | status = readl(nand->base + JZ_REG_NAND_IRQ_STAT); | |
226 | } while (!(status & JZ_NAND_STATUS_DEC_FINISH) && --timeout); | |
227 | ||
228 | if (timeout == 0) | |
229 | return -1; | |
230 | ||
231 | reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL); | |
232 | reg &= ~JZ_NAND_ECC_CTRL_ENABLE; | |
233 | writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL); | |
234 | ||
235 | if (status & JZ_NAND_STATUS_ERROR) { | |
236 | if (status & JZ_NAND_STATUS_UNCOR_ERROR) | |
237 | return -1; | |
238 | ||
239 | error_count = (status & JZ_NAND_STATUS_ERR_COUNT) >> 29; | |
240 | ||
241 | for (i = 0; i < error_count; ++i) { | |
242 | error = readl(nand->base + JZ_REG_NAND_ERR(i)); | |
243 | index = ((error >> 16) & 0x1ff) - 1; | |
244 | if (index >= 0 && index < 512) | |
245 | jz_nand_correct_data(dat, index, error & 0x1ff); | |
246 | } | |
247 | ||
248 | return error_count; | |
249 | } | |
250 | ||
251 | return 0; | |
252 | } | |
253 | ||
ba01d6ec LPC |
254 | static int jz_nand_ioremap_resource(struct platform_device *pdev, |
255 | const char *name, struct resource **res, void __iomem **base) | |
256 | { | |
257 | int ret; | |
258 | ||
259 | *res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); | |
260 | if (!*res) { | |
261 | dev_err(&pdev->dev, "Failed to get platform %s memory\n", name); | |
262 | ret = -ENXIO; | |
263 | goto err; | |
264 | } | |
265 | ||
266 | *res = request_mem_region((*res)->start, resource_size(*res), | |
267 | pdev->name); | |
268 | if (!*res) { | |
269 | dev_err(&pdev->dev, "Failed to request %s memory region\n", name); | |
270 | ret = -EBUSY; | |
271 | goto err; | |
272 | } | |
273 | ||
274 | *base = ioremap((*res)->start, resource_size(*res)); | |
275 | if (!*base) { | |
276 | dev_err(&pdev->dev, "Failed to ioremap %s memory region\n", name); | |
277 | ret = -EBUSY; | |
278 | goto err_release_mem; | |
279 | } | |
280 | ||
281 | return 0; | |
282 | ||
283 | err_release_mem: | |
284 | release_mem_region((*res)->start, resource_size(*res)); | |
285 | err: | |
286 | *res = NULL; | |
287 | *base = NULL; | |
288 | return ret; | |
289 | } | |
290 | ||
291 | static int __devinit jz_nand_probe(struct platform_device *pdev) | |
292 | { | |
293 | int ret; | |
294 | struct jz_nand *nand; | |
295 | struct nand_chip *chip; | |
296 | struct mtd_info *mtd; | |
297 | struct jz_nand_platform_data *pdata = pdev->dev.platform_data; | |
ba01d6ec LPC |
298 | |
299 | nand = kzalloc(sizeof(*nand), GFP_KERNEL); | |
300 | if (!nand) { | |
301 | dev_err(&pdev->dev, "Failed to allocate device structure.\n"); | |
302 | return -ENOMEM; | |
303 | } | |
304 | ||
305 | ret = jz_nand_ioremap_resource(pdev, "mmio", &nand->mem, &nand->base); | |
306 | if (ret) | |
307 | goto err_free; | |
308 | ret = jz_nand_ioremap_resource(pdev, "bank", &nand->bank_mem, | |
309 | &nand->bank_base); | |
310 | if (ret) | |
311 | goto err_iounmap_mmio; | |
312 | ||
313 | if (pdata && gpio_is_valid(pdata->busy_gpio)) { | |
314 | ret = gpio_request(pdata->busy_gpio, "NAND busy pin"); | |
315 | if (ret) { | |
316 | dev_err(&pdev->dev, | |
317 | "Failed to request busy gpio %d: %d\n", | |
318 | pdata->busy_gpio, ret); | |
319 | goto err_iounmap_mem; | |
320 | } | |
321 | } | |
322 | ||
323 | mtd = &nand->mtd; | |
324 | chip = &nand->chip; | |
325 | mtd->priv = chip; | |
326 | mtd->owner = THIS_MODULE; | |
327 | mtd->name = "jz4740-nand"; | |
328 | ||
329 | chip->ecc.hwctl = jz_nand_hwctl; | |
330 | chip->ecc.calculate = jz_nand_calculate_ecc_rs; | |
331 | chip->ecc.correct = jz_nand_correct_ecc_rs; | |
332 | chip->ecc.mode = NAND_ECC_HW_OOB_FIRST; | |
333 | chip->ecc.size = 512; | |
334 | chip->ecc.bytes = 9; | |
6a918bad MD |
335 | chip->ecc.strength = 2; |
336 | /* | |
337 | * FIXME: ecc_strength value of 2 bits per 512 bytes of data is a | |
338 | * conservative guess, given 9 ecc bytes and reed-solomon alg. | |
339 | */ | |
ba01d6ec | 340 | |
ba01d6ec LPC |
341 | if (pdata) |
342 | chip->ecc.layout = pdata->ecc_layout; | |
343 | ||
344 | chip->chip_delay = 50; | |
345 | chip->cmd_ctrl = jz_nand_cmd_ctrl; | |
346 | ||
347 | if (pdata && gpio_is_valid(pdata->busy_gpio)) | |
348 | chip->dev_ready = jz_nand_dev_ready; | |
349 | ||
350 | chip->IO_ADDR_R = nand->bank_base; | |
351 | chip->IO_ADDR_W = nand->bank_base; | |
352 | ||
353 | nand->pdata = pdata; | |
354 | platform_set_drvdata(pdev, nand); | |
355 | ||
356 | writel(JZ_NAND_CTRL_ENABLE_CHIP(0), nand->base + JZ_REG_NAND_CTRL); | |
357 | ||
358 | ret = nand_scan_ident(mtd, 1, NULL); | |
359 | if (ret) { | |
360 | dev_err(&pdev->dev, "Failed to scan nand\n"); | |
361 | goto err_gpio_free; | |
362 | } | |
363 | ||
364 | if (pdata && pdata->ident_callback) { | |
365 | pdata->ident_callback(pdev, chip, &pdata->partitions, | |
366 | &pdata->num_partitions); | |
367 | } | |
368 | ||
369 | ret = nand_scan_tail(mtd); | |
370 | if (ret) { | |
371 | dev_err(&pdev->dev, "Failed to scan nand\n"); | |
372 | goto err_gpio_free; | |
373 | } | |
374 | ||
42d7fbe2 AB |
375 | ret = mtd_device_parse_register(mtd, NULL, NULL, |
376 | pdata ? pdata->partitions : NULL, | |
377 | pdata ? pdata->num_partitions : 0); | |
ba01d6ec LPC |
378 | |
379 | if (ret) { | |
380 | dev_err(&pdev->dev, "Failed to add mtd device\n"); | |
381 | goto err_nand_release; | |
382 | } | |
383 | ||
384 | dev_info(&pdev->dev, "Successfully registered JZ4740 NAND driver\n"); | |
385 | ||
386 | return 0; | |
387 | ||
388 | err_nand_release: | |
389 | nand_release(&nand->mtd); | |
390 | err_gpio_free: | |
391 | platform_set_drvdata(pdev, NULL); | |
392 | gpio_free(pdata->busy_gpio); | |
393 | err_iounmap_mem: | |
394 | iounmap(nand->bank_base); | |
395 | err_iounmap_mmio: | |
396 | iounmap(nand->base); | |
397 | err_free: | |
398 | kfree(nand); | |
399 | return ret; | |
400 | } | |
401 | ||
402 | static int __devexit jz_nand_remove(struct platform_device *pdev) | |
403 | { | |
404 | struct jz_nand *nand = platform_get_drvdata(pdev); | |
405 | ||
406 | nand_release(&nand->mtd); | |
407 | ||
408 | /* Deassert and disable all chips */ | |
409 | writel(0, nand->base + JZ_REG_NAND_CTRL); | |
410 | ||
411 | iounmap(nand->bank_base); | |
412 | release_mem_region(nand->bank_mem->start, resource_size(nand->bank_mem)); | |
413 | iounmap(nand->base); | |
414 | release_mem_region(nand->mem->start, resource_size(nand->mem)); | |
415 | ||
416 | platform_set_drvdata(pdev, NULL); | |
417 | kfree(nand); | |
418 | ||
419 | return 0; | |
420 | } | |
421 | ||
a338adaf | 422 | static struct platform_driver jz_nand_driver = { |
ba01d6ec LPC |
423 | .probe = jz_nand_probe, |
424 | .remove = __devexit_p(jz_nand_remove), | |
425 | .driver = { | |
426 | .name = "jz4740-nand", | |
427 | .owner = THIS_MODULE, | |
428 | }, | |
429 | }; | |
430 | ||
f99640de | 431 | module_platform_driver(jz_nand_driver); |
ba01d6ec LPC |
432 | |
433 | MODULE_LICENSE("GPL"); | |
434 | MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); | |
435 | MODULE_DESCRIPTION("NAND controller driver for JZ4740 SoC"); | |
436 | MODULE_ALIAS("platform:jz4740-nand"); |