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ae02ab00 AS |
1 | /* |
2 | * JZ4780 NAND driver | |
3 | * | |
4 | * Copyright (c) 2015 Imagination Technologies | |
5 | * Author: Alex Smith <alex.smith@imgtec.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License version 2 as published | |
9 | * by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/delay.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/list.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/of.h> | |
18 | #include <linux/of_address.h> | |
19 | #include <linux/gpio/consumer.h> | |
ae02ab00 AS |
20 | #include <linux/platform_device.h> |
21 | #include <linux/slab.h> | |
22 | #include <linux/mtd/mtd.h> | |
23 | #include <linux/mtd/nand.h> | |
24 | #include <linux/mtd/partitions.h> | |
25 | ||
26 | #include <linux/jz4780-nemc.h> | |
27 | ||
28 | #include "jz4780_bch.h" | |
29 | ||
30 | #define DRV_NAME "jz4780-nand" | |
31 | ||
32 | #define OFFSET_DATA 0x00000000 | |
33 | #define OFFSET_CMD 0x00400000 | |
34 | #define OFFSET_ADDR 0x00800000 | |
35 | ||
36 | /* Command delay when there is no R/B pin. */ | |
37 | #define RB_DELAY_US 100 | |
38 | ||
39 | struct jz4780_nand_cs { | |
40 | unsigned int bank; | |
41 | void __iomem *base; | |
42 | }; | |
43 | ||
44 | struct jz4780_nand_controller { | |
45 | struct device *dev; | |
46 | struct jz4780_bch *bch; | |
47 | struct nand_hw_control controller; | |
48 | unsigned int num_banks; | |
49 | struct list_head chips; | |
50 | int selected; | |
51 | struct jz4780_nand_cs cs[]; | |
52 | }; | |
53 | ||
54 | struct jz4780_nand_chip { | |
55 | struct nand_chip chip; | |
56 | struct list_head chip_list; | |
57 | ||
ae02ab00 AS |
58 | struct gpio_desc *busy_gpio; |
59 | struct gpio_desc *wp_gpio; | |
60 | unsigned int reading: 1; | |
61 | }; | |
62 | ||
63 | static inline struct jz4780_nand_chip *to_jz4780_nand_chip(struct mtd_info *mtd) | |
64 | { | |
65 | return container_of(mtd_to_nand(mtd), struct jz4780_nand_chip, chip); | |
66 | } | |
67 | ||
68 | static inline struct jz4780_nand_controller *to_jz4780_nand_controller(struct nand_hw_control *ctrl) | |
69 | { | |
70 | return container_of(ctrl, struct jz4780_nand_controller, controller); | |
71 | } | |
72 | ||
73 | static void jz4780_nand_select_chip(struct mtd_info *mtd, int chipnr) | |
74 | { | |
75 | struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd); | |
76 | struct jz4780_nand_controller *nfc = to_jz4780_nand_controller(nand->chip.controller); | |
77 | struct jz4780_nand_cs *cs; | |
78 | ||
79 | /* Ensure the currently selected chip is deasserted. */ | |
80 | if (chipnr == -1 && nfc->selected >= 0) { | |
81 | cs = &nfc->cs[nfc->selected]; | |
82 | jz4780_nemc_assert(nfc->dev, cs->bank, false); | |
83 | } | |
84 | ||
85 | nfc->selected = chipnr; | |
86 | } | |
87 | ||
88 | static void jz4780_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, | |
89 | unsigned int ctrl) | |
90 | { | |
91 | struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd); | |
92 | struct jz4780_nand_controller *nfc = to_jz4780_nand_controller(nand->chip.controller); | |
93 | struct jz4780_nand_cs *cs; | |
94 | ||
95 | if (WARN_ON(nfc->selected < 0)) | |
96 | return; | |
97 | ||
98 | cs = &nfc->cs[nfc->selected]; | |
99 | ||
100 | jz4780_nemc_assert(nfc->dev, cs->bank, ctrl & NAND_NCE); | |
101 | ||
102 | if (cmd == NAND_CMD_NONE) | |
103 | return; | |
104 | ||
105 | if (ctrl & NAND_ALE) | |
106 | writeb(cmd, cs->base + OFFSET_ADDR); | |
107 | else if (ctrl & NAND_CLE) | |
108 | writeb(cmd, cs->base + OFFSET_CMD); | |
109 | } | |
110 | ||
111 | static int jz4780_nand_dev_ready(struct mtd_info *mtd) | |
112 | { | |
113 | struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd); | |
114 | ||
115 | return !gpiod_get_value_cansleep(nand->busy_gpio); | |
116 | } | |
117 | ||
118 | static void jz4780_nand_ecc_hwctl(struct mtd_info *mtd, int mode) | |
119 | { | |
120 | struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd); | |
121 | ||
122 | nand->reading = (mode == NAND_ECC_READ); | |
123 | } | |
124 | ||
125 | static int jz4780_nand_ecc_calculate(struct mtd_info *mtd, const u8 *dat, | |
126 | u8 *ecc_code) | |
127 | { | |
128 | struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd); | |
129 | struct jz4780_nand_controller *nfc = to_jz4780_nand_controller(nand->chip.controller); | |
130 | struct jz4780_bch_params params; | |
131 | ||
132 | /* | |
133 | * Don't need to generate the ECC when reading, BCH does it for us as | |
134 | * part of decoding/correction. | |
135 | */ | |
136 | if (nand->reading) | |
137 | return 0; | |
138 | ||
139 | params.size = nand->chip.ecc.size; | |
140 | params.bytes = nand->chip.ecc.bytes; | |
141 | params.strength = nand->chip.ecc.strength; | |
142 | ||
143 | return jz4780_bch_calculate(nfc->bch, ¶ms, dat, ecc_code); | |
144 | } | |
145 | ||
146 | static int jz4780_nand_ecc_correct(struct mtd_info *mtd, u8 *dat, | |
147 | u8 *read_ecc, u8 *calc_ecc) | |
148 | { | |
149 | struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd); | |
150 | struct jz4780_nand_controller *nfc = to_jz4780_nand_controller(nand->chip.controller); | |
151 | struct jz4780_bch_params params; | |
152 | ||
153 | params.size = nand->chip.ecc.size; | |
154 | params.bytes = nand->chip.ecc.bytes; | |
155 | params.strength = nand->chip.ecc.strength; | |
156 | ||
157 | return jz4780_bch_correct(nfc->bch, ¶ms, dat, read_ecc); | |
158 | } | |
159 | ||
160 | static int jz4780_nand_init_ecc(struct jz4780_nand_chip *nand, struct device *dev) | |
161 | { | |
162 | struct nand_chip *chip = &nand->chip; | |
163 | struct mtd_info *mtd = nand_to_mtd(chip); | |
164 | struct jz4780_nand_controller *nfc = to_jz4780_nand_controller(chip->controller); | |
36886be7 | 165 | int eccbytes; |
ae02ab00 AS |
166 | |
167 | chip->ecc.bytes = fls((1 + 8) * chip->ecc.size) * | |
168 | (chip->ecc.strength / 8); | |
169 | ||
9146cbd5 BN |
170 | switch (chip->ecc.mode) { |
171 | case NAND_ECC_HW: | |
172 | if (!nfc->bch) { | |
173 | dev_err(dev, "HW BCH selected, but BCH controller not found\n"); | |
174 | return -ENODEV; | |
175 | } | |
176 | ||
ae02ab00 AS |
177 | chip->ecc.hwctl = jz4780_nand_ecc_hwctl; |
178 | chip->ecc.calculate = jz4780_nand_ecc_calculate; | |
179 | chip->ecc.correct = jz4780_nand_ecc_correct; | |
9146cbd5 BN |
180 | /* fall through */ |
181 | case NAND_ECC_SOFT: | |
ae02ab00 AS |
182 | dev_info(dev, "using %s (strength %d, size %d, bytes %d)\n", |
183 | (nfc->bch) ? "hardware BCH" : "software ECC", | |
184 | chip->ecc.strength, chip->ecc.size, chip->ecc.bytes); | |
9146cbd5 BN |
185 | break; |
186 | case NAND_ECC_NONE: | |
ae02ab00 | 187 | dev_info(dev, "not using ECC\n"); |
9146cbd5 BN |
188 | break; |
189 | default: | |
190 | dev_err(dev, "ECC mode %d not supported\n", chip->ecc.mode); | |
191 | return -EINVAL; | |
192 | } | |
ae02ab00 | 193 | |
9146cbd5 BN |
194 | /* The NAND core will generate the ECC layout for SW ECC */ |
195 | if (chip->ecc.mode != NAND_ECC_HW) | |
ae02ab00 AS |
196 | return 0; |
197 | ||
198 | /* Generate ECC layout. ECC codes are right aligned in the OOB area. */ | |
36886be7 | 199 | eccbytes = mtd->writesize / chip->ecc.size * chip->ecc.bytes; |
ae02ab00 | 200 | |
36886be7 | 201 | if (eccbytes > mtd->oobsize - 2) { |
ae02ab00 AS |
202 | dev_err(dev, |
203 | "invalid ECC config: required %d ECC bytes, but only %d are available", | |
36886be7 | 204 | eccbytes, mtd->oobsize - 2); |
ae02ab00 AS |
205 | return -EINVAL; |
206 | } | |
207 | ||
36886be7 | 208 | mtd->ooblayout = &nand_ooblayout_lp_ops; |
ae02ab00 | 209 | |
ae02ab00 AS |
210 | return 0; |
211 | } | |
212 | ||
213 | static int jz4780_nand_init_chip(struct platform_device *pdev, | |
214 | struct jz4780_nand_controller *nfc, | |
215 | struct device_node *np, | |
216 | unsigned int chipnr) | |
217 | { | |
218 | struct device *dev = &pdev->dev; | |
219 | struct jz4780_nand_chip *nand; | |
220 | struct jz4780_nand_cs *cs; | |
221 | struct resource *res; | |
222 | struct nand_chip *chip; | |
223 | struct mtd_info *mtd; | |
224 | const __be32 *reg; | |
225 | int ret = 0; | |
226 | ||
227 | cs = &nfc->cs[chipnr]; | |
228 | ||
229 | reg = of_get_property(np, "reg", NULL); | |
230 | if (!reg) | |
231 | return -EINVAL; | |
232 | ||
233 | cs->bank = be32_to_cpu(*reg); | |
234 | ||
235 | jz4780_nemc_set_type(nfc->dev, cs->bank, JZ4780_NEMC_BANK_NAND); | |
236 | ||
237 | res = platform_get_resource(pdev, IORESOURCE_MEM, chipnr); | |
238 | cs->base = devm_ioremap_resource(dev, res); | |
239 | if (IS_ERR(cs->base)) | |
240 | return PTR_ERR(cs->base); | |
241 | ||
242 | nand = devm_kzalloc(dev, sizeof(*nand), GFP_KERNEL); | |
243 | if (!nand) | |
244 | return -ENOMEM; | |
245 | ||
246 | nand->busy_gpio = devm_gpiod_get_optional(dev, "rb", GPIOD_IN); | |
247 | ||
248 | if (IS_ERR(nand->busy_gpio)) { | |
249 | ret = PTR_ERR(nand->busy_gpio); | |
250 | dev_err(dev, "failed to request busy GPIO: %d\n", ret); | |
251 | return ret; | |
252 | } else if (nand->busy_gpio) { | |
253 | nand->chip.dev_ready = jz4780_nand_dev_ready; | |
254 | } | |
255 | ||
256 | nand->wp_gpio = devm_gpiod_get_optional(dev, "wp", GPIOD_OUT_LOW); | |
257 | ||
258 | if (IS_ERR(nand->wp_gpio)) { | |
259 | ret = PTR_ERR(nand->wp_gpio); | |
260 | dev_err(dev, "failed to request WP GPIO: %d\n", ret); | |
261 | return ret; | |
262 | } | |
263 | ||
264 | chip = &nand->chip; | |
265 | mtd = nand_to_mtd(chip); | |
ae02ab00 AS |
266 | mtd->name = devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), |
267 | cs->bank); | |
268 | if (!mtd->name) | |
269 | return -ENOMEM; | |
270 | mtd->dev.parent = dev; | |
271 | ||
272 | chip->IO_ADDR_R = cs->base + OFFSET_DATA; | |
273 | chip->IO_ADDR_W = cs->base + OFFSET_DATA; | |
274 | chip->chip_delay = RB_DELAY_US; | |
275 | chip->options = NAND_NO_SUBPAGE_WRITE; | |
276 | chip->select_chip = jz4780_nand_select_chip; | |
277 | chip->cmd_ctrl = jz4780_nand_cmd_ctrl; | |
278 | chip->ecc.mode = NAND_ECC_HW; | |
279 | chip->controller = &nfc->controller; | |
280 | nand_set_flash_node(chip, np); | |
281 | ||
282 | ret = nand_scan_ident(mtd, 1, NULL); | |
283 | if (ret) | |
284 | return ret; | |
285 | ||
286 | ret = jz4780_nand_init_ecc(nand, dev); | |
287 | if (ret) | |
288 | return ret; | |
289 | ||
290 | ret = nand_scan_tail(mtd); | |
291 | if (ret) | |
292 | return ret; | |
293 | ||
294 | ret = mtd_device_register(mtd, NULL, 0); | |
295 | if (ret) { | |
296 | nand_release(mtd); | |
297 | return ret; | |
298 | } | |
299 | ||
300 | list_add_tail(&nand->chip_list, &nfc->chips); | |
301 | ||
302 | return 0; | |
303 | } | |
304 | ||
305 | static void jz4780_nand_cleanup_chips(struct jz4780_nand_controller *nfc) | |
306 | { | |
307 | struct jz4780_nand_chip *chip; | |
308 | ||
309 | while (!list_empty(&nfc->chips)) { | |
310 | chip = list_first_entry(&nfc->chips, struct jz4780_nand_chip, chip_list); | |
311 | nand_release(nand_to_mtd(&chip->chip)); | |
312 | list_del(&chip->chip_list); | |
313 | } | |
314 | } | |
315 | ||
316 | static int jz4780_nand_init_chips(struct jz4780_nand_controller *nfc, | |
317 | struct platform_device *pdev) | |
318 | { | |
319 | struct device *dev = &pdev->dev; | |
320 | struct device_node *np; | |
321 | int i = 0; | |
322 | int ret; | |
323 | int num_chips = of_get_child_count(dev->of_node); | |
324 | ||
325 | if (num_chips > nfc->num_banks) { | |
326 | dev_err(dev, "found %d chips but only %d banks\n", num_chips, nfc->num_banks); | |
327 | return -EINVAL; | |
328 | } | |
329 | ||
330 | for_each_child_of_node(dev->of_node, np) { | |
331 | ret = jz4780_nand_init_chip(pdev, nfc, np, i); | |
332 | if (ret) { | |
333 | jz4780_nand_cleanup_chips(nfc); | |
334 | return ret; | |
335 | } | |
336 | ||
337 | i++; | |
338 | } | |
339 | ||
340 | return 0; | |
341 | } | |
342 | ||
343 | static int jz4780_nand_probe(struct platform_device *pdev) | |
344 | { | |
345 | struct device *dev = &pdev->dev; | |
346 | unsigned int num_banks; | |
347 | struct jz4780_nand_controller *nfc; | |
348 | int ret; | |
349 | ||
350 | num_banks = jz4780_nemc_num_banks(dev); | |
351 | if (num_banks == 0) { | |
352 | dev_err(dev, "no banks found\n"); | |
353 | return -ENODEV; | |
354 | } | |
355 | ||
356 | nfc = devm_kzalloc(dev, sizeof(*nfc) + (sizeof(nfc->cs[0]) * num_banks), GFP_KERNEL); | |
357 | if (!nfc) | |
358 | return -ENOMEM; | |
359 | ||
360 | /* | |
361 | * Check for BCH HW before we call nand_scan_ident, to prevent us from | |
362 | * having to call it again if the BCH driver returns -EPROBE_DEFER. | |
363 | */ | |
364 | nfc->bch = of_jz4780_bch_get(dev->of_node); | |
365 | if (IS_ERR(nfc->bch)) | |
366 | return PTR_ERR(nfc->bch); | |
367 | ||
368 | nfc->dev = dev; | |
369 | nfc->num_banks = num_banks; | |
370 | ||
371 | spin_lock_init(&nfc->controller.lock); | |
372 | INIT_LIST_HEAD(&nfc->chips); | |
373 | init_waitqueue_head(&nfc->controller.wq); | |
374 | ||
375 | ret = jz4780_nand_init_chips(nfc, pdev); | |
376 | if (ret) { | |
377 | if (nfc->bch) | |
378 | jz4780_bch_release(nfc->bch); | |
379 | return ret; | |
380 | } | |
381 | ||
382 | platform_set_drvdata(pdev, nfc); | |
383 | return 0; | |
384 | } | |
385 | ||
386 | static int jz4780_nand_remove(struct platform_device *pdev) | |
387 | { | |
388 | struct jz4780_nand_controller *nfc = platform_get_drvdata(pdev); | |
389 | ||
390 | if (nfc->bch) | |
391 | jz4780_bch_release(nfc->bch); | |
392 | ||
393 | jz4780_nand_cleanup_chips(nfc); | |
394 | ||
395 | return 0; | |
396 | } | |
397 | ||
398 | static const struct of_device_id jz4780_nand_dt_match[] = { | |
399 | { .compatible = "ingenic,jz4780-nand" }, | |
400 | {}, | |
401 | }; | |
402 | MODULE_DEVICE_TABLE(of, jz4780_nand_dt_match); | |
403 | ||
404 | static struct platform_driver jz4780_nand_driver = { | |
405 | .probe = jz4780_nand_probe, | |
406 | .remove = jz4780_nand_remove, | |
407 | .driver = { | |
408 | .name = DRV_NAME, | |
409 | .of_match_table = of_match_ptr(jz4780_nand_dt_match), | |
410 | }, | |
411 | }; | |
412 | module_platform_driver(jz4780_nand_driver); | |
413 | ||
414 | MODULE_AUTHOR("Alex Smith <alex@alex-smith.me.uk>"); | |
415 | MODULE_AUTHOR("Harvey Hunt <harvey.hunt@imgtec.com>"); | |
416 | MODULE_DESCRIPTION("Ingenic JZ4780 NAND driver"); | |
417 | MODULE_LICENSE("GPL v2"); |