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mtd: nand: kill NAND_NO_AUTOINCR option
[deliverable/linux.git] / drivers / mtd / nand / mpc5121_nfc.c
CommitLineData
bb315f74
AG		 1/*
2 * Copyright 2004-2008 Freescale Semiconductor, Inc.
3 * Copyright 2009 Semihalf.
4 *
5 * Approved as OSADL project by a majority of OSADL members and funded
6 * by OSADL membership fees in 2009; for details see www.osadl.org.
7 *
8 * Based on original driver from Freescale Semiconductor
9 * written by John Rigby <jrigby@freescale.com> on basis
10 * of drivers/mtd/nand/mxc_nand.c. Reworked and extended
11 * Piotr Ziecik <kosmo@semihalf.com>.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version 2
16 * of the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
25 * MA 02110-1301, USA.
26 */
27
28#include <linux/module.h>
29#include <linux/clk.h>
05d71b46 30#include <linux/gfp.h>
bb315f74 31#include <linux/delay.h>
83025c82 32#include <linux/err.h>
bb315f74
AG		 33#include <linux/init.h>
34#include <linux/interrupt.h>
35#include <linux/io.h>
36#include <linux/mtd/mtd.h>
37#include <linux/mtd/nand.h>
38#include <linux/mtd/partitions.h>
39#include <linux/of_device.h>
40#include <linux/of_platform.h>
41
42#include <asm/mpc5121.h>
43
44/* Addresses for NFC MAIN RAM BUFFER areas */
45#define NFC_MAIN_AREA(n) ((n) * 0x200)
46
47/* Addresses for NFC SPARE BUFFER areas */
48#define NFC_SPARE_BUFFERS 8
49#define NFC_SPARE_LEN 0x40
50#define NFC_SPARE_AREA(n) (0x1000 + ((n) * NFC_SPARE_LEN))
51
52/* MPC5121 NFC registers */
53#define NFC_BUF_ADDR 0x1E04
54#define NFC_FLASH_ADDR 0x1E06
55#define NFC_FLASH_CMD 0x1E08
56#define NFC_CONFIG 0x1E0A
57#define NFC_ECC_STATUS1 0x1E0C
58#define NFC_ECC_STATUS2 0x1E0E
59#define NFC_SPAS 0x1E10
60#define NFC_WRPROT 0x1E12
61#define NFC_NF_WRPRST 0x1E18
62#define NFC_CONFIG1 0x1E1A
63#define NFC_CONFIG2 0x1E1C
64#define NFC_UNLOCKSTART_BLK0 0x1E20
65#define NFC_UNLOCKEND_BLK0 0x1E22
66#define NFC_UNLOCKSTART_BLK1 0x1E24
67#define NFC_UNLOCKEND_BLK1 0x1E26
68#define NFC_UNLOCKSTART_BLK2 0x1E28
69#define NFC_UNLOCKEND_BLK2 0x1E2A
70#define NFC_UNLOCKSTART_BLK3 0x1E2C
71#define NFC_UNLOCKEND_BLK3 0x1E2E
72
73/* Bit Definitions: NFC_BUF_ADDR */
74#define NFC_RBA_MASK (7 << 0)
75#define NFC_ACTIVE_CS_SHIFT 5
76#define NFC_ACTIVE_CS_MASK (3 << NFC_ACTIVE_CS_SHIFT)
77
78/* Bit Definitions: NFC_CONFIG */
79#define NFC_BLS_UNLOCKED (1 << 1)
80
81/* Bit Definitions: NFC_CONFIG1 */
82#define NFC_ECC_4BIT (1 << 0)
83#define NFC_FULL_PAGE_DMA (1 << 1)
84#define NFC_SPARE_ONLY (1 << 2)
85#define NFC_ECC_ENABLE (1 << 3)
86#define NFC_INT_MASK (1 << 4)
87#define NFC_BIG_ENDIAN (1 << 5)
88#define NFC_RESET (1 << 6)
89#define NFC_CE (1 << 7)
90#define NFC_ONE_CYCLE (1 << 8)
91#define NFC_PPB_32 (0 << 9)
92#define NFC_PPB_64 (1 << 9)
93#define NFC_PPB_128 (2 << 9)
94#define NFC_PPB_256 (3 << 9)
95#define NFC_PPB_MASK (3 << 9)
96#define NFC_FULL_PAGE_INT (1 << 11)
97
98/* Bit Definitions: NFC_CONFIG2 */
99#define NFC_COMMAND (1 << 0)
100#define NFC_ADDRESS (1 << 1)
101#define NFC_INPUT (1 << 2)
102#define NFC_OUTPUT (1 << 3)
103#define NFC_ID (1 << 4)
104#define NFC_STATUS (1 << 5)
105#define NFC_CMD_FAIL (1 << 15)
106#define NFC_INT (1 << 15)
107
108/* Bit Definitions: NFC_WRPROT */
109#define NFC_WPC_LOCK_TIGHT (1 << 0)
110#define NFC_WPC_LOCK (1 << 1)
111#define NFC_WPC_UNLOCK (1 << 2)
112
113#define DRV_NAME "mpc5121_nfc"
114
115/* Timeouts */
116#define NFC_RESET_TIMEOUT 1000 /* 1 ms */
117#define NFC_TIMEOUT (HZ / 10) /* 1/10 s */
118
119struct mpc5121_nfc_prv {
120 struct mtd_info mtd;
121 struct nand_chip chip;
122 int irq;
123 void __iomem *regs;
124 struct clk *clk;
125 wait_queue_head_t irq_waitq;
126 uint column;
127 int spareonly;
128 void __iomem *csreg;
129 struct device *dev;
130};
131
132static void mpc5121_nfc_done(struct mtd_info *mtd);
133
bb315f74
AG		 134/* Read NFC register */
135static inline u16 nfc_read(struct mtd_info *mtd, uint reg)
136{
137 struct nand_chip *chip = mtd->priv;
138 struct mpc5121_nfc_prv *prv = chip->priv;
139
140 return in_be16(prv->regs + reg);
141}
142
143/* Write NFC register */
144static inline void nfc_write(struct mtd_info *mtd, uint reg, u16 val)
145{
146 struct nand_chip *chip = mtd->priv;
147 struct mpc5121_nfc_prv *prv = chip->priv;
148
149 out_be16(prv->regs + reg, val);
150}
151
152/* Set bits in NFC register */
153static inline void nfc_set(struct mtd_info *mtd, uint reg, u16 bits)
154{
155 nfc_write(mtd, reg, nfc_read(mtd, reg) | bits);
156}
157
158/* Clear bits in NFC register */
159static inline void nfc_clear(struct mtd_info *mtd, uint reg, u16 bits)
160{
161 nfc_write(mtd, reg, nfc_read(mtd, reg) & ~bits);
162}
163
164/* Invoke address cycle */
165static inline void mpc5121_nfc_send_addr(struct mtd_info *mtd, u16 addr)
166{
167 nfc_write(mtd, NFC_FLASH_ADDR, addr);
168 nfc_write(mtd, NFC_CONFIG2, NFC_ADDRESS);
169 mpc5121_nfc_done(mtd);
170}
171
172/* Invoke command cycle */
173static inline void mpc5121_nfc_send_cmd(struct mtd_info *mtd, u16 cmd)
174{
175 nfc_write(mtd, NFC_FLASH_CMD, cmd);
176 nfc_write(mtd, NFC_CONFIG2, NFC_COMMAND);
177 mpc5121_nfc_done(mtd);
178}
179
180/* Send data from NFC buffers to NAND flash */
181static inline void mpc5121_nfc_send_prog_page(struct mtd_info *mtd)
182{
183 nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
184 nfc_write(mtd, NFC_CONFIG2, NFC_INPUT);
185 mpc5121_nfc_done(mtd);
186}
187
188/* Receive data from NAND flash */
189static inline void mpc5121_nfc_send_read_page(struct mtd_info *mtd)
190{
191 nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
192 nfc_write(mtd, NFC_CONFIG2, NFC_OUTPUT);
193 mpc5121_nfc_done(mtd);
194}
195
196/* Receive ID from NAND flash */
197static inline void mpc5121_nfc_send_read_id(struct mtd_info *mtd)
198{
199 nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
200 nfc_write(mtd, NFC_CONFIG2, NFC_ID);
201 mpc5121_nfc_done(mtd);
202}
203
204/* Receive status from NAND flash */
205static inline void mpc5121_nfc_send_read_status(struct mtd_info *mtd)
206{
207 nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
208 nfc_write(mtd, NFC_CONFIG2, NFC_STATUS);
209 mpc5121_nfc_done(mtd);
210}
211
212/* NFC interrupt handler */
213static irqreturn_t mpc5121_nfc_irq(int irq, void *data)
214{
215 struct mtd_info *mtd = data;
216 struct nand_chip *chip = mtd->priv;
217 struct mpc5121_nfc_prv *prv = chip->priv;
218
219 nfc_set(mtd, NFC_CONFIG1, NFC_INT_MASK);
220 wake_up(&prv->irq_waitq);
221
222 return IRQ_HANDLED;
223}
224
225/* Wait for operation complete */
226static void mpc5121_nfc_done(struct mtd_info *mtd)
227{
228 struct nand_chip *chip = mtd->priv;
229 struct mpc5121_nfc_prv *prv = chip->priv;
230 int rv;
231
232 if ((nfc_read(mtd, NFC_CONFIG2) & NFC_INT) == 0) {
233 nfc_clear(mtd, NFC_CONFIG1, NFC_INT_MASK);
234 rv = wait_event_timeout(prv->irq_waitq,
235 (nfc_read(mtd, NFC_CONFIG2) & NFC_INT), NFC_TIMEOUT);
236
237 if (!rv)
238 dev_warn(prv->dev,
239 "Timeout while waiting for interrupt.\n");
240 }
241
242 nfc_clear(mtd, NFC_CONFIG2, NFC_INT);
243}
244
245/* Do address cycle(s) */
246static void mpc5121_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
247{
248 struct nand_chip *chip = mtd->priv;
249 u32 pagemask = chip->pagemask;
250
251 if (column != -1) {
252 mpc5121_nfc_send_addr(mtd, column);
253 if (mtd->writesize > 512)
254 mpc5121_nfc_send_addr(mtd, column >> 8);
255 }
256
257 if (page != -1) {
258 do {
259 mpc5121_nfc_send_addr(mtd, page & 0xFF);
260 page >>= 8;
261 pagemask >>= 8;
262 } while (pagemask);
263 }
264}
265
266/* Control chip select signals */
267static void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip)
268{
269 if (chip < 0) {
270 nfc_clear(mtd, NFC_CONFIG1, NFC_CE);
271 return;
272 }
273
274 nfc_clear(mtd, NFC_BUF_ADDR, NFC_ACTIVE_CS_MASK);
275 nfc_set(mtd, NFC_BUF_ADDR, (chip << NFC_ACTIVE_CS_SHIFT) &
276 NFC_ACTIVE_CS_MASK);
277 nfc_set(mtd, NFC_CONFIG1, NFC_CE);
278}
279
280/* Init external chip select logic on ADS5121 board */
281static int ads5121_chipselect_init(struct mtd_info *mtd)
282{
283 struct nand_chip *chip = mtd->priv;
284 struct mpc5121_nfc_prv *prv = chip->priv;
285 struct device_node *dn;
286
287 dn = of_find_compatible_node(NULL, NULL, "fsl,mpc5121ads-cpld");
288 if (dn) {
289 prv->csreg = of_iomap(dn, 0);
290 of_node_put(dn);
291 if (!prv->csreg)
292 return -ENOMEM;
293
294 /* CPLD Register 9 controls NAND /CE Lines */
295 prv->csreg += 9;
296 return 0;
297 }
298
299 return -EINVAL;
300}
301
302/* Control chips select signal on ADS5121 board */
303static void ads5121_select_chip(struct mtd_info *mtd, int chip)
304{
305 struct nand_chip *nand = mtd->priv;
306 struct mpc5121_nfc_prv *prv = nand->priv;
307 u8 v;
308
309 v = in_8(prv->csreg);
310 v |= 0x0F;
311
312 if (chip >= 0) {
313 mpc5121_nfc_select_chip(mtd, 0);
314 v &= ~(1 << chip);
315 } else
316 mpc5121_nfc_select_chip(mtd, -1);
317
318 out_8(prv->csreg, v);
319}
320
321/* Read NAND Ready/Busy signal */
322static int mpc5121_nfc_dev_ready(struct mtd_info *mtd)
323{
324 /*
325 * NFC handles ready/busy signal internally. Therefore, this function
326 * always returns status as ready.
327 */
328 return 1;
329}
330
331/* Write command to NAND flash */
332static void mpc5121_nfc_command(struct mtd_info *mtd, unsigned command,
333 int column, int page)
334{
335 struct nand_chip *chip = mtd->priv;
336 struct mpc5121_nfc_prv *prv = chip->priv;
337
338 prv->column = (column >= 0) ? column : 0;
339 prv->spareonly = 0;
340
341 switch (command) {
342 case NAND_CMD_PAGEPROG:
343 mpc5121_nfc_send_prog_page(mtd);
344 break;
345 /*
346 * NFC does not support sub-page reads and writes,
347 * so emulate them using full page transfers.
348 */
349 case NAND_CMD_READ0:
350 column = 0;
351 break;
352
353 case NAND_CMD_READ1:
354 prv->column += 256;
355 command = NAND_CMD_READ0;
356 column = 0;
357 break;
358
359 case NAND_CMD_READOOB:
360 prv->spareonly = 1;
361 command = NAND_CMD_READ0;
362 column = 0;
363 break;
364
365 case NAND_CMD_SEQIN:
366 mpc5121_nfc_command(mtd, NAND_CMD_READ0, column, page);
367 column = 0;
368 break;
369
370 case NAND_CMD_ERASE1:
371 case NAND_CMD_ERASE2:
372 case NAND_CMD_READID:
373 case NAND_CMD_STATUS:
374 break;
375
376 default:
377 return;
378 }
379
380 mpc5121_nfc_send_cmd(mtd, command);
381 mpc5121_nfc_addr_cycle(mtd, column, page);
382
383 switch (command) {
384 case NAND_CMD_READ0:
385 if (mtd->writesize > 512)
386 mpc5121_nfc_send_cmd(mtd, NAND_CMD_READSTART);
387 mpc5121_nfc_send_read_page(mtd);
388 break;
389
390 case NAND_CMD_READID:
391 mpc5121_nfc_send_read_id(mtd);
392 break;
393
394 case NAND_CMD_STATUS:
395 mpc5121_nfc_send_read_status(mtd);
396 if (chip->options & NAND_BUSWIDTH_16)
397 prv->column = 1;
398 else
399 prv->column = 0;
400 break;
401 }
402}
403
404/* Copy data from/to NFC spare buffers. */
405static void mpc5121_nfc_copy_spare(struct mtd_info *mtd, uint offset,
406 u8 *buffer, uint size, int wr)
407{
408 struct nand_chip *nand = mtd->priv;
409 struct mpc5121_nfc_prv *prv = nand->priv;
410 uint o, s, sbsize, blksize;
411
412 /*
413 * NAND spare area is available through NFC spare buffers.
414 * The NFC divides spare area into (page_size / 512) chunks.
415 * Each chunk is placed into separate spare memory area, using
416 * first (spare_size / num_of_chunks) bytes of the buffer.
417 *
418 * For NAND device in which the spare area is not divided fully
419 * by the number of chunks, number of used bytes in each spare
420 * buffer is rounded down to the nearest even number of bytes,
421 * and all remaining bytes are added to the last used spare area.
422 *
423 * For more information read section 26.6.10 of MPC5121e
424 * Microcontroller Reference Manual, Rev. 3.
425 */
426
427 /* Calculate number of valid bytes in each spare buffer */
428 sbsize = (mtd->oobsize / (mtd->writesize / 512)) & ~1;
429
430 while (size) {
431 /* Calculate spare buffer number */
432 s = offset / sbsize;
433 if (s > NFC_SPARE_BUFFERS - 1)
434 s = NFC_SPARE_BUFFERS - 1;
435
436 /*
437 * Calculate offset to requested data block in selected spare
438 * buffer and its size.
439 */
440 o = offset - (s * sbsize);
441 blksize = min(sbsize - o, size);
442
443 if (wr)
444 memcpy_toio(prv->regs + NFC_SPARE_AREA(s) + o,
445 buffer, blksize);
446 else
447 memcpy_fromio(buffer,
448 prv->regs + NFC_SPARE_AREA(s) + o, blksize);
449
450 buffer += blksize;
451 offset += blksize;
452 size -= blksize;
453 };
454}
455
456/* Copy data from/to NFC main and spare buffers */
457static void mpc5121_nfc_buf_copy(struct mtd_info *mtd, u_char *buf, int len,
458 int wr)
459{
460 struct nand_chip *chip = mtd->priv;
461 struct mpc5121_nfc_prv *prv = chip->priv;
462 uint c = prv->column;
463 uint l;
464
465 /* Handle spare area access */
466 if (prv->spareonly || c >= mtd->writesize) {
467 /* Calculate offset from beginning of spare area */
468 if (c >= mtd->writesize)
469 c -= mtd->writesize;
470
471 prv->column += len;
472 mpc5121_nfc_copy_spare(mtd, c, buf, len, wr);
473 return;
474 }
475
476 /*
477 * Handle main area access - limit copy length to prevent
478 * crossing main/spare boundary.
479 */
480 l = min((uint)len, mtd->writesize - c);
481 prv->column += l;
482
483 if (wr)
484 memcpy_toio(prv->regs + NFC_MAIN_AREA(0) + c, buf, l);
485 else
486 memcpy_fromio(buf, prv->regs + NFC_MAIN_AREA(0) + c, l);
487
488 /* Handle crossing main/spare boundary */
489 if (l != len) {
490 buf += l;
491 len -= l;
492 mpc5121_nfc_buf_copy(mtd, buf, len, wr);
493 }
494}
495
496/* Read data from NFC buffers */
497static void mpc5121_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len)
498{
499 mpc5121_nfc_buf_copy(mtd, buf, len, 0);
500}
501
502/* Write data to NFC buffers */
503static void mpc5121_nfc_write_buf(struct mtd_info *mtd,
504 const u_char *buf, int len)
505{
506 mpc5121_nfc_buf_copy(mtd, (u_char *)buf, len, 1);
507}
508
509/* Compare buffer with NAND flash */
510static int mpc5121_nfc_verify_buf(struct mtd_info *mtd,
511 const u_char *buf, int len)
512{
513 u_char tmp[256];
514 uint bsize;
515
516 while (len) {
517 bsize = min(len, 256);
518 mpc5121_nfc_read_buf(mtd, tmp, bsize);
519
520 if (memcmp(buf, tmp, bsize))
521 return 1;
522
523 buf += bsize;
524 len -= bsize;
525 }
526
527 return 0;
528}
529
530/* Read byte from NFC buffers */
531static u8 mpc5121_nfc_read_byte(struct mtd_info *mtd)
532{
533 u8 tmp;
534
535 mpc5121_nfc_read_buf(mtd, &tmp, sizeof(tmp));
536
537 return tmp;
538}
539
540/* Read word from NFC buffers */
541static u16 mpc5121_nfc_read_word(struct mtd_info *mtd)
542{
543 u16 tmp;
544
545 mpc5121_nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp));
546
547 return tmp;
548}
549
550/*
551 * Read NFC configuration from Reset Config Word
552 *
553 * NFC is configured during reset in basis of information stored
554 * in Reset Config Word. There is no other way to set NAND block
555 * size, spare size and bus width.
556 */
557static int mpc5121_nfc_read_hw_config(struct mtd_info *mtd)
558{
559 struct nand_chip *chip = mtd->priv;
560 struct mpc5121_nfc_prv *prv = chip->priv;
561 struct mpc512x_reset_module *rm;
562 struct device_node *rmnode;
563 uint rcw_pagesize = 0;
564 uint rcw_sparesize = 0;
565 uint rcw_width;
566 uint rcwh;
567 uint romloc, ps;
cf363518 568 int ret = 0;
bb315f74
AG		 569
570 rmnode = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-reset");
571 if (!rmnode) {
572 dev_err(prv->dev, "Missing 'fsl,mpc5121-reset' "
573 "node in device tree!\n");
574 return -ENODEV;
575 }
576
577 rm = of_iomap(rmnode, 0);
578 if (!rm) {
579 dev_err(prv->dev, "Error mapping reset module node!\n");
cf363518
JL		 580 ret = -EBUSY;
581 goto out;
bb315f74
AG		 582 }
583
584 rcwh = in_be32(&rm->rcwhr);
585
586 /* Bit 6: NFC bus width */
587 rcw_width = ((rcwh >> 6) & 0x1) ? 2 : 1;
588
589 /* Bit 7: NFC Page/Spare size */
590 ps = (rcwh >> 7) & 0x1;
591
592 /* Bits [22:21]: ROM Location */
593 romloc = (rcwh >> 21) & 0x3;
594
595 /* Decode RCW bits */
596 switch ((ps << 2) | romloc) {
597 case 0x00:
598 case 0x01:
599 rcw_pagesize = 512;
600 rcw_sparesize = 16;
601 break;
602 case 0x02:
603 case 0x03:
604 rcw_pagesize = 4096;
605 rcw_sparesize = 128;
606 break;
607 case 0x04:
608 case 0x05:
609 rcw_pagesize = 2048;
610 rcw_sparesize = 64;
611 break;
612 case 0x06:
613 case 0x07:
614 rcw_pagesize = 4096;
615 rcw_sparesize = 218;
616 break;
617 }
618
619 mtd->writesize = rcw_pagesize;
620 mtd->oobsize = rcw_sparesize;
621 if (rcw_width == 2)
622 chip->options |= NAND_BUSWIDTH_16;
623
624 dev_notice(prv->dev, "Configured for "
625 "%u-bit NAND, page size %u "
626 "with %u spare.\n",
627 rcw_width * 8, rcw_pagesize,
628 rcw_sparesize);
629 iounmap(rm);
cf363518 630out:
bb315f74 631 of_node_put(rmnode);
cf363518 632 return ret;
bb315f74
AG		 633}
634
635/* Free driver resources */
636static void mpc5121_nfc_free(struct device *dev, struct mtd_info *mtd)
637{
638 struct nand_chip *chip = mtd->priv;
639 struct mpc5121_nfc_prv *prv = chip->priv;
640
641 if (prv->clk) {
642 clk_disable(prv->clk);
643 clk_put(prv->clk);
644 }
645
646 if (prv->csreg)
647 iounmap(prv->csreg);
648}
649
1c48a5c9 650static int __devinit mpc5121_nfc_probe(struct platform_device *op)
bb315f74 651{
14acbbf8 652 struct device_node *rootnode, *dn = op->dev.of_node;
bb315f74
AG		 653 struct device *dev = &op->dev;
654 struct mpc5121_nfc_prv *prv;
655 struct resource res;
656 struct mtd_info *mtd;
bb315f74
AG		 657 struct nand_chip *chip;
658 unsigned long regs_paddr, regs_size;
766f271a 659 const __be32 *chips_no;
bb315f74
AG		 660 int resettime = 0;
661 int retval = 0;
662 int rev, len;
b3702ea4 663 struct mtd_part_parser_data ppdata;
bb315f74
AG		 664
665 /*
666 * Check SoC revision. This driver supports only NFC
6f1f3d0a 667 * in MPC5121 revision 2 and MPC5123 revision 3.
bb315f74
AG		 668 */
669 rev = (mfspr(SPRN_SVR) >> 4) & 0xF;
6f1f3d0a 670 if ((rev != 2) && (rev != 3)) {
bb315f74
AG		 671 dev_err(dev, "SoC revision %u is not supported!\n", rev);
672 return -ENXIO;
673 }
674
675 prv = devm_kzalloc(dev, sizeof(*prv), GFP_KERNEL);
676 if (!prv) {
677 dev_err(dev, "Memory exhausted!\n");
678 return -ENOMEM;
679 }
680
681 mtd = &prv->mtd;
682 chip = &prv->chip;
683
684 mtd->priv = chip;
685 chip->priv = prv;
686 prv->dev = dev;
687
688 /* Read NFC configuration from Reset Config Word */
689 retval = mpc5121_nfc_read_hw_config(mtd);
690 if (retval) {
691 dev_err(dev, "Unable to read NFC config!\n");
692 return retval;
693 }
694
695 prv->irq = irq_of_parse_and_map(dn, 0);
696 if (prv->irq == NO_IRQ) {
697 dev_err(dev, "Error mapping IRQ!\n");
698 return -EINVAL;
699 }
700
701 retval = of_address_to_resource(dn, 0, &res);
702 if (retval) {
703 dev_err(dev, "Error parsing memory region!\n");
704 return retval;
705 }
706
707 chips_no = of_get_property(dn, "chips", &len);
708 if (!chips_no || len != sizeof(*chips_no)) {
709 dev_err(dev, "Invalid/missing 'chips' property!\n");
710 return -EINVAL;
711 }
712
713 regs_paddr = res.start;
28f65c11 714 regs_size = resource_size(&res);
bb315f74
AG		 715
716 if (!devm_request_mem_region(dev, regs_paddr, regs_size, DRV_NAME)) {
717 dev_err(dev, "Error requesting memory region!\n");
718 return -EBUSY;
719 }
720
721 prv->regs = devm_ioremap(dev, regs_paddr, regs_size);
722 if (!prv->regs) {
723 dev_err(dev, "Error mapping memory region!\n");
724 return -ENOMEM;
725 }
726
727 mtd->name = "MPC5121 NAND";
b3702ea4 728 ppdata.of_node = dn;
bb315f74
AG		 729 chip->dev_ready = mpc5121_nfc_dev_ready;
730 chip->cmdfunc = mpc5121_nfc_command;
731 chip->read_byte = mpc5121_nfc_read_byte;
732 chip->read_word = mpc5121_nfc_read_word;
733 chip->read_buf = mpc5121_nfc_read_buf;
734 chip->write_buf = mpc5121_nfc_write_buf;
735 chip->verify_buf = mpc5121_nfc_verify_buf;
736 chip->select_chip = mpc5121_nfc_select_chip;
bb9ebd4e 737 chip->bbt_options = NAND_BBT_USE_FLASH;
bb315f74
AG		 738 chip->ecc.mode = NAND_ECC_SOFT;
739
740 /* Support external chip-select logic on ADS5121 board */
741 rootnode = of_find_node_by_path("/");
742 if (of_device_is_compatible(rootnode, "fsl,mpc5121ads")) {
743 retval = ads5121_chipselect_init(mtd);
744 if (retval) {
745 dev_err(dev, "Chipselect init error!\n");
746 of_node_put(rootnode);
747 return retval;
748 }
749
750 chip->select_chip = ads5121_select_chip;
751 }
752 of_node_put(rootnode);
753
754 /* Enable NFC clock */
755 prv->clk = clk_get(dev, "nfc_clk");
83025c82 756 if (IS_ERR(prv->clk)) {
bb315f74 757 dev_err(dev, "Unable to acquire NFC clock!\n");
83025c82 758 retval = PTR_ERR(prv->clk);
bb315f74
AG		 759 goto error;
760 }
761
762 clk_enable(prv->clk);
763
764 /* Reset NAND Flash controller */
765 nfc_set(mtd, NFC_CONFIG1, NFC_RESET);
766 while (nfc_read(mtd, NFC_CONFIG1) & NFC_RESET) {
767 if (resettime++ >= NFC_RESET_TIMEOUT) {
768 dev_err(dev, "Timeout while resetting NFC!\n");
769 retval = -EINVAL;
770 goto error;
771 }
772
773 udelay(1);
774 }
775
776 /* Enable write to NFC memory */
777 nfc_write(mtd, NFC_CONFIG, NFC_BLS_UNLOCKED);
778
779 /* Enable write to all NAND pages */
780 nfc_write(mtd, NFC_UNLOCKSTART_BLK0, 0x0000);
781 nfc_write(mtd, NFC_UNLOCKEND_BLK0, 0xFFFF);
782 nfc_write(mtd, NFC_WRPROT, NFC_WPC_UNLOCK);
783
784 /*
785 * Setup NFC:
786 * - Big Endian transfers,
787 * - Interrupt after full page read/write.
788 */
789 nfc_write(mtd, NFC_CONFIG1, NFC_BIG_ENDIAN | NFC_INT_MASK |
790 NFC_FULL_PAGE_INT);
791
792 /* Set spare area size */
793 nfc_write(mtd, NFC_SPAS, mtd->oobsize >> 1);
794
795 init_waitqueue_head(&prv->irq_waitq);
796 retval = devm_request_irq(dev, prv->irq, &mpc5121_nfc_irq, 0, DRV_NAME,
797 mtd);
798 if (retval) {
799 dev_err(dev, "Error requesting IRQ!\n");
800 goto error;
801 }
802
803 /* Detect NAND chips */
766f271a 804 if (nand_scan(mtd, be32_to_cpup(chips_no))) {
bb315f74
AG		 805 dev_err(dev, "NAND Flash not found !\n");
806 devm_free_irq(dev, prv->irq, mtd);
807 retval = -ENXIO;
808 goto error;
809 }
810
811 /* Set erase block size */
812 switch (mtd->erasesize / mtd->writesize) {
813 case 32:
814 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_32);
815 break;
816
817 case 64:
818 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_64);
819 break;
820
821 case 128:
822 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_128);
823 break;
824
825 case 256:
826 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_256);
827 break;
828
829 default:
830 dev_err(dev, "Unsupported NAND flash!\n");
831 devm_free_irq(dev, prv->irq, mtd);
832 retval = -ENXIO;
833 goto error;
834 }
835
836 dev_set_drvdata(dev, mtd);
837
838 /* Register device in MTD */
a9093f06 839 retval = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
bb315f74
AG		 840 if (retval) {
841 dev_err(dev, "Error adding MTD device!\n");
842 devm_free_irq(dev, prv->irq, mtd);
843 goto error;
844 }
845
846 return 0;
847error:
848 mpc5121_nfc_free(dev, mtd);
849 return retval;
850}
851
2dc11581 852static int __devexit mpc5121_nfc_remove(struct platform_device *op)
bb315f74
AG		 853{
854 struct device *dev = &op->dev;
855 struct mtd_info *mtd = dev_get_drvdata(dev);
856 struct nand_chip *chip = mtd->priv;
857 struct mpc5121_nfc_prv *prv = chip->priv;
858
859 nand_release(mtd);
860 devm_free_irq(dev, prv->irq, mtd);
861 mpc5121_nfc_free(dev, mtd);
862
863 return 0;
864}
865
866static struct of_device_id mpc5121_nfc_match[] __devinitdata = {
867 { .compatible = "fsl,mpc5121-nfc", },
868 {},
869};
870
1c48a5c9 871static struct platform_driver mpc5121_nfc_driver = {
bb315f74
AG		 872 .probe = mpc5121_nfc_probe,
873 .remove = __devexit_p(mpc5121_nfc_remove),
874 .driver = {
14acbbf8
AG		 875 .name = DRV_NAME,
876 .owner = THIS_MODULE,
877 .of_match_table = mpc5121_nfc_match,
bb315f74
AG		 878 },
879};
880
f99640de 881module_platform_driver(mpc5121_nfc_driver);
bb315f74
AG		 882
883MODULE_AUTHOR("Freescale Semiconductor, Inc.");
884MODULE_DESCRIPTION("MPC5121 NAND MTD driver");
885MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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