Commit | Line | Data |
---|---|---|
34f6e157 SH |
1 | /* |
2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * Copyright 2008 Sascha Hauer, kernel@pengutronix.de | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
17 | * MA 02110-1301, USA. | |
18 | */ | |
19 | ||
20 | #include <linux/delay.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/mtd/mtd.h> | |
25 | #include <linux/mtd/nand.h> | |
26 | #include <linux/mtd/partitions.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/device.h> | |
29 | #include <linux/platform_device.h> | |
30 | #include <linux/clk.h> | |
31 | #include <linux/err.h> | |
32 | #include <linux/io.h> | |
63f1474c SH |
33 | #include <linux/irq.h> |
34 | #include <linux/completion.h> | |
d367e37e | 35 | #include <linux/of.h> |
6436356b | 36 | #include <linux/of_device.h> |
34f6e157 SH |
37 | |
38 | #include <asm/mach/flash.h> | |
82906b13 | 39 | #include <linux/platform_data/mtd-mxc_nand.h> |
34f6e157 SH |
40 | |
41 | #define DRIVER_NAME "mxc_nand" | |
42 | ||
43 | /* Addresses for NFC registers */ | |
1bc99180 SH |
44 | #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00) |
45 | #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04) | |
46 | #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06) | |
47 | #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08) | |
48 | #define NFC_V1_V2_CONFIG (host->regs + 0x0a) | |
49 | #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c) | |
50 | #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e) | |
51 | #define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10) | |
52 | #define NFC_V1_V2_WRPROT (host->regs + 0x12) | |
53 | #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14) | |
54 | #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16) | |
d178e3e8 BS |
55 | #define NFC_V21_UNLOCKSTART_BLKADDR0 (host->regs + 0x20) |
56 | #define NFC_V21_UNLOCKSTART_BLKADDR1 (host->regs + 0x24) | |
57 | #define NFC_V21_UNLOCKSTART_BLKADDR2 (host->regs + 0x28) | |
58 | #define NFC_V21_UNLOCKSTART_BLKADDR3 (host->regs + 0x2c) | |
59 | #define NFC_V21_UNLOCKEND_BLKADDR0 (host->regs + 0x22) | |
60 | #define NFC_V21_UNLOCKEND_BLKADDR1 (host->regs + 0x26) | |
61 | #define NFC_V21_UNLOCKEND_BLKADDR2 (host->regs + 0x2a) | |
62 | #define NFC_V21_UNLOCKEND_BLKADDR3 (host->regs + 0x2e) | |
1bc99180 SH |
63 | #define NFC_V1_V2_NF_WRPRST (host->regs + 0x18) |
64 | #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a) | |
65 | #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c) | |
66 | ||
6e85dfdc | 67 | #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0) |
1bc99180 SH |
68 | #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2) |
69 | #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3) | |
70 | #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4) | |
71 | #define NFC_V1_V2_CONFIG1_BIG (1 << 5) | |
72 | #define NFC_V1_V2_CONFIG1_RST (1 << 6) | |
73 | #define NFC_V1_V2_CONFIG1_CE (1 << 7) | |
b8db2f51 SH |
74 | #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8) |
75 | #define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9) | |
76 | #define NFC_V2_CONFIG1_FP_INT (1 << 11) | |
1bc99180 SH |
77 | |
78 | #define NFC_V1_V2_CONFIG2_INT (1 << 15) | |
79 | ||
80 | /* | |
81 | * Operation modes for the NFC. Valid for v1, v2 and v3 | |
82 | * type controllers. | |
83 | */ | |
84 | #define NFC_CMD (1 << 0) | |
85 | #define NFC_ADDR (1 << 1) | |
86 | #define NFC_INPUT (1 << 2) | |
87 | #define NFC_OUTPUT (1 << 3) | |
88 | #define NFC_ID (1 << 4) | |
89 | #define NFC_STATUS (1 << 5) | |
34f6e157 | 90 | |
71ec5155 SH |
91 | #define NFC_V3_FLASH_CMD (host->regs_axi + 0x00) |
92 | #define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04) | |
93 | ||
94 | #define NFC_V3_CONFIG1 (host->regs_axi + 0x34) | |
95 | #define NFC_V3_CONFIG1_SP_EN (1 << 0) | |
96 | #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4) | |
97 | ||
98 | #define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38) | |
99 | ||
100 | #define NFC_V3_LAUNCH (host->regs_axi + 0x40) | |
101 | ||
102 | #define NFC_V3_WRPROT (host->regs_ip + 0x0) | |
103 | #define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0) | |
104 | #define NFC_V3_WRPROT_LOCK (1 << 1) | |
105 | #define NFC_V3_WRPROT_UNLOCK (1 << 2) | |
106 | #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6) | |
107 | ||
108 | #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04) | |
109 | ||
110 | #define NFC_V3_CONFIG2 (host->regs_ip + 0x24) | |
111 | #define NFC_V3_CONFIG2_PS_512 (0 << 0) | |
112 | #define NFC_V3_CONFIG2_PS_2048 (1 << 0) | |
113 | #define NFC_V3_CONFIG2_PS_4096 (2 << 0) | |
114 | #define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2) | |
115 | #define NFC_V3_CONFIG2_ECC_EN (1 << 3) | |
116 | #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4) | |
117 | #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5) | |
118 | #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6) | |
71718a8e | 119 | #define NFC_V3_CONFIG2_PPB(x, shift) (((x) & 0x3) << shift) |
71ec5155 SH |
120 | #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12) |
121 | #define NFC_V3_CONFIG2_INT_MSK (1 << 15) | |
122 | #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24) | |
123 | #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16) | |
124 | ||
125 | #define NFC_V3_CONFIG3 (host->regs_ip + 0x28) | |
126 | #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0) | |
127 | #define NFC_V3_CONFIG3_FW8 (1 << 3) | |
128 | #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8) | |
129 | #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12) | |
130 | #define NFC_V3_CONFIG3_RBB_MODE (1 << 15) | |
131 | #define NFC_V3_CONFIG3_NO_SDMA (1 << 20) | |
132 | ||
133 | #define NFC_V3_IPC (host->regs_ip + 0x2C) | |
134 | #define NFC_V3_IPC_CREQ (1 << 0) | |
135 | #define NFC_V3_IPC_INT (1 << 31) | |
136 | ||
137 | #define NFC_V3_DELAY_LINE (host->regs_ip + 0x34) | |
34f6e157 | 138 | |
e4303b25 UKK |
139 | struct mxc_nand_host; |
140 | ||
141 | struct mxc_nand_devtype_data { | |
142 | void (*preset)(struct mtd_info *); | |
143 | void (*send_cmd)(struct mxc_nand_host *, uint16_t, int); | |
144 | void (*send_addr)(struct mxc_nand_host *, uint16_t, int); | |
145 | void (*send_page)(struct mtd_info *, unsigned int); | |
146 | void (*send_read_id)(struct mxc_nand_host *); | |
147 | uint16_t (*get_dev_status)(struct mxc_nand_host *); | |
148 | int (*check_int)(struct mxc_nand_host *); | |
149 | void (*irq_control)(struct mxc_nand_host *, int); | |
6d38af25 | 150 | u32 (*get_ecc_status)(struct mxc_nand_host *); |
a894cf6c | 151 | const struct mtd_ooblayout_ops *ooblayout; |
5e05a2d6 | 152 | void (*select_chip)(struct mtd_info *mtd, int chip); |
69d023be UKK |
153 | int (*correct_data)(struct mtd_info *mtd, u_char *dat, |
154 | u_char *read_ecc, u_char *calc_ecc); | |
f48d0f9a UKK |
155 | |
156 | /* | |
157 | * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked | |
158 | * (CONFIG1:INT_MSK is set). To handle this the driver uses | |
159 | * enable_irq/disable_irq_nosync instead of CONFIG1:INT_MSK | |
160 | */ | |
161 | int irqpending_quirk; | |
162 | int needs_ip; | |
163 | ||
164 | size_t regs_offset; | |
165 | size_t spare0_offset; | |
166 | size_t axi_offset; | |
167 | ||
168 | int spare_len; | |
169 | int eccbytes; | |
170 | int eccsize; | |
71718a8e | 171 | int ppb_shift; |
e4303b25 UKK |
172 | }; |
173 | ||
34f6e157 | 174 | struct mxc_nand_host { |
34f6e157 | 175 | struct nand_chip nand; |
34f6e157 SH |
176 | struct device *dev; |
177 | ||
4b6f05e1 UKK |
178 | void __iomem *spare0; |
179 | void __iomem *main_area0; | |
c6de7e1b SH |
180 | |
181 | void __iomem *base; | |
34f6e157 | 182 | void __iomem *regs; |
71ec5155 SH |
183 | void __iomem *regs_axi; |
184 | void __iomem *regs_ip; | |
34f6e157 | 185 | int status_request; |
34f6e157 SH |
186 | struct clk *clk; |
187 | int clk_act; | |
188 | int irq; | |
94f77e50 | 189 | int eccsize; |
7e7e4730 | 190 | int used_oobsize; |
d178e3e8 | 191 | int active_cs; |
34f6e157 | 192 | |
63f1474c | 193 | struct completion op_completion; |
34f6e157 | 194 | |
f8f9608d SH |
195 | uint8_t *data_buf; |
196 | unsigned int buf_start; | |
5f97304e | 197 | |
e4303b25 | 198 | const struct mxc_nand_devtype_data *devtype_data; |
6436356b | 199 | struct mxc_nand_platform_data pdata; |
34f6e157 SH |
200 | }; |
201 | ||
b2ac0376 | 202 | static const char * const part_probes[] = { |
740bb0c4 | 203 | "cmdlinepart", "RedBoot", "ofpart", NULL }; |
34f6e157 | 204 | |
096bcc23 SH |
205 | static void memcpy32_fromio(void *trg, const void __iomem *src, size_t size) |
206 | { | |
207 | int i; | |
208 | u32 *t = trg; | |
209 | const __iomem u32 *s = src; | |
210 | ||
211 | for (i = 0; i < (size >> 2); i++) | |
212 | *t++ = __raw_readl(s++); | |
213 | } | |
214 | ||
0d17fc3e BS |
215 | static void memcpy16_fromio(void *trg, const void __iomem *src, size_t size) |
216 | { | |
217 | int i; | |
218 | u16 *t = trg; | |
219 | const __iomem u16 *s = src; | |
220 | ||
221 | /* We assume that src (IO) is always 32bit aligned */ | |
222 | if (PTR_ALIGN(trg, 4) == trg && IS_ALIGNED(size, 4)) { | |
223 | memcpy32_fromio(trg, src, size); | |
224 | return; | |
225 | } | |
226 | ||
227 | for (i = 0; i < (size >> 1); i++) | |
228 | *t++ = __raw_readw(s++); | |
229 | } | |
230 | ||
33a87a15 | 231 | static inline void memcpy32_toio(void __iomem *trg, const void *src, int size) |
096bcc23 | 232 | { |
33a87a15 KV |
233 | /* __iowrite32_copy use 32bit size values so divide by 4 */ |
234 | __iowrite32_copy(trg, src, size / 4); | |
096bcc23 SH |
235 | } |
236 | ||
0d17fc3e BS |
237 | static void memcpy16_toio(void __iomem *trg, const void *src, int size) |
238 | { | |
239 | int i; | |
240 | __iomem u16 *t = trg; | |
241 | const u16 *s = src; | |
242 | ||
243 | /* We assume that trg (IO) is always 32bit aligned */ | |
244 | if (PTR_ALIGN(src, 4) == src && IS_ALIGNED(size, 4)) { | |
245 | memcpy32_toio(trg, src, size); | |
246 | return; | |
247 | } | |
248 | ||
249 | for (i = 0; i < (size >> 1); i++) | |
250 | __raw_writew(*s++, t++); | |
251 | } | |
252 | ||
71ec5155 SH |
253 | static int check_int_v3(struct mxc_nand_host *host) |
254 | { | |
255 | uint32_t tmp; | |
256 | ||
257 | tmp = readl(NFC_V3_IPC); | |
258 | if (!(tmp & NFC_V3_IPC_INT)) | |
259 | return 0; | |
260 | ||
261 | tmp &= ~NFC_V3_IPC_INT; | |
262 | writel(tmp, NFC_V3_IPC); | |
263 | ||
264 | return 1; | |
265 | } | |
266 | ||
7aaf28ac SH |
267 | static int check_int_v1_v2(struct mxc_nand_host *host) |
268 | { | |
269 | uint32_t tmp; | |
270 | ||
1bc99180 SH |
271 | tmp = readw(NFC_V1_V2_CONFIG2); |
272 | if (!(tmp & NFC_V1_V2_CONFIG2_INT)) | |
7aaf28ac SH |
273 | return 0; |
274 | ||
f48d0f9a | 275 | if (!host->devtype_data->irqpending_quirk) |
63f1474c | 276 | writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2); |
7aaf28ac SH |
277 | |
278 | return 1; | |
279 | } | |
280 | ||
63f1474c SH |
281 | static void irq_control_v1_v2(struct mxc_nand_host *host, int activate) |
282 | { | |
283 | uint16_t tmp; | |
284 | ||
285 | tmp = readw(NFC_V1_V2_CONFIG1); | |
286 | ||
287 | if (activate) | |
288 | tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK; | |
289 | else | |
290 | tmp |= NFC_V1_V2_CONFIG1_INT_MSK; | |
291 | ||
292 | writew(tmp, NFC_V1_V2_CONFIG1); | |
293 | } | |
294 | ||
295 | static void irq_control_v3(struct mxc_nand_host *host, int activate) | |
296 | { | |
297 | uint32_t tmp; | |
298 | ||
299 | tmp = readl(NFC_V3_CONFIG2); | |
300 | ||
301 | if (activate) | |
302 | tmp &= ~NFC_V3_CONFIG2_INT_MSK; | |
303 | else | |
304 | tmp |= NFC_V3_CONFIG2_INT_MSK; | |
305 | ||
306 | writel(tmp, NFC_V3_CONFIG2); | |
307 | } | |
308 | ||
8556958a UKK |
309 | static void irq_control(struct mxc_nand_host *host, int activate) |
310 | { | |
f48d0f9a | 311 | if (host->devtype_data->irqpending_quirk) { |
8556958a UKK |
312 | if (activate) |
313 | enable_irq(host->irq); | |
314 | else | |
315 | disable_irq_nosync(host->irq); | |
316 | } else { | |
e4303b25 | 317 | host->devtype_data->irq_control(host, activate); |
8556958a UKK |
318 | } |
319 | } | |
320 | ||
6d38af25 UKK |
321 | static u32 get_ecc_status_v1(struct mxc_nand_host *host) |
322 | { | |
323 | return readw(NFC_V1_V2_ECC_STATUS_RESULT); | |
324 | } | |
325 | ||
326 | static u32 get_ecc_status_v2(struct mxc_nand_host *host) | |
327 | { | |
328 | return readl(NFC_V1_V2_ECC_STATUS_RESULT); | |
329 | } | |
330 | ||
331 | static u32 get_ecc_status_v3(struct mxc_nand_host *host) | |
332 | { | |
333 | return readl(NFC_V3_ECC_STATUS_RESULT); | |
334 | } | |
335 | ||
8556958a UKK |
336 | static irqreturn_t mxc_nfc_irq(int irq, void *dev_id) |
337 | { | |
338 | struct mxc_nand_host *host = dev_id; | |
339 | ||
e4303b25 | 340 | if (!host->devtype_data->check_int(host)) |
8556958a UKK |
341 | return IRQ_NONE; |
342 | ||
343 | irq_control(host, 0); | |
344 | ||
345 | complete(&host->op_completion); | |
346 | ||
347 | return IRQ_HANDLED; | |
348 | } | |
349 | ||
34f6e157 SH |
350 | /* This function polls the NANDFC to wait for the basic operation to |
351 | * complete by checking the INT bit of config2 register. | |
352 | */ | |
e35d1d8a | 353 | static int wait_op_done(struct mxc_nand_host *host, int useirq) |
34f6e157 | 354 | { |
e35d1d8a UKK |
355 | int ret = 0; |
356 | ||
357 | /* | |
358 | * If operation is already complete, don't bother to setup an irq or a | |
359 | * loop. | |
360 | */ | |
361 | if (host->devtype_data->check_int(host)) | |
362 | return 0; | |
34f6e157 SH |
363 | |
364 | if (useirq) { | |
e35d1d8a UKK |
365 | unsigned long timeout; |
366 | ||
367 | reinit_completion(&host->op_completion); | |
368 | ||
369 | irq_control(host, 1); | |
370 | ||
371 | timeout = wait_for_completion_timeout(&host->op_completion, HZ); | |
372 | if (!timeout && !host->devtype_data->check_int(host)) { | |
373 | dev_dbg(host->dev, "timeout waiting for irq\n"); | |
374 | ret = -ETIMEDOUT; | |
34f6e157 SH |
375 | } |
376 | } else { | |
e35d1d8a UKK |
377 | int max_retries = 8000; |
378 | int done; | |
7aaf28ac | 379 | |
e35d1d8a | 380 | do { |
34f6e157 | 381 | udelay(1); |
e35d1d8a UKK |
382 | |
383 | done = host->devtype_data->check_int(host); | |
384 | if (done) | |
385 | break; | |
386 | ||
387 | } while (--max_retries); | |
388 | ||
389 | if (!done) { | |
390 | dev_dbg(host->dev, "timeout polling for completion\n"); | |
391 | ret = -ETIMEDOUT; | |
34f6e157 | 392 | } |
34f6e157 | 393 | } |
e35d1d8a UKK |
394 | |
395 | WARN_ONCE(ret < 0, "timeout! useirq=%d\n", useirq); | |
396 | ||
397 | return ret; | |
34f6e157 SH |
398 | } |
399 | ||
71ec5155 SH |
400 | static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq) |
401 | { | |
402 | /* fill command */ | |
403 | writel(cmd, NFC_V3_FLASH_CMD); | |
404 | ||
405 | /* send out command */ | |
406 | writel(NFC_CMD, NFC_V3_LAUNCH); | |
407 | ||
408 | /* Wait for operation to complete */ | |
409 | wait_op_done(host, useirq); | |
410 | } | |
411 | ||
34f6e157 SH |
412 | /* This function issues the specified command to the NAND device and |
413 | * waits for completion. */ | |
5f97304e | 414 | static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq) |
34f6e157 | 415 | { |
289c0522 | 416 | pr_debug("send_cmd(host, 0x%x, %d)\n", cmd, useirq); |
34f6e157 | 417 | |
1bc99180 SH |
418 | writew(cmd, NFC_V1_V2_FLASH_CMD); |
419 | writew(NFC_CMD, NFC_V1_V2_CONFIG2); | |
34f6e157 | 420 | |
f48d0f9a | 421 | if (host->devtype_data->irqpending_quirk && (cmd == NAND_CMD_RESET)) { |
a47bfd2e IC |
422 | int max_retries = 100; |
423 | /* Reset completion is indicated by NFC_CONFIG2 */ | |
424 | /* being set to 0 */ | |
425 | while (max_retries-- > 0) { | |
1bc99180 | 426 | if (readw(NFC_V1_V2_CONFIG2) == 0) { |
a47bfd2e IC |
427 | break; |
428 | } | |
429 | udelay(1); | |
430 | } | |
431 | if (max_retries < 0) | |
0a32a102 | 432 | pr_debug("%s: RESET failed\n", __func__); |
a47bfd2e IC |
433 | } else { |
434 | /* Wait for operation to complete */ | |
435 | wait_op_done(host, useirq); | |
436 | } | |
34f6e157 SH |
437 | } |
438 | ||
71ec5155 SH |
439 | static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast) |
440 | { | |
441 | /* fill address */ | |
442 | writel(addr, NFC_V3_FLASH_ADDR0); | |
443 | ||
444 | /* send out address */ | |
445 | writel(NFC_ADDR, NFC_V3_LAUNCH); | |
446 | ||
447 | wait_op_done(host, 0); | |
448 | } | |
449 | ||
34f6e157 SH |
450 | /* This function sends an address (or partial address) to the |
451 | * NAND device. The address is used to select the source/destination for | |
452 | * a NAND command. */ | |
5f97304e | 453 | static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast) |
34f6e157 | 454 | { |
289c0522 | 455 | pr_debug("send_addr(host, 0x%x %d)\n", addr, islast); |
34f6e157 | 456 | |
1bc99180 SH |
457 | writew(addr, NFC_V1_V2_FLASH_ADDR); |
458 | writew(NFC_ADDR, NFC_V1_V2_CONFIG2); | |
34f6e157 SH |
459 | |
460 | /* Wait for operation to complete */ | |
c110eaf4 | 461 | wait_op_done(host, islast); |
34f6e157 SH |
462 | } |
463 | ||
71ec5155 SH |
464 | static void send_page_v3(struct mtd_info *mtd, unsigned int ops) |
465 | { | |
4bd4ebcc | 466 | struct nand_chip *nand_chip = mtd_to_nand(mtd); |
d699ed25 | 467 | struct mxc_nand_host *host = nand_get_controller_data(nand_chip); |
71ec5155 SH |
468 | uint32_t tmp; |
469 | ||
470 | tmp = readl(NFC_V3_CONFIG1); | |
471 | tmp &= ~(7 << 4); | |
472 | writel(tmp, NFC_V3_CONFIG1); | |
473 | ||
474 | /* transfer data from NFC ram to nand */ | |
475 | writel(ops, NFC_V3_LAUNCH); | |
476 | ||
477 | wait_op_done(host, false); | |
478 | } | |
479 | ||
6d38af25 UKK |
480 | static void send_page_v2(struct mtd_info *mtd, unsigned int ops) |
481 | { | |
4bd4ebcc | 482 | struct nand_chip *nand_chip = mtd_to_nand(mtd); |
d699ed25 | 483 | struct mxc_nand_host *host = nand_get_controller_data(nand_chip); |
6d38af25 UKK |
484 | |
485 | /* NANDFC buffer 0 is used for page read/write */ | |
486 | writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR); | |
487 | ||
488 | writew(ops, NFC_V1_V2_CONFIG2); | |
489 | ||
490 | /* Wait for operation to complete */ | |
491 | wait_op_done(host, true); | |
492 | } | |
493 | ||
494 | static void send_page_v1(struct mtd_info *mtd, unsigned int ops) | |
34f6e157 | 495 | { |
4bd4ebcc | 496 | struct nand_chip *nand_chip = mtd_to_nand(mtd); |
d699ed25 | 497 | struct mxc_nand_host *host = nand_get_controller_data(nand_chip); |
c5d23f1b | 498 | int bufs, i; |
34f6e157 | 499 | |
6d38af25 | 500 | if (mtd->writesize > 512) |
c5d23f1b SH |
501 | bufs = 4; |
502 | else | |
503 | bufs = 1; | |
34f6e157 | 504 | |
c5d23f1b | 505 | for (i = 0; i < bufs; i++) { |
34f6e157 | 506 | |
c5d23f1b | 507 | /* NANDFC buffer 0 is used for page read/write */ |
d178e3e8 | 508 | writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR); |
34f6e157 | 509 | |
1bc99180 | 510 | writew(ops, NFC_V1_V2_CONFIG2); |
34f6e157 | 511 | |
c5d23f1b | 512 | /* Wait for operation to complete */ |
c110eaf4 | 513 | wait_op_done(host, true); |
34f6e157 | 514 | } |
34f6e157 SH |
515 | } |
516 | ||
71ec5155 SH |
517 | static void send_read_id_v3(struct mxc_nand_host *host) |
518 | { | |
519 | /* Read ID into main buffer */ | |
520 | writel(NFC_ID, NFC_V3_LAUNCH); | |
521 | ||
522 | wait_op_done(host, true); | |
523 | ||
096bcc23 | 524 | memcpy32_fromio(host->data_buf, host->main_area0, 16); |
71ec5155 SH |
525 | } |
526 | ||
34f6e157 | 527 | /* Request the NANDFC to perform a read of the NAND device ID. */ |
5f97304e | 528 | static void send_read_id_v1_v2(struct mxc_nand_host *host) |
34f6e157 | 529 | { |
34f6e157 | 530 | /* NANDFC buffer 0 is used for device ID output */ |
d178e3e8 | 531 | writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR); |
34f6e157 | 532 | |
1bc99180 | 533 | writew(NFC_ID, NFC_V1_V2_CONFIG2); |
34f6e157 SH |
534 | |
535 | /* Wait for operation to complete */ | |
c110eaf4 | 536 | wait_op_done(host, true); |
34f6e157 | 537 | |
096bcc23 | 538 | memcpy32_fromio(host->data_buf, host->main_area0, 16); |
34f6e157 SH |
539 | } |
540 | ||
71ec5155 SH |
541 | static uint16_t get_dev_status_v3(struct mxc_nand_host *host) |
542 | { | |
543 | writew(NFC_STATUS, NFC_V3_LAUNCH); | |
544 | wait_op_done(host, true); | |
545 | ||
546 | return readl(NFC_V3_CONFIG1) >> 16; | |
547 | } | |
548 | ||
34f6e157 SH |
549 | /* This function requests the NANDFC to perform a read of the |
550 | * NAND device status and returns the current status. */ | |
5f97304e | 551 | static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host) |
34f6e157 | 552 | { |
c29c607a | 553 | void __iomem *main_buf = host->main_area0; |
34f6e157 | 554 | uint32_t store; |
f06368f7 | 555 | uint16_t ret; |
34f6e157 | 556 | |
d178e3e8 | 557 | writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR); |
34f6e157 | 558 | |
c29c607a SH |
559 | /* |
560 | * The device status is stored in main_area0. To | |
561 | * prevent corruption of the buffer save the value | |
562 | * and restore it afterwards. | |
563 | */ | |
34f6e157 | 564 | store = readl(main_buf); |
34f6e157 | 565 | |
1bc99180 | 566 | writew(NFC_STATUS, NFC_V1_V2_CONFIG2); |
c110eaf4 | 567 | wait_op_done(host, true); |
34f6e157 | 568 | |
34f6e157 | 569 | ret = readw(main_buf); |
c29c607a | 570 | |
34f6e157 SH |
571 | writel(store, main_buf); |
572 | ||
573 | return ret; | |
574 | } | |
575 | ||
576 | /* This functions is used by upper layer to checks if device is ready */ | |
577 | static int mxc_nand_dev_ready(struct mtd_info *mtd) | |
578 | { | |
579 | /* | |
580 | * NFC handles R/B internally. Therefore, this function | |
581 | * always returns status as ready. | |
582 | */ | |
583 | return 1; | |
584 | } | |
585 | ||
586 | static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode) | |
587 | { | |
588 | /* | |
589 | * If HW ECC is enabled, we turn it on during init. There is | |
590 | * no need to enable again here. | |
591 | */ | |
592 | } | |
593 | ||
94f77e50 | 594 | static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat, |
34f6e157 SH |
595 | u_char *read_ecc, u_char *calc_ecc) |
596 | { | |
4bd4ebcc | 597 | struct nand_chip *nand_chip = mtd_to_nand(mtd); |
d699ed25 | 598 | struct mxc_nand_host *host = nand_get_controller_data(nand_chip); |
34f6e157 SH |
599 | |
600 | /* | |
601 | * 1-Bit errors are automatically corrected in HW. No need for | |
602 | * additional correction. 2-Bit errors cannot be corrected by | |
603 | * HW ECC, so we need to return failure | |
604 | */ | |
6d38af25 | 605 | uint16_t ecc_status = get_ecc_status_v1(host); |
34f6e157 SH |
606 | |
607 | if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) { | |
289c0522 | 608 | pr_debug("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n"); |
6e941192 | 609 | return -EBADMSG; |
34f6e157 SH |
610 | } |
611 | ||
612 | return 0; | |
613 | } | |
614 | ||
94f77e50 SH |
615 | static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat, |
616 | u_char *read_ecc, u_char *calc_ecc) | |
617 | { | |
4bd4ebcc | 618 | struct nand_chip *nand_chip = mtd_to_nand(mtd); |
d699ed25 | 619 | struct mxc_nand_host *host = nand_get_controller_data(nand_chip); |
94f77e50 SH |
620 | u32 ecc_stat, err; |
621 | int no_subpages = 1; | |
622 | int ret = 0; | |
623 | u8 ecc_bit_mask, err_limit; | |
624 | ||
625 | ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf; | |
626 | err_limit = (host->eccsize == 4) ? 0x4 : 0x8; | |
627 | ||
628 | no_subpages = mtd->writesize >> 9; | |
629 | ||
6d38af25 | 630 | ecc_stat = host->devtype_data->get_ecc_status(host); |
94f77e50 SH |
631 | |
632 | do { | |
633 | err = ecc_stat & ecc_bit_mask; | |
634 | if (err > err_limit) { | |
635 | printk(KERN_WARNING "UnCorrectable RS-ECC Error\n"); | |
6e941192 | 636 | return -EBADMSG; |
94f77e50 SH |
637 | } else { |
638 | ret += err; | |
639 | } | |
640 | ecc_stat >>= 4; | |
641 | } while (--no_subpages); | |
642 | ||
94f77e50 SH |
643 | pr_debug("%d Symbol Correctable RS-ECC Error\n", ret); |
644 | ||
645 | return ret; | |
646 | } | |
647 | ||
34f6e157 SH |
648 | static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, |
649 | u_char *ecc_code) | |
650 | { | |
651 | return 0; | |
652 | } | |
653 | ||
654 | static u_char mxc_nand_read_byte(struct mtd_info *mtd) | |
655 | { | |
4bd4ebcc | 656 | struct nand_chip *nand_chip = mtd_to_nand(mtd); |
d699ed25 | 657 | struct mxc_nand_host *host = nand_get_controller_data(nand_chip); |
f8f9608d | 658 | uint8_t ret; |
34f6e157 SH |
659 | |
660 | /* Check for status request */ | |
661 | if (host->status_request) | |
e4303b25 | 662 | return host->devtype_data->get_dev_status(host) & 0xFF; |
34f6e157 | 663 | |
3f410690 UKK |
664 | if (nand_chip->options & NAND_BUSWIDTH_16) { |
665 | /* only take the lower byte of each word */ | |
666 | ret = *(uint16_t *)(host->data_buf + host->buf_start); | |
667 | ||
668 | host->buf_start += 2; | |
669 | } else { | |
670 | ret = *(uint8_t *)(host->data_buf + host->buf_start); | |
671 | host->buf_start++; | |
672 | } | |
34f6e157 | 673 | |
3f410690 | 674 | pr_debug("%s: ret=0x%hhx (start=%u)\n", __func__, ret, host->buf_start); |
34f6e157 SH |
675 | return ret; |
676 | } | |
677 | ||
678 | static uint16_t mxc_nand_read_word(struct mtd_info *mtd) | |
679 | { | |
4bd4ebcc | 680 | struct nand_chip *nand_chip = mtd_to_nand(mtd); |
d699ed25 | 681 | struct mxc_nand_host *host = nand_get_controller_data(nand_chip); |
f8f9608d | 682 | uint16_t ret; |
34f6e157 | 683 | |
f8f9608d SH |
684 | ret = *(uint16_t *)(host->data_buf + host->buf_start); |
685 | host->buf_start += 2; | |
34f6e157 SH |
686 | |
687 | return ret; | |
688 | } | |
689 | ||
690 | /* Write data of length len to buffer buf. The data to be | |
691 | * written on NAND Flash is first copied to RAMbuffer. After the Data Input | |
692 | * Operation by the NFC, the data is written to NAND Flash */ | |
693 | static void mxc_nand_write_buf(struct mtd_info *mtd, | |
694 | const u_char *buf, int len) | |
695 | { | |
4bd4ebcc | 696 | struct nand_chip *nand_chip = mtd_to_nand(mtd); |
d699ed25 | 697 | struct mxc_nand_host *host = nand_get_controller_data(nand_chip); |
f8f9608d SH |
698 | u16 col = host->buf_start; |
699 | int n = mtd->oobsize + mtd->writesize - col; | |
34f6e157 | 700 | |
f8f9608d | 701 | n = min(n, len); |
34f6e157 | 702 | |
f8f9608d | 703 | memcpy(host->data_buf + col, buf, n); |
34f6e157 | 704 | |
f8f9608d | 705 | host->buf_start += n; |
34f6e157 SH |
706 | } |
707 | ||
708 | /* Read the data buffer from the NAND Flash. To read the data from NAND | |
709 | * Flash first the data output cycle is initiated by the NFC, which copies | |
710 | * the data to RAMbuffer. This data of length len is then copied to buffer buf. | |
711 | */ | |
712 | static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) | |
713 | { | |
4bd4ebcc | 714 | struct nand_chip *nand_chip = mtd_to_nand(mtd); |
d699ed25 | 715 | struct mxc_nand_host *host = nand_get_controller_data(nand_chip); |
f8f9608d SH |
716 | u16 col = host->buf_start; |
717 | int n = mtd->oobsize + mtd->writesize - col; | |
34f6e157 | 718 | |
f8f9608d | 719 | n = min(n, len); |
34f6e157 | 720 | |
5d9d9936 | 721 | memcpy(buf, host->data_buf + col, n); |
34f6e157 | 722 | |
5d9d9936 | 723 | host->buf_start += n; |
34f6e157 SH |
724 | } |
725 | ||
34f6e157 SH |
726 | /* This function is used by upper layer for select and |
727 | * deselect of the NAND chip */ | |
5e05a2d6 | 728 | static void mxc_nand_select_chip_v1_v3(struct mtd_info *mtd, int chip) |
34f6e157 | 729 | { |
4bd4ebcc | 730 | struct nand_chip *nand_chip = mtd_to_nand(mtd); |
d699ed25 | 731 | struct mxc_nand_host *host = nand_get_controller_data(nand_chip); |
34f6e157 | 732 | |
d178e3e8 | 733 | if (chip == -1) { |
34f6e157 SH |
734 | /* Disable the NFC clock */ |
735 | if (host->clk_act) { | |
97c3213f | 736 | clk_disable_unprepare(host->clk); |
34f6e157 SH |
737 | host->clk_act = 0; |
738 | } | |
d178e3e8 BS |
739 | return; |
740 | } | |
741 | ||
742 | if (!host->clk_act) { | |
34f6e157 | 743 | /* Enable the NFC clock */ |
97c3213f | 744 | clk_prepare_enable(host->clk); |
d178e3e8 BS |
745 | host->clk_act = 1; |
746 | } | |
5e05a2d6 | 747 | } |
34f6e157 | 748 | |
5e05a2d6 UKK |
749 | static void mxc_nand_select_chip_v2(struct mtd_info *mtd, int chip) |
750 | { | |
4bd4ebcc | 751 | struct nand_chip *nand_chip = mtd_to_nand(mtd); |
d699ed25 | 752 | struct mxc_nand_host *host = nand_get_controller_data(nand_chip); |
5e05a2d6 UKK |
753 | |
754 | if (chip == -1) { | |
755 | /* Disable the NFC clock */ | |
756 | if (host->clk_act) { | |
3d059693 | 757 | clk_disable_unprepare(host->clk); |
5e05a2d6 UKK |
758 | host->clk_act = 0; |
759 | } | |
760 | return; | |
761 | } | |
34f6e157 | 762 | |
5e05a2d6 UKK |
763 | if (!host->clk_act) { |
764 | /* Enable the NFC clock */ | |
3d059693 | 765 | clk_prepare_enable(host->clk); |
5e05a2d6 | 766 | host->clk_act = 1; |
34f6e157 | 767 | } |
5e05a2d6 UKK |
768 | |
769 | host->active_cs = chip; | |
770 | writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR); | |
34f6e157 SH |
771 | } |
772 | ||
f8f9608d | 773 | /* |
35d5d20e UKK |
774 | * The controller splits a page into data chunks of 512 bytes + partial oob. |
775 | * There are writesize / 512 such chunks, the size of the partial oob parts is | |
776 | * oobsize / #chunks rounded down to a multiple of 2. The last oob chunk then | |
777 | * contains additionally the byte lost by rounding (if any). | |
778 | * This function handles the needed shuffling between host->data_buf (which | |
779 | * holds a page in natural order, i.e. writesize bytes data + oobsize bytes | |
780 | * spare) and the NFC buffer. | |
f8f9608d SH |
781 | */ |
782 | static void copy_spare(struct mtd_info *mtd, bool bfrom) | |
34f6e157 | 783 | { |
4bd4ebcc | 784 | struct nand_chip *this = mtd_to_nand(mtd); |
d699ed25 | 785 | struct mxc_nand_host *host = nand_get_controller_data(this); |
35d5d20e UKK |
786 | u16 i, oob_chunk_size; |
787 | u16 num_chunks = mtd->writesize / 512; | |
788 | ||
f8f9608d | 789 | u8 *d = host->data_buf + mtd->writesize; |
4b6f05e1 | 790 | u8 __iomem *s = host->spare0; |
35d5d20e | 791 | u16 sparebuf_size = host->devtype_data->spare_len; |
f8f9608d | 792 | |
35d5d20e | 793 | /* size of oob chunk for all but possibly the last one */ |
7e7e4730 | 794 | oob_chunk_size = (host->used_oobsize / num_chunks) & ~1; |
f8f9608d SH |
795 | |
796 | if (bfrom) { | |
35d5d20e | 797 | for (i = 0; i < num_chunks - 1; i++) |
0d17fc3e | 798 | memcpy16_fromio(d + i * oob_chunk_size, |
35d5d20e UKK |
799 | s + i * sparebuf_size, |
800 | oob_chunk_size); | |
801 | ||
802 | /* the last chunk */ | |
0d17fc3e | 803 | memcpy16_fromio(d + i * oob_chunk_size, |
35d5d20e | 804 | s + i * sparebuf_size, |
7e7e4730 | 805 | host->used_oobsize - i * oob_chunk_size); |
f8f9608d | 806 | } else { |
35d5d20e | 807 | for (i = 0; i < num_chunks - 1; i++) |
0d17fc3e | 808 | memcpy16_toio(&s[i * sparebuf_size], |
35d5d20e UKK |
809 | &d[i * oob_chunk_size], |
810 | oob_chunk_size); | |
811 | ||
812 | /* the last chunk */ | |
e5a5d92d | 813 | memcpy16_toio(&s[i * sparebuf_size], |
35d5d20e | 814 | &d[i * oob_chunk_size], |
7e7e4730 | 815 | host->used_oobsize - i * oob_chunk_size); |
34f6e157 | 816 | } |
f8f9608d | 817 | } |
34f6e157 | 818 | |
c4ca3997 UKK |
819 | /* |
820 | * MXC NANDFC can only perform full page+spare or spare-only read/write. When | |
821 | * the upper layers perform a read/write buf operation, the saved column address | |
822 | * is used to index into the full page. So usually this function is called with | |
823 | * column == 0 (unless no column cycle is needed indicated by column == -1) | |
824 | */ | |
a3e65b64 SH |
825 | static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr) |
826 | { | |
4bd4ebcc | 827 | struct nand_chip *nand_chip = mtd_to_nand(mtd); |
d699ed25 | 828 | struct mxc_nand_host *host = nand_get_controller_data(nand_chip); |
34f6e157 SH |
829 | |
830 | /* Write out column address, if necessary */ | |
831 | if (column != -1) { | |
c4ca3997 UKK |
832 | host->devtype_data->send_addr(host, column & 0xff, |
833 | page_addr == -1); | |
2d69c7fa | 834 | if (mtd->writesize > 512) |
34f6e157 | 835 | /* another col addr cycle for 2k page */ |
c4ca3997 UKK |
836 | host->devtype_data->send_addr(host, |
837 | (column >> 8) & 0xff, | |
838 | false); | |
34f6e157 SH |
839 | } |
840 | ||
841 | /* Write out page address, if necessary */ | |
842 | if (page_addr != -1) { | |
843 | /* paddr_0 - p_addr_7 */ | |
e4303b25 | 844 | host->devtype_data->send_addr(host, (page_addr & 0xff), false); |
34f6e157 | 845 | |
2d69c7fa | 846 | if (mtd->writesize > 512) { |
bd3fd62e VB |
847 | if (mtd->size >= 0x10000000) { |
848 | /* paddr_8 - paddr_15 */ | |
e4303b25 UKK |
849 | host->devtype_data->send_addr(host, |
850 | (page_addr >> 8) & 0xff, | |
851 | false); | |
852 | host->devtype_data->send_addr(host, | |
853 | (page_addr >> 16) & 0xff, | |
854 | true); | |
bd3fd62e VB |
855 | } else |
856 | /* paddr_8 - paddr_15 */ | |
e4303b25 UKK |
857 | host->devtype_data->send_addr(host, |
858 | (page_addr >> 8) & 0xff, true); | |
34f6e157 SH |
859 | } else { |
860 | /* One more address cycle for higher density devices */ | |
861 | if (mtd->size >= 0x4000000) { | |
862 | /* paddr_8 - paddr_15 */ | |
e4303b25 UKK |
863 | host->devtype_data->send_addr(host, |
864 | (page_addr >> 8) & 0xff, | |
865 | false); | |
866 | host->devtype_data->send_addr(host, | |
867 | (page_addr >> 16) & 0xff, | |
868 | true); | |
34f6e157 SH |
869 | } else |
870 | /* paddr_8 - paddr_15 */ | |
e4303b25 UKK |
871 | host->devtype_data->send_addr(host, |
872 | (page_addr >> 8) & 0xff, true); | |
34f6e157 SH |
873 | } |
874 | } | |
a3e65b64 SH |
875 | } |
876 | ||
a894cf6c BB |
877 | static int mxc_v1_ooblayout_ecc(struct mtd_info *mtd, int section, |
878 | struct mtd_oob_region *oobregion) | |
879 | { | |
880 | struct nand_chip *nand_chip = mtd_to_nand(mtd); | |
881 | ||
882 | if (section >= nand_chip->ecc.steps) | |
883 | return -ERANGE; | |
884 | ||
885 | oobregion->offset = (section * 16) + 6; | |
886 | oobregion->length = nand_chip->ecc.bytes; | |
887 | ||
888 | return 0; | |
889 | } | |
890 | ||
891 | static int mxc_v1_ooblayout_free(struct mtd_info *mtd, int section, | |
892 | struct mtd_oob_region *oobregion) | |
893 | { | |
894 | struct nand_chip *nand_chip = mtd_to_nand(mtd); | |
895 | ||
896 | if (section > nand_chip->ecc.steps) | |
897 | return -ERANGE; | |
898 | ||
899 | if (!section) { | |
900 | if (mtd->writesize <= 512) { | |
901 | oobregion->offset = 0; | |
902 | oobregion->length = 5; | |
903 | } else { | |
904 | oobregion->offset = 2; | |
905 | oobregion->length = 4; | |
906 | } | |
907 | } else { | |
908 | oobregion->offset = ((section - 1) * 16) + | |
909 | nand_chip->ecc.bytes + 6; | |
910 | if (section < nand_chip->ecc.steps) | |
911 | oobregion->length = (section * 16) + 6 - | |
912 | oobregion->offset; | |
913 | else | |
914 | oobregion->length = mtd->oobsize - oobregion->offset; | |
915 | } | |
916 | ||
917 | return 0; | |
918 | } | |
919 | ||
920 | static const struct mtd_ooblayout_ops mxc_v1_ooblayout_ops = { | |
921 | .ecc = mxc_v1_ooblayout_ecc, | |
922 | .free = mxc_v1_ooblayout_free, | |
923 | }; | |
924 | ||
925 | static int mxc_v2_ooblayout_ecc(struct mtd_info *mtd, int section, | |
926 | struct mtd_oob_region *oobregion) | |
927 | { | |
928 | struct nand_chip *nand_chip = mtd_to_nand(mtd); | |
929 | int stepsize = nand_chip->ecc.bytes == 9 ? 16 : 26; | |
930 | ||
931 | if (section >= nand_chip->ecc.steps) | |
932 | return -ERANGE; | |
933 | ||
934 | oobregion->offset = (section * stepsize) + 7; | |
935 | oobregion->length = nand_chip->ecc.bytes; | |
936 | ||
937 | return 0; | |
938 | } | |
939 | ||
940 | static int mxc_v2_ooblayout_free(struct mtd_info *mtd, int section, | |
941 | struct mtd_oob_region *oobregion) | |
942 | { | |
943 | struct nand_chip *nand_chip = mtd_to_nand(mtd); | |
944 | int stepsize = nand_chip->ecc.bytes == 9 ? 16 : 26; | |
945 | ||
946 | if (section > nand_chip->ecc.steps) | |
947 | return -ERANGE; | |
948 | ||
949 | if (!section) { | |
950 | if (mtd->writesize <= 512) { | |
951 | oobregion->offset = 0; | |
952 | oobregion->length = 5; | |
953 | } else { | |
954 | oobregion->offset = 2; | |
955 | oobregion->length = 4; | |
956 | } | |
957 | } else { | |
958 | oobregion->offset = section * stepsize; | |
959 | oobregion->length = 7; | |
960 | } | |
961 | ||
962 | return 0; | |
963 | } | |
964 | ||
965 | static const struct mtd_ooblayout_ops mxc_v2_ooblayout_ops = { | |
966 | .ecc = mxc_v2_ooblayout_ecc, | |
967 | .free = mxc_v2_ooblayout_free, | |
968 | }; | |
969 | ||
6e85dfdc SH |
970 | /* |
971 | * v2 and v3 type controllers can do 4bit or 8bit ecc depending | |
972 | * on how much oob the nand chip has. For 8bit ecc we need at least | |
973 | * 26 bytes of oob data per 512 byte block. | |
974 | */ | |
975 | static int get_eccsize(struct mtd_info *mtd) | |
976 | { | |
977 | int oobbytes_per_512 = 0; | |
978 | ||
979 | oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize; | |
980 | ||
981 | if (oobbytes_per_512 < 26) | |
982 | return 4; | |
983 | else | |
984 | return 8; | |
985 | } | |
986 | ||
6d38af25 | 987 | static void preset_v1(struct mtd_info *mtd) |
d4840180 | 988 | { |
4bd4ebcc | 989 | struct nand_chip *nand_chip = mtd_to_nand(mtd); |
d699ed25 | 990 | struct mxc_nand_host *host = nand_get_controller_data(nand_chip); |
b8db2f51 SH |
991 | uint16_t config1 = 0; |
992 | ||
1f42adc8 | 993 | if (nand_chip->ecc.mode == NAND_ECC_HW && mtd->writesize) |
b8db2f51 SH |
994 | config1 |= NFC_V1_V2_CONFIG1_ECC_EN; |
995 | ||
f48d0f9a | 996 | if (!host->devtype_data->irqpending_quirk) |
6d38af25 UKK |
997 | config1 |= NFC_V1_V2_CONFIG1_INT_MSK; |
998 | ||
999 | host->eccsize = 1; | |
1000 | ||
1001 | writew(config1, NFC_V1_V2_CONFIG1); | |
1002 | /* preset operation */ | |
1003 | ||
1004 | /* Unlock the internal RAM Buffer */ | |
1005 | writew(0x2, NFC_V1_V2_CONFIG); | |
1006 | ||
1007 | /* Blocks to be unlocked */ | |
1008 | writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR); | |
1009 | writew(0xffff, NFC_V1_UNLOCKEND_BLKADDR); | |
1010 | ||
1011 | /* Unlock Block Command for given address range */ | |
1012 | writew(0x4, NFC_V1_V2_WRPROT); | |
1013 | } | |
1014 | ||
1015 | static void preset_v2(struct mtd_info *mtd) | |
d4840180 | 1016 | { |
4bd4ebcc | 1017 | struct nand_chip *nand_chip = mtd_to_nand(mtd); |
d699ed25 | 1018 | struct mxc_nand_host *host = nand_get_controller_data(nand_chip); |
b8db2f51 SH |
1019 | uint16_t config1 = 0; |
1020 | ||
6d38af25 | 1021 | config1 |= NFC_V2_CONFIG1_FP_INT; |
b8db2f51 | 1022 | |
f48d0f9a | 1023 | if (!host->devtype_data->irqpending_quirk) |
b8db2f51 | 1024 | config1 |= NFC_V1_V2_CONFIG1_INT_MSK; |
6e85dfdc | 1025 | |
6d38af25 | 1026 | if (mtd->writesize) { |
b8db2f51 SH |
1027 | uint16_t pages_per_block = mtd->erasesize / mtd->writesize; |
1028 | ||
1f42adc8 UKK |
1029 | if (nand_chip->ecc.mode == NAND_ECC_HW) |
1030 | config1 |= NFC_V1_V2_CONFIG1_ECC_EN; | |
1031 | ||
6e85dfdc SH |
1032 | host->eccsize = get_eccsize(mtd); |
1033 | if (host->eccsize == 4) | |
b8db2f51 SH |
1034 | config1 |= NFC_V2_CONFIG1_ECC_MODE_4; |
1035 | ||
1036 | config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6); | |
d4840180 | 1037 | } else { |
6e85dfdc | 1038 | host->eccsize = 1; |
d4840180 | 1039 | } |
6e85dfdc | 1040 | |
b8db2f51 | 1041 | writew(config1, NFC_V1_V2_CONFIG1); |
d4840180 IC |
1042 | /* preset operation */ |
1043 | ||
1044 | /* Unlock the internal RAM Buffer */ | |
1bc99180 | 1045 | writew(0x2, NFC_V1_V2_CONFIG); |
d4840180 IC |
1046 | |
1047 | /* Blocks to be unlocked */ | |
6d38af25 UKK |
1048 | writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0); |
1049 | writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1); | |
1050 | writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2); | |
1051 | writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3); | |
1052 | writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0); | |
1053 | writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1); | |
1054 | writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2); | |
1055 | writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3); | |
d4840180 IC |
1056 | |
1057 | /* Unlock Block Command for given address range */ | |
1bc99180 | 1058 | writew(0x4, NFC_V1_V2_WRPROT); |
d4840180 IC |
1059 | } |
1060 | ||
71ec5155 SH |
1061 | static void preset_v3(struct mtd_info *mtd) |
1062 | { | |
4bd4ebcc | 1063 | struct nand_chip *chip = mtd_to_nand(mtd); |
d699ed25 | 1064 | struct mxc_nand_host *host = nand_get_controller_data(chip); |
71ec5155 SH |
1065 | uint32_t config2, config3; |
1066 | int i, addr_phases; | |
1067 | ||
1068 | writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1); | |
1069 | writel(NFC_V3_IPC_CREQ, NFC_V3_IPC); | |
1070 | ||
1071 | /* Unlock the internal RAM Buffer */ | |
1072 | writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK, | |
1073 | NFC_V3_WRPROT); | |
1074 | ||
1075 | /* Blocks to be unlocked */ | |
1076 | for (i = 0; i < NAND_MAX_CHIPS; i++) | |
1b15b1f5 | 1077 | writel(0xffff << 16, NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2)); |
71ec5155 SH |
1078 | |
1079 | writel(0, NFC_V3_IPC); | |
1080 | ||
1081 | config2 = NFC_V3_CONFIG2_ONE_CYCLE | | |
1082 | NFC_V3_CONFIG2_2CMD_PHASES | | |
1083 | NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) | | |
1084 | NFC_V3_CONFIG2_ST_CMD(0x70) | | |
63f1474c | 1085 | NFC_V3_CONFIG2_INT_MSK | |
71ec5155 SH |
1086 | NFC_V3_CONFIG2_NUM_ADDR_PHASE0; |
1087 | ||
71ec5155 SH |
1088 | addr_phases = fls(chip->pagemask) >> 3; |
1089 | ||
1090 | if (mtd->writesize == 2048) { | |
1091 | config2 |= NFC_V3_CONFIG2_PS_2048; | |
1092 | config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases); | |
1093 | } else if (mtd->writesize == 4096) { | |
1094 | config2 |= NFC_V3_CONFIG2_PS_4096; | |
1095 | config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases); | |
1096 | } else { | |
1097 | config2 |= NFC_V3_CONFIG2_PS_512; | |
1098 | config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1); | |
1099 | } | |
1100 | ||
1101 | if (mtd->writesize) { | |
1f42adc8 UKK |
1102 | if (chip->ecc.mode == NAND_ECC_HW) |
1103 | config2 |= NFC_V3_CONFIG2_ECC_EN; | |
1104 | ||
71718a8e SH |
1105 | config2 |= NFC_V3_CONFIG2_PPB( |
1106 | ffs(mtd->erasesize / mtd->writesize) - 6, | |
1107 | host->devtype_data->ppb_shift); | |
71ec5155 SH |
1108 | host->eccsize = get_eccsize(mtd); |
1109 | if (host->eccsize == 8) | |
1110 | config2 |= NFC_V3_CONFIG2_ECC_MODE_8; | |
1111 | } | |
1112 | ||
1113 | writel(config2, NFC_V3_CONFIG2); | |
1114 | ||
1115 | config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) | | |
1116 | NFC_V3_CONFIG3_NO_SDMA | | |
1117 | NFC_V3_CONFIG3_RBB_MODE | | |
1118 | NFC_V3_CONFIG3_SBB(6) | /* Reset default */ | |
1119 | NFC_V3_CONFIG3_ADD_OP(0); | |
1120 | ||
1121 | if (!(chip->options & NAND_BUSWIDTH_16)) | |
1122 | config3 |= NFC_V3_CONFIG3_FW8; | |
1123 | ||
1124 | writel(config3, NFC_V3_CONFIG3); | |
1125 | ||
1126 | writel(0, NFC_V3_DELAY_LINE); | |
d4840180 IC |
1127 | } |
1128 | ||
34f6e157 SH |
1129 | /* Used by the upper layer to write command to NAND Flash for |
1130 | * different operations to be carried out on NAND Flash */ | |
1131 | static void mxc_nand_command(struct mtd_info *mtd, unsigned command, | |
1132 | int column, int page_addr) | |
1133 | { | |
4bd4ebcc | 1134 | struct nand_chip *nand_chip = mtd_to_nand(mtd); |
d699ed25 | 1135 | struct mxc_nand_host *host = nand_get_controller_data(nand_chip); |
34f6e157 | 1136 | |
289c0522 | 1137 | pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n", |
34f6e157 SH |
1138 | command, column, page_addr); |
1139 | ||
1140 | /* Reset command state information */ | |
1141 | host->status_request = false; | |
34f6e157 | 1142 | |
34f6e157 | 1143 | /* Command pre-processing step */ |
34f6e157 | 1144 | switch (command) { |
d4840180 | 1145 | case NAND_CMD_RESET: |
e4303b25 UKK |
1146 | host->devtype_data->preset(mtd); |
1147 | host->devtype_data->send_cmd(host, command, false); | |
d4840180 | 1148 | break; |
34f6e157 | 1149 | |
34f6e157 | 1150 | case NAND_CMD_STATUS: |
f8f9608d | 1151 | host->buf_start = 0; |
34f6e157 | 1152 | host->status_request = true; |
34f6e157 | 1153 | |
e4303b25 | 1154 | host->devtype_data->send_cmd(host, command, true); |
c4ca3997 UKK |
1155 | WARN_ONCE(column != -1 || page_addr != -1, |
1156 | "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n", | |
1157 | command, column, page_addr); | |
89121a6b | 1158 | mxc_do_addr_cycle(mtd, column, page_addr); |
34f6e157 SH |
1159 | break; |
1160 | ||
34f6e157 | 1161 | case NAND_CMD_READ0: |
34f6e157 | 1162 | case NAND_CMD_READOOB: |
89121a6b SH |
1163 | if (command == NAND_CMD_READ0) |
1164 | host->buf_start = column; | |
1165 | else | |
1166 | host->buf_start = column + mtd->writesize; | |
f8f9608d | 1167 | |
5ea32021 | 1168 | command = NAND_CMD_READ0; /* only READ0 is valid */ |
89121a6b | 1169 | |
e4303b25 | 1170 | host->devtype_data->send_cmd(host, command, false); |
c4ca3997 UKK |
1171 | WARN_ONCE(column < 0, |
1172 | "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n", | |
1173 | command, column, page_addr); | |
1174 | mxc_do_addr_cycle(mtd, 0, page_addr); | |
89121a6b | 1175 | |
2d69c7fa | 1176 | if (mtd->writesize > 512) |
e4303b25 UKK |
1177 | host->devtype_data->send_cmd(host, |
1178 | NAND_CMD_READSTART, true); | |
c5d23f1b | 1179 | |
e4303b25 | 1180 | host->devtype_data->send_page(mtd, NFC_OUTPUT); |
89121a6b | 1181 | |
096bcc23 SH |
1182 | memcpy32_fromio(host->data_buf, host->main_area0, |
1183 | mtd->writesize); | |
89121a6b | 1184 | copy_spare(mtd, true); |
34f6e157 SH |
1185 | break; |
1186 | ||
34f6e157 | 1187 | case NAND_CMD_SEQIN: |
5ea32021 SH |
1188 | if (column >= mtd->writesize) |
1189 | /* call ourself to read a page */ | |
1190 | mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr); | |
34f6e157 | 1191 | |
5ea32021 | 1192 | host->buf_start = column; |
89121a6b | 1193 | |
e4303b25 | 1194 | host->devtype_data->send_cmd(host, command, false); |
c4ca3997 UKK |
1195 | WARN_ONCE(column < -1, |
1196 | "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n", | |
1197 | command, column, page_addr); | |
1198 | mxc_do_addr_cycle(mtd, 0, page_addr); | |
34f6e157 SH |
1199 | break; |
1200 | ||
1201 | case NAND_CMD_PAGEPROG: | |
096bcc23 | 1202 | memcpy32_toio(host->main_area0, host->data_buf, mtd->writesize); |
f8f9608d | 1203 | copy_spare(mtd, false); |
e4303b25 UKK |
1204 | host->devtype_data->send_page(mtd, NFC_INPUT); |
1205 | host->devtype_data->send_cmd(host, command, true); | |
c4ca3997 UKK |
1206 | WARN_ONCE(column != -1 || page_addr != -1, |
1207 | "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n", | |
1208 | command, column, page_addr); | |
89121a6b | 1209 | mxc_do_addr_cycle(mtd, column, page_addr); |
34f6e157 SH |
1210 | break; |
1211 | ||
34f6e157 | 1212 | case NAND_CMD_READID: |
e4303b25 | 1213 | host->devtype_data->send_cmd(host, command, true); |
89121a6b | 1214 | mxc_do_addr_cycle(mtd, column, page_addr); |
e4303b25 | 1215 | host->devtype_data->send_read_id(host); |
c4ca3997 | 1216 | host->buf_start = 0; |
34f6e157 SH |
1217 | break; |
1218 | ||
89121a6b | 1219 | case NAND_CMD_ERASE1: |
34f6e157 | 1220 | case NAND_CMD_ERASE2: |
e4303b25 | 1221 | host->devtype_data->send_cmd(host, command, false); |
c4ca3997 UKK |
1222 | WARN_ONCE(column != -1, |
1223 | "Unexpected column value (cmd=%u, col=%d)\n", | |
1224 | command, column); | |
89121a6b SH |
1225 | mxc_do_addr_cycle(mtd, column, page_addr); |
1226 | ||
3d6e81c0 UKK |
1227 | break; |
1228 | case NAND_CMD_PARAM: | |
1229 | host->devtype_data->send_cmd(host, command, false); | |
1230 | mxc_do_addr_cycle(mtd, column, page_addr); | |
1231 | host->devtype_data->send_page(mtd, NFC_OUTPUT); | |
1232 | memcpy32_fromio(host->data_buf, host->main_area0, 512); | |
1233 | host->buf_start = 0; | |
34f6e157 | 1234 | break; |
98ebb521 UKK |
1235 | default: |
1236 | WARN_ONCE(1, "Unimplemented command (cmd=%u)\n", | |
1237 | command); | |
1238 | break; | |
34f6e157 SH |
1239 | } |
1240 | } | |
1241 | ||
f1372055 SH |
1242 | /* |
1243 | * The generic flash bbt decriptors overlap with our ecc | |
1244 | * hardware, so define some i.MX specific ones. | |
1245 | */ | |
1246 | static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' }; | |
1247 | static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' }; | |
1248 | ||
1249 | static struct nand_bbt_descr bbt_main_descr = { | |
1250 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
1251 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
1252 | .offs = 0, | |
1253 | .len = 4, | |
1254 | .veroffs = 4, | |
1255 | .maxblocks = 4, | |
1256 | .pattern = bbt_pattern, | |
1257 | }; | |
1258 | ||
1259 | static struct nand_bbt_descr bbt_mirror_descr = { | |
1260 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
1261 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
1262 | .offs = 0, | |
1263 | .len = 4, | |
1264 | .veroffs = 4, | |
1265 | .maxblocks = 4, | |
1266 | .pattern = mirror_pattern, | |
1267 | }; | |
1268 | ||
f48d0f9a | 1269 | /* v1 + irqpending_quirk: i.MX21 */ |
e4303b25 | 1270 | static const struct mxc_nand_devtype_data imx21_nand_devtype_data = { |
6d38af25 | 1271 | .preset = preset_v1, |
e4303b25 UKK |
1272 | .send_cmd = send_cmd_v1_v2, |
1273 | .send_addr = send_addr_v1_v2, | |
6d38af25 | 1274 | .send_page = send_page_v1, |
e4303b25 UKK |
1275 | .send_read_id = send_read_id_v1_v2, |
1276 | .get_dev_status = get_dev_status_v1_v2, | |
1277 | .check_int = check_int_v1_v2, | |
1278 | .irq_control = irq_control_v1_v2, | |
6d38af25 | 1279 | .get_ecc_status = get_ecc_status_v1, |
a894cf6c | 1280 | .ooblayout = &mxc_v1_ooblayout_ops, |
5e05a2d6 | 1281 | .select_chip = mxc_nand_select_chip_v1_v3, |
69d023be | 1282 | .correct_data = mxc_nand_correct_data_v1, |
f48d0f9a UKK |
1283 | .irqpending_quirk = 1, |
1284 | .needs_ip = 0, | |
1285 | .regs_offset = 0xe00, | |
1286 | .spare0_offset = 0x800, | |
1287 | .spare_len = 16, | |
1288 | .eccbytes = 3, | |
1289 | .eccsize = 1, | |
1290 | }; | |
1291 | ||
1292 | /* v1 + !irqpending_quirk: i.MX27, i.MX31 */ | |
1293 | static const struct mxc_nand_devtype_data imx27_nand_devtype_data = { | |
1294 | .preset = preset_v1, | |
1295 | .send_cmd = send_cmd_v1_v2, | |
1296 | .send_addr = send_addr_v1_v2, | |
1297 | .send_page = send_page_v1, | |
1298 | .send_read_id = send_read_id_v1_v2, | |
1299 | .get_dev_status = get_dev_status_v1_v2, | |
1300 | .check_int = check_int_v1_v2, | |
1301 | .irq_control = irq_control_v1_v2, | |
1302 | .get_ecc_status = get_ecc_status_v1, | |
a894cf6c | 1303 | .ooblayout = &mxc_v1_ooblayout_ops, |
f48d0f9a UKK |
1304 | .select_chip = mxc_nand_select_chip_v1_v3, |
1305 | .correct_data = mxc_nand_correct_data_v1, | |
1306 | .irqpending_quirk = 0, | |
1307 | .needs_ip = 0, | |
1308 | .regs_offset = 0xe00, | |
1309 | .spare0_offset = 0x800, | |
1310 | .axi_offset = 0, | |
1311 | .spare_len = 16, | |
1312 | .eccbytes = 3, | |
1313 | .eccsize = 1, | |
e4303b25 UKK |
1314 | }; |
1315 | ||
1316 | /* v21: i.MX25, i.MX35 */ | |
1317 | static const struct mxc_nand_devtype_data imx25_nand_devtype_data = { | |
6d38af25 | 1318 | .preset = preset_v2, |
e4303b25 UKK |
1319 | .send_cmd = send_cmd_v1_v2, |
1320 | .send_addr = send_addr_v1_v2, | |
6d38af25 | 1321 | .send_page = send_page_v2, |
e4303b25 UKK |
1322 | .send_read_id = send_read_id_v1_v2, |
1323 | .get_dev_status = get_dev_status_v1_v2, | |
1324 | .check_int = check_int_v1_v2, | |
1325 | .irq_control = irq_control_v1_v2, | |
6d38af25 | 1326 | .get_ecc_status = get_ecc_status_v2, |
a894cf6c | 1327 | .ooblayout = &mxc_v2_ooblayout_ops, |
5e05a2d6 | 1328 | .select_chip = mxc_nand_select_chip_v2, |
69d023be | 1329 | .correct_data = mxc_nand_correct_data_v2_v3, |
f48d0f9a UKK |
1330 | .irqpending_quirk = 0, |
1331 | .needs_ip = 0, | |
1332 | .regs_offset = 0x1e00, | |
1333 | .spare0_offset = 0x1000, | |
1334 | .axi_offset = 0, | |
1335 | .spare_len = 64, | |
1336 | .eccbytes = 9, | |
1337 | .eccsize = 0, | |
e4303b25 UKK |
1338 | }; |
1339 | ||
71718a8e | 1340 | /* v3.2a: i.MX51 */ |
e4303b25 UKK |
1341 | static const struct mxc_nand_devtype_data imx51_nand_devtype_data = { |
1342 | .preset = preset_v3, | |
1343 | .send_cmd = send_cmd_v3, | |
1344 | .send_addr = send_addr_v3, | |
1345 | .send_page = send_page_v3, | |
1346 | .send_read_id = send_read_id_v3, | |
1347 | .get_dev_status = get_dev_status_v3, | |
1348 | .check_int = check_int_v3, | |
1349 | .irq_control = irq_control_v3, | |
6d38af25 | 1350 | .get_ecc_status = get_ecc_status_v3, |
a894cf6c | 1351 | .ooblayout = &mxc_v2_ooblayout_ops, |
5e05a2d6 | 1352 | .select_chip = mxc_nand_select_chip_v1_v3, |
69d023be | 1353 | .correct_data = mxc_nand_correct_data_v2_v3, |
f48d0f9a UKK |
1354 | .irqpending_quirk = 0, |
1355 | .needs_ip = 1, | |
1356 | .regs_offset = 0, | |
1357 | .spare0_offset = 0x1000, | |
1358 | .axi_offset = 0x1e00, | |
1359 | .spare_len = 64, | |
1360 | .eccbytes = 0, | |
1361 | .eccsize = 0, | |
71718a8e SH |
1362 | .ppb_shift = 7, |
1363 | }; | |
1364 | ||
1365 | /* v3.2b: i.MX53 */ | |
1366 | static const struct mxc_nand_devtype_data imx53_nand_devtype_data = { | |
1367 | .preset = preset_v3, | |
1368 | .send_cmd = send_cmd_v3, | |
1369 | .send_addr = send_addr_v3, | |
1370 | .send_page = send_page_v3, | |
1371 | .send_read_id = send_read_id_v3, | |
1372 | .get_dev_status = get_dev_status_v3, | |
1373 | .check_int = check_int_v3, | |
1374 | .irq_control = irq_control_v3, | |
1375 | .get_ecc_status = get_ecc_status_v3, | |
a894cf6c | 1376 | .ooblayout = &mxc_v2_ooblayout_ops, |
71718a8e SH |
1377 | .select_chip = mxc_nand_select_chip_v1_v3, |
1378 | .correct_data = mxc_nand_correct_data_v2_v3, | |
1379 | .irqpending_quirk = 0, | |
1380 | .needs_ip = 1, | |
1381 | .regs_offset = 0, | |
1382 | .spare0_offset = 0x1000, | |
1383 | .axi_offset = 0x1e00, | |
1384 | .spare_len = 64, | |
1385 | .eccbytes = 0, | |
1386 | .eccsize = 0, | |
1387 | .ppb_shift = 8, | |
e4303b25 UKK |
1388 | }; |
1389 | ||
4d62435f SG |
1390 | static inline int is_imx21_nfc(struct mxc_nand_host *host) |
1391 | { | |
1392 | return host->devtype_data == &imx21_nand_devtype_data; | |
1393 | } | |
1394 | ||
1395 | static inline int is_imx27_nfc(struct mxc_nand_host *host) | |
1396 | { | |
1397 | return host->devtype_data == &imx27_nand_devtype_data; | |
1398 | } | |
1399 | ||
1400 | static inline int is_imx25_nfc(struct mxc_nand_host *host) | |
1401 | { | |
1402 | return host->devtype_data == &imx25_nand_devtype_data; | |
1403 | } | |
1404 | ||
1405 | static inline int is_imx51_nfc(struct mxc_nand_host *host) | |
1406 | { | |
1407 | return host->devtype_data == &imx51_nand_devtype_data; | |
1408 | } | |
1409 | ||
1410 | static inline int is_imx53_nfc(struct mxc_nand_host *host) | |
1411 | { | |
1412 | return host->devtype_data == &imx53_nand_devtype_data; | |
1413 | } | |
1414 | ||
8d1e568d | 1415 | static const struct platform_device_id mxcnd_devtype[] = { |
4d62435f SG |
1416 | { |
1417 | .name = "imx21-nand", | |
1418 | .driver_data = (kernel_ulong_t) &imx21_nand_devtype_data, | |
1419 | }, { | |
1420 | .name = "imx27-nand", | |
1421 | .driver_data = (kernel_ulong_t) &imx27_nand_devtype_data, | |
1422 | }, { | |
1423 | .name = "imx25-nand", | |
1424 | .driver_data = (kernel_ulong_t) &imx25_nand_devtype_data, | |
1425 | }, { | |
1426 | .name = "imx51-nand", | |
1427 | .driver_data = (kernel_ulong_t) &imx51_nand_devtype_data, | |
1428 | }, { | |
1429 | .name = "imx53-nand", | |
1430 | .driver_data = (kernel_ulong_t) &imx53_nand_devtype_data, | |
1431 | }, { | |
1432 | /* sentinel */ | |
1433 | } | |
1434 | }; | |
1435 | MODULE_DEVICE_TABLE(platform, mxcnd_devtype); | |
1436 | ||
6436356b UKK |
1437 | #ifdef CONFIG_OF_MTD |
1438 | static const struct of_device_id mxcnd_dt_ids[] = { | |
1439 | { | |
1440 | .compatible = "fsl,imx21-nand", | |
1441 | .data = &imx21_nand_devtype_data, | |
1442 | }, { | |
1443 | .compatible = "fsl,imx27-nand", | |
1444 | .data = &imx27_nand_devtype_data, | |
1445 | }, { | |
1446 | .compatible = "fsl,imx25-nand", | |
1447 | .data = &imx25_nand_devtype_data, | |
1448 | }, { | |
1449 | .compatible = "fsl,imx51-nand", | |
1450 | .data = &imx51_nand_devtype_data, | |
71718a8e SH |
1451 | }, { |
1452 | .compatible = "fsl,imx53-nand", | |
1453 | .data = &imx53_nand_devtype_data, | |
6436356b UKK |
1454 | }, |
1455 | { /* sentinel */ } | |
1456 | }; | |
b33c35b1 | 1457 | MODULE_DEVICE_TABLE(of, mxcnd_dt_ids); |
6436356b UKK |
1458 | |
1459 | static int __init mxcnd_probe_dt(struct mxc_nand_host *host) | |
1460 | { | |
1461 | struct device_node *np = host->dev->of_node; | |
6436356b UKK |
1462 | const struct of_device_id *of_id = |
1463 | of_match_device(mxcnd_dt_ids, host->dev); | |
6436356b UKK |
1464 | |
1465 | if (!np) | |
1466 | return 1; | |
1467 | ||
6436356b UKK |
1468 | host->devtype_data = of_id->data; |
1469 | ||
1470 | return 0; | |
1471 | } | |
1472 | #else | |
1473 | static int __init mxcnd_probe_dt(struct mxc_nand_host *host) | |
1474 | { | |
1475 | return 1; | |
1476 | } | |
1477 | #endif | |
1478 | ||
06f25510 | 1479 | static int mxcnd_probe(struct platform_device *pdev) |
34f6e157 SH |
1480 | { |
1481 | struct nand_chip *this; | |
1482 | struct mtd_info *mtd; | |
34f6e157 SH |
1483 | struct mxc_nand_host *host; |
1484 | struct resource *res; | |
d4ed8f12 | 1485 | int err = 0; |
34f6e157 SH |
1486 | |
1487 | /* Allocate memory for MTD device structure and private data */ | |
a5900554 HS |
1488 | host = devm_kzalloc(&pdev->dev, sizeof(struct mxc_nand_host), |
1489 | GFP_KERNEL); | |
34f6e157 SH |
1490 | if (!host) |
1491 | return -ENOMEM; | |
1492 | ||
a5900554 HS |
1493 | /* allocate a temporary buffer for the nand_scan_ident() */ |
1494 | host->data_buf = devm_kzalloc(&pdev->dev, PAGE_SIZE, GFP_KERNEL); | |
1495 | if (!host->data_buf) | |
1496 | return -ENOMEM; | |
f8f9608d | 1497 | |
34f6e157 SH |
1498 | host->dev = &pdev->dev; |
1499 | /* structures must be linked */ | |
1500 | this = &host->nand; | |
a008deb1 | 1501 | mtd = nand_to_mtd(this); |
87f39f04 | 1502 | mtd->dev.parent = &pdev->dev; |
1fbff0a6 | 1503 | mtd->name = DRIVER_NAME; |
34f6e157 SH |
1504 | |
1505 | /* 50 us command delay time */ | |
1506 | this->chip_delay = 5; | |
1507 | ||
d699ed25 | 1508 | nand_set_controller_data(this, host); |
a61ae81a | 1509 | nand_set_flash_node(this, pdev->dev.of_node), |
34f6e157 SH |
1510 | this->dev_ready = mxc_nand_dev_ready; |
1511 | this->cmdfunc = mxc_nand_command; | |
34f6e157 SH |
1512 | this->read_byte = mxc_nand_read_byte; |
1513 | this->read_word = mxc_nand_read_word; | |
1514 | this->write_buf = mxc_nand_write_buf; | |
1515 | this->read_buf = mxc_nand_read_buf; | |
34f6e157 | 1516 | |
24b82d3c | 1517 | host->clk = devm_clk_get(&pdev->dev, NULL); |
e4a09cbf SH |
1518 | if (IS_ERR(host->clk)) |
1519 | return PTR_ERR(host->clk); | |
34f6e157 | 1520 | |
71885b65 | 1521 | err = mxcnd_probe_dt(host); |
4d62435f | 1522 | if (err > 0) { |
453810b7 JH |
1523 | struct mxc_nand_platform_data *pdata = |
1524 | dev_get_platdata(&pdev->dev); | |
4d62435f SG |
1525 | if (pdata) { |
1526 | host->pdata = *pdata; | |
1527 | host->devtype_data = (struct mxc_nand_devtype_data *) | |
1528 | pdev->id_entry->driver_data; | |
1529 | } else { | |
1530 | err = -ENODEV; | |
1531 | } | |
1532 | } | |
71885b65 SH |
1533 | if (err < 0) |
1534 | return err; | |
1535 | ||
1536 | if (host->devtype_data->needs_ip) { | |
1537 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
b0de774c TR |
1538 | host->regs_ip = devm_ioremap_resource(&pdev->dev, res); |
1539 | if (IS_ERR(host->regs_ip)) | |
1540 | return PTR_ERR(host->regs_ip); | |
71885b65 SH |
1541 | |
1542 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1543 | } else { | |
1544 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1545 | } | |
1546 | ||
b0de774c TR |
1547 | host->base = devm_ioremap_resource(&pdev->dev, res); |
1548 | if (IS_ERR(host->base)) | |
1549 | return PTR_ERR(host->base); | |
34f6e157 | 1550 | |
c6de7e1b | 1551 | host->main_area0 = host->base; |
9467114e | 1552 | |
f48d0f9a UKK |
1553 | if (host->devtype_data->regs_offset) |
1554 | host->regs = host->base + host->devtype_data->regs_offset; | |
1555 | host->spare0 = host->base + host->devtype_data->spare0_offset; | |
1556 | if (host->devtype_data->axi_offset) | |
1557 | host->regs_axi = host->base + host->devtype_data->axi_offset; | |
1558 | ||
1559 | this->ecc.bytes = host->devtype_data->eccbytes; | |
1560 | host->eccsize = host->devtype_data->eccsize; | |
1561 | ||
1562 | this->select_chip = host->devtype_data->select_chip; | |
1563 | this->ecc.size = 512; | |
a894cf6c | 1564 | mtd_set_ooblayout(mtd, host->devtype_data->ooblayout); |
f48d0f9a | 1565 | |
6436356b | 1566 | if (host->pdata.hw_ecc) { |
34f6e157 | 1567 | this->ecc.mode = NAND_ECC_HW; |
34f6e157 | 1568 | } else { |
34f6e157 | 1569 | this->ecc.mode = NAND_ECC_SOFT; |
c1c7040e | 1570 | this->ecc.algo = NAND_ECC_HAMMING; |
34f6e157 SH |
1571 | } |
1572 | ||
6436356b UKK |
1573 | /* NAND bus width determines access functions used by upper layer */ |
1574 | if (host->pdata.width == 2) | |
34f6e157 | 1575 | this->options |= NAND_BUSWIDTH_16; |
34f6e157 | 1576 | |
609468f9 BB |
1577 | /* update flash based bbt */ |
1578 | if (host->pdata.flash_bbt) | |
bb9ebd4e | 1579 | this->bbt_options |= NAND_BBT_USE_FLASH; |
34f6e157 | 1580 | |
63f1474c | 1581 | init_completion(&host->op_completion); |
d4840180 IC |
1582 | |
1583 | host->irq = platform_get_irq(pdev, 0); | |
26fbf48b FE |
1584 | if (host->irq < 0) |
1585 | return host->irq; | |
d4840180 | 1586 | |
63f1474c | 1587 | /* |
e4303b25 UKK |
1588 | * Use host->devtype_data->irq_control() here instead of irq_control() |
1589 | * because we must not disable_irq_nosync without having requested the | |
1590 | * irq. | |
63f1474c | 1591 | */ |
e4303b25 | 1592 | host->devtype_data->irq_control(host, 0); |
63f1474c | 1593 | |
e4a09cbf | 1594 | err = devm_request_irq(&pdev->dev, host->irq, mxc_nfc_irq, |
b1eb234f | 1595 | 0, DRIVER_NAME, host); |
d4840180 | 1596 | if (err) |
e4a09cbf SH |
1597 | return err; |
1598 | ||
dcedf628 FE |
1599 | err = clk_prepare_enable(host->clk); |
1600 | if (err) | |
1601 | return err; | |
e4a09cbf | 1602 | host->clk_act = 1; |
d4840180 | 1603 | |
63f1474c | 1604 | /* |
8556958a UKK |
1605 | * Now that we "own" the interrupt make sure the interrupt mask bit is |
1606 | * cleared on i.MX21. Otherwise we can't read the interrupt status bit | |
1607 | * on this machine. | |
63f1474c | 1608 | */ |
f48d0f9a | 1609 | if (host->devtype_data->irqpending_quirk) { |
8556958a | 1610 | disable_irq_nosync(host->irq); |
e4303b25 | 1611 | host->devtype_data->irq_control(host, 1); |
8556958a | 1612 | } |
63f1474c | 1613 | |
bd3fd62e | 1614 | /* first scan to find the device and get the page size */ |
4d62435f | 1615 | if (nand_scan_ident(mtd, is_imx25_nfc(host) ? 4 : 1, NULL)) { |
bd3fd62e VB |
1616 | err = -ENXIO; |
1617 | goto escan; | |
1618 | } | |
34f6e157 | 1619 | |
609468f9 BB |
1620 | switch (this->ecc.mode) { |
1621 | case NAND_ECC_HW: | |
1622 | this->ecc.calculate = mxc_nand_calculate_ecc; | |
1623 | this->ecc.hwctl = mxc_nand_enable_hwecc; | |
1624 | this->ecc.correct = host->devtype_data->correct_data; | |
1625 | break; | |
1626 | ||
1627 | case NAND_ECC_SOFT: | |
609468f9 BB |
1628 | break; |
1629 | ||
1630 | default: | |
1631 | err = -EINVAL; | |
1632 | goto escan; | |
1633 | } | |
1634 | ||
1635 | if (this->bbt_options & NAND_BBT_USE_FLASH) { | |
1636 | this->bbt_td = &bbt_main_descr; | |
1637 | this->bbt_md = &bbt_mirror_descr; | |
1638 | } | |
1639 | ||
a5900554 HS |
1640 | /* allocate the right size buffer now */ |
1641 | devm_kfree(&pdev->dev, (void *)host->data_buf); | |
1642 | host->data_buf = devm_kzalloc(&pdev->dev, mtd->writesize + mtd->oobsize, | |
1643 | GFP_KERNEL); | |
1644 | if (!host->data_buf) { | |
1645 | err = -ENOMEM; | |
1646 | goto escan; | |
1647 | } | |
1648 | ||
6e85dfdc | 1649 | /* Call preset again, with correct writesize this time */ |
e4303b25 | 1650 | host->devtype_data->preset(mtd); |
6e85dfdc | 1651 | |
a894cf6c BB |
1652 | if (!this->ecc.bytes) { |
1653 | if (host->eccsize == 8) | |
1654 | this->ecc.bytes = 18; | |
1655 | else if (host->eccsize == 4) | |
1656 | this->ecc.bytes = 9; | |
8eeb4c52 | 1657 | } |
34f6e157 | 1658 | |
7e7e4730 BS |
1659 | /* |
1660 | * Experimentation shows that i.MX NFC can only handle up to 218 oob | |
1661 | * bytes. Limit used_oobsize to 218 so as to not confuse copy_spare() | |
1662 | * into copying invalid data to/from the spare IO buffer, as this | |
1663 | * might cause ECC data corruption when doing sub-page write to a | |
1664 | * partially written page. | |
1665 | */ | |
1666 | host->used_oobsize = min(mtd->oobsize, 218U); | |
1667 | ||
6a918bad | 1668 | if (this->ecc.mode == NAND_ECC_HW) { |
4d62435f | 1669 | if (is_imx21_nfc(host) || is_imx27_nfc(host)) |
6a918bad MD |
1670 | this->ecc.strength = 1; |
1671 | else | |
1672 | this->ecc.strength = (host->eccsize == 4) ? 4 : 8; | |
1673 | } | |
1674 | ||
4a43faf5 SH |
1675 | /* second phase scan */ |
1676 | if (nand_scan_tail(mtd)) { | |
1677 | err = -ENXIO; | |
1678 | goto escan; | |
1679 | } | |
1680 | ||
34f6e157 | 1681 | /* Register the partitions */ |
6436356b | 1682 | mtd_device_parse_register(mtd, part_probes, |
a61ae81a | 1683 | NULL, |
6436356b UKK |
1684 | host->pdata.parts, |
1685 | host->pdata.nr_parts); | |
34f6e157 SH |
1686 | |
1687 | platform_set_drvdata(pdev, host); | |
1688 | ||
1689 | return 0; | |
1690 | ||
1691 | escan: | |
c10d8ee3 LW |
1692 | if (host->clk_act) |
1693 | clk_disable_unprepare(host->clk); | |
34f6e157 SH |
1694 | |
1695 | return err; | |
1696 | } | |
1697 | ||
810b7e06 | 1698 | static int mxcnd_remove(struct platform_device *pdev) |
34f6e157 SH |
1699 | { |
1700 | struct mxc_nand_host *host = platform_get_drvdata(pdev); | |
1701 | ||
a008deb1 | 1702 | nand_release(nand_to_mtd(&host->nand)); |
8bfd4f7f WY |
1703 | if (host->clk_act) |
1704 | clk_disable_unprepare(host->clk); | |
34f6e157 SH |
1705 | |
1706 | return 0; | |
1707 | } | |
1708 | ||
34f6e157 SH |
1709 | static struct platform_driver mxcnd_driver = { |
1710 | .driver = { | |
1711 | .name = DRIVER_NAME, | |
6436356b | 1712 | .of_match_table = of_match_ptr(mxcnd_dt_ids), |
04dd0d3a | 1713 | }, |
4d62435f | 1714 | .id_table = mxcnd_devtype, |
ddf16d62 | 1715 | .probe = mxcnd_probe, |
5153b88c | 1716 | .remove = mxcnd_remove, |
34f6e157 | 1717 | }; |
ddf16d62 | 1718 | module_platform_driver(mxcnd_driver); |
34f6e157 SH |
1719 | |
1720 | MODULE_AUTHOR("Freescale Semiconductor, Inc."); | |
1721 | MODULE_DESCRIPTION("MXC NAND MTD driver"); | |
1722 | MODULE_LICENSE("GPL"); |