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Merge branches 'regmap-linus' and 'regmap-interface' into regmap-next
[deliverable/linux.git] / drivers / mtd / nand / mxc_nand.c
CommitLineData
34f6e157
SH		 1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#include <linux/delay.h>
21#include <linux/slab.h>
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/mtd/mtd.h>
25#include <linux/mtd/nand.h>
26#include <linux/mtd/partitions.h>
27#include <linux/interrupt.h>
28#include <linux/device.h>
29#include <linux/platform_device.h>
30#include <linux/clk.h>
31#include <linux/err.h>
32#include <linux/io.h>
63f1474c
SH		 33#include <linux/irq.h>
34#include <linux/completion.h>
34f6e157
SH		 35
36#include <asm/mach/flash.h>
37#include <mach/mxc_nand.h>
9467114e 38#include <mach/hardware.h>
34f6e157
SH		 39
40#define DRIVER_NAME "mxc_nand"
41
9467114e 42#define nfc_is_v21() (cpu_is_mx25() || cpu_is_mx35())
a47bfd2e 43#define nfc_is_v1() (cpu_is_mx31() || cpu_is_mx27() || cpu_is_mx21())
71ec5155
SH		 44#define nfc_is_v3_2() cpu_is_mx51()
45#define nfc_is_v3() nfc_is_v3_2()
9467114e 46
34f6e157 47/* Addresses for NFC registers */
1bc99180
SH		 48#define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
49#define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
50#define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
51#define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
52#define NFC_V1_V2_CONFIG (host->regs + 0x0a)
53#define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
54#define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
55#define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10)
56#define NFC_V1_V2_WRPROT (host->regs + 0x12)
57#define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14)
58#define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16)
d178e3e8
BS		 59#define NFC_V21_UNLOCKSTART_BLKADDR0 (host->regs + 0x20)
60#define NFC_V21_UNLOCKSTART_BLKADDR1 (host->regs + 0x24)
61#define NFC_V21_UNLOCKSTART_BLKADDR2 (host->regs + 0x28)
62#define NFC_V21_UNLOCKSTART_BLKADDR3 (host->regs + 0x2c)
63#define NFC_V21_UNLOCKEND_BLKADDR0 (host->regs + 0x22)
64#define NFC_V21_UNLOCKEND_BLKADDR1 (host->regs + 0x26)
65#define NFC_V21_UNLOCKEND_BLKADDR2 (host->regs + 0x2a)
66#define NFC_V21_UNLOCKEND_BLKADDR3 (host->regs + 0x2e)
1bc99180
SH		 67#define NFC_V1_V2_NF_WRPRST (host->regs + 0x18)
68#define NFC_V1_V2_CONFIG1 (host->regs + 0x1a)
69#define NFC_V1_V2_CONFIG2 (host->regs + 0x1c)
70
6e85dfdc 71#define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
1bc99180
SH		 72#define NFC_V1_V2_CONFIG1_SP_EN (1 << 2)
73#define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
74#define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
75#define NFC_V1_V2_CONFIG1_BIG (1 << 5)
76#define NFC_V1_V2_CONFIG1_RST (1 << 6)
77#define NFC_V1_V2_CONFIG1_CE (1 << 7)
b8db2f51
SH		 78#define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
79#define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9)
80#define NFC_V2_CONFIG1_FP_INT (1 << 11)
1bc99180
SH		 81
82#define NFC_V1_V2_CONFIG2_INT (1 << 15)
83
84/*
85 * Operation modes for the NFC. Valid for v1, v2 and v3
86 * type controllers.
87 */
88#define NFC_CMD (1 << 0)
89#define NFC_ADDR (1 << 1)
90#define NFC_INPUT (1 << 2)
91#define NFC_OUTPUT (1 << 3)
92#define NFC_ID (1 << 4)
93#define NFC_STATUS (1 << 5)
34f6e157 94
71ec5155
SH		 95#define NFC_V3_FLASH_CMD (host->regs_axi + 0x00)
96#define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04)
97
98#define NFC_V3_CONFIG1 (host->regs_axi + 0x34)
99#define NFC_V3_CONFIG1_SP_EN (1 << 0)
100#define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4)
101
102#define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38)
103
104#define NFC_V3_LAUNCH (host->regs_axi + 0x40)
105
106#define NFC_V3_WRPROT (host->regs_ip + 0x0)
107#define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0)
108#define NFC_V3_WRPROT_LOCK (1 << 1)
109#define NFC_V3_WRPROT_UNLOCK (1 << 2)
110#define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
111
112#define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04)
113
114#define NFC_V3_CONFIG2 (host->regs_ip + 0x24)
115#define NFC_V3_CONFIG2_PS_512 (0 << 0)
116#define NFC_V3_CONFIG2_PS_2048 (1 << 0)
117#define NFC_V3_CONFIG2_PS_4096 (2 << 0)
118#define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
119#define NFC_V3_CONFIG2_ECC_EN (1 << 3)
120#define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
121#define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5)
122#define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
123#define NFC_V3_CONFIG2_PPB(x) (((x) & 0x3) << 7)
124#define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12)
125#define NFC_V3_CONFIG2_INT_MSK (1 << 15)
126#define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
127#define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
128
129#define NFC_V3_CONFIG3 (host->regs_ip + 0x28)
130#define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
131#define NFC_V3_CONFIG3_FW8 (1 << 3)
132#define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
133#define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12)
134#define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
135#define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
136
137#define NFC_V3_IPC (host->regs_ip + 0x2C)
138#define NFC_V3_IPC_CREQ (1 << 0)
139#define NFC_V3_IPC_INT (1 << 31)
140
141#define NFC_V3_DELAY_LINE (host->regs_ip + 0x34)
34f6e157
SH		 142
143struct mxc_nand_host {
144 struct mtd_info mtd;
145 struct nand_chip nand;
146 struct mtd_partition *parts;
147 struct device *dev;
148
c6de7e1b
SH		 149 void *spare0;
150 void *main_area0;
c6de7e1b
SH		 151
152 void __iomem *base;
34f6e157 153 void __iomem *regs;
71ec5155
SH		 154 void __iomem *regs_axi;
155 void __iomem *regs_ip;
34f6e157 156 int status_request;
34f6e157
SH		 157 struct clk *clk;
158 int clk_act;
159 int irq;
94f77e50 160 int eccsize;
d178e3e8 161 int active_cs;
34f6e157 162
63f1474c 163 struct completion op_completion;
34f6e157 164
f8f9608d
SH		 165 uint8_t *data_buf;
166 unsigned int buf_start;
167 int spare_len;
5f97304e
SH		 168
169 void (*preset)(struct mtd_info *);
170 void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
171 void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
172 void (*send_page)(struct mtd_info *, unsigned int);
173 void (*send_read_id)(struct mxc_nand_host *);
174 uint16_t (*get_dev_status)(struct mxc_nand_host *);
7aaf28ac 175 int (*check_int)(struct mxc_nand_host *);
63f1474c 176 void (*irq_control)(struct mxc_nand_host *, int);
34f6e157
SH		 177};
178
34f6e157 179/* OOB placement block for use with hardware ecc generation */
9467114e 180static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
34f6e157
SH		 181 .eccbytes = 5,
182 .eccpos = {6, 7, 8, 9, 10},
8c1fd89a 183 .oobfree = {{0, 5}, {12, 4}, }
bd3fd62e
VB		 184};
185
9467114e 186static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
bd3fd62e
VB		 187 .eccbytes = 20,
188 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
189 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
190 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
34f6e157
SH		 191};
192
9467114e
SH		 193/* OOB description for 512 byte pages with 16 byte OOB */
194static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
195 .eccbytes = 1 * 9,
196 .eccpos = {
197 7, 8, 9, 10, 11, 12, 13, 14, 15
198 },
199 .oobfree = {
200 {.offset = 0, .length = 5}
201 }
202};
203
204/* OOB description for 2048 byte pages with 64 byte OOB */
205static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
206 .eccbytes = 4 * 9,
207 .eccpos = {
208 7, 8, 9, 10, 11, 12, 13, 14, 15,
209 23, 24, 25, 26, 27, 28, 29, 30, 31,
210 39, 40, 41, 42, 43, 44, 45, 46, 47,
211 55, 56, 57, 58, 59, 60, 61, 62, 63
212 },
213 .oobfree = {
214 {.offset = 2, .length = 4},
215 {.offset = 16, .length = 7},
216 {.offset = 32, .length = 7},
217 {.offset = 48, .length = 7}
218 }
219};
220
2c1c5f19
BS		 221/* OOB description for 4096 byte pages with 128 byte OOB */
222static struct nand_ecclayout nandv2_hw_eccoob_4k = {
223 .eccbytes = 8 * 9,
224 .eccpos = {
225 7, 8, 9, 10, 11, 12, 13, 14, 15,
226 23, 24, 25, 26, 27, 28, 29, 30, 31,
227 39, 40, 41, 42, 43, 44, 45, 46, 47,
228 55, 56, 57, 58, 59, 60, 61, 62, 63,
229 71, 72, 73, 74, 75, 76, 77, 78, 79,
230 87, 88, 89, 90, 91, 92, 93, 94, 95,
231 103, 104, 105, 106, 107, 108, 109, 110, 111,
232 119, 120, 121, 122, 123, 124, 125, 126, 127,
233 },
234 .oobfree = {
235 {.offset = 2, .length = 4},
236 {.offset = 16, .length = 7},
237 {.offset = 32, .length = 7},
238 {.offset = 48, .length = 7},
239 {.offset = 64, .length = 7},
240 {.offset = 80, .length = 7},
241 {.offset = 96, .length = 7},
242 {.offset = 112, .length = 7},
243 }
244};
245
34f6e157 246static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL };
34f6e157
SH		 247
248static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
249{
250 struct mxc_nand_host *host = dev_id;
251
63f1474c
SH		 252 if (!host->check_int(host))
253 return IRQ_NONE;
34f6e157 254
63f1474c
SH		 255 host->irq_control(host, 0);
256
257 complete(&host->op_completion);
34f6e157
SH		 258
259 return IRQ_HANDLED;
260}
261
71ec5155
SH		 262static int check_int_v3(struct mxc_nand_host *host)
263{
264 uint32_t tmp;
265
266 tmp = readl(NFC_V3_IPC);
267 if (!(tmp & NFC_V3_IPC_INT))
268 return 0;
269
270 tmp &= ~NFC_V3_IPC_INT;
271 writel(tmp, NFC_V3_IPC);
272
273 return 1;
274}
275
7aaf28ac
SH		 276static int check_int_v1_v2(struct mxc_nand_host *host)
277{
278 uint32_t tmp;
279
1bc99180
SH		 280 tmp = readw(NFC_V1_V2_CONFIG2);
281 if (!(tmp & NFC_V1_V2_CONFIG2_INT))
7aaf28ac
SH		 282 return 0;
283
63f1474c
SH		 284 if (!cpu_is_mx21())
285 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
7aaf28ac
SH		 286
287 return 1;
288}
289
63f1474c
SH		 290/*
291 * It has been observed that the i.MX21 cannot read the CONFIG2:INT bit
292 * if interrupts are masked (CONFIG1:INT_MSK is set). To handle this, the
293 * driver can enable/disable the irq line rather than simply masking the
294 * interrupts.
295 */
296static void irq_control_mx21(struct mxc_nand_host *host, int activate)
297{
298 if (activate)
299 enable_irq(host->irq);
300 else
301 disable_irq_nosync(host->irq);
302}
303
304static void irq_control_v1_v2(struct mxc_nand_host *host, int activate)
305{
306 uint16_t tmp;
307
308 tmp = readw(NFC_V1_V2_CONFIG1);
309
310 if (activate)
311 tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK;
312 else
313 tmp |= NFC_V1_V2_CONFIG1_INT_MSK;
314
315 writew(tmp, NFC_V1_V2_CONFIG1);
316}
317
318static void irq_control_v3(struct mxc_nand_host *host, int activate)
319{
320 uint32_t tmp;
321
322 tmp = readl(NFC_V3_CONFIG2);
323
324 if (activate)
325 tmp &= ~NFC_V3_CONFIG2_INT_MSK;
326 else
327 tmp |= NFC_V3_CONFIG2_INT_MSK;
328
329 writel(tmp, NFC_V3_CONFIG2);
330}
331
34f6e157
SH		 332/* This function polls the NANDFC to wait for the basic operation to
333 * complete by checking the INT bit of config2 register.
334 */
c110eaf4 335static void wait_op_done(struct mxc_nand_host *host, int useirq)
34f6e157 336{
a47bfd2e 337 int max_retries = 8000;
34f6e157
SH		 338
339 if (useirq) {
7aaf28ac 340 if (!host->check_int(host)) {
63f1474c
SH		 341 INIT_COMPLETION(host->op_completion);
342 host->irq_control(host, 1);
343 wait_for_completion(&host->op_completion);
34f6e157
SH		 344 }
345 } else {
346 while (max_retries-- > 0) {
7aaf28ac 347 if (host->check_int(host))
34f6e157 348 break;
7aaf28ac 349
34f6e157
SH		 350 udelay(1);
351 }
43950a60 352 if (max_retries < 0)
62465491
SH		 353 DEBUG(MTD_DEBUG_LEVEL0, "%s: INT not set\n",
354 __func__);
34f6e157
SH		 355 }
356}
357
71ec5155
SH		 358static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
359{
360 /* fill command */
361 writel(cmd, NFC_V3_FLASH_CMD);
362
363 /* send out command */
364 writel(NFC_CMD, NFC_V3_LAUNCH);
365
366 /* Wait for operation to complete */
367 wait_op_done(host, useirq);
368}
369
34f6e157
SH		 370/* This function issues the specified command to the NAND device and
371 * waits for completion. */
5f97304e 372static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
34f6e157
SH		 373{
374 DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x, %d)\n", cmd, useirq);
375
1bc99180
SH		 376 writew(cmd, NFC_V1_V2_FLASH_CMD);
377 writew(NFC_CMD, NFC_V1_V2_CONFIG2);
34f6e157 378
a47bfd2e
IC		 379 if (cpu_is_mx21() && (cmd == NAND_CMD_RESET)) {
380 int max_retries = 100;
381 /* Reset completion is indicated by NFC_CONFIG2 */
382 /* being set to 0 */
383 while (max_retries-- > 0) {
1bc99180 384 if (readw(NFC_V1_V2_CONFIG2) == 0) {
a47bfd2e
IC		 385 break;
386 }
387 udelay(1);
388 }
389 if (max_retries < 0)
390 DEBUG(MTD_DEBUG_LEVEL0, "%s: RESET failed\n",
391 __func__);
392 } else {
393 /* Wait for operation to complete */
394 wait_op_done(host, useirq);
395 }
34f6e157
SH		 396}
397
71ec5155
SH		 398static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
399{
400 /* fill address */
401 writel(addr, NFC_V3_FLASH_ADDR0);
402
403 /* send out address */
404 writel(NFC_ADDR, NFC_V3_LAUNCH);
405
406 wait_op_done(host, 0);
407}
408
34f6e157
SH		 409/* This function sends an address (or partial address) to the
410 * NAND device. The address is used to select the source/destination for
411 * a NAND command. */
5f97304e 412static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
34f6e157
SH		 413{
414 DEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x %d)\n", addr, islast);
415
1bc99180
SH		 416 writew(addr, NFC_V1_V2_FLASH_ADDR);
417 writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
34f6e157
SH		 418
419 /* Wait for operation to complete */
c110eaf4 420 wait_op_done(host, islast);
34f6e157
SH		 421}
422
71ec5155
SH		 423static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
424{
425 struct nand_chip *nand_chip = mtd->priv;
426 struct mxc_nand_host *host = nand_chip->priv;
427 uint32_t tmp;
428
429 tmp = readl(NFC_V3_CONFIG1);
430 tmp &= ~(7 << 4);
431 writel(tmp, NFC_V3_CONFIG1);
432
433 /* transfer data from NFC ram to nand */
434 writel(ops, NFC_V3_LAUNCH);
435
436 wait_op_done(host, false);
437}
438
5f97304e 439static void send_page_v1_v2(struct mtd_info *mtd, unsigned int ops)
34f6e157 440{
2d69c7fa
SH		 441 struct nand_chip *nand_chip = mtd->priv;
442 struct mxc_nand_host *host = nand_chip->priv;
c5d23f1b 443 int bufs, i;
34f6e157 444
9467114e 445 if (nfc_is_v1() && mtd->writesize > 512)
c5d23f1b
SH		 446 bufs = 4;
447 else
448 bufs = 1;
34f6e157 449
c5d23f1b 450 for (i = 0; i < bufs; i++) {
34f6e157 451
c5d23f1b 452 /* NANDFC buffer 0 is used for page read/write */
d178e3e8 453 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
34f6e157 454
1bc99180 455 writew(ops, NFC_V1_V2_CONFIG2);
34f6e157 456
c5d23f1b 457 /* Wait for operation to complete */
c110eaf4 458 wait_op_done(host, true);
34f6e157 459 }
34f6e157
SH		 460}
461
71ec5155
SH		 462static void send_read_id_v3(struct mxc_nand_host *host)
463{
464 /* Read ID into main buffer */
465 writel(NFC_ID, NFC_V3_LAUNCH);
466
467 wait_op_done(host, true);
468
469 memcpy(host->data_buf, host->main_area0, 16);
470}
471
34f6e157 472/* Request the NANDFC to perform a read of the NAND device ID. */
5f97304e 473static void send_read_id_v1_v2(struct mxc_nand_host *host)
34f6e157
SH		 474{
475 struct nand_chip *this = &host->nand;
34f6e157
SH		 476
477 /* NANDFC buffer 0 is used for device ID output */
d178e3e8 478 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
34f6e157 479
1bc99180 480 writew(NFC_ID, NFC_V1_V2_CONFIG2);
34f6e157
SH		 481
482 /* Wait for operation to complete */
c110eaf4 483 wait_op_done(host, true);
34f6e157 484
f7b66e5e
JO		 485 memcpy(host->data_buf, host->main_area0, 16);
486
34f6e157 487 if (this->options & NAND_BUSWIDTH_16) {
34f6e157 488 /* compress the ID info */
f7b66e5e
JO		 489 host->data_buf[1] = host->data_buf[2];
490 host->data_buf[2] = host->data_buf[4];
491 host->data_buf[3] = host->data_buf[6];
492 host->data_buf[4] = host->data_buf[8];
493 host->data_buf[5] = host->data_buf[10];
34f6e157
SH		 494 }
495}
496
71ec5155
SH		 497static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
498{
499 writew(NFC_STATUS, NFC_V3_LAUNCH);
500 wait_op_done(host, true);
501
502 return readl(NFC_V3_CONFIG1) >> 16;
503}
504
34f6e157
SH		 505/* This function requests the NANDFC to perform a read of the
506 * NAND device status and returns the current status. */
5f97304e 507static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
34f6e157 508{
c29c607a 509 void __iomem *main_buf = host->main_area0;
34f6e157 510 uint32_t store;
f06368f7 511 uint16_t ret;
34f6e157 512
d178e3e8 513 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
34f6e157 514
c29c607a
SH		 515 /*
516 * The device status is stored in main_area0. To
517 * prevent corruption of the buffer save the value
518 * and restore it afterwards.
519 */
34f6e157 520 store = readl(main_buf);
34f6e157 521
1bc99180 522 writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
c110eaf4 523 wait_op_done(host, true);
34f6e157 524
34f6e157 525 ret = readw(main_buf);
c29c607a 526
34f6e157
SH		 527 writel(store, main_buf);
528
529 return ret;
530}
531
532/* This functions is used by upper layer to checks if device is ready */
533static int mxc_nand_dev_ready(struct mtd_info *mtd)
534{
535 /*
536 * NFC handles R/B internally. Therefore, this function
537 * always returns status as ready.
538 */
539 return 1;
540}
541
542static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
543{
544 /*
545 * If HW ECC is enabled, we turn it on during init. There is
546 * no need to enable again here.
547 */
548}
549
94f77e50 550static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat,
34f6e157
SH		 551 u_char *read_ecc, u_char *calc_ecc)
552{
553 struct nand_chip *nand_chip = mtd->priv;
554 struct mxc_nand_host *host = nand_chip->priv;
555
556 /*
557 * 1-Bit errors are automatically corrected in HW. No need for
558 * additional correction. 2-Bit errors cannot be corrected by
559 * HW ECC, so we need to return failure
560 */
1bc99180 561 uint16_t ecc_status = readw(NFC_V1_V2_ECC_STATUS_RESULT);
34f6e157
SH		 562
563 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
564 DEBUG(MTD_DEBUG_LEVEL0,
565 "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
566 return -1;
567 }
568
569 return 0;
570}
571
94f77e50
SH		 572static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat,
573 u_char *read_ecc, u_char *calc_ecc)
574{
575 struct nand_chip *nand_chip = mtd->priv;
576 struct mxc_nand_host *host = nand_chip->priv;
577 u32 ecc_stat, err;
578 int no_subpages = 1;
579 int ret = 0;
580 u8 ecc_bit_mask, err_limit;
581
582 ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
583 err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
584
585 no_subpages = mtd->writesize >> 9;
586
71ec5155
SH		 587 if (nfc_is_v21())
588 ecc_stat = readl(NFC_V1_V2_ECC_STATUS_RESULT);
589 else
590 ecc_stat = readl(NFC_V3_ECC_STATUS_RESULT);
94f77e50
SH		 591
592 do {
593 err = ecc_stat & ecc_bit_mask;
594 if (err > err_limit) {
595 printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
596 return -1;
597 } else {
598 ret += err;
599 }
600 ecc_stat >>= 4;
601 } while (--no_subpages);
602
603 mtd->ecc_stats.corrected += ret;
604 pr_debug("%d Symbol Correctable RS-ECC Error\n", ret);
605
606 return ret;
607}
608
34f6e157
SH		 609static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
610 u_char *ecc_code)
611{
612 return 0;
613}
614
615static u_char mxc_nand_read_byte(struct mtd_info *mtd)
616{
617 struct nand_chip *nand_chip = mtd->priv;
618 struct mxc_nand_host *host = nand_chip->priv;
f8f9608d 619 uint8_t ret;
34f6e157
SH		 620
621 /* Check for status request */
622 if (host->status_request)
5f97304e 623 return host->get_dev_status(host) & 0xFF;
34f6e157 624
f8f9608d
SH		 625 ret = *(uint8_t *)(host->data_buf + host->buf_start);
626 host->buf_start++;
34f6e157
SH		 627
628 return ret;
629}
630
631static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
632{
633 struct nand_chip *nand_chip = mtd->priv;
634 struct mxc_nand_host *host = nand_chip->priv;
f8f9608d 635 uint16_t ret;
34f6e157 636
f8f9608d
SH		 637 ret = *(uint16_t *)(host->data_buf + host->buf_start);
638 host->buf_start += 2;
34f6e157
SH		 639
640 return ret;
641}
642
643/* Write data of length len to buffer buf. The data to be
644 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
645 * Operation by the NFC, the data is written to NAND Flash */
646static void mxc_nand_write_buf(struct mtd_info *mtd,
647 const u_char *buf, int len)
648{
649 struct nand_chip *nand_chip = mtd->priv;
650 struct mxc_nand_host *host = nand_chip->priv;
f8f9608d
SH		 651 u16 col = host->buf_start;
652 int n = mtd->oobsize + mtd->writesize - col;
34f6e157 653
f8f9608d 654 n = min(n, len);
34f6e157 655
f8f9608d 656 memcpy(host->data_buf + col, buf, n);
34f6e157 657
f8f9608d 658 host->buf_start += n;
34f6e157
SH		 659}
660
661/* Read the data buffer from the NAND Flash. To read the data from NAND
662 * Flash first the data output cycle is initiated by the NFC, which copies
663 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
664 */
665static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
666{
667 struct nand_chip *nand_chip = mtd->priv;
668 struct mxc_nand_host *host = nand_chip->priv;
f8f9608d
SH		 669 u16 col = host->buf_start;
670 int n = mtd->oobsize + mtd->writesize - col;
34f6e157 671
f8f9608d 672 n = min(n, len);
34f6e157 673
5d9d9936 674 memcpy(buf, host->data_buf + col, n);
34f6e157 675
5d9d9936 676 host->buf_start += n;
34f6e157
SH		 677}
678
679/* Used by the upper layer to verify the data in NAND Flash
680 * with the data in the buf. */
681static int mxc_nand_verify_buf(struct mtd_info *mtd,
682 const u_char *buf, int len)
683{
684 return -EFAULT;
685}
686
687/* This function is used by upper layer for select and
688 * deselect of the NAND chip */
689static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
690{
691 struct nand_chip *nand_chip = mtd->priv;
692 struct mxc_nand_host *host = nand_chip->priv;
693
d178e3e8 694 if (chip == -1) {
34f6e157
SH		 695 /* Disable the NFC clock */
696 if (host->clk_act) {
697 clk_disable(host->clk);
698 host->clk_act = 0;
699 }
d178e3e8
BS		 700 return;
701 }
702
703 if (!host->clk_act) {
34f6e157 704 /* Enable the NFC clock */
d178e3e8
BS		 705 clk_enable(host->clk);
706 host->clk_act = 1;
707 }
34f6e157 708
d178e3e8
BS		 709 if (nfc_is_v21()) {
710 host->active_cs = chip;
711 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
34f6e157
SH		 712 }
713}
714
f8f9608d
SH		 715/*
716 * Function to transfer data to/from spare area.
717 */
718static void copy_spare(struct mtd_info *mtd, bool bfrom)
34f6e157 719{
f8f9608d
SH		 720 struct nand_chip *this = mtd->priv;
721 struct mxc_nand_host *host = this->priv;
722 u16 i, j;
723 u16 n = mtd->writesize >> 9;
724 u8 *d = host->data_buf + mtd->writesize;
c6de7e1b 725 u8 *s = host->spare0;
f8f9608d
SH		 726 u16 t = host->spare_len;
727
728 j = (mtd->oobsize / n >> 1) << 1;
729
730 if (bfrom) {
731 for (i = 0; i < n - 1; i++)
732 memcpy(d + i * j, s + i * t, j);
733
734 /* the last section */
735 memcpy(d + i * j, s + i * t, mtd->oobsize - i * j);
736 } else {
737 for (i = 0; i < n - 1; i++)
738 memcpy(&s[i * t], &d[i * j], j);
34f6e157 739
f8f9608d
SH		 740 /* the last section */
741 memcpy(&s[i * t], &d[i * j], mtd->oobsize - i * j);
34f6e157 742 }
f8f9608d 743}
34f6e157 744
a3e65b64
SH		 745static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
746{
747 struct nand_chip *nand_chip = mtd->priv;
748 struct mxc_nand_host *host = nand_chip->priv;
34f6e157
SH		 749
750 /* Write out column address, if necessary */
751 if (column != -1) {
752 /*
753 * MXC NANDFC can only perform full page+spare or
754 * spare-only read/write. When the upper layers
177b241d
GE		 755 * perform a read/write buf operation, the saved column
756 * address is used to index into the full page.
34f6e157 757 */
5f97304e 758 host->send_addr(host, 0, page_addr == -1);
2d69c7fa 759 if (mtd->writesize > 512)
34f6e157 760 /* another col addr cycle for 2k page */
5f97304e 761 host->send_addr(host, 0, false);
34f6e157
SH		 762 }
763
764 /* Write out page address, if necessary */
765 if (page_addr != -1) {
766 /* paddr_0 - p_addr_7 */
5f97304e 767 host->send_addr(host, (page_addr & 0xff), false);
34f6e157 768
2d69c7fa 769 if (mtd->writesize > 512) {
bd3fd62e
VB		 770 if (mtd->size >= 0x10000000) {
771 /* paddr_8 - paddr_15 */
5f97304e
SH		 772 host->send_addr(host, (page_addr >> 8) & 0xff, false);
773 host->send_addr(host, (page_addr >> 16) & 0xff, true);
bd3fd62e
VB		 774 } else
775 /* paddr_8 - paddr_15 */
5f97304e 776 host->send_addr(host, (page_addr >> 8) & 0xff, true);
34f6e157
SH		 777 } else {
778 /* One more address cycle for higher density devices */
779 if (mtd->size >= 0x4000000) {
780 /* paddr_8 - paddr_15 */
5f97304e
SH		 781 host->send_addr(host, (page_addr >> 8) & 0xff, false);
782 host->send_addr(host, (page_addr >> 16) & 0xff, true);
34f6e157
SH		 783 } else
784 /* paddr_8 - paddr_15 */
5f97304e 785 host->send_addr(host, (page_addr >> 8) & 0xff, true);
34f6e157
SH		 786 }
787 }
a3e65b64
SH		 788}
789
6e85dfdc
SH		 790/*
791 * v2 and v3 type controllers can do 4bit or 8bit ecc depending
792 * on how much oob the nand chip has. For 8bit ecc we need at least
793 * 26 bytes of oob data per 512 byte block.
794 */
795static int get_eccsize(struct mtd_info *mtd)
796{
797 int oobbytes_per_512 = 0;
798
799 oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
800
801 if (oobbytes_per_512 < 26)
802 return 4;
803 else
804 return 8;
805}
806
5f97304e 807static void preset_v1_v2(struct mtd_info *mtd)
d4840180
IC		 808{
809 struct nand_chip *nand_chip = mtd->priv;
810 struct mxc_nand_host *host = nand_chip->priv;
b8db2f51
SH		 811 uint16_t config1 = 0;
812
813 if (nand_chip->ecc.mode == NAND_ECC_HW)
814 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
815
816 if (nfc_is_v21())
817 config1 |= NFC_V2_CONFIG1_FP_INT;
818
819 if (!cpu_is_mx21())
820 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
6e85dfdc
SH		 821
822 if (nfc_is_v21() && mtd->writesize) {
b8db2f51
SH		 823 uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
824
6e85dfdc
SH		 825 host->eccsize = get_eccsize(mtd);
826 if (host->eccsize == 4)
b8db2f51
SH		 827 config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
828
829 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
d4840180 830 } else {
6e85dfdc 831 host->eccsize = 1;
d4840180 832 }
6e85dfdc 833
b8db2f51 834 writew(config1, NFC_V1_V2_CONFIG1);
d4840180
IC		 835 /* preset operation */
836
837 /* Unlock the internal RAM Buffer */
1bc99180 838 writew(0x2, NFC_V1_V2_CONFIG);
d4840180
IC		 839
840 /* Blocks to be unlocked */
841 if (nfc_is_v21()) {
d178e3e8
BS		 842 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0);
843 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1);
844 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2);
845 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3);
846 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0);
847 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1);
848 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2);
849 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3);
d4840180 850 } else if (nfc_is_v1()) {
1bc99180
SH		 851 writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
852 writew(0x4000, NFC_V1_UNLOCKEND_BLKADDR);
d4840180
IC		 853 } else
854 BUG();
855
856 /* Unlock Block Command for given address range */
1bc99180 857 writew(0x4, NFC_V1_V2_WRPROT);
d4840180
IC		 858}
859
71ec5155
SH		 860static void preset_v3(struct mtd_info *mtd)
861{
862 struct nand_chip *chip = mtd->priv;
863 struct mxc_nand_host *host = chip->priv;
864 uint32_t config2, config3;
865 int i, addr_phases;
866
867 writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
868 writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
869
870 /* Unlock the internal RAM Buffer */
871 writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
872 NFC_V3_WRPROT);
873
874 /* Blocks to be unlocked */
875 for (i = 0; i < NAND_MAX_CHIPS; i++)
876 writel(0x0 | (0xffff << 16),
877 NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
878
879 writel(0, NFC_V3_IPC);
880
881 config2 = NFC_V3_CONFIG2_ONE_CYCLE |
882 NFC_V3_CONFIG2_2CMD_PHASES |
883 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
884 NFC_V3_CONFIG2_ST_CMD(0x70) |
63f1474c 885 NFC_V3_CONFIG2_INT_MSK |
71ec5155
SH		 886 NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
887
888 if (chip->ecc.mode == NAND_ECC_HW)
889 config2 |= NFC_V3_CONFIG2_ECC_EN;
890
891 addr_phases = fls(chip->pagemask) >> 3;
892
893 if (mtd->writesize == 2048) {
894 config2 |= NFC_V3_CONFIG2_PS_2048;
895 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
896 } else if (mtd->writesize == 4096) {
897 config2 |= NFC_V3_CONFIG2_PS_4096;
898 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
899 } else {
900 config2 |= NFC_V3_CONFIG2_PS_512;
901 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
902 }
903
904 if (mtd->writesize) {
905 config2 |= NFC_V3_CONFIG2_PPB(ffs(mtd->erasesize / mtd->writesize) - 6);
906 host->eccsize = get_eccsize(mtd);
907 if (host->eccsize == 8)
908 config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
909 }
910
911 writel(config2, NFC_V3_CONFIG2);
912
913 config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
914 NFC_V3_CONFIG3_NO_SDMA |
915 NFC_V3_CONFIG3_RBB_MODE |
916 NFC_V3_CONFIG3_SBB(6) | /* Reset default */
917 NFC_V3_CONFIG3_ADD_OP(0);
918
919 if (!(chip->options & NAND_BUSWIDTH_16))
920 config3 |= NFC_V3_CONFIG3_FW8;
921
922 writel(config3, NFC_V3_CONFIG3);
923
924 writel(0, NFC_V3_DELAY_LINE);
d4840180
IC		 925}
926
34f6e157
SH		 927/* Used by the upper layer to write command to NAND Flash for
928 * different operations to be carried out on NAND Flash */
929static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
930 int column, int page_addr)
931{
932 struct nand_chip *nand_chip = mtd->priv;
933 struct mxc_nand_host *host = nand_chip->priv;
34f6e157
SH		 934
935 DEBUG(MTD_DEBUG_LEVEL3,
936 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
937 command, column, page_addr);
938
939 /* Reset command state information */
940 host->status_request = false;
34f6e157 941
34f6e157 942 /* Command pre-processing step */
34f6e157 943 switch (command) {
d4840180 944 case NAND_CMD_RESET:
5f97304e
SH		 945 host->preset(mtd);
946 host->send_cmd(host, command, false);
d4840180 947 break;
34f6e157 948
34f6e157 949 case NAND_CMD_STATUS:
f8f9608d 950 host->buf_start = 0;
34f6e157 951 host->status_request = true;
34f6e157 952
5f97304e 953 host->send_cmd(host, command, true);
89121a6b 954 mxc_do_addr_cycle(mtd, column, page_addr);
34f6e157
SH		 955 break;
956
34f6e157 957 case NAND_CMD_READ0:
34f6e157 958 case NAND_CMD_READOOB:
89121a6b
SH		 959 if (command == NAND_CMD_READ0)
960 host->buf_start = column;
961 else
962 host->buf_start = column + mtd->writesize;
f8f9608d 963
5ea32021 964 command = NAND_CMD_READ0; /* only READ0 is valid */
89121a6b 965
5f97304e 966 host->send_cmd(host, command, false);
89121a6b
SH		 967 mxc_do_addr_cycle(mtd, column, page_addr);
968
2d69c7fa 969 if (mtd->writesize > 512)
5f97304e 970 host->send_cmd(host, NAND_CMD_READSTART, true);
c5d23f1b 971
5f97304e 972 host->send_page(mtd, NFC_OUTPUT);
89121a6b 973
c6de7e1b 974 memcpy(host->data_buf, host->main_area0, mtd->writesize);
89121a6b 975 copy_spare(mtd, true);
34f6e157
SH		 976 break;
977
34f6e157 978 case NAND_CMD_SEQIN:
5ea32021
SH		 979 if (column >= mtd->writesize)
980 /* call ourself to read a page */
981 mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
34f6e157 982
5ea32021 983 host->buf_start = column;
89121a6b 984
5f97304e 985 host->send_cmd(host, command, false);
89121a6b 986 mxc_do_addr_cycle(mtd, column, page_addr);
34f6e157
SH		 987 break;
988
989 case NAND_CMD_PAGEPROG:
c6de7e1b 990 memcpy(host->main_area0, host->data_buf, mtd->writesize);
f8f9608d 991 copy_spare(mtd, false);
5f97304e
SH		 992 host->send_page(mtd, NFC_INPUT);
993 host->send_cmd(host, command, true);
89121a6b 994 mxc_do_addr_cycle(mtd, column, page_addr);
34f6e157
SH		 995 break;
996
34f6e157 997 case NAND_CMD_READID:
5f97304e 998 host->send_cmd(host, command, true);
89121a6b 999 mxc_do_addr_cycle(mtd, column, page_addr);
5f97304e 1000 host->send_read_id(host);
9467114e 1001 host->buf_start = column;
34f6e157
SH		 1002 break;
1003
89121a6b 1004 case NAND_CMD_ERASE1:
34f6e157 1005 case NAND_CMD_ERASE2:
5f97304e 1006 host->send_cmd(host, command, false);
89121a6b
SH		 1007 mxc_do_addr_cycle(mtd, column, page_addr);
1008
34f6e157
SH		 1009 break;
1010 }
1011}
1012
f1372055
SH		 1013/*
1014 * The generic flash bbt decriptors overlap with our ecc
1015 * hardware, so define some i.MX specific ones.
1016 */
1017static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
1018static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
1019
1020static struct nand_bbt_descr bbt_main_descr = {
1021 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1022 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1023 .offs = 0,
1024 .len = 4,
1025 .veroffs = 4,
1026 .maxblocks = 4,
1027 .pattern = bbt_pattern,
1028};
1029
1030static struct nand_bbt_descr bbt_mirror_descr = {
1031 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1032 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1033 .offs = 0,
1034 .len = 4,
1035 .veroffs = 4,
1036 .maxblocks = 4,
1037 .pattern = mirror_pattern,
1038};
1039
34f6e157
SH		 1040static int __init mxcnd_probe(struct platform_device *pdev)
1041{
1042 struct nand_chip *this;
1043 struct mtd_info *mtd;
1044 struct mxc_nand_platform_data *pdata = pdev->dev.platform_data;
1045 struct mxc_nand_host *host;
1046 struct resource *res;
2ebf0622 1047 int err = 0, __maybe_unused nr_parts = 0;
9467114e 1048 struct nand_ecclayout *oob_smallpage, *oob_largepage;
34f6e157
SH		 1049
1050 /* Allocate memory for MTD device structure and private data */
f8f9608d
SH		 1051 host = kzalloc(sizeof(struct mxc_nand_host) + NAND_MAX_PAGESIZE +
1052 NAND_MAX_OOBSIZE, GFP_KERNEL);
34f6e157
SH		 1053 if (!host)
1054 return -ENOMEM;
1055
f8f9608d 1056 host->data_buf = (uint8_t *)(host + 1);
f8f9608d 1057
34f6e157
SH		 1058 host->dev = &pdev->dev;
1059 /* structures must be linked */
1060 this = &host->nand;
1061 mtd = &host->mtd;
1062 mtd->priv = this;
1063 mtd->owner = THIS_MODULE;
87f39f04 1064 mtd->dev.parent = &pdev->dev;
1fbff0a6 1065 mtd->name = DRIVER_NAME;
34f6e157
SH		 1066
1067 /* 50 us command delay time */
1068 this->chip_delay = 5;
1069
1070 this->priv = host;
1071 this->dev_ready = mxc_nand_dev_ready;
1072 this->cmdfunc = mxc_nand_command;
1073 this->select_chip = mxc_nand_select_chip;
1074 this->read_byte = mxc_nand_read_byte;
1075 this->read_word = mxc_nand_read_word;
1076 this->write_buf = mxc_nand_write_buf;
1077 this->read_buf = mxc_nand_read_buf;
1078 this->verify_buf = mxc_nand_verify_buf;
1079
e65fb009 1080 host->clk = clk_get(&pdev->dev, "nfc");
8541c118
VB		 1081 if (IS_ERR(host->clk)) {
1082 err = PTR_ERR(host->clk);
34f6e157 1083 goto eclk;
8541c118 1084 }
34f6e157
SH		 1085
1086 clk_enable(host->clk);
1087 host->clk_act = 1;
1088
1089 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1090 if (!res) {
1091 err = -ENODEV;
1092 goto eres;
1093 }
1094
c6de7e1b
SH		 1095 host->base = ioremap(res->start, resource_size(res));
1096 if (!host->base) {
8541c118 1097 err = -ENOMEM;
34f6e157
SH		 1098 goto eres;
1099 }
1100
c6de7e1b 1101 host->main_area0 = host->base;
9467114e 1102
5f97304e
SH		 1103 if (nfc_is_v1() || nfc_is_v21()) {
1104 host->preset = preset_v1_v2;
1105 host->send_cmd = send_cmd_v1_v2;
1106 host->send_addr = send_addr_v1_v2;
1107 host->send_page = send_page_v1_v2;
1108 host->send_read_id = send_read_id_v1_v2;
1109 host->get_dev_status = get_dev_status_v1_v2;
7aaf28ac 1110 host->check_int = check_int_v1_v2;
63f1474c
SH		 1111 if (cpu_is_mx21())
1112 host->irq_control = irq_control_mx21;
1113 else
1114 host->irq_control = irq_control_v1_v2;
5f97304e 1115 }
9467114e
SH		 1116
1117 if (nfc_is_v21()) {
938cf997 1118 host->regs = host->base + 0x1e00;
9467114e
SH		 1119 host->spare0 = host->base + 0x1000;
1120 host->spare_len = 64;
1121 oob_smallpage = &nandv2_hw_eccoob_smallpage;
1122 oob_largepage = &nandv2_hw_eccoob_largepage;
d4840180 1123 this->ecc.bytes = 9;
9467114e 1124 } else if (nfc_is_v1()) {
938cf997 1125 host->regs = host->base + 0xe00;
9467114e
SH		 1126 host->spare0 = host->base + 0x800;
1127 host->spare_len = 16;
1128 oob_smallpage = &nandv1_hw_eccoob_smallpage;
1129 oob_largepage = &nandv1_hw_eccoob_largepage;
9467114e 1130 this->ecc.bytes = 3;
71ec5155
SH		 1131 host->eccsize = 1;
1132 } else if (nfc_is_v3_2()) {
1133 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1134 if (!res) {
1135 err = -ENODEV;
1136 goto eirq;
1137 }
1138 host->regs_ip = ioremap(res->start, resource_size(res));
1139 if (!host->regs_ip) {
1140 err = -ENOMEM;
1141 goto eirq;
1142 }
1143 host->regs_axi = host->base + 0x1e00;
1144 host->spare0 = host->base + 0x1000;
1145 host->spare_len = 64;
1146 host->preset = preset_v3;
1147 host->send_cmd = send_cmd_v3;
1148 host->send_addr = send_addr_v3;
1149 host->send_page = send_page_v3;
1150 host->send_read_id = send_read_id_v3;
1151 host->check_int = check_int_v3;
1152 host->get_dev_status = get_dev_status_v3;
63f1474c 1153 host->irq_control = irq_control_v3;
71ec5155
SH		 1154 oob_smallpage = &nandv2_hw_eccoob_smallpage;
1155 oob_largepage = &nandv2_hw_eccoob_largepage;
9467114e
SH		 1156 } else
1157 BUG();
13e1add1 1158
13e1add1 1159 this->ecc.size = 512;
9467114e 1160 this->ecc.layout = oob_smallpage;
13e1add1 1161
34f6e157
SH		 1162 if (pdata->hw_ecc) {
1163 this->ecc.calculate = mxc_nand_calculate_ecc;
1164 this->ecc.hwctl = mxc_nand_enable_hwecc;
94f77e50
SH		 1165 if (nfc_is_v1())
1166 this->ecc.correct = mxc_nand_correct_data_v1;
1167 else
1168 this->ecc.correct = mxc_nand_correct_data_v2_v3;
34f6e157 1169 this->ecc.mode = NAND_ECC_HW;
34f6e157 1170 } else {
34f6e157 1171 this->ecc.mode = NAND_ECC_SOFT;
34f6e157
SH		 1172 }
1173
34f6e157 1174 /* NAND bus width determines access funtions used by upper layer */
13e1add1 1175 if (pdata->width == 2)
34f6e157 1176 this->options |= NAND_BUSWIDTH_16;
34f6e157 1177
f1372055
SH		 1178 if (pdata->flash_bbt) {
1179 this->bbt_td = &bbt_main_descr;
1180 this->bbt_md = &bbt_mirror_descr;
1181 /* update flash based bbt */
1182 this->options |= NAND_USE_FLASH_BBT;
34f6e157
SH		 1183 }
1184
63f1474c 1185 init_completion(&host->op_completion);
d4840180
IC		 1186
1187 host->irq = platform_get_irq(pdev, 0);
1188
63f1474c
SH		 1189 /*
1190 * mask the interrupt. For i.MX21 explicitely call
1191 * irq_control_v1_v2 to use the mask bit. We can't call
1192 * disable_irq_nosync() for an interrupt we do not own yet.
1193 */
1194 if (cpu_is_mx21())
1195 irq_control_v1_v2(host, 0);
1196 else
1197 host->irq_control(host, 0);
1198
a47bfd2e 1199 err = request_irq(host->irq, mxc_nfc_irq, IRQF_DISABLED, DRIVER_NAME, host);
d4840180
IC		 1200 if (err)
1201 goto eirq;
1202
63f1474c
SH		 1203 host->irq_control(host, 0);
1204
1205 /*
1206 * Now that the interrupt is disabled make sure the interrupt
1207 * mask bit is cleared on i.MX21. Otherwise we can't read
1208 * the interrupt status bit on this machine.
1209 */
1210 if (cpu_is_mx21())
1211 irq_control_v1_v2(host, 1);
1212
bd3fd62e 1213 /* first scan to find the device and get the page size */
d178e3e8 1214 if (nand_scan_ident(mtd, nfc_is_v21() ? 4 : 1, NULL)) {
bd3fd62e
VB		 1215 err = -ENXIO;
1216 goto escan;
1217 }
34f6e157 1218
6e85dfdc
SH		 1219 /* Call preset again, with correct writesize this time */
1220 host->preset(mtd);
1221
2d69c7fa 1222 if (mtd->writesize == 2048)
9467114e 1223 this->ecc.layout = oob_largepage;
2c1c5f19
BS		 1224 if (nfc_is_v21() && mtd->writesize == 4096)
1225 this->ecc.layout = &nandv2_hw_eccoob_4k;
bd3fd62e
VB		 1226
1227 /* second phase scan */
1228 if (nand_scan_tail(mtd)) {
34f6e157
SH		 1229 err = -ENXIO;
1230 goto escan;
1231 }
1232
1233 /* Register the partitions */
34f6e157
SH		 1234 nr_parts =
1235 parse_mtd_partitions(mtd, part_probes, &host->parts, 0);
1236 if (nr_parts > 0)
759f1d32 1237 mtd_device_register(mtd, host->parts, nr_parts);
cce02464 1238 else if (pdata->parts)
759f1d32
JI		 1239 mtd_device_register(mtd, pdata->parts, pdata->nr_parts);
1240 else {
34f6e157 1241 pr_info("Registering %s as whole device\n", mtd->name);
759f1d32 1242 mtd_device_register(mtd, NULL, 0);
34f6e157
SH		 1243 }
1244
1245 platform_set_drvdata(pdev, host);
1246
1247 return 0;
1248
1249escan:
b258fd8d 1250 free_irq(host->irq, host);
34f6e157 1251eirq:
71ec5155
SH		 1252 if (host->regs_ip)
1253 iounmap(host->regs_ip);
c6de7e1b 1254 iounmap(host->base);
34f6e157
SH		 1255eres:
1256 clk_put(host->clk);
1257eclk:
1258 kfree(host);
1259
1260 return err;
1261}
1262
51eeb878 1263static int __devexit mxcnd_remove(struct platform_device *pdev)
34f6e157
SH		 1264{
1265 struct mxc_nand_host *host = platform_get_drvdata(pdev);
1266
1267 clk_put(host->clk);
1268
1269 platform_set_drvdata(pdev, NULL);
1270
1271 nand_release(&host->mtd);
b258fd8d 1272 free_irq(host->irq, host);
71ec5155
SH		 1273 if (host->regs_ip)
1274 iounmap(host->regs_ip);
c6de7e1b 1275 iounmap(host->base);
34f6e157
SH		 1276 kfree(host);
1277
1278 return 0;
1279}
1280
34f6e157
SH		 1281static struct platform_driver mxcnd_driver = {
1282 .driver = {
1283 .name = DRIVER_NAME,
04dd0d3a 1284 },
daa0f15a 1285 .remove = __devexit_p(mxcnd_remove),
34f6e157
SH		 1286};
1287
1288static int __init mxc_nd_init(void)
1289{
8541c118 1290 return platform_driver_probe(&mxcnd_driver, mxcnd_probe);
34f6e157
SH		 1291}
1292
1293static void __exit mxc_nd_cleanup(void)
1294{
1295 /* Unregister the device structure */
1296 platform_driver_unregister(&mxcnd_driver);
1297}
1298
1299module_init(mxc_nd_init);
1300module_exit(mxc_nd_cleanup);
1301
1302MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1303MODULE_DESCRIPTION("MXC NAND MTD driver");
1304MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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