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34f6e157 SH |
1 | /* |
2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * Copyright 2008 Sascha Hauer, kernel@pengutronix.de | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
17 | * MA 02110-1301, USA. | |
18 | */ | |
19 | ||
20 | #include <linux/delay.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/mtd/mtd.h> | |
25 | #include <linux/mtd/nand.h> | |
26 | #include <linux/mtd/partitions.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/device.h> | |
29 | #include <linux/platform_device.h> | |
30 | #include <linux/clk.h> | |
31 | #include <linux/err.h> | |
32 | #include <linux/io.h> | |
63f1474c SH |
33 | #include <linux/irq.h> |
34 | #include <linux/completion.h> | |
6436356b UKK |
35 | #include <linux/of_device.h> |
36 | #include <linux/of_mtd.h> | |
34f6e157 SH |
37 | |
38 | #include <asm/mach/flash.h> | |
82906b13 | 39 | #include <linux/platform_data/mtd-mxc_nand.h> |
34f6e157 SH |
40 | |
41 | #define DRIVER_NAME "mxc_nand" | |
42 | ||
43 | /* Addresses for NFC registers */ | |
1bc99180 SH |
44 | #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00) |
45 | #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04) | |
46 | #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06) | |
47 | #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08) | |
48 | #define NFC_V1_V2_CONFIG (host->regs + 0x0a) | |
49 | #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c) | |
50 | #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e) | |
51 | #define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10) | |
52 | #define NFC_V1_V2_WRPROT (host->regs + 0x12) | |
53 | #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14) | |
54 | #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16) | |
d178e3e8 BS |
55 | #define NFC_V21_UNLOCKSTART_BLKADDR0 (host->regs + 0x20) |
56 | #define NFC_V21_UNLOCKSTART_BLKADDR1 (host->regs + 0x24) | |
57 | #define NFC_V21_UNLOCKSTART_BLKADDR2 (host->regs + 0x28) | |
58 | #define NFC_V21_UNLOCKSTART_BLKADDR3 (host->regs + 0x2c) | |
59 | #define NFC_V21_UNLOCKEND_BLKADDR0 (host->regs + 0x22) | |
60 | #define NFC_V21_UNLOCKEND_BLKADDR1 (host->regs + 0x26) | |
61 | #define NFC_V21_UNLOCKEND_BLKADDR2 (host->regs + 0x2a) | |
62 | #define NFC_V21_UNLOCKEND_BLKADDR3 (host->regs + 0x2e) | |
1bc99180 SH |
63 | #define NFC_V1_V2_NF_WRPRST (host->regs + 0x18) |
64 | #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a) | |
65 | #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c) | |
66 | ||
6e85dfdc | 67 | #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0) |
1bc99180 SH |
68 | #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2) |
69 | #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3) | |
70 | #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4) | |
71 | #define NFC_V1_V2_CONFIG1_BIG (1 << 5) | |
72 | #define NFC_V1_V2_CONFIG1_RST (1 << 6) | |
73 | #define NFC_V1_V2_CONFIG1_CE (1 << 7) | |
b8db2f51 SH |
74 | #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8) |
75 | #define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9) | |
76 | #define NFC_V2_CONFIG1_FP_INT (1 << 11) | |
1bc99180 SH |
77 | |
78 | #define NFC_V1_V2_CONFIG2_INT (1 << 15) | |
79 | ||
80 | /* | |
81 | * Operation modes for the NFC. Valid for v1, v2 and v3 | |
82 | * type controllers. | |
83 | */ | |
84 | #define NFC_CMD (1 << 0) | |
85 | #define NFC_ADDR (1 << 1) | |
86 | #define NFC_INPUT (1 << 2) | |
87 | #define NFC_OUTPUT (1 << 3) | |
88 | #define NFC_ID (1 << 4) | |
89 | #define NFC_STATUS (1 << 5) | |
34f6e157 | 90 | |
71ec5155 SH |
91 | #define NFC_V3_FLASH_CMD (host->regs_axi + 0x00) |
92 | #define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04) | |
93 | ||
94 | #define NFC_V3_CONFIG1 (host->regs_axi + 0x34) | |
95 | #define NFC_V3_CONFIG1_SP_EN (1 << 0) | |
96 | #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4) | |
97 | ||
98 | #define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38) | |
99 | ||
100 | #define NFC_V3_LAUNCH (host->regs_axi + 0x40) | |
101 | ||
102 | #define NFC_V3_WRPROT (host->regs_ip + 0x0) | |
103 | #define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0) | |
104 | #define NFC_V3_WRPROT_LOCK (1 << 1) | |
105 | #define NFC_V3_WRPROT_UNLOCK (1 << 2) | |
106 | #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6) | |
107 | ||
108 | #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04) | |
109 | ||
110 | #define NFC_V3_CONFIG2 (host->regs_ip + 0x24) | |
111 | #define NFC_V3_CONFIG2_PS_512 (0 << 0) | |
112 | #define NFC_V3_CONFIG2_PS_2048 (1 << 0) | |
113 | #define NFC_V3_CONFIG2_PS_4096 (2 << 0) | |
114 | #define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2) | |
115 | #define NFC_V3_CONFIG2_ECC_EN (1 << 3) | |
116 | #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4) | |
117 | #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5) | |
118 | #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6) | |
71718a8e | 119 | #define NFC_V3_CONFIG2_PPB(x, shift) (((x) & 0x3) << shift) |
71ec5155 SH |
120 | #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12) |
121 | #define NFC_V3_CONFIG2_INT_MSK (1 << 15) | |
122 | #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24) | |
123 | #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16) | |
124 | ||
125 | #define NFC_V3_CONFIG3 (host->regs_ip + 0x28) | |
126 | #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0) | |
127 | #define NFC_V3_CONFIG3_FW8 (1 << 3) | |
128 | #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8) | |
129 | #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12) | |
130 | #define NFC_V3_CONFIG3_RBB_MODE (1 << 15) | |
131 | #define NFC_V3_CONFIG3_NO_SDMA (1 << 20) | |
132 | ||
133 | #define NFC_V3_IPC (host->regs_ip + 0x2C) | |
134 | #define NFC_V3_IPC_CREQ (1 << 0) | |
135 | #define NFC_V3_IPC_INT (1 << 31) | |
136 | ||
137 | #define NFC_V3_DELAY_LINE (host->regs_ip + 0x34) | |
34f6e157 | 138 | |
e4303b25 UKK |
139 | struct mxc_nand_host; |
140 | ||
141 | struct mxc_nand_devtype_data { | |
142 | void (*preset)(struct mtd_info *); | |
143 | void (*send_cmd)(struct mxc_nand_host *, uint16_t, int); | |
144 | void (*send_addr)(struct mxc_nand_host *, uint16_t, int); | |
145 | void (*send_page)(struct mtd_info *, unsigned int); | |
146 | void (*send_read_id)(struct mxc_nand_host *); | |
147 | uint16_t (*get_dev_status)(struct mxc_nand_host *); | |
148 | int (*check_int)(struct mxc_nand_host *); | |
149 | void (*irq_control)(struct mxc_nand_host *, int); | |
6d38af25 | 150 | u32 (*get_ecc_status)(struct mxc_nand_host *); |
6dcdf99d | 151 | struct nand_ecclayout *ecclayout_512, *ecclayout_2k, *ecclayout_4k; |
5e05a2d6 | 152 | void (*select_chip)(struct mtd_info *mtd, int chip); |
69d023be UKK |
153 | int (*correct_data)(struct mtd_info *mtd, u_char *dat, |
154 | u_char *read_ecc, u_char *calc_ecc); | |
f48d0f9a UKK |
155 | |
156 | /* | |
157 | * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked | |
158 | * (CONFIG1:INT_MSK is set). To handle this the driver uses | |
159 | * enable_irq/disable_irq_nosync instead of CONFIG1:INT_MSK | |
160 | */ | |
161 | int irqpending_quirk; | |
162 | int needs_ip; | |
163 | ||
164 | size_t regs_offset; | |
165 | size_t spare0_offset; | |
166 | size_t axi_offset; | |
167 | ||
168 | int spare_len; | |
169 | int eccbytes; | |
170 | int eccsize; | |
71718a8e | 171 | int ppb_shift; |
e4303b25 UKK |
172 | }; |
173 | ||
34f6e157 SH |
174 | struct mxc_nand_host { |
175 | struct mtd_info mtd; | |
176 | struct nand_chip nand; | |
34f6e157 SH |
177 | struct device *dev; |
178 | ||
4b6f05e1 UKK |
179 | void __iomem *spare0; |
180 | void __iomem *main_area0; | |
c6de7e1b SH |
181 | |
182 | void __iomem *base; | |
34f6e157 | 183 | void __iomem *regs; |
71ec5155 SH |
184 | void __iomem *regs_axi; |
185 | void __iomem *regs_ip; | |
34f6e157 | 186 | int status_request; |
34f6e157 SH |
187 | struct clk *clk; |
188 | int clk_act; | |
189 | int irq; | |
94f77e50 | 190 | int eccsize; |
d178e3e8 | 191 | int active_cs; |
34f6e157 | 192 | |
63f1474c | 193 | struct completion op_completion; |
34f6e157 | 194 | |
f8f9608d SH |
195 | uint8_t *data_buf; |
196 | unsigned int buf_start; | |
5f97304e | 197 | |
e4303b25 | 198 | const struct mxc_nand_devtype_data *devtype_data; |
6436356b | 199 | struct mxc_nand_platform_data pdata; |
34f6e157 SH |
200 | }; |
201 | ||
34f6e157 | 202 | /* OOB placement block for use with hardware ecc generation */ |
9467114e | 203 | static struct nand_ecclayout nandv1_hw_eccoob_smallpage = { |
34f6e157 SH |
204 | .eccbytes = 5, |
205 | .eccpos = {6, 7, 8, 9, 10}, | |
8c1fd89a | 206 | .oobfree = {{0, 5}, {12, 4}, } |
bd3fd62e VB |
207 | }; |
208 | ||
9467114e | 209 | static struct nand_ecclayout nandv1_hw_eccoob_largepage = { |
bd3fd62e VB |
210 | .eccbytes = 20, |
211 | .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26, | |
212 | 38, 39, 40, 41, 42, 54, 55, 56, 57, 58}, | |
213 | .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, } | |
34f6e157 SH |
214 | }; |
215 | ||
9467114e SH |
216 | /* OOB description for 512 byte pages with 16 byte OOB */ |
217 | static struct nand_ecclayout nandv2_hw_eccoob_smallpage = { | |
218 | .eccbytes = 1 * 9, | |
219 | .eccpos = { | |
220 | 7, 8, 9, 10, 11, 12, 13, 14, 15 | |
221 | }, | |
222 | .oobfree = { | |
223 | {.offset = 0, .length = 5} | |
224 | } | |
225 | }; | |
226 | ||
227 | /* OOB description for 2048 byte pages with 64 byte OOB */ | |
228 | static struct nand_ecclayout nandv2_hw_eccoob_largepage = { | |
229 | .eccbytes = 4 * 9, | |
230 | .eccpos = { | |
231 | 7, 8, 9, 10, 11, 12, 13, 14, 15, | |
232 | 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
233 | 39, 40, 41, 42, 43, 44, 45, 46, 47, | |
234 | 55, 56, 57, 58, 59, 60, 61, 62, 63 | |
235 | }, | |
236 | .oobfree = { | |
237 | {.offset = 2, .length = 4}, | |
238 | {.offset = 16, .length = 7}, | |
239 | {.offset = 32, .length = 7}, | |
240 | {.offset = 48, .length = 7} | |
241 | } | |
242 | }; | |
243 | ||
2c1c5f19 BS |
244 | /* OOB description for 4096 byte pages with 128 byte OOB */ |
245 | static struct nand_ecclayout nandv2_hw_eccoob_4k = { | |
246 | .eccbytes = 8 * 9, | |
247 | .eccpos = { | |
248 | 7, 8, 9, 10, 11, 12, 13, 14, 15, | |
249 | 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
250 | 39, 40, 41, 42, 43, 44, 45, 46, 47, | |
251 | 55, 56, 57, 58, 59, 60, 61, 62, 63, | |
252 | 71, 72, 73, 74, 75, 76, 77, 78, 79, | |
253 | 87, 88, 89, 90, 91, 92, 93, 94, 95, | |
254 | 103, 104, 105, 106, 107, 108, 109, 110, 111, | |
255 | 119, 120, 121, 122, 123, 124, 125, 126, 127, | |
256 | }, | |
257 | .oobfree = { | |
258 | {.offset = 2, .length = 4}, | |
259 | {.offset = 16, .length = 7}, | |
260 | {.offset = 32, .length = 7}, | |
261 | {.offset = 48, .length = 7}, | |
262 | {.offset = 64, .length = 7}, | |
263 | {.offset = 80, .length = 7}, | |
264 | {.offset = 96, .length = 7}, | |
265 | {.offset = 112, .length = 7}, | |
266 | } | |
267 | }; | |
268 | ||
b2ac0376 | 269 | static const char * const part_probes[] = { |
740bb0c4 | 270 | "cmdlinepart", "RedBoot", "ofpart", NULL }; |
34f6e157 | 271 | |
096bcc23 SH |
272 | static void memcpy32_fromio(void *trg, const void __iomem *src, size_t size) |
273 | { | |
274 | int i; | |
275 | u32 *t = trg; | |
276 | const __iomem u32 *s = src; | |
277 | ||
278 | for (i = 0; i < (size >> 2); i++) | |
279 | *t++ = __raw_readl(s++); | |
280 | } | |
281 | ||
282 | static void memcpy32_toio(void __iomem *trg, const void *src, int size) | |
283 | { | |
284 | int i; | |
285 | u32 __iomem *t = trg; | |
286 | const u32 *s = src; | |
287 | ||
288 | for (i = 0; i < (size >> 2); i++) | |
289 | __raw_writel(*s++, t++); | |
290 | } | |
291 | ||
71ec5155 SH |
292 | static int check_int_v3(struct mxc_nand_host *host) |
293 | { | |
294 | uint32_t tmp; | |
295 | ||
296 | tmp = readl(NFC_V3_IPC); | |
297 | if (!(tmp & NFC_V3_IPC_INT)) | |
298 | return 0; | |
299 | ||
300 | tmp &= ~NFC_V3_IPC_INT; | |
301 | writel(tmp, NFC_V3_IPC); | |
302 | ||
303 | return 1; | |
304 | } | |
305 | ||
7aaf28ac SH |
306 | static int check_int_v1_v2(struct mxc_nand_host *host) |
307 | { | |
308 | uint32_t tmp; | |
309 | ||
1bc99180 SH |
310 | tmp = readw(NFC_V1_V2_CONFIG2); |
311 | if (!(tmp & NFC_V1_V2_CONFIG2_INT)) | |
7aaf28ac SH |
312 | return 0; |
313 | ||
f48d0f9a | 314 | if (!host->devtype_data->irqpending_quirk) |
63f1474c | 315 | writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2); |
7aaf28ac SH |
316 | |
317 | return 1; | |
318 | } | |
319 | ||
63f1474c SH |
320 | static void irq_control_v1_v2(struct mxc_nand_host *host, int activate) |
321 | { | |
322 | uint16_t tmp; | |
323 | ||
324 | tmp = readw(NFC_V1_V2_CONFIG1); | |
325 | ||
326 | if (activate) | |
327 | tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK; | |
328 | else | |
329 | tmp |= NFC_V1_V2_CONFIG1_INT_MSK; | |
330 | ||
331 | writew(tmp, NFC_V1_V2_CONFIG1); | |
332 | } | |
333 | ||
334 | static void irq_control_v3(struct mxc_nand_host *host, int activate) | |
335 | { | |
336 | uint32_t tmp; | |
337 | ||
338 | tmp = readl(NFC_V3_CONFIG2); | |
339 | ||
340 | if (activate) | |
341 | tmp &= ~NFC_V3_CONFIG2_INT_MSK; | |
342 | else | |
343 | tmp |= NFC_V3_CONFIG2_INT_MSK; | |
344 | ||
345 | writel(tmp, NFC_V3_CONFIG2); | |
346 | } | |
347 | ||
8556958a UKK |
348 | static void irq_control(struct mxc_nand_host *host, int activate) |
349 | { | |
f48d0f9a | 350 | if (host->devtype_data->irqpending_quirk) { |
8556958a UKK |
351 | if (activate) |
352 | enable_irq(host->irq); | |
353 | else | |
354 | disable_irq_nosync(host->irq); | |
355 | } else { | |
e4303b25 | 356 | host->devtype_data->irq_control(host, activate); |
8556958a UKK |
357 | } |
358 | } | |
359 | ||
6d38af25 UKK |
360 | static u32 get_ecc_status_v1(struct mxc_nand_host *host) |
361 | { | |
362 | return readw(NFC_V1_V2_ECC_STATUS_RESULT); | |
363 | } | |
364 | ||
365 | static u32 get_ecc_status_v2(struct mxc_nand_host *host) | |
366 | { | |
367 | return readl(NFC_V1_V2_ECC_STATUS_RESULT); | |
368 | } | |
369 | ||
370 | static u32 get_ecc_status_v3(struct mxc_nand_host *host) | |
371 | { | |
372 | return readl(NFC_V3_ECC_STATUS_RESULT); | |
373 | } | |
374 | ||
8556958a UKK |
375 | static irqreturn_t mxc_nfc_irq(int irq, void *dev_id) |
376 | { | |
377 | struct mxc_nand_host *host = dev_id; | |
378 | ||
e4303b25 | 379 | if (!host->devtype_data->check_int(host)) |
8556958a UKK |
380 | return IRQ_NONE; |
381 | ||
382 | irq_control(host, 0); | |
383 | ||
384 | complete(&host->op_completion); | |
385 | ||
386 | return IRQ_HANDLED; | |
387 | } | |
388 | ||
34f6e157 SH |
389 | /* This function polls the NANDFC to wait for the basic operation to |
390 | * complete by checking the INT bit of config2 register. | |
391 | */ | |
c110eaf4 | 392 | static void wait_op_done(struct mxc_nand_host *host, int useirq) |
34f6e157 | 393 | { |
a47bfd2e | 394 | int max_retries = 8000; |
34f6e157 SH |
395 | |
396 | if (useirq) { | |
e4303b25 | 397 | if (!host->devtype_data->check_int(host)) { |
63f1474c | 398 | INIT_COMPLETION(host->op_completion); |
8556958a | 399 | irq_control(host, 1); |
63f1474c | 400 | wait_for_completion(&host->op_completion); |
34f6e157 SH |
401 | } |
402 | } else { | |
403 | while (max_retries-- > 0) { | |
e4303b25 | 404 | if (host->devtype_data->check_int(host)) |
34f6e157 | 405 | break; |
7aaf28ac | 406 | |
34f6e157 SH |
407 | udelay(1); |
408 | } | |
43950a60 | 409 | if (max_retries < 0) |
0a32a102 | 410 | pr_debug("%s: INT not set\n", __func__); |
34f6e157 SH |
411 | } |
412 | } | |
413 | ||
71ec5155 SH |
414 | static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq) |
415 | { | |
416 | /* fill command */ | |
417 | writel(cmd, NFC_V3_FLASH_CMD); | |
418 | ||
419 | /* send out command */ | |
420 | writel(NFC_CMD, NFC_V3_LAUNCH); | |
421 | ||
422 | /* Wait for operation to complete */ | |
423 | wait_op_done(host, useirq); | |
424 | } | |
425 | ||
34f6e157 SH |
426 | /* This function issues the specified command to the NAND device and |
427 | * waits for completion. */ | |
5f97304e | 428 | static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq) |
34f6e157 | 429 | { |
289c0522 | 430 | pr_debug("send_cmd(host, 0x%x, %d)\n", cmd, useirq); |
34f6e157 | 431 | |
1bc99180 SH |
432 | writew(cmd, NFC_V1_V2_FLASH_CMD); |
433 | writew(NFC_CMD, NFC_V1_V2_CONFIG2); | |
34f6e157 | 434 | |
f48d0f9a | 435 | if (host->devtype_data->irqpending_quirk && (cmd == NAND_CMD_RESET)) { |
a47bfd2e IC |
436 | int max_retries = 100; |
437 | /* Reset completion is indicated by NFC_CONFIG2 */ | |
438 | /* being set to 0 */ | |
439 | while (max_retries-- > 0) { | |
1bc99180 | 440 | if (readw(NFC_V1_V2_CONFIG2) == 0) { |
a47bfd2e IC |
441 | break; |
442 | } | |
443 | udelay(1); | |
444 | } | |
445 | if (max_retries < 0) | |
0a32a102 | 446 | pr_debug("%s: RESET failed\n", __func__); |
a47bfd2e IC |
447 | } else { |
448 | /* Wait for operation to complete */ | |
449 | wait_op_done(host, useirq); | |
450 | } | |
34f6e157 SH |
451 | } |
452 | ||
71ec5155 SH |
453 | static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast) |
454 | { | |
455 | /* fill address */ | |
456 | writel(addr, NFC_V3_FLASH_ADDR0); | |
457 | ||
458 | /* send out address */ | |
459 | writel(NFC_ADDR, NFC_V3_LAUNCH); | |
460 | ||
461 | wait_op_done(host, 0); | |
462 | } | |
463 | ||
34f6e157 SH |
464 | /* This function sends an address (or partial address) to the |
465 | * NAND device. The address is used to select the source/destination for | |
466 | * a NAND command. */ | |
5f97304e | 467 | static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast) |
34f6e157 | 468 | { |
289c0522 | 469 | pr_debug("send_addr(host, 0x%x %d)\n", addr, islast); |
34f6e157 | 470 | |
1bc99180 SH |
471 | writew(addr, NFC_V1_V2_FLASH_ADDR); |
472 | writew(NFC_ADDR, NFC_V1_V2_CONFIG2); | |
34f6e157 SH |
473 | |
474 | /* Wait for operation to complete */ | |
c110eaf4 | 475 | wait_op_done(host, islast); |
34f6e157 SH |
476 | } |
477 | ||
71ec5155 SH |
478 | static void send_page_v3(struct mtd_info *mtd, unsigned int ops) |
479 | { | |
480 | struct nand_chip *nand_chip = mtd->priv; | |
481 | struct mxc_nand_host *host = nand_chip->priv; | |
482 | uint32_t tmp; | |
483 | ||
484 | tmp = readl(NFC_V3_CONFIG1); | |
485 | tmp &= ~(7 << 4); | |
486 | writel(tmp, NFC_V3_CONFIG1); | |
487 | ||
488 | /* transfer data from NFC ram to nand */ | |
489 | writel(ops, NFC_V3_LAUNCH); | |
490 | ||
491 | wait_op_done(host, false); | |
492 | } | |
493 | ||
6d38af25 UKK |
494 | static void send_page_v2(struct mtd_info *mtd, unsigned int ops) |
495 | { | |
496 | struct nand_chip *nand_chip = mtd->priv; | |
497 | struct mxc_nand_host *host = nand_chip->priv; | |
498 | ||
499 | /* NANDFC buffer 0 is used for page read/write */ | |
500 | writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR); | |
501 | ||
502 | writew(ops, NFC_V1_V2_CONFIG2); | |
503 | ||
504 | /* Wait for operation to complete */ | |
505 | wait_op_done(host, true); | |
506 | } | |
507 | ||
508 | static void send_page_v1(struct mtd_info *mtd, unsigned int ops) | |
34f6e157 | 509 | { |
2d69c7fa SH |
510 | struct nand_chip *nand_chip = mtd->priv; |
511 | struct mxc_nand_host *host = nand_chip->priv; | |
c5d23f1b | 512 | int bufs, i; |
34f6e157 | 513 | |
6d38af25 | 514 | if (mtd->writesize > 512) |
c5d23f1b SH |
515 | bufs = 4; |
516 | else | |
517 | bufs = 1; | |
34f6e157 | 518 | |
c5d23f1b | 519 | for (i = 0; i < bufs; i++) { |
34f6e157 | 520 | |
c5d23f1b | 521 | /* NANDFC buffer 0 is used for page read/write */ |
d178e3e8 | 522 | writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR); |
34f6e157 | 523 | |
1bc99180 | 524 | writew(ops, NFC_V1_V2_CONFIG2); |
34f6e157 | 525 | |
c5d23f1b | 526 | /* Wait for operation to complete */ |
c110eaf4 | 527 | wait_op_done(host, true); |
34f6e157 | 528 | } |
34f6e157 SH |
529 | } |
530 | ||
71ec5155 SH |
531 | static void send_read_id_v3(struct mxc_nand_host *host) |
532 | { | |
a8459f21 RS |
533 | struct nand_chip *this = &host->nand; |
534 | ||
71ec5155 SH |
535 | /* Read ID into main buffer */ |
536 | writel(NFC_ID, NFC_V3_LAUNCH); | |
537 | ||
538 | wait_op_done(host, true); | |
539 | ||
096bcc23 | 540 | memcpy32_fromio(host->data_buf, host->main_area0, 16); |
a8459f21 RS |
541 | |
542 | if (this->options & NAND_BUSWIDTH_16) { | |
543 | /* compress the ID info */ | |
544 | host->data_buf[1] = host->data_buf[2]; | |
545 | host->data_buf[2] = host->data_buf[4]; | |
546 | host->data_buf[3] = host->data_buf[6]; | |
547 | host->data_buf[4] = host->data_buf[8]; | |
548 | host->data_buf[5] = host->data_buf[10]; | |
549 | } | |
71ec5155 SH |
550 | } |
551 | ||
34f6e157 | 552 | /* Request the NANDFC to perform a read of the NAND device ID. */ |
5f97304e | 553 | static void send_read_id_v1_v2(struct mxc_nand_host *host) |
34f6e157 SH |
554 | { |
555 | struct nand_chip *this = &host->nand; | |
34f6e157 SH |
556 | |
557 | /* NANDFC buffer 0 is used for device ID output */ | |
d178e3e8 | 558 | writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR); |
34f6e157 | 559 | |
1bc99180 | 560 | writew(NFC_ID, NFC_V1_V2_CONFIG2); |
34f6e157 SH |
561 | |
562 | /* Wait for operation to complete */ | |
c110eaf4 | 563 | wait_op_done(host, true); |
34f6e157 | 564 | |
096bcc23 | 565 | memcpy32_fromio(host->data_buf, host->main_area0, 16); |
f7b66e5e | 566 | |
34f6e157 | 567 | if (this->options & NAND_BUSWIDTH_16) { |
34f6e157 | 568 | /* compress the ID info */ |
f7b66e5e JO |
569 | host->data_buf[1] = host->data_buf[2]; |
570 | host->data_buf[2] = host->data_buf[4]; | |
571 | host->data_buf[3] = host->data_buf[6]; | |
572 | host->data_buf[4] = host->data_buf[8]; | |
573 | host->data_buf[5] = host->data_buf[10]; | |
34f6e157 SH |
574 | } |
575 | } | |
576 | ||
71ec5155 SH |
577 | static uint16_t get_dev_status_v3(struct mxc_nand_host *host) |
578 | { | |
579 | writew(NFC_STATUS, NFC_V3_LAUNCH); | |
580 | wait_op_done(host, true); | |
581 | ||
582 | return readl(NFC_V3_CONFIG1) >> 16; | |
583 | } | |
584 | ||
34f6e157 SH |
585 | /* This function requests the NANDFC to perform a read of the |
586 | * NAND device status and returns the current status. */ | |
5f97304e | 587 | static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host) |
34f6e157 | 588 | { |
c29c607a | 589 | void __iomem *main_buf = host->main_area0; |
34f6e157 | 590 | uint32_t store; |
f06368f7 | 591 | uint16_t ret; |
34f6e157 | 592 | |
d178e3e8 | 593 | writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR); |
34f6e157 | 594 | |
c29c607a SH |
595 | /* |
596 | * The device status is stored in main_area0. To | |
597 | * prevent corruption of the buffer save the value | |
598 | * and restore it afterwards. | |
599 | */ | |
34f6e157 | 600 | store = readl(main_buf); |
34f6e157 | 601 | |
1bc99180 | 602 | writew(NFC_STATUS, NFC_V1_V2_CONFIG2); |
c110eaf4 | 603 | wait_op_done(host, true); |
34f6e157 | 604 | |
34f6e157 | 605 | ret = readw(main_buf); |
c29c607a | 606 | |
34f6e157 SH |
607 | writel(store, main_buf); |
608 | ||
609 | return ret; | |
610 | } | |
611 | ||
612 | /* This functions is used by upper layer to checks if device is ready */ | |
613 | static int mxc_nand_dev_ready(struct mtd_info *mtd) | |
614 | { | |
615 | /* | |
616 | * NFC handles R/B internally. Therefore, this function | |
617 | * always returns status as ready. | |
618 | */ | |
619 | return 1; | |
620 | } | |
621 | ||
622 | static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode) | |
623 | { | |
624 | /* | |
625 | * If HW ECC is enabled, we turn it on during init. There is | |
626 | * no need to enable again here. | |
627 | */ | |
628 | } | |
629 | ||
94f77e50 | 630 | static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat, |
34f6e157 SH |
631 | u_char *read_ecc, u_char *calc_ecc) |
632 | { | |
633 | struct nand_chip *nand_chip = mtd->priv; | |
634 | struct mxc_nand_host *host = nand_chip->priv; | |
635 | ||
636 | /* | |
637 | * 1-Bit errors are automatically corrected in HW. No need for | |
638 | * additional correction. 2-Bit errors cannot be corrected by | |
639 | * HW ECC, so we need to return failure | |
640 | */ | |
6d38af25 | 641 | uint16_t ecc_status = get_ecc_status_v1(host); |
34f6e157 SH |
642 | |
643 | if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) { | |
289c0522 | 644 | pr_debug("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n"); |
34f6e157 SH |
645 | return -1; |
646 | } | |
647 | ||
648 | return 0; | |
649 | } | |
650 | ||
94f77e50 SH |
651 | static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat, |
652 | u_char *read_ecc, u_char *calc_ecc) | |
653 | { | |
654 | struct nand_chip *nand_chip = mtd->priv; | |
655 | struct mxc_nand_host *host = nand_chip->priv; | |
656 | u32 ecc_stat, err; | |
657 | int no_subpages = 1; | |
658 | int ret = 0; | |
659 | u8 ecc_bit_mask, err_limit; | |
660 | ||
661 | ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf; | |
662 | err_limit = (host->eccsize == 4) ? 0x4 : 0x8; | |
663 | ||
664 | no_subpages = mtd->writesize >> 9; | |
665 | ||
6d38af25 | 666 | ecc_stat = host->devtype_data->get_ecc_status(host); |
94f77e50 SH |
667 | |
668 | do { | |
669 | err = ecc_stat & ecc_bit_mask; | |
670 | if (err > err_limit) { | |
671 | printk(KERN_WARNING "UnCorrectable RS-ECC Error\n"); | |
672 | return -1; | |
673 | } else { | |
674 | ret += err; | |
675 | } | |
676 | ecc_stat >>= 4; | |
677 | } while (--no_subpages); | |
678 | ||
679 | mtd->ecc_stats.corrected += ret; | |
680 | pr_debug("%d Symbol Correctable RS-ECC Error\n", ret); | |
681 | ||
682 | return ret; | |
683 | } | |
684 | ||
34f6e157 SH |
685 | static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, |
686 | u_char *ecc_code) | |
687 | { | |
688 | return 0; | |
689 | } | |
690 | ||
691 | static u_char mxc_nand_read_byte(struct mtd_info *mtd) | |
692 | { | |
693 | struct nand_chip *nand_chip = mtd->priv; | |
694 | struct mxc_nand_host *host = nand_chip->priv; | |
f8f9608d | 695 | uint8_t ret; |
34f6e157 SH |
696 | |
697 | /* Check for status request */ | |
698 | if (host->status_request) | |
e4303b25 | 699 | return host->devtype_data->get_dev_status(host) & 0xFF; |
34f6e157 | 700 | |
f8f9608d SH |
701 | ret = *(uint8_t *)(host->data_buf + host->buf_start); |
702 | host->buf_start++; | |
34f6e157 SH |
703 | |
704 | return ret; | |
705 | } | |
706 | ||
707 | static uint16_t mxc_nand_read_word(struct mtd_info *mtd) | |
708 | { | |
709 | struct nand_chip *nand_chip = mtd->priv; | |
710 | struct mxc_nand_host *host = nand_chip->priv; | |
f8f9608d | 711 | uint16_t ret; |
34f6e157 | 712 | |
f8f9608d SH |
713 | ret = *(uint16_t *)(host->data_buf + host->buf_start); |
714 | host->buf_start += 2; | |
34f6e157 SH |
715 | |
716 | return ret; | |
717 | } | |
718 | ||
719 | /* Write data of length len to buffer buf. The data to be | |
720 | * written on NAND Flash is first copied to RAMbuffer. After the Data Input | |
721 | * Operation by the NFC, the data is written to NAND Flash */ | |
722 | static void mxc_nand_write_buf(struct mtd_info *mtd, | |
723 | const u_char *buf, int len) | |
724 | { | |
725 | struct nand_chip *nand_chip = mtd->priv; | |
726 | struct mxc_nand_host *host = nand_chip->priv; | |
f8f9608d SH |
727 | u16 col = host->buf_start; |
728 | int n = mtd->oobsize + mtd->writesize - col; | |
34f6e157 | 729 | |
f8f9608d | 730 | n = min(n, len); |
34f6e157 | 731 | |
f8f9608d | 732 | memcpy(host->data_buf + col, buf, n); |
34f6e157 | 733 | |
f8f9608d | 734 | host->buf_start += n; |
34f6e157 SH |
735 | } |
736 | ||
737 | /* Read the data buffer from the NAND Flash. To read the data from NAND | |
738 | * Flash first the data output cycle is initiated by the NFC, which copies | |
739 | * the data to RAMbuffer. This data of length len is then copied to buffer buf. | |
740 | */ | |
741 | static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) | |
742 | { | |
743 | struct nand_chip *nand_chip = mtd->priv; | |
744 | struct mxc_nand_host *host = nand_chip->priv; | |
f8f9608d SH |
745 | u16 col = host->buf_start; |
746 | int n = mtd->oobsize + mtd->writesize - col; | |
34f6e157 | 747 | |
f8f9608d | 748 | n = min(n, len); |
34f6e157 | 749 | |
5d9d9936 | 750 | memcpy(buf, host->data_buf + col, n); |
34f6e157 | 751 | |
5d9d9936 | 752 | host->buf_start += n; |
34f6e157 SH |
753 | } |
754 | ||
34f6e157 SH |
755 | /* This function is used by upper layer for select and |
756 | * deselect of the NAND chip */ | |
5e05a2d6 | 757 | static void mxc_nand_select_chip_v1_v3(struct mtd_info *mtd, int chip) |
34f6e157 SH |
758 | { |
759 | struct nand_chip *nand_chip = mtd->priv; | |
760 | struct mxc_nand_host *host = nand_chip->priv; | |
761 | ||
d178e3e8 | 762 | if (chip == -1) { |
34f6e157 SH |
763 | /* Disable the NFC clock */ |
764 | if (host->clk_act) { | |
97c3213f | 765 | clk_disable_unprepare(host->clk); |
34f6e157 SH |
766 | host->clk_act = 0; |
767 | } | |
d178e3e8 BS |
768 | return; |
769 | } | |
770 | ||
771 | if (!host->clk_act) { | |
34f6e157 | 772 | /* Enable the NFC clock */ |
97c3213f | 773 | clk_prepare_enable(host->clk); |
d178e3e8 BS |
774 | host->clk_act = 1; |
775 | } | |
5e05a2d6 | 776 | } |
34f6e157 | 777 | |
5e05a2d6 UKK |
778 | static void mxc_nand_select_chip_v2(struct mtd_info *mtd, int chip) |
779 | { | |
780 | struct nand_chip *nand_chip = mtd->priv; | |
781 | struct mxc_nand_host *host = nand_chip->priv; | |
782 | ||
783 | if (chip == -1) { | |
784 | /* Disable the NFC clock */ | |
785 | if (host->clk_act) { | |
3d059693 | 786 | clk_disable_unprepare(host->clk); |
5e05a2d6 UKK |
787 | host->clk_act = 0; |
788 | } | |
789 | return; | |
790 | } | |
34f6e157 | 791 | |
5e05a2d6 UKK |
792 | if (!host->clk_act) { |
793 | /* Enable the NFC clock */ | |
3d059693 | 794 | clk_prepare_enable(host->clk); |
5e05a2d6 | 795 | host->clk_act = 1; |
34f6e157 | 796 | } |
5e05a2d6 UKK |
797 | |
798 | host->active_cs = chip; | |
799 | writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR); | |
34f6e157 SH |
800 | } |
801 | ||
f8f9608d SH |
802 | /* |
803 | * Function to transfer data to/from spare area. | |
804 | */ | |
805 | static void copy_spare(struct mtd_info *mtd, bool bfrom) | |
34f6e157 | 806 | { |
f8f9608d SH |
807 | struct nand_chip *this = mtd->priv; |
808 | struct mxc_nand_host *host = this->priv; | |
809 | u16 i, j; | |
810 | u16 n = mtd->writesize >> 9; | |
811 | u8 *d = host->data_buf + mtd->writesize; | |
4b6f05e1 | 812 | u8 __iomem *s = host->spare0; |
f48d0f9a | 813 | u16 t = host->devtype_data->spare_len; |
f8f9608d SH |
814 | |
815 | j = (mtd->oobsize / n >> 1) << 1; | |
816 | ||
817 | if (bfrom) { | |
818 | for (i = 0; i < n - 1; i++) | |
096bcc23 | 819 | memcpy32_fromio(d + i * j, s + i * t, j); |
f8f9608d SH |
820 | |
821 | /* the last section */ | |
096bcc23 | 822 | memcpy32_fromio(d + i * j, s + i * t, mtd->oobsize - i * j); |
f8f9608d SH |
823 | } else { |
824 | for (i = 0; i < n - 1; i++) | |
096bcc23 | 825 | memcpy32_toio(&s[i * t], &d[i * j], j); |
34f6e157 | 826 | |
f8f9608d | 827 | /* the last section */ |
096bcc23 | 828 | memcpy32_toio(&s[i * t], &d[i * j], mtd->oobsize - i * j); |
34f6e157 | 829 | } |
f8f9608d | 830 | } |
34f6e157 | 831 | |
a3e65b64 SH |
832 | static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr) |
833 | { | |
834 | struct nand_chip *nand_chip = mtd->priv; | |
835 | struct mxc_nand_host *host = nand_chip->priv; | |
34f6e157 SH |
836 | |
837 | /* Write out column address, if necessary */ | |
838 | if (column != -1) { | |
839 | /* | |
840 | * MXC NANDFC can only perform full page+spare or | |
841 | * spare-only read/write. When the upper layers | |
177b241d GE |
842 | * perform a read/write buf operation, the saved column |
843 | * address is used to index into the full page. | |
34f6e157 | 844 | */ |
e4303b25 | 845 | host->devtype_data->send_addr(host, 0, page_addr == -1); |
2d69c7fa | 846 | if (mtd->writesize > 512) |
34f6e157 | 847 | /* another col addr cycle for 2k page */ |
e4303b25 | 848 | host->devtype_data->send_addr(host, 0, false); |
34f6e157 SH |
849 | } |
850 | ||
851 | /* Write out page address, if necessary */ | |
852 | if (page_addr != -1) { | |
853 | /* paddr_0 - p_addr_7 */ | |
e4303b25 | 854 | host->devtype_data->send_addr(host, (page_addr & 0xff), false); |
34f6e157 | 855 | |
2d69c7fa | 856 | if (mtd->writesize > 512) { |
bd3fd62e VB |
857 | if (mtd->size >= 0x10000000) { |
858 | /* paddr_8 - paddr_15 */ | |
e4303b25 UKK |
859 | host->devtype_data->send_addr(host, |
860 | (page_addr >> 8) & 0xff, | |
861 | false); | |
862 | host->devtype_data->send_addr(host, | |
863 | (page_addr >> 16) & 0xff, | |
864 | true); | |
bd3fd62e VB |
865 | } else |
866 | /* paddr_8 - paddr_15 */ | |
e4303b25 UKK |
867 | host->devtype_data->send_addr(host, |
868 | (page_addr >> 8) & 0xff, true); | |
34f6e157 SH |
869 | } else { |
870 | /* One more address cycle for higher density devices */ | |
871 | if (mtd->size >= 0x4000000) { | |
872 | /* paddr_8 - paddr_15 */ | |
e4303b25 UKK |
873 | host->devtype_data->send_addr(host, |
874 | (page_addr >> 8) & 0xff, | |
875 | false); | |
876 | host->devtype_data->send_addr(host, | |
877 | (page_addr >> 16) & 0xff, | |
878 | true); | |
34f6e157 SH |
879 | } else |
880 | /* paddr_8 - paddr_15 */ | |
e4303b25 UKK |
881 | host->devtype_data->send_addr(host, |
882 | (page_addr >> 8) & 0xff, true); | |
34f6e157 SH |
883 | } |
884 | } | |
a3e65b64 SH |
885 | } |
886 | ||
6e85dfdc SH |
887 | /* |
888 | * v2 and v3 type controllers can do 4bit or 8bit ecc depending | |
889 | * on how much oob the nand chip has. For 8bit ecc we need at least | |
890 | * 26 bytes of oob data per 512 byte block. | |
891 | */ | |
892 | static int get_eccsize(struct mtd_info *mtd) | |
893 | { | |
894 | int oobbytes_per_512 = 0; | |
895 | ||
896 | oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize; | |
897 | ||
898 | if (oobbytes_per_512 < 26) | |
899 | return 4; | |
900 | else | |
901 | return 8; | |
902 | } | |
903 | ||
6d38af25 | 904 | static void preset_v1(struct mtd_info *mtd) |
d4840180 IC |
905 | { |
906 | struct nand_chip *nand_chip = mtd->priv; | |
907 | struct mxc_nand_host *host = nand_chip->priv; | |
b8db2f51 SH |
908 | uint16_t config1 = 0; |
909 | ||
910 | if (nand_chip->ecc.mode == NAND_ECC_HW) | |
911 | config1 |= NFC_V1_V2_CONFIG1_ECC_EN; | |
912 | ||
f48d0f9a | 913 | if (!host->devtype_data->irqpending_quirk) |
6d38af25 UKK |
914 | config1 |= NFC_V1_V2_CONFIG1_INT_MSK; |
915 | ||
916 | host->eccsize = 1; | |
917 | ||
918 | writew(config1, NFC_V1_V2_CONFIG1); | |
919 | /* preset operation */ | |
920 | ||
921 | /* Unlock the internal RAM Buffer */ | |
922 | writew(0x2, NFC_V1_V2_CONFIG); | |
923 | ||
924 | /* Blocks to be unlocked */ | |
925 | writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR); | |
926 | writew(0xffff, NFC_V1_UNLOCKEND_BLKADDR); | |
927 | ||
928 | /* Unlock Block Command for given address range */ | |
929 | writew(0x4, NFC_V1_V2_WRPROT); | |
930 | } | |
931 | ||
932 | static void preset_v2(struct mtd_info *mtd) | |
d4840180 IC |
933 | { |
934 | struct nand_chip *nand_chip = mtd->priv; | |
935 | struct mxc_nand_host *host = nand_chip->priv; | |
b8db2f51 SH |
936 | uint16_t config1 = 0; |
937 | ||
938 | if (nand_chip->ecc.mode == NAND_ECC_HW) | |
939 | config1 |= NFC_V1_V2_CONFIG1_ECC_EN; | |
940 | ||
6d38af25 | 941 | config1 |= NFC_V2_CONFIG1_FP_INT; |
b8db2f51 | 942 | |
f48d0f9a | 943 | if (!host->devtype_data->irqpending_quirk) |
b8db2f51 | 944 | config1 |= NFC_V1_V2_CONFIG1_INT_MSK; |
6e85dfdc | 945 | |
6d38af25 | 946 | if (mtd->writesize) { |
b8db2f51 SH |
947 | uint16_t pages_per_block = mtd->erasesize / mtd->writesize; |
948 | ||
6e85dfdc SH |
949 | host->eccsize = get_eccsize(mtd); |
950 | if (host->eccsize == 4) | |
b8db2f51 SH |
951 | config1 |= NFC_V2_CONFIG1_ECC_MODE_4; |
952 | ||
953 | config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6); | |
d4840180 | 954 | } else { |
6e85dfdc | 955 | host->eccsize = 1; |
d4840180 | 956 | } |
6e85dfdc | 957 | |
b8db2f51 | 958 | writew(config1, NFC_V1_V2_CONFIG1); |
d4840180 IC |
959 | /* preset operation */ |
960 | ||
961 | /* Unlock the internal RAM Buffer */ | |
1bc99180 | 962 | writew(0x2, NFC_V1_V2_CONFIG); |
d4840180 IC |
963 | |
964 | /* Blocks to be unlocked */ | |
6d38af25 UKK |
965 | writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0); |
966 | writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1); | |
967 | writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2); | |
968 | writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3); | |
969 | writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0); | |
970 | writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1); | |
971 | writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2); | |
972 | writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3); | |
d4840180 IC |
973 | |
974 | /* Unlock Block Command for given address range */ | |
1bc99180 | 975 | writew(0x4, NFC_V1_V2_WRPROT); |
d4840180 IC |
976 | } |
977 | ||
71ec5155 SH |
978 | static void preset_v3(struct mtd_info *mtd) |
979 | { | |
980 | struct nand_chip *chip = mtd->priv; | |
981 | struct mxc_nand_host *host = chip->priv; | |
982 | uint32_t config2, config3; | |
983 | int i, addr_phases; | |
984 | ||
985 | writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1); | |
986 | writel(NFC_V3_IPC_CREQ, NFC_V3_IPC); | |
987 | ||
988 | /* Unlock the internal RAM Buffer */ | |
989 | writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK, | |
990 | NFC_V3_WRPROT); | |
991 | ||
992 | /* Blocks to be unlocked */ | |
993 | for (i = 0; i < NAND_MAX_CHIPS; i++) | |
994 | writel(0x0 | (0xffff << 16), | |
995 | NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2)); | |
996 | ||
997 | writel(0, NFC_V3_IPC); | |
998 | ||
999 | config2 = NFC_V3_CONFIG2_ONE_CYCLE | | |
1000 | NFC_V3_CONFIG2_2CMD_PHASES | | |
1001 | NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) | | |
1002 | NFC_V3_CONFIG2_ST_CMD(0x70) | | |
63f1474c | 1003 | NFC_V3_CONFIG2_INT_MSK | |
71ec5155 SH |
1004 | NFC_V3_CONFIG2_NUM_ADDR_PHASE0; |
1005 | ||
1006 | if (chip->ecc.mode == NAND_ECC_HW) | |
1007 | config2 |= NFC_V3_CONFIG2_ECC_EN; | |
1008 | ||
1009 | addr_phases = fls(chip->pagemask) >> 3; | |
1010 | ||
1011 | if (mtd->writesize == 2048) { | |
1012 | config2 |= NFC_V3_CONFIG2_PS_2048; | |
1013 | config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases); | |
1014 | } else if (mtd->writesize == 4096) { | |
1015 | config2 |= NFC_V3_CONFIG2_PS_4096; | |
1016 | config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases); | |
1017 | } else { | |
1018 | config2 |= NFC_V3_CONFIG2_PS_512; | |
1019 | config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1); | |
1020 | } | |
1021 | ||
1022 | if (mtd->writesize) { | |
71718a8e SH |
1023 | config2 |= NFC_V3_CONFIG2_PPB( |
1024 | ffs(mtd->erasesize / mtd->writesize) - 6, | |
1025 | host->devtype_data->ppb_shift); | |
71ec5155 SH |
1026 | host->eccsize = get_eccsize(mtd); |
1027 | if (host->eccsize == 8) | |
1028 | config2 |= NFC_V3_CONFIG2_ECC_MODE_8; | |
1029 | } | |
1030 | ||
1031 | writel(config2, NFC_V3_CONFIG2); | |
1032 | ||
1033 | config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) | | |
1034 | NFC_V3_CONFIG3_NO_SDMA | | |
1035 | NFC_V3_CONFIG3_RBB_MODE | | |
1036 | NFC_V3_CONFIG3_SBB(6) | /* Reset default */ | |
1037 | NFC_V3_CONFIG3_ADD_OP(0); | |
1038 | ||
1039 | if (!(chip->options & NAND_BUSWIDTH_16)) | |
1040 | config3 |= NFC_V3_CONFIG3_FW8; | |
1041 | ||
1042 | writel(config3, NFC_V3_CONFIG3); | |
1043 | ||
1044 | writel(0, NFC_V3_DELAY_LINE); | |
d4840180 IC |
1045 | } |
1046 | ||
34f6e157 SH |
1047 | /* Used by the upper layer to write command to NAND Flash for |
1048 | * different operations to be carried out on NAND Flash */ | |
1049 | static void mxc_nand_command(struct mtd_info *mtd, unsigned command, | |
1050 | int column, int page_addr) | |
1051 | { | |
1052 | struct nand_chip *nand_chip = mtd->priv; | |
1053 | struct mxc_nand_host *host = nand_chip->priv; | |
34f6e157 | 1054 | |
289c0522 | 1055 | pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n", |
34f6e157 SH |
1056 | command, column, page_addr); |
1057 | ||
1058 | /* Reset command state information */ | |
1059 | host->status_request = false; | |
34f6e157 | 1060 | |
34f6e157 | 1061 | /* Command pre-processing step */ |
34f6e157 | 1062 | switch (command) { |
d4840180 | 1063 | case NAND_CMD_RESET: |
e4303b25 UKK |
1064 | host->devtype_data->preset(mtd); |
1065 | host->devtype_data->send_cmd(host, command, false); | |
d4840180 | 1066 | break; |
34f6e157 | 1067 | |
34f6e157 | 1068 | case NAND_CMD_STATUS: |
f8f9608d | 1069 | host->buf_start = 0; |
34f6e157 | 1070 | host->status_request = true; |
34f6e157 | 1071 | |
e4303b25 | 1072 | host->devtype_data->send_cmd(host, command, true); |
89121a6b | 1073 | mxc_do_addr_cycle(mtd, column, page_addr); |
34f6e157 SH |
1074 | break; |
1075 | ||
34f6e157 | 1076 | case NAND_CMD_READ0: |
34f6e157 | 1077 | case NAND_CMD_READOOB: |
89121a6b SH |
1078 | if (command == NAND_CMD_READ0) |
1079 | host->buf_start = column; | |
1080 | else | |
1081 | host->buf_start = column + mtd->writesize; | |
f8f9608d | 1082 | |
5ea32021 | 1083 | command = NAND_CMD_READ0; /* only READ0 is valid */ |
89121a6b | 1084 | |
e4303b25 | 1085 | host->devtype_data->send_cmd(host, command, false); |
89121a6b SH |
1086 | mxc_do_addr_cycle(mtd, column, page_addr); |
1087 | ||
2d69c7fa | 1088 | if (mtd->writesize > 512) |
e4303b25 UKK |
1089 | host->devtype_data->send_cmd(host, |
1090 | NAND_CMD_READSTART, true); | |
c5d23f1b | 1091 | |
e4303b25 | 1092 | host->devtype_data->send_page(mtd, NFC_OUTPUT); |
89121a6b | 1093 | |
096bcc23 SH |
1094 | memcpy32_fromio(host->data_buf, host->main_area0, |
1095 | mtd->writesize); | |
89121a6b | 1096 | copy_spare(mtd, true); |
34f6e157 SH |
1097 | break; |
1098 | ||
34f6e157 | 1099 | case NAND_CMD_SEQIN: |
5ea32021 SH |
1100 | if (column >= mtd->writesize) |
1101 | /* call ourself to read a page */ | |
1102 | mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr); | |
34f6e157 | 1103 | |
5ea32021 | 1104 | host->buf_start = column; |
89121a6b | 1105 | |
e4303b25 | 1106 | host->devtype_data->send_cmd(host, command, false); |
89121a6b | 1107 | mxc_do_addr_cycle(mtd, column, page_addr); |
34f6e157 SH |
1108 | break; |
1109 | ||
1110 | case NAND_CMD_PAGEPROG: | |
096bcc23 | 1111 | memcpy32_toio(host->main_area0, host->data_buf, mtd->writesize); |
f8f9608d | 1112 | copy_spare(mtd, false); |
e4303b25 UKK |
1113 | host->devtype_data->send_page(mtd, NFC_INPUT); |
1114 | host->devtype_data->send_cmd(host, command, true); | |
89121a6b | 1115 | mxc_do_addr_cycle(mtd, column, page_addr); |
34f6e157 SH |
1116 | break; |
1117 | ||
34f6e157 | 1118 | case NAND_CMD_READID: |
e4303b25 | 1119 | host->devtype_data->send_cmd(host, command, true); |
89121a6b | 1120 | mxc_do_addr_cycle(mtd, column, page_addr); |
e4303b25 | 1121 | host->devtype_data->send_read_id(host); |
9467114e | 1122 | host->buf_start = column; |
34f6e157 SH |
1123 | break; |
1124 | ||
89121a6b | 1125 | case NAND_CMD_ERASE1: |
34f6e157 | 1126 | case NAND_CMD_ERASE2: |
e4303b25 | 1127 | host->devtype_data->send_cmd(host, command, false); |
89121a6b SH |
1128 | mxc_do_addr_cycle(mtd, column, page_addr); |
1129 | ||
34f6e157 SH |
1130 | break; |
1131 | } | |
1132 | } | |
1133 | ||
f1372055 SH |
1134 | /* |
1135 | * The generic flash bbt decriptors overlap with our ecc | |
1136 | * hardware, so define some i.MX specific ones. | |
1137 | */ | |
1138 | static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' }; | |
1139 | static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' }; | |
1140 | ||
1141 | static struct nand_bbt_descr bbt_main_descr = { | |
1142 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
1143 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
1144 | .offs = 0, | |
1145 | .len = 4, | |
1146 | .veroffs = 4, | |
1147 | .maxblocks = 4, | |
1148 | .pattern = bbt_pattern, | |
1149 | }; | |
1150 | ||
1151 | static struct nand_bbt_descr bbt_mirror_descr = { | |
1152 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
1153 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
1154 | .offs = 0, | |
1155 | .len = 4, | |
1156 | .veroffs = 4, | |
1157 | .maxblocks = 4, | |
1158 | .pattern = mirror_pattern, | |
1159 | }; | |
1160 | ||
f48d0f9a | 1161 | /* v1 + irqpending_quirk: i.MX21 */ |
e4303b25 | 1162 | static const struct mxc_nand_devtype_data imx21_nand_devtype_data = { |
6d38af25 | 1163 | .preset = preset_v1, |
e4303b25 UKK |
1164 | .send_cmd = send_cmd_v1_v2, |
1165 | .send_addr = send_addr_v1_v2, | |
6d38af25 | 1166 | .send_page = send_page_v1, |
e4303b25 UKK |
1167 | .send_read_id = send_read_id_v1_v2, |
1168 | .get_dev_status = get_dev_status_v1_v2, | |
1169 | .check_int = check_int_v1_v2, | |
1170 | .irq_control = irq_control_v1_v2, | |
6d38af25 | 1171 | .get_ecc_status = get_ecc_status_v1, |
6dcdf99d UKK |
1172 | .ecclayout_512 = &nandv1_hw_eccoob_smallpage, |
1173 | .ecclayout_2k = &nandv1_hw_eccoob_largepage, | |
1174 | .ecclayout_4k = &nandv1_hw_eccoob_smallpage, /* XXX: needs fix */ | |
5e05a2d6 | 1175 | .select_chip = mxc_nand_select_chip_v1_v3, |
69d023be | 1176 | .correct_data = mxc_nand_correct_data_v1, |
f48d0f9a UKK |
1177 | .irqpending_quirk = 1, |
1178 | .needs_ip = 0, | |
1179 | .regs_offset = 0xe00, | |
1180 | .spare0_offset = 0x800, | |
1181 | .spare_len = 16, | |
1182 | .eccbytes = 3, | |
1183 | .eccsize = 1, | |
1184 | }; | |
1185 | ||
1186 | /* v1 + !irqpending_quirk: i.MX27, i.MX31 */ | |
1187 | static const struct mxc_nand_devtype_data imx27_nand_devtype_data = { | |
1188 | .preset = preset_v1, | |
1189 | .send_cmd = send_cmd_v1_v2, | |
1190 | .send_addr = send_addr_v1_v2, | |
1191 | .send_page = send_page_v1, | |
1192 | .send_read_id = send_read_id_v1_v2, | |
1193 | .get_dev_status = get_dev_status_v1_v2, | |
1194 | .check_int = check_int_v1_v2, | |
1195 | .irq_control = irq_control_v1_v2, | |
1196 | .get_ecc_status = get_ecc_status_v1, | |
1197 | .ecclayout_512 = &nandv1_hw_eccoob_smallpage, | |
1198 | .ecclayout_2k = &nandv1_hw_eccoob_largepage, | |
1199 | .ecclayout_4k = &nandv1_hw_eccoob_smallpage, /* XXX: needs fix */ | |
1200 | .select_chip = mxc_nand_select_chip_v1_v3, | |
1201 | .correct_data = mxc_nand_correct_data_v1, | |
1202 | .irqpending_quirk = 0, | |
1203 | .needs_ip = 0, | |
1204 | .regs_offset = 0xe00, | |
1205 | .spare0_offset = 0x800, | |
1206 | .axi_offset = 0, | |
1207 | .spare_len = 16, | |
1208 | .eccbytes = 3, | |
1209 | .eccsize = 1, | |
e4303b25 UKK |
1210 | }; |
1211 | ||
1212 | /* v21: i.MX25, i.MX35 */ | |
1213 | static const struct mxc_nand_devtype_data imx25_nand_devtype_data = { | |
6d38af25 | 1214 | .preset = preset_v2, |
e4303b25 UKK |
1215 | .send_cmd = send_cmd_v1_v2, |
1216 | .send_addr = send_addr_v1_v2, | |
6d38af25 | 1217 | .send_page = send_page_v2, |
e4303b25 UKK |
1218 | .send_read_id = send_read_id_v1_v2, |
1219 | .get_dev_status = get_dev_status_v1_v2, | |
1220 | .check_int = check_int_v1_v2, | |
1221 | .irq_control = irq_control_v1_v2, | |
6d38af25 | 1222 | .get_ecc_status = get_ecc_status_v2, |
6dcdf99d UKK |
1223 | .ecclayout_512 = &nandv2_hw_eccoob_smallpage, |
1224 | .ecclayout_2k = &nandv2_hw_eccoob_largepage, | |
1225 | .ecclayout_4k = &nandv2_hw_eccoob_4k, | |
5e05a2d6 | 1226 | .select_chip = mxc_nand_select_chip_v2, |
69d023be | 1227 | .correct_data = mxc_nand_correct_data_v2_v3, |
f48d0f9a UKK |
1228 | .irqpending_quirk = 0, |
1229 | .needs_ip = 0, | |
1230 | .regs_offset = 0x1e00, | |
1231 | .spare0_offset = 0x1000, | |
1232 | .axi_offset = 0, | |
1233 | .spare_len = 64, | |
1234 | .eccbytes = 9, | |
1235 | .eccsize = 0, | |
e4303b25 UKK |
1236 | }; |
1237 | ||
71718a8e | 1238 | /* v3.2a: i.MX51 */ |
e4303b25 UKK |
1239 | static const struct mxc_nand_devtype_data imx51_nand_devtype_data = { |
1240 | .preset = preset_v3, | |
1241 | .send_cmd = send_cmd_v3, | |
1242 | .send_addr = send_addr_v3, | |
1243 | .send_page = send_page_v3, | |
1244 | .send_read_id = send_read_id_v3, | |
1245 | .get_dev_status = get_dev_status_v3, | |
1246 | .check_int = check_int_v3, | |
1247 | .irq_control = irq_control_v3, | |
6d38af25 | 1248 | .get_ecc_status = get_ecc_status_v3, |
6dcdf99d UKK |
1249 | .ecclayout_512 = &nandv2_hw_eccoob_smallpage, |
1250 | .ecclayout_2k = &nandv2_hw_eccoob_largepage, | |
1251 | .ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */ | |
5e05a2d6 | 1252 | .select_chip = mxc_nand_select_chip_v1_v3, |
69d023be | 1253 | .correct_data = mxc_nand_correct_data_v2_v3, |
f48d0f9a UKK |
1254 | .irqpending_quirk = 0, |
1255 | .needs_ip = 1, | |
1256 | .regs_offset = 0, | |
1257 | .spare0_offset = 0x1000, | |
1258 | .axi_offset = 0x1e00, | |
1259 | .spare_len = 64, | |
1260 | .eccbytes = 0, | |
1261 | .eccsize = 0, | |
71718a8e SH |
1262 | .ppb_shift = 7, |
1263 | }; | |
1264 | ||
1265 | /* v3.2b: i.MX53 */ | |
1266 | static const struct mxc_nand_devtype_data imx53_nand_devtype_data = { | |
1267 | .preset = preset_v3, | |
1268 | .send_cmd = send_cmd_v3, | |
1269 | .send_addr = send_addr_v3, | |
1270 | .send_page = send_page_v3, | |
1271 | .send_read_id = send_read_id_v3, | |
1272 | .get_dev_status = get_dev_status_v3, | |
1273 | .check_int = check_int_v3, | |
1274 | .irq_control = irq_control_v3, | |
1275 | .get_ecc_status = get_ecc_status_v3, | |
1276 | .ecclayout_512 = &nandv2_hw_eccoob_smallpage, | |
1277 | .ecclayout_2k = &nandv2_hw_eccoob_largepage, | |
1278 | .ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */ | |
1279 | .select_chip = mxc_nand_select_chip_v1_v3, | |
1280 | .correct_data = mxc_nand_correct_data_v2_v3, | |
1281 | .irqpending_quirk = 0, | |
1282 | .needs_ip = 1, | |
1283 | .regs_offset = 0, | |
1284 | .spare0_offset = 0x1000, | |
1285 | .axi_offset = 0x1e00, | |
1286 | .spare_len = 64, | |
1287 | .eccbytes = 0, | |
1288 | .eccsize = 0, | |
1289 | .ppb_shift = 8, | |
e4303b25 UKK |
1290 | }; |
1291 | ||
4d62435f SG |
1292 | static inline int is_imx21_nfc(struct mxc_nand_host *host) |
1293 | { | |
1294 | return host->devtype_data == &imx21_nand_devtype_data; | |
1295 | } | |
1296 | ||
1297 | static inline int is_imx27_nfc(struct mxc_nand_host *host) | |
1298 | { | |
1299 | return host->devtype_data == &imx27_nand_devtype_data; | |
1300 | } | |
1301 | ||
1302 | static inline int is_imx25_nfc(struct mxc_nand_host *host) | |
1303 | { | |
1304 | return host->devtype_data == &imx25_nand_devtype_data; | |
1305 | } | |
1306 | ||
1307 | static inline int is_imx51_nfc(struct mxc_nand_host *host) | |
1308 | { | |
1309 | return host->devtype_data == &imx51_nand_devtype_data; | |
1310 | } | |
1311 | ||
1312 | static inline int is_imx53_nfc(struct mxc_nand_host *host) | |
1313 | { | |
1314 | return host->devtype_data == &imx53_nand_devtype_data; | |
1315 | } | |
1316 | ||
1317 | static struct platform_device_id mxcnd_devtype[] = { | |
1318 | { | |
1319 | .name = "imx21-nand", | |
1320 | .driver_data = (kernel_ulong_t) &imx21_nand_devtype_data, | |
1321 | }, { | |
1322 | .name = "imx27-nand", | |
1323 | .driver_data = (kernel_ulong_t) &imx27_nand_devtype_data, | |
1324 | }, { | |
1325 | .name = "imx25-nand", | |
1326 | .driver_data = (kernel_ulong_t) &imx25_nand_devtype_data, | |
1327 | }, { | |
1328 | .name = "imx51-nand", | |
1329 | .driver_data = (kernel_ulong_t) &imx51_nand_devtype_data, | |
1330 | }, { | |
1331 | .name = "imx53-nand", | |
1332 | .driver_data = (kernel_ulong_t) &imx53_nand_devtype_data, | |
1333 | }, { | |
1334 | /* sentinel */ | |
1335 | } | |
1336 | }; | |
1337 | MODULE_DEVICE_TABLE(platform, mxcnd_devtype); | |
1338 | ||
6436356b UKK |
1339 | #ifdef CONFIG_OF_MTD |
1340 | static const struct of_device_id mxcnd_dt_ids[] = { | |
1341 | { | |
1342 | .compatible = "fsl,imx21-nand", | |
1343 | .data = &imx21_nand_devtype_data, | |
1344 | }, { | |
1345 | .compatible = "fsl,imx27-nand", | |
1346 | .data = &imx27_nand_devtype_data, | |
1347 | }, { | |
1348 | .compatible = "fsl,imx25-nand", | |
1349 | .data = &imx25_nand_devtype_data, | |
1350 | }, { | |
1351 | .compatible = "fsl,imx51-nand", | |
1352 | .data = &imx51_nand_devtype_data, | |
71718a8e SH |
1353 | }, { |
1354 | .compatible = "fsl,imx53-nand", | |
1355 | .data = &imx53_nand_devtype_data, | |
6436356b UKK |
1356 | }, |
1357 | { /* sentinel */ } | |
1358 | }; | |
1359 | ||
1360 | static int __init mxcnd_probe_dt(struct mxc_nand_host *host) | |
1361 | { | |
1362 | struct device_node *np = host->dev->of_node; | |
1363 | struct mxc_nand_platform_data *pdata = &host->pdata; | |
1364 | const struct of_device_id *of_id = | |
1365 | of_match_device(mxcnd_dt_ids, host->dev); | |
1366 | int buswidth; | |
1367 | ||
1368 | if (!np) | |
1369 | return 1; | |
1370 | ||
1371 | if (of_get_nand_ecc_mode(np) >= 0) | |
1372 | pdata->hw_ecc = 1; | |
1373 | ||
1374 | pdata->flash_bbt = of_get_nand_on_flash_bbt(np); | |
1375 | ||
1376 | buswidth = of_get_nand_bus_width(np); | |
1377 | if (buswidth < 0) | |
1378 | return buswidth; | |
1379 | ||
1380 | pdata->width = buswidth / 8; | |
1381 | ||
1382 | host->devtype_data = of_id->data; | |
1383 | ||
1384 | return 0; | |
1385 | } | |
1386 | #else | |
1387 | static int __init mxcnd_probe_dt(struct mxc_nand_host *host) | |
1388 | { | |
1389 | return 1; | |
1390 | } | |
1391 | #endif | |
1392 | ||
06f25510 | 1393 | static int mxcnd_probe(struct platform_device *pdev) |
34f6e157 SH |
1394 | { |
1395 | struct nand_chip *this; | |
1396 | struct mtd_info *mtd; | |
34f6e157 SH |
1397 | struct mxc_nand_host *host; |
1398 | struct resource *res; | |
d4ed8f12 | 1399 | int err = 0; |
34f6e157 SH |
1400 | |
1401 | /* Allocate memory for MTD device structure and private data */ | |
e4a09cbf SH |
1402 | host = devm_kzalloc(&pdev->dev, sizeof(struct mxc_nand_host) + |
1403 | NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE, GFP_KERNEL); | |
34f6e157 SH |
1404 | if (!host) |
1405 | return -ENOMEM; | |
1406 | ||
f8f9608d | 1407 | host->data_buf = (uint8_t *)(host + 1); |
f8f9608d | 1408 | |
34f6e157 SH |
1409 | host->dev = &pdev->dev; |
1410 | /* structures must be linked */ | |
1411 | this = &host->nand; | |
1412 | mtd = &host->mtd; | |
1413 | mtd->priv = this; | |
1414 | mtd->owner = THIS_MODULE; | |
87f39f04 | 1415 | mtd->dev.parent = &pdev->dev; |
1fbff0a6 | 1416 | mtd->name = DRIVER_NAME; |
34f6e157 SH |
1417 | |
1418 | /* 50 us command delay time */ | |
1419 | this->chip_delay = 5; | |
1420 | ||
1421 | this->priv = host; | |
1422 | this->dev_ready = mxc_nand_dev_ready; | |
1423 | this->cmdfunc = mxc_nand_command; | |
34f6e157 SH |
1424 | this->read_byte = mxc_nand_read_byte; |
1425 | this->read_word = mxc_nand_read_word; | |
1426 | this->write_buf = mxc_nand_write_buf; | |
1427 | this->read_buf = mxc_nand_read_buf; | |
34f6e157 | 1428 | |
24b82d3c | 1429 | host->clk = devm_clk_get(&pdev->dev, NULL); |
e4a09cbf SH |
1430 | if (IS_ERR(host->clk)) |
1431 | return PTR_ERR(host->clk); | |
34f6e157 | 1432 | |
71885b65 | 1433 | err = mxcnd_probe_dt(host); |
4d62435f | 1434 | if (err > 0) { |
453810b7 JH |
1435 | struct mxc_nand_platform_data *pdata = |
1436 | dev_get_platdata(&pdev->dev); | |
4d62435f SG |
1437 | if (pdata) { |
1438 | host->pdata = *pdata; | |
1439 | host->devtype_data = (struct mxc_nand_devtype_data *) | |
1440 | pdev->id_entry->driver_data; | |
1441 | } else { | |
1442 | err = -ENODEV; | |
1443 | } | |
1444 | } | |
71885b65 SH |
1445 | if (err < 0) |
1446 | return err; | |
1447 | ||
1448 | if (host->devtype_data->needs_ip) { | |
1449 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
b0de774c TR |
1450 | host->regs_ip = devm_ioremap_resource(&pdev->dev, res); |
1451 | if (IS_ERR(host->regs_ip)) | |
1452 | return PTR_ERR(host->regs_ip); | |
71885b65 SH |
1453 | |
1454 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1455 | } else { | |
1456 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1457 | } | |
1458 | ||
b0de774c TR |
1459 | host->base = devm_ioremap_resource(&pdev->dev, res); |
1460 | if (IS_ERR(host->base)) | |
1461 | return PTR_ERR(host->base); | |
34f6e157 | 1462 | |
c6de7e1b | 1463 | host->main_area0 = host->base; |
9467114e | 1464 | |
f48d0f9a UKK |
1465 | if (host->devtype_data->regs_offset) |
1466 | host->regs = host->base + host->devtype_data->regs_offset; | |
1467 | host->spare0 = host->base + host->devtype_data->spare0_offset; | |
1468 | if (host->devtype_data->axi_offset) | |
1469 | host->regs_axi = host->base + host->devtype_data->axi_offset; | |
1470 | ||
1471 | this->ecc.bytes = host->devtype_data->eccbytes; | |
1472 | host->eccsize = host->devtype_data->eccsize; | |
1473 | ||
1474 | this->select_chip = host->devtype_data->select_chip; | |
1475 | this->ecc.size = 512; | |
1476 | this->ecc.layout = host->devtype_data->ecclayout_512; | |
1477 | ||
6436356b | 1478 | if (host->pdata.hw_ecc) { |
34f6e157 SH |
1479 | this->ecc.calculate = mxc_nand_calculate_ecc; |
1480 | this->ecc.hwctl = mxc_nand_enable_hwecc; | |
69d023be | 1481 | this->ecc.correct = host->devtype_data->correct_data; |
34f6e157 | 1482 | this->ecc.mode = NAND_ECC_HW; |
34f6e157 | 1483 | } else { |
34f6e157 | 1484 | this->ecc.mode = NAND_ECC_SOFT; |
34f6e157 SH |
1485 | } |
1486 | ||
6436356b UKK |
1487 | /* NAND bus width determines access functions used by upper layer */ |
1488 | if (host->pdata.width == 2) | |
34f6e157 | 1489 | this->options |= NAND_BUSWIDTH_16; |
34f6e157 | 1490 | |
6436356b | 1491 | if (host->pdata.flash_bbt) { |
f1372055 SH |
1492 | this->bbt_td = &bbt_main_descr; |
1493 | this->bbt_md = &bbt_mirror_descr; | |
1494 | /* update flash based bbt */ | |
bb9ebd4e | 1495 | this->bbt_options |= NAND_BBT_USE_FLASH; |
34f6e157 SH |
1496 | } |
1497 | ||
63f1474c | 1498 | init_completion(&host->op_completion); |
d4840180 IC |
1499 | |
1500 | host->irq = platform_get_irq(pdev, 0); | |
1501 | ||
63f1474c | 1502 | /* |
e4303b25 UKK |
1503 | * Use host->devtype_data->irq_control() here instead of irq_control() |
1504 | * because we must not disable_irq_nosync without having requested the | |
1505 | * irq. | |
63f1474c | 1506 | */ |
e4303b25 | 1507 | host->devtype_data->irq_control(host, 0); |
63f1474c | 1508 | |
e4a09cbf SH |
1509 | err = devm_request_irq(&pdev->dev, host->irq, mxc_nfc_irq, |
1510 | IRQF_DISABLED, DRIVER_NAME, host); | |
d4840180 | 1511 | if (err) |
e4a09cbf SH |
1512 | return err; |
1513 | ||
1514 | clk_prepare_enable(host->clk); | |
1515 | host->clk_act = 1; | |
d4840180 | 1516 | |
63f1474c | 1517 | /* |
8556958a UKK |
1518 | * Now that we "own" the interrupt make sure the interrupt mask bit is |
1519 | * cleared on i.MX21. Otherwise we can't read the interrupt status bit | |
1520 | * on this machine. | |
63f1474c | 1521 | */ |
f48d0f9a | 1522 | if (host->devtype_data->irqpending_quirk) { |
8556958a | 1523 | disable_irq_nosync(host->irq); |
e4303b25 | 1524 | host->devtype_data->irq_control(host, 1); |
8556958a | 1525 | } |
63f1474c | 1526 | |
bd3fd62e | 1527 | /* first scan to find the device and get the page size */ |
4d62435f | 1528 | if (nand_scan_ident(mtd, is_imx25_nfc(host) ? 4 : 1, NULL)) { |
bd3fd62e VB |
1529 | err = -ENXIO; |
1530 | goto escan; | |
1531 | } | |
34f6e157 | 1532 | |
6e85dfdc | 1533 | /* Call preset again, with correct writesize this time */ |
e4303b25 | 1534 | host->devtype_data->preset(mtd); |
6e85dfdc | 1535 | |
2d69c7fa | 1536 | if (mtd->writesize == 2048) |
6dcdf99d UKK |
1537 | this->ecc.layout = host->devtype_data->ecclayout_2k; |
1538 | else if (mtd->writesize == 4096) | |
1539 | this->ecc.layout = host->devtype_data->ecclayout_4k; | |
34f6e157 | 1540 | |
6a918bad | 1541 | if (this->ecc.mode == NAND_ECC_HW) { |
4d62435f | 1542 | if (is_imx21_nfc(host) || is_imx27_nfc(host)) |
6a918bad MD |
1543 | this->ecc.strength = 1; |
1544 | else | |
1545 | this->ecc.strength = (host->eccsize == 4) ? 4 : 8; | |
1546 | } | |
1547 | ||
4a43faf5 SH |
1548 | /* second phase scan */ |
1549 | if (nand_scan_tail(mtd)) { | |
1550 | err = -ENXIO; | |
1551 | goto escan; | |
1552 | } | |
1553 | ||
34f6e157 | 1554 | /* Register the partitions */ |
6436356b UKK |
1555 | mtd_device_parse_register(mtd, part_probes, |
1556 | &(struct mtd_part_parser_data){ | |
1557 | .of_node = pdev->dev.of_node, | |
1558 | }, | |
1559 | host->pdata.parts, | |
1560 | host->pdata.nr_parts); | |
34f6e157 SH |
1561 | |
1562 | platform_set_drvdata(pdev, host); | |
1563 | ||
1564 | return 0; | |
1565 | ||
1566 | escan: | |
c10d8ee3 LW |
1567 | if (host->clk_act) |
1568 | clk_disable_unprepare(host->clk); | |
34f6e157 SH |
1569 | |
1570 | return err; | |
1571 | } | |
1572 | ||
810b7e06 | 1573 | static int mxcnd_remove(struct platform_device *pdev) |
34f6e157 SH |
1574 | { |
1575 | struct mxc_nand_host *host = platform_get_drvdata(pdev); | |
1576 | ||
34f6e157 | 1577 | nand_release(&host->mtd); |
34f6e157 SH |
1578 | |
1579 | return 0; | |
1580 | } | |
1581 | ||
34f6e157 SH |
1582 | static struct platform_driver mxcnd_driver = { |
1583 | .driver = { | |
1584 | .name = DRIVER_NAME, | |
8d1fd16d | 1585 | .owner = THIS_MODULE, |
6436356b | 1586 | .of_match_table = of_match_ptr(mxcnd_dt_ids), |
04dd0d3a | 1587 | }, |
4d62435f | 1588 | .id_table = mxcnd_devtype, |
ddf16d62 | 1589 | .probe = mxcnd_probe, |
5153b88c | 1590 | .remove = mxcnd_remove, |
34f6e157 | 1591 | }; |
ddf16d62 | 1592 | module_platform_driver(mxcnd_driver); |
34f6e157 SH |
1593 | |
1594 | MODULE_AUTHOR("Freescale Semiconductor, Inc."); | |
1595 | MODULE_DESCRIPTION("MXC NAND MTD driver"); | |
1596 | MODULE_LICENSE("GPL"); |