Commit | Line | Data |
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34f6e157 SH |
1 | /* |
2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * Copyright 2008 Sascha Hauer, kernel@pengutronix.de | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
17 | * MA 02110-1301, USA. | |
18 | */ | |
19 | ||
20 | #include <linux/delay.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/mtd/mtd.h> | |
25 | #include <linux/mtd/nand.h> | |
26 | #include <linux/mtd/partitions.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/device.h> | |
29 | #include <linux/platform_device.h> | |
30 | #include <linux/clk.h> | |
31 | #include <linux/err.h> | |
32 | #include <linux/io.h> | |
63f1474c SH |
33 | #include <linux/irq.h> |
34 | #include <linux/completion.h> | |
d367e37e | 35 | #include <linux/of.h> |
6436356b UKK |
36 | #include <linux/of_device.h> |
37 | #include <linux/of_mtd.h> | |
34f6e157 SH |
38 | |
39 | #include <asm/mach/flash.h> | |
82906b13 | 40 | #include <linux/platform_data/mtd-mxc_nand.h> |
34f6e157 SH |
41 | |
42 | #define DRIVER_NAME "mxc_nand" | |
43 | ||
44 | /* Addresses for NFC registers */ | |
1bc99180 SH |
45 | #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00) |
46 | #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04) | |
47 | #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06) | |
48 | #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08) | |
49 | #define NFC_V1_V2_CONFIG (host->regs + 0x0a) | |
50 | #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c) | |
51 | #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e) | |
52 | #define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10) | |
53 | #define NFC_V1_V2_WRPROT (host->regs + 0x12) | |
54 | #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14) | |
55 | #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16) | |
d178e3e8 BS |
56 | #define NFC_V21_UNLOCKSTART_BLKADDR0 (host->regs + 0x20) |
57 | #define NFC_V21_UNLOCKSTART_BLKADDR1 (host->regs + 0x24) | |
58 | #define NFC_V21_UNLOCKSTART_BLKADDR2 (host->regs + 0x28) | |
59 | #define NFC_V21_UNLOCKSTART_BLKADDR3 (host->regs + 0x2c) | |
60 | #define NFC_V21_UNLOCKEND_BLKADDR0 (host->regs + 0x22) | |
61 | #define NFC_V21_UNLOCKEND_BLKADDR1 (host->regs + 0x26) | |
62 | #define NFC_V21_UNLOCKEND_BLKADDR2 (host->regs + 0x2a) | |
63 | #define NFC_V21_UNLOCKEND_BLKADDR3 (host->regs + 0x2e) | |
1bc99180 SH |
64 | #define NFC_V1_V2_NF_WRPRST (host->regs + 0x18) |
65 | #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a) | |
66 | #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c) | |
67 | ||
6e85dfdc | 68 | #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0) |
1bc99180 SH |
69 | #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2) |
70 | #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3) | |
71 | #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4) | |
72 | #define NFC_V1_V2_CONFIG1_BIG (1 << 5) | |
73 | #define NFC_V1_V2_CONFIG1_RST (1 << 6) | |
74 | #define NFC_V1_V2_CONFIG1_CE (1 << 7) | |
b8db2f51 SH |
75 | #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8) |
76 | #define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9) | |
77 | #define NFC_V2_CONFIG1_FP_INT (1 << 11) | |
1bc99180 SH |
78 | |
79 | #define NFC_V1_V2_CONFIG2_INT (1 << 15) | |
80 | ||
81 | /* | |
82 | * Operation modes for the NFC. Valid for v1, v2 and v3 | |
83 | * type controllers. | |
84 | */ | |
85 | #define NFC_CMD (1 << 0) | |
86 | #define NFC_ADDR (1 << 1) | |
87 | #define NFC_INPUT (1 << 2) | |
88 | #define NFC_OUTPUT (1 << 3) | |
89 | #define NFC_ID (1 << 4) | |
90 | #define NFC_STATUS (1 << 5) | |
34f6e157 | 91 | |
71ec5155 SH |
92 | #define NFC_V3_FLASH_CMD (host->regs_axi + 0x00) |
93 | #define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04) | |
94 | ||
95 | #define NFC_V3_CONFIG1 (host->regs_axi + 0x34) | |
96 | #define NFC_V3_CONFIG1_SP_EN (1 << 0) | |
97 | #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4) | |
98 | ||
99 | #define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38) | |
100 | ||
101 | #define NFC_V3_LAUNCH (host->regs_axi + 0x40) | |
102 | ||
103 | #define NFC_V3_WRPROT (host->regs_ip + 0x0) | |
104 | #define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0) | |
105 | #define NFC_V3_WRPROT_LOCK (1 << 1) | |
106 | #define NFC_V3_WRPROT_UNLOCK (1 << 2) | |
107 | #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6) | |
108 | ||
109 | #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04) | |
110 | ||
111 | #define NFC_V3_CONFIG2 (host->regs_ip + 0x24) | |
112 | #define NFC_V3_CONFIG2_PS_512 (0 << 0) | |
113 | #define NFC_V3_CONFIG2_PS_2048 (1 << 0) | |
114 | #define NFC_V3_CONFIG2_PS_4096 (2 << 0) | |
115 | #define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2) | |
116 | #define NFC_V3_CONFIG2_ECC_EN (1 << 3) | |
117 | #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4) | |
118 | #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5) | |
119 | #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6) | |
71718a8e | 120 | #define NFC_V3_CONFIG2_PPB(x, shift) (((x) & 0x3) << shift) |
71ec5155 SH |
121 | #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12) |
122 | #define NFC_V3_CONFIG2_INT_MSK (1 << 15) | |
123 | #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24) | |
124 | #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16) | |
125 | ||
126 | #define NFC_V3_CONFIG3 (host->regs_ip + 0x28) | |
127 | #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0) | |
128 | #define NFC_V3_CONFIG3_FW8 (1 << 3) | |
129 | #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8) | |
130 | #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12) | |
131 | #define NFC_V3_CONFIG3_RBB_MODE (1 << 15) | |
132 | #define NFC_V3_CONFIG3_NO_SDMA (1 << 20) | |
133 | ||
134 | #define NFC_V3_IPC (host->regs_ip + 0x2C) | |
135 | #define NFC_V3_IPC_CREQ (1 << 0) | |
136 | #define NFC_V3_IPC_INT (1 << 31) | |
137 | ||
138 | #define NFC_V3_DELAY_LINE (host->regs_ip + 0x34) | |
34f6e157 | 139 | |
e4303b25 UKK |
140 | struct mxc_nand_host; |
141 | ||
142 | struct mxc_nand_devtype_data { | |
143 | void (*preset)(struct mtd_info *); | |
144 | void (*send_cmd)(struct mxc_nand_host *, uint16_t, int); | |
145 | void (*send_addr)(struct mxc_nand_host *, uint16_t, int); | |
146 | void (*send_page)(struct mtd_info *, unsigned int); | |
147 | void (*send_read_id)(struct mxc_nand_host *); | |
148 | uint16_t (*get_dev_status)(struct mxc_nand_host *); | |
149 | int (*check_int)(struct mxc_nand_host *); | |
150 | void (*irq_control)(struct mxc_nand_host *, int); | |
6d38af25 | 151 | u32 (*get_ecc_status)(struct mxc_nand_host *); |
6dcdf99d | 152 | struct nand_ecclayout *ecclayout_512, *ecclayout_2k, *ecclayout_4k; |
5e05a2d6 | 153 | void (*select_chip)(struct mtd_info *mtd, int chip); |
69d023be UKK |
154 | int (*correct_data)(struct mtd_info *mtd, u_char *dat, |
155 | u_char *read_ecc, u_char *calc_ecc); | |
f48d0f9a UKK |
156 | |
157 | /* | |
158 | * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked | |
159 | * (CONFIG1:INT_MSK is set). To handle this the driver uses | |
160 | * enable_irq/disable_irq_nosync instead of CONFIG1:INT_MSK | |
161 | */ | |
162 | int irqpending_quirk; | |
163 | int needs_ip; | |
164 | ||
165 | size_t regs_offset; | |
166 | size_t spare0_offset; | |
167 | size_t axi_offset; | |
168 | ||
169 | int spare_len; | |
170 | int eccbytes; | |
171 | int eccsize; | |
71718a8e | 172 | int ppb_shift; |
e4303b25 UKK |
173 | }; |
174 | ||
34f6e157 | 175 | struct mxc_nand_host { |
34f6e157 | 176 | struct nand_chip nand; |
34f6e157 SH |
177 | struct device *dev; |
178 | ||
4b6f05e1 UKK |
179 | void __iomem *spare0; |
180 | void __iomem *main_area0; | |
c6de7e1b SH |
181 | |
182 | void __iomem *base; | |
34f6e157 | 183 | void __iomem *regs; |
71ec5155 SH |
184 | void __iomem *regs_axi; |
185 | void __iomem *regs_ip; | |
34f6e157 | 186 | int status_request; |
34f6e157 SH |
187 | struct clk *clk; |
188 | int clk_act; | |
189 | int irq; | |
94f77e50 | 190 | int eccsize; |
7e7e4730 | 191 | int used_oobsize; |
d178e3e8 | 192 | int active_cs; |
34f6e157 | 193 | |
63f1474c | 194 | struct completion op_completion; |
34f6e157 | 195 | |
f8f9608d SH |
196 | uint8_t *data_buf; |
197 | unsigned int buf_start; | |
5f97304e | 198 | |
e4303b25 | 199 | const struct mxc_nand_devtype_data *devtype_data; |
6436356b | 200 | struct mxc_nand_platform_data pdata; |
34f6e157 SH |
201 | }; |
202 | ||
34f6e157 | 203 | /* OOB placement block for use with hardware ecc generation */ |
9467114e | 204 | static struct nand_ecclayout nandv1_hw_eccoob_smallpage = { |
34f6e157 SH |
205 | .eccbytes = 5, |
206 | .eccpos = {6, 7, 8, 9, 10}, | |
8c1fd89a | 207 | .oobfree = {{0, 5}, {12, 4}, } |
bd3fd62e VB |
208 | }; |
209 | ||
9467114e | 210 | static struct nand_ecclayout nandv1_hw_eccoob_largepage = { |
bd3fd62e VB |
211 | .eccbytes = 20, |
212 | .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26, | |
213 | 38, 39, 40, 41, 42, 54, 55, 56, 57, 58}, | |
214 | .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, } | |
34f6e157 SH |
215 | }; |
216 | ||
9467114e SH |
217 | /* OOB description for 512 byte pages with 16 byte OOB */ |
218 | static struct nand_ecclayout nandv2_hw_eccoob_smallpage = { | |
219 | .eccbytes = 1 * 9, | |
220 | .eccpos = { | |
221 | 7, 8, 9, 10, 11, 12, 13, 14, 15 | |
222 | }, | |
223 | .oobfree = { | |
224 | {.offset = 0, .length = 5} | |
225 | } | |
226 | }; | |
227 | ||
228 | /* OOB description for 2048 byte pages with 64 byte OOB */ | |
229 | static struct nand_ecclayout nandv2_hw_eccoob_largepage = { | |
230 | .eccbytes = 4 * 9, | |
231 | .eccpos = { | |
232 | 7, 8, 9, 10, 11, 12, 13, 14, 15, | |
233 | 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
234 | 39, 40, 41, 42, 43, 44, 45, 46, 47, | |
235 | 55, 56, 57, 58, 59, 60, 61, 62, 63 | |
236 | }, | |
237 | .oobfree = { | |
238 | {.offset = 2, .length = 4}, | |
239 | {.offset = 16, .length = 7}, | |
240 | {.offset = 32, .length = 7}, | |
241 | {.offset = 48, .length = 7} | |
242 | } | |
243 | }; | |
244 | ||
2c1c5f19 BS |
245 | /* OOB description for 4096 byte pages with 128 byte OOB */ |
246 | static struct nand_ecclayout nandv2_hw_eccoob_4k = { | |
247 | .eccbytes = 8 * 9, | |
248 | .eccpos = { | |
249 | 7, 8, 9, 10, 11, 12, 13, 14, 15, | |
250 | 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
251 | 39, 40, 41, 42, 43, 44, 45, 46, 47, | |
252 | 55, 56, 57, 58, 59, 60, 61, 62, 63, | |
253 | 71, 72, 73, 74, 75, 76, 77, 78, 79, | |
254 | 87, 88, 89, 90, 91, 92, 93, 94, 95, | |
255 | 103, 104, 105, 106, 107, 108, 109, 110, 111, | |
256 | 119, 120, 121, 122, 123, 124, 125, 126, 127, | |
257 | }, | |
258 | .oobfree = { | |
259 | {.offset = 2, .length = 4}, | |
260 | {.offset = 16, .length = 7}, | |
261 | {.offset = 32, .length = 7}, | |
262 | {.offset = 48, .length = 7}, | |
263 | {.offset = 64, .length = 7}, | |
264 | {.offset = 80, .length = 7}, | |
265 | {.offset = 96, .length = 7}, | |
266 | {.offset = 112, .length = 7}, | |
267 | } | |
268 | }; | |
269 | ||
b2ac0376 | 270 | static const char * const part_probes[] = { |
740bb0c4 | 271 | "cmdlinepart", "RedBoot", "ofpart", NULL }; |
34f6e157 | 272 | |
096bcc23 SH |
273 | static void memcpy32_fromio(void *trg, const void __iomem *src, size_t size) |
274 | { | |
275 | int i; | |
276 | u32 *t = trg; | |
277 | const __iomem u32 *s = src; | |
278 | ||
279 | for (i = 0; i < (size >> 2); i++) | |
280 | *t++ = __raw_readl(s++); | |
281 | } | |
282 | ||
0d17fc3e BS |
283 | static void memcpy16_fromio(void *trg, const void __iomem *src, size_t size) |
284 | { | |
285 | int i; | |
286 | u16 *t = trg; | |
287 | const __iomem u16 *s = src; | |
288 | ||
289 | /* We assume that src (IO) is always 32bit aligned */ | |
290 | if (PTR_ALIGN(trg, 4) == trg && IS_ALIGNED(size, 4)) { | |
291 | memcpy32_fromio(trg, src, size); | |
292 | return; | |
293 | } | |
294 | ||
295 | for (i = 0; i < (size >> 1); i++) | |
296 | *t++ = __raw_readw(s++); | |
297 | } | |
298 | ||
33a87a15 | 299 | static inline void memcpy32_toio(void __iomem *trg, const void *src, int size) |
096bcc23 | 300 | { |
33a87a15 KV |
301 | /* __iowrite32_copy use 32bit size values so divide by 4 */ |
302 | __iowrite32_copy(trg, src, size / 4); | |
096bcc23 SH |
303 | } |
304 | ||
0d17fc3e BS |
305 | static void memcpy16_toio(void __iomem *trg, const void *src, int size) |
306 | { | |
307 | int i; | |
308 | __iomem u16 *t = trg; | |
309 | const u16 *s = src; | |
310 | ||
311 | /* We assume that trg (IO) is always 32bit aligned */ | |
312 | if (PTR_ALIGN(src, 4) == src && IS_ALIGNED(size, 4)) { | |
313 | memcpy32_toio(trg, src, size); | |
314 | return; | |
315 | } | |
316 | ||
317 | for (i = 0; i < (size >> 1); i++) | |
318 | __raw_writew(*s++, t++); | |
319 | } | |
320 | ||
71ec5155 SH |
321 | static int check_int_v3(struct mxc_nand_host *host) |
322 | { | |
323 | uint32_t tmp; | |
324 | ||
325 | tmp = readl(NFC_V3_IPC); | |
326 | if (!(tmp & NFC_V3_IPC_INT)) | |
327 | return 0; | |
328 | ||
329 | tmp &= ~NFC_V3_IPC_INT; | |
330 | writel(tmp, NFC_V3_IPC); | |
331 | ||
332 | return 1; | |
333 | } | |
334 | ||
7aaf28ac SH |
335 | static int check_int_v1_v2(struct mxc_nand_host *host) |
336 | { | |
337 | uint32_t tmp; | |
338 | ||
1bc99180 SH |
339 | tmp = readw(NFC_V1_V2_CONFIG2); |
340 | if (!(tmp & NFC_V1_V2_CONFIG2_INT)) | |
7aaf28ac SH |
341 | return 0; |
342 | ||
f48d0f9a | 343 | if (!host->devtype_data->irqpending_quirk) |
63f1474c | 344 | writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2); |
7aaf28ac SH |
345 | |
346 | return 1; | |
347 | } | |
348 | ||
63f1474c SH |
349 | static void irq_control_v1_v2(struct mxc_nand_host *host, int activate) |
350 | { | |
351 | uint16_t tmp; | |
352 | ||
353 | tmp = readw(NFC_V1_V2_CONFIG1); | |
354 | ||
355 | if (activate) | |
356 | tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK; | |
357 | else | |
358 | tmp |= NFC_V1_V2_CONFIG1_INT_MSK; | |
359 | ||
360 | writew(tmp, NFC_V1_V2_CONFIG1); | |
361 | } | |
362 | ||
363 | static void irq_control_v3(struct mxc_nand_host *host, int activate) | |
364 | { | |
365 | uint32_t tmp; | |
366 | ||
367 | tmp = readl(NFC_V3_CONFIG2); | |
368 | ||
369 | if (activate) | |
370 | tmp &= ~NFC_V3_CONFIG2_INT_MSK; | |
371 | else | |
372 | tmp |= NFC_V3_CONFIG2_INT_MSK; | |
373 | ||
374 | writel(tmp, NFC_V3_CONFIG2); | |
375 | } | |
376 | ||
8556958a UKK |
377 | static void irq_control(struct mxc_nand_host *host, int activate) |
378 | { | |
f48d0f9a | 379 | if (host->devtype_data->irqpending_quirk) { |
8556958a UKK |
380 | if (activate) |
381 | enable_irq(host->irq); | |
382 | else | |
383 | disable_irq_nosync(host->irq); | |
384 | } else { | |
e4303b25 | 385 | host->devtype_data->irq_control(host, activate); |
8556958a UKK |
386 | } |
387 | } | |
388 | ||
6d38af25 UKK |
389 | static u32 get_ecc_status_v1(struct mxc_nand_host *host) |
390 | { | |
391 | return readw(NFC_V1_V2_ECC_STATUS_RESULT); | |
392 | } | |
393 | ||
394 | static u32 get_ecc_status_v2(struct mxc_nand_host *host) | |
395 | { | |
396 | return readl(NFC_V1_V2_ECC_STATUS_RESULT); | |
397 | } | |
398 | ||
399 | static u32 get_ecc_status_v3(struct mxc_nand_host *host) | |
400 | { | |
401 | return readl(NFC_V3_ECC_STATUS_RESULT); | |
402 | } | |
403 | ||
8556958a UKK |
404 | static irqreturn_t mxc_nfc_irq(int irq, void *dev_id) |
405 | { | |
406 | struct mxc_nand_host *host = dev_id; | |
407 | ||
e4303b25 | 408 | if (!host->devtype_data->check_int(host)) |
8556958a UKK |
409 | return IRQ_NONE; |
410 | ||
411 | irq_control(host, 0); | |
412 | ||
413 | complete(&host->op_completion); | |
414 | ||
415 | return IRQ_HANDLED; | |
416 | } | |
417 | ||
34f6e157 SH |
418 | /* This function polls the NANDFC to wait for the basic operation to |
419 | * complete by checking the INT bit of config2 register. | |
420 | */ | |
e35d1d8a | 421 | static int wait_op_done(struct mxc_nand_host *host, int useirq) |
34f6e157 | 422 | { |
e35d1d8a UKK |
423 | int ret = 0; |
424 | ||
425 | /* | |
426 | * If operation is already complete, don't bother to setup an irq or a | |
427 | * loop. | |
428 | */ | |
429 | if (host->devtype_data->check_int(host)) | |
430 | return 0; | |
34f6e157 SH |
431 | |
432 | if (useirq) { | |
e35d1d8a UKK |
433 | unsigned long timeout; |
434 | ||
435 | reinit_completion(&host->op_completion); | |
436 | ||
437 | irq_control(host, 1); | |
438 | ||
439 | timeout = wait_for_completion_timeout(&host->op_completion, HZ); | |
440 | if (!timeout && !host->devtype_data->check_int(host)) { | |
441 | dev_dbg(host->dev, "timeout waiting for irq\n"); | |
442 | ret = -ETIMEDOUT; | |
34f6e157 SH |
443 | } |
444 | } else { | |
e35d1d8a UKK |
445 | int max_retries = 8000; |
446 | int done; | |
7aaf28ac | 447 | |
e35d1d8a | 448 | do { |
34f6e157 | 449 | udelay(1); |
e35d1d8a UKK |
450 | |
451 | done = host->devtype_data->check_int(host); | |
452 | if (done) | |
453 | break; | |
454 | ||
455 | } while (--max_retries); | |
456 | ||
457 | if (!done) { | |
458 | dev_dbg(host->dev, "timeout polling for completion\n"); | |
459 | ret = -ETIMEDOUT; | |
34f6e157 | 460 | } |
34f6e157 | 461 | } |
e35d1d8a UKK |
462 | |
463 | WARN_ONCE(ret < 0, "timeout! useirq=%d\n", useirq); | |
464 | ||
465 | return ret; | |
34f6e157 SH |
466 | } |
467 | ||
71ec5155 SH |
468 | static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq) |
469 | { | |
470 | /* fill command */ | |
471 | writel(cmd, NFC_V3_FLASH_CMD); | |
472 | ||
473 | /* send out command */ | |
474 | writel(NFC_CMD, NFC_V3_LAUNCH); | |
475 | ||
476 | /* Wait for operation to complete */ | |
477 | wait_op_done(host, useirq); | |
478 | } | |
479 | ||
34f6e157 SH |
480 | /* This function issues the specified command to the NAND device and |
481 | * waits for completion. */ | |
5f97304e | 482 | static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq) |
34f6e157 | 483 | { |
289c0522 | 484 | pr_debug("send_cmd(host, 0x%x, %d)\n", cmd, useirq); |
34f6e157 | 485 | |
1bc99180 SH |
486 | writew(cmd, NFC_V1_V2_FLASH_CMD); |
487 | writew(NFC_CMD, NFC_V1_V2_CONFIG2); | |
34f6e157 | 488 | |
f48d0f9a | 489 | if (host->devtype_data->irqpending_quirk && (cmd == NAND_CMD_RESET)) { |
a47bfd2e IC |
490 | int max_retries = 100; |
491 | /* Reset completion is indicated by NFC_CONFIG2 */ | |
492 | /* being set to 0 */ | |
493 | while (max_retries-- > 0) { | |
1bc99180 | 494 | if (readw(NFC_V1_V2_CONFIG2) == 0) { |
a47bfd2e IC |
495 | break; |
496 | } | |
497 | udelay(1); | |
498 | } | |
499 | if (max_retries < 0) | |
0a32a102 | 500 | pr_debug("%s: RESET failed\n", __func__); |
a47bfd2e IC |
501 | } else { |
502 | /* Wait for operation to complete */ | |
503 | wait_op_done(host, useirq); | |
504 | } | |
34f6e157 SH |
505 | } |
506 | ||
71ec5155 SH |
507 | static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast) |
508 | { | |
509 | /* fill address */ | |
510 | writel(addr, NFC_V3_FLASH_ADDR0); | |
511 | ||
512 | /* send out address */ | |
513 | writel(NFC_ADDR, NFC_V3_LAUNCH); | |
514 | ||
515 | wait_op_done(host, 0); | |
516 | } | |
517 | ||
34f6e157 SH |
518 | /* This function sends an address (or partial address) to the |
519 | * NAND device. The address is used to select the source/destination for | |
520 | * a NAND command. */ | |
5f97304e | 521 | static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast) |
34f6e157 | 522 | { |
289c0522 | 523 | pr_debug("send_addr(host, 0x%x %d)\n", addr, islast); |
34f6e157 | 524 | |
1bc99180 SH |
525 | writew(addr, NFC_V1_V2_FLASH_ADDR); |
526 | writew(NFC_ADDR, NFC_V1_V2_CONFIG2); | |
34f6e157 SH |
527 | |
528 | /* Wait for operation to complete */ | |
c110eaf4 | 529 | wait_op_done(host, islast); |
34f6e157 SH |
530 | } |
531 | ||
71ec5155 SH |
532 | static void send_page_v3(struct mtd_info *mtd, unsigned int ops) |
533 | { | |
4bd4ebcc | 534 | struct nand_chip *nand_chip = mtd_to_nand(mtd); |
d699ed25 | 535 | struct mxc_nand_host *host = nand_get_controller_data(nand_chip); |
71ec5155 SH |
536 | uint32_t tmp; |
537 | ||
538 | tmp = readl(NFC_V3_CONFIG1); | |
539 | tmp &= ~(7 << 4); | |
540 | writel(tmp, NFC_V3_CONFIG1); | |
541 | ||
542 | /* transfer data from NFC ram to nand */ | |
543 | writel(ops, NFC_V3_LAUNCH); | |
544 | ||
545 | wait_op_done(host, false); | |
546 | } | |
547 | ||
6d38af25 UKK |
548 | static void send_page_v2(struct mtd_info *mtd, unsigned int ops) |
549 | { | |
4bd4ebcc | 550 | struct nand_chip *nand_chip = mtd_to_nand(mtd); |
d699ed25 | 551 | struct mxc_nand_host *host = nand_get_controller_data(nand_chip); |
6d38af25 UKK |
552 | |
553 | /* NANDFC buffer 0 is used for page read/write */ | |
554 | writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR); | |
555 | ||
556 | writew(ops, NFC_V1_V2_CONFIG2); | |
557 | ||
558 | /* Wait for operation to complete */ | |
559 | wait_op_done(host, true); | |
560 | } | |
561 | ||
562 | static void send_page_v1(struct mtd_info *mtd, unsigned int ops) | |
34f6e157 | 563 | { |
4bd4ebcc | 564 | struct nand_chip *nand_chip = mtd_to_nand(mtd); |
d699ed25 | 565 | struct mxc_nand_host *host = nand_get_controller_data(nand_chip); |
c5d23f1b | 566 | int bufs, i; |
34f6e157 | 567 | |
6d38af25 | 568 | if (mtd->writesize > 512) |
c5d23f1b SH |
569 | bufs = 4; |
570 | else | |
571 | bufs = 1; | |
34f6e157 | 572 | |
c5d23f1b | 573 | for (i = 0; i < bufs; i++) { |
34f6e157 | 574 | |
c5d23f1b | 575 | /* NANDFC buffer 0 is used for page read/write */ |
d178e3e8 | 576 | writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR); |
34f6e157 | 577 | |
1bc99180 | 578 | writew(ops, NFC_V1_V2_CONFIG2); |
34f6e157 | 579 | |
c5d23f1b | 580 | /* Wait for operation to complete */ |
c110eaf4 | 581 | wait_op_done(host, true); |
34f6e157 | 582 | } |
34f6e157 SH |
583 | } |
584 | ||
71ec5155 SH |
585 | static void send_read_id_v3(struct mxc_nand_host *host) |
586 | { | |
587 | /* Read ID into main buffer */ | |
588 | writel(NFC_ID, NFC_V3_LAUNCH); | |
589 | ||
590 | wait_op_done(host, true); | |
591 | ||
096bcc23 | 592 | memcpy32_fromio(host->data_buf, host->main_area0, 16); |
71ec5155 SH |
593 | } |
594 | ||
34f6e157 | 595 | /* Request the NANDFC to perform a read of the NAND device ID. */ |
5f97304e | 596 | static void send_read_id_v1_v2(struct mxc_nand_host *host) |
34f6e157 | 597 | { |
34f6e157 | 598 | /* NANDFC buffer 0 is used for device ID output */ |
d178e3e8 | 599 | writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR); |
34f6e157 | 600 | |
1bc99180 | 601 | writew(NFC_ID, NFC_V1_V2_CONFIG2); |
34f6e157 SH |
602 | |
603 | /* Wait for operation to complete */ | |
c110eaf4 | 604 | wait_op_done(host, true); |
34f6e157 | 605 | |
096bcc23 | 606 | memcpy32_fromio(host->data_buf, host->main_area0, 16); |
34f6e157 SH |
607 | } |
608 | ||
71ec5155 SH |
609 | static uint16_t get_dev_status_v3(struct mxc_nand_host *host) |
610 | { | |
611 | writew(NFC_STATUS, NFC_V3_LAUNCH); | |
612 | wait_op_done(host, true); | |
613 | ||
614 | return readl(NFC_V3_CONFIG1) >> 16; | |
615 | } | |
616 | ||
34f6e157 SH |
617 | /* This function requests the NANDFC to perform a read of the |
618 | * NAND device status and returns the current status. */ | |
5f97304e | 619 | static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host) |
34f6e157 | 620 | { |
c29c607a | 621 | void __iomem *main_buf = host->main_area0; |
34f6e157 | 622 | uint32_t store; |
f06368f7 | 623 | uint16_t ret; |
34f6e157 | 624 | |
d178e3e8 | 625 | writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR); |
34f6e157 | 626 | |
c29c607a SH |
627 | /* |
628 | * The device status is stored in main_area0. To | |
629 | * prevent corruption of the buffer save the value | |
630 | * and restore it afterwards. | |
631 | */ | |
34f6e157 | 632 | store = readl(main_buf); |
34f6e157 | 633 | |
1bc99180 | 634 | writew(NFC_STATUS, NFC_V1_V2_CONFIG2); |
c110eaf4 | 635 | wait_op_done(host, true); |
34f6e157 | 636 | |
34f6e157 | 637 | ret = readw(main_buf); |
c29c607a | 638 | |
34f6e157 SH |
639 | writel(store, main_buf); |
640 | ||
641 | return ret; | |
642 | } | |
643 | ||
644 | /* This functions is used by upper layer to checks if device is ready */ | |
645 | static int mxc_nand_dev_ready(struct mtd_info *mtd) | |
646 | { | |
647 | /* | |
648 | * NFC handles R/B internally. Therefore, this function | |
649 | * always returns status as ready. | |
650 | */ | |
651 | return 1; | |
652 | } | |
653 | ||
654 | static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode) | |
655 | { | |
656 | /* | |
657 | * If HW ECC is enabled, we turn it on during init. There is | |
658 | * no need to enable again here. | |
659 | */ | |
660 | } | |
661 | ||
94f77e50 | 662 | static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat, |
34f6e157 SH |
663 | u_char *read_ecc, u_char *calc_ecc) |
664 | { | |
4bd4ebcc | 665 | struct nand_chip *nand_chip = mtd_to_nand(mtd); |
d699ed25 | 666 | struct mxc_nand_host *host = nand_get_controller_data(nand_chip); |
34f6e157 SH |
667 | |
668 | /* | |
669 | * 1-Bit errors are automatically corrected in HW. No need for | |
670 | * additional correction. 2-Bit errors cannot be corrected by | |
671 | * HW ECC, so we need to return failure | |
672 | */ | |
6d38af25 | 673 | uint16_t ecc_status = get_ecc_status_v1(host); |
34f6e157 SH |
674 | |
675 | if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) { | |
289c0522 | 676 | pr_debug("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n"); |
6e941192 | 677 | return -EBADMSG; |
34f6e157 SH |
678 | } |
679 | ||
680 | return 0; | |
681 | } | |
682 | ||
94f77e50 SH |
683 | static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat, |
684 | u_char *read_ecc, u_char *calc_ecc) | |
685 | { | |
4bd4ebcc | 686 | struct nand_chip *nand_chip = mtd_to_nand(mtd); |
d699ed25 | 687 | struct mxc_nand_host *host = nand_get_controller_data(nand_chip); |
94f77e50 SH |
688 | u32 ecc_stat, err; |
689 | int no_subpages = 1; | |
690 | int ret = 0; | |
691 | u8 ecc_bit_mask, err_limit; | |
692 | ||
693 | ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf; | |
694 | err_limit = (host->eccsize == 4) ? 0x4 : 0x8; | |
695 | ||
696 | no_subpages = mtd->writesize >> 9; | |
697 | ||
6d38af25 | 698 | ecc_stat = host->devtype_data->get_ecc_status(host); |
94f77e50 SH |
699 | |
700 | do { | |
701 | err = ecc_stat & ecc_bit_mask; | |
702 | if (err > err_limit) { | |
703 | printk(KERN_WARNING "UnCorrectable RS-ECC Error\n"); | |
6e941192 | 704 | return -EBADMSG; |
94f77e50 SH |
705 | } else { |
706 | ret += err; | |
707 | } | |
708 | ecc_stat >>= 4; | |
709 | } while (--no_subpages); | |
710 | ||
94f77e50 SH |
711 | pr_debug("%d Symbol Correctable RS-ECC Error\n", ret); |
712 | ||
713 | return ret; | |
714 | } | |
715 | ||
34f6e157 SH |
716 | static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, |
717 | u_char *ecc_code) | |
718 | { | |
719 | return 0; | |
720 | } | |
721 | ||
722 | static u_char mxc_nand_read_byte(struct mtd_info *mtd) | |
723 | { | |
4bd4ebcc | 724 | struct nand_chip *nand_chip = mtd_to_nand(mtd); |
d699ed25 | 725 | struct mxc_nand_host *host = nand_get_controller_data(nand_chip); |
f8f9608d | 726 | uint8_t ret; |
34f6e157 SH |
727 | |
728 | /* Check for status request */ | |
729 | if (host->status_request) | |
e4303b25 | 730 | return host->devtype_data->get_dev_status(host) & 0xFF; |
34f6e157 | 731 | |
3f410690 UKK |
732 | if (nand_chip->options & NAND_BUSWIDTH_16) { |
733 | /* only take the lower byte of each word */ | |
734 | ret = *(uint16_t *)(host->data_buf + host->buf_start); | |
735 | ||
736 | host->buf_start += 2; | |
737 | } else { | |
738 | ret = *(uint8_t *)(host->data_buf + host->buf_start); | |
739 | host->buf_start++; | |
740 | } | |
34f6e157 | 741 | |
3f410690 | 742 | pr_debug("%s: ret=0x%hhx (start=%u)\n", __func__, ret, host->buf_start); |
34f6e157 SH |
743 | return ret; |
744 | } | |
745 | ||
746 | static uint16_t mxc_nand_read_word(struct mtd_info *mtd) | |
747 | { | |
4bd4ebcc | 748 | struct nand_chip *nand_chip = mtd_to_nand(mtd); |
d699ed25 | 749 | struct mxc_nand_host *host = nand_get_controller_data(nand_chip); |
f8f9608d | 750 | uint16_t ret; |
34f6e157 | 751 | |
f8f9608d SH |
752 | ret = *(uint16_t *)(host->data_buf + host->buf_start); |
753 | host->buf_start += 2; | |
34f6e157 SH |
754 | |
755 | return ret; | |
756 | } | |
757 | ||
758 | /* Write data of length len to buffer buf. The data to be | |
759 | * written on NAND Flash is first copied to RAMbuffer. After the Data Input | |
760 | * Operation by the NFC, the data is written to NAND Flash */ | |
761 | static void mxc_nand_write_buf(struct mtd_info *mtd, | |
762 | const u_char *buf, int len) | |
763 | { | |
4bd4ebcc | 764 | struct nand_chip *nand_chip = mtd_to_nand(mtd); |
d699ed25 | 765 | struct mxc_nand_host *host = nand_get_controller_data(nand_chip); |
f8f9608d SH |
766 | u16 col = host->buf_start; |
767 | int n = mtd->oobsize + mtd->writesize - col; | |
34f6e157 | 768 | |
f8f9608d | 769 | n = min(n, len); |
34f6e157 | 770 | |
f8f9608d | 771 | memcpy(host->data_buf + col, buf, n); |
34f6e157 | 772 | |
f8f9608d | 773 | host->buf_start += n; |
34f6e157 SH |
774 | } |
775 | ||
776 | /* Read the data buffer from the NAND Flash. To read the data from NAND | |
777 | * Flash first the data output cycle is initiated by the NFC, which copies | |
778 | * the data to RAMbuffer. This data of length len is then copied to buffer buf. | |
779 | */ | |
780 | static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) | |
781 | { | |
4bd4ebcc | 782 | struct nand_chip *nand_chip = mtd_to_nand(mtd); |
d699ed25 | 783 | struct mxc_nand_host *host = nand_get_controller_data(nand_chip); |
f8f9608d SH |
784 | u16 col = host->buf_start; |
785 | int n = mtd->oobsize + mtd->writesize - col; | |
34f6e157 | 786 | |
f8f9608d | 787 | n = min(n, len); |
34f6e157 | 788 | |
5d9d9936 | 789 | memcpy(buf, host->data_buf + col, n); |
34f6e157 | 790 | |
5d9d9936 | 791 | host->buf_start += n; |
34f6e157 SH |
792 | } |
793 | ||
34f6e157 SH |
794 | /* This function is used by upper layer for select and |
795 | * deselect of the NAND chip */ | |
5e05a2d6 | 796 | static void mxc_nand_select_chip_v1_v3(struct mtd_info *mtd, int chip) |
34f6e157 | 797 | { |
4bd4ebcc | 798 | struct nand_chip *nand_chip = mtd_to_nand(mtd); |
d699ed25 | 799 | struct mxc_nand_host *host = nand_get_controller_data(nand_chip); |
34f6e157 | 800 | |
d178e3e8 | 801 | if (chip == -1) { |
34f6e157 SH |
802 | /* Disable the NFC clock */ |
803 | if (host->clk_act) { | |
97c3213f | 804 | clk_disable_unprepare(host->clk); |
34f6e157 SH |
805 | host->clk_act = 0; |
806 | } | |
d178e3e8 BS |
807 | return; |
808 | } | |
809 | ||
810 | if (!host->clk_act) { | |
34f6e157 | 811 | /* Enable the NFC clock */ |
97c3213f | 812 | clk_prepare_enable(host->clk); |
d178e3e8 BS |
813 | host->clk_act = 1; |
814 | } | |
5e05a2d6 | 815 | } |
34f6e157 | 816 | |
5e05a2d6 UKK |
817 | static void mxc_nand_select_chip_v2(struct mtd_info *mtd, int chip) |
818 | { | |
4bd4ebcc | 819 | struct nand_chip *nand_chip = mtd_to_nand(mtd); |
d699ed25 | 820 | struct mxc_nand_host *host = nand_get_controller_data(nand_chip); |
5e05a2d6 UKK |
821 | |
822 | if (chip == -1) { | |
823 | /* Disable the NFC clock */ | |
824 | if (host->clk_act) { | |
3d059693 | 825 | clk_disable_unprepare(host->clk); |
5e05a2d6 UKK |
826 | host->clk_act = 0; |
827 | } | |
828 | return; | |
829 | } | |
34f6e157 | 830 | |
5e05a2d6 UKK |
831 | if (!host->clk_act) { |
832 | /* Enable the NFC clock */ | |
3d059693 | 833 | clk_prepare_enable(host->clk); |
5e05a2d6 | 834 | host->clk_act = 1; |
34f6e157 | 835 | } |
5e05a2d6 UKK |
836 | |
837 | host->active_cs = chip; | |
838 | writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR); | |
34f6e157 SH |
839 | } |
840 | ||
f8f9608d | 841 | /* |
35d5d20e UKK |
842 | * The controller splits a page into data chunks of 512 bytes + partial oob. |
843 | * There are writesize / 512 such chunks, the size of the partial oob parts is | |
844 | * oobsize / #chunks rounded down to a multiple of 2. The last oob chunk then | |
845 | * contains additionally the byte lost by rounding (if any). | |
846 | * This function handles the needed shuffling between host->data_buf (which | |
847 | * holds a page in natural order, i.e. writesize bytes data + oobsize bytes | |
848 | * spare) and the NFC buffer. | |
f8f9608d SH |
849 | */ |
850 | static void copy_spare(struct mtd_info *mtd, bool bfrom) | |
34f6e157 | 851 | { |
4bd4ebcc | 852 | struct nand_chip *this = mtd_to_nand(mtd); |
d699ed25 | 853 | struct mxc_nand_host *host = nand_get_controller_data(this); |
35d5d20e UKK |
854 | u16 i, oob_chunk_size; |
855 | u16 num_chunks = mtd->writesize / 512; | |
856 | ||
f8f9608d | 857 | u8 *d = host->data_buf + mtd->writesize; |
4b6f05e1 | 858 | u8 __iomem *s = host->spare0; |
35d5d20e | 859 | u16 sparebuf_size = host->devtype_data->spare_len; |
f8f9608d | 860 | |
35d5d20e | 861 | /* size of oob chunk for all but possibly the last one */ |
7e7e4730 | 862 | oob_chunk_size = (host->used_oobsize / num_chunks) & ~1; |
f8f9608d SH |
863 | |
864 | if (bfrom) { | |
35d5d20e | 865 | for (i = 0; i < num_chunks - 1; i++) |
0d17fc3e | 866 | memcpy16_fromio(d + i * oob_chunk_size, |
35d5d20e UKK |
867 | s + i * sparebuf_size, |
868 | oob_chunk_size); | |
869 | ||
870 | /* the last chunk */ | |
0d17fc3e | 871 | memcpy16_fromio(d + i * oob_chunk_size, |
35d5d20e | 872 | s + i * sparebuf_size, |
7e7e4730 | 873 | host->used_oobsize - i * oob_chunk_size); |
f8f9608d | 874 | } else { |
35d5d20e | 875 | for (i = 0; i < num_chunks - 1; i++) |
0d17fc3e | 876 | memcpy16_toio(&s[i * sparebuf_size], |
35d5d20e UKK |
877 | &d[i * oob_chunk_size], |
878 | oob_chunk_size); | |
879 | ||
880 | /* the last chunk */ | |
e5a5d92d | 881 | memcpy16_toio(&s[i * sparebuf_size], |
35d5d20e | 882 | &d[i * oob_chunk_size], |
7e7e4730 | 883 | host->used_oobsize - i * oob_chunk_size); |
34f6e157 | 884 | } |
f8f9608d | 885 | } |
34f6e157 | 886 | |
c4ca3997 UKK |
887 | /* |
888 | * MXC NANDFC can only perform full page+spare or spare-only read/write. When | |
889 | * the upper layers perform a read/write buf operation, the saved column address | |
890 | * is used to index into the full page. So usually this function is called with | |
891 | * column == 0 (unless no column cycle is needed indicated by column == -1) | |
892 | */ | |
a3e65b64 SH |
893 | static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr) |
894 | { | |
4bd4ebcc | 895 | struct nand_chip *nand_chip = mtd_to_nand(mtd); |
d699ed25 | 896 | struct mxc_nand_host *host = nand_get_controller_data(nand_chip); |
34f6e157 SH |
897 | |
898 | /* Write out column address, if necessary */ | |
899 | if (column != -1) { | |
c4ca3997 UKK |
900 | host->devtype_data->send_addr(host, column & 0xff, |
901 | page_addr == -1); | |
2d69c7fa | 902 | if (mtd->writesize > 512) |
34f6e157 | 903 | /* another col addr cycle for 2k page */ |
c4ca3997 UKK |
904 | host->devtype_data->send_addr(host, |
905 | (column >> 8) & 0xff, | |
906 | false); | |
34f6e157 SH |
907 | } |
908 | ||
909 | /* Write out page address, if necessary */ | |
910 | if (page_addr != -1) { | |
911 | /* paddr_0 - p_addr_7 */ | |
e4303b25 | 912 | host->devtype_data->send_addr(host, (page_addr & 0xff), false); |
34f6e157 | 913 | |
2d69c7fa | 914 | if (mtd->writesize > 512) { |
bd3fd62e VB |
915 | if (mtd->size >= 0x10000000) { |
916 | /* paddr_8 - paddr_15 */ | |
e4303b25 UKK |
917 | host->devtype_data->send_addr(host, |
918 | (page_addr >> 8) & 0xff, | |
919 | false); | |
920 | host->devtype_data->send_addr(host, | |
921 | (page_addr >> 16) & 0xff, | |
922 | true); | |
bd3fd62e VB |
923 | } else |
924 | /* paddr_8 - paddr_15 */ | |
e4303b25 UKK |
925 | host->devtype_data->send_addr(host, |
926 | (page_addr >> 8) & 0xff, true); | |
34f6e157 SH |
927 | } else { |
928 | /* One more address cycle for higher density devices */ | |
929 | if (mtd->size >= 0x4000000) { | |
930 | /* paddr_8 - paddr_15 */ | |
e4303b25 UKK |
931 | host->devtype_data->send_addr(host, |
932 | (page_addr >> 8) & 0xff, | |
933 | false); | |
934 | host->devtype_data->send_addr(host, | |
935 | (page_addr >> 16) & 0xff, | |
936 | true); | |
34f6e157 SH |
937 | } else |
938 | /* paddr_8 - paddr_15 */ | |
e4303b25 UKK |
939 | host->devtype_data->send_addr(host, |
940 | (page_addr >> 8) & 0xff, true); | |
34f6e157 SH |
941 | } |
942 | } | |
a3e65b64 SH |
943 | } |
944 | ||
6e85dfdc SH |
945 | /* |
946 | * v2 and v3 type controllers can do 4bit or 8bit ecc depending | |
947 | * on how much oob the nand chip has. For 8bit ecc we need at least | |
948 | * 26 bytes of oob data per 512 byte block. | |
949 | */ | |
950 | static int get_eccsize(struct mtd_info *mtd) | |
951 | { | |
952 | int oobbytes_per_512 = 0; | |
953 | ||
954 | oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize; | |
955 | ||
956 | if (oobbytes_per_512 < 26) | |
957 | return 4; | |
958 | else | |
959 | return 8; | |
960 | } | |
961 | ||
8eeb4c52 BS |
962 | static void ecc_8bit_layout_4k(struct nand_ecclayout *layout) |
963 | { | |
964 | int i, j; | |
965 | ||
966 | layout->eccbytes = 8*18; | |
967 | for (i = 0; i < 8; i++) | |
968 | for (j = 0; j < 18; j++) | |
969 | layout->eccpos[i*18 + j] = i*26 + j + 7; | |
970 | ||
971 | layout->oobfree[0].offset = 2; | |
972 | layout->oobfree[0].length = 4; | |
973 | for (i = 1; i < 8; i++) { | |
974 | layout->oobfree[i].offset = i*26; | |
975 | layout->oobfree[i].length = 7; | |
976 | } | |
977 | } | |
978 | ||
6d38af25 | 979 | static void preset_v1(struct mtd_info *mtd) |
d4840180 | 980 | { |
4bd4ebcc | 981 | struct nand_chip *nand_chip = mtd_to_nand(mtd); |
d699ed25 | 982 | struct mxc_nand_host *host = nand_get_controller_data(nand_chip); |
b8db2f51 SH |
983 | uint16_t config1 = 0; |
984 | ||
1f42adc8 | 985 | if (nand_chip->ecc.mode == NAND_ECC_HW && mtd->writesize) |
b8db2f51 SH |
986 | config1 |= NFC_V1_V2_CONFIG1_ECC_EN; |
987 | ||
f48d0f9a | 988 | if (!host->devtype_data->irqpending_quirk) |
6d38af25 UKK |
989 | config1 |= NFC_V1_V2_CONFIG1_INT_MSK; |
990 | ||
991 | host->eccsize = 1; | |
992 | ||
993 | writew(config1, NFC_V1_V2_CONFIG1); | |
994 | /* preset operation */ | |
995 | ||
996 | /* Unlock the internal RAM Buffer */ | |
997 | writew(0x2, NFC_V1_V2_CONFIG); | |
998 | ||
999 | /* Blocks to be unlocked */ | |
1000 | writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR); | |
1001 | writew(0xffff, NFC_V1_UNLOCKEND_BLKADDR); | |
1002 | ||
1003 | /* Unlock Block Command for given address range */ | |
1004 | writew(0x4, NFC_V1_V2_WRPROT); | |
1005 | } | |
1006 | ||
1007 | static void preset_v2(struct mtd_info *mtd) | |
d4840180 | 1008 | { |
4bd4ebcc | 1009 | struct nand_chip *nand_chip = mtd_to_nand(mtd); |
d699ed25 | 1010 | struct mxc_nand_host *host = nand_get_controller_data(nand_chip); |
b8db2f51 SH |
1011 | uint16_t config1 = 0; |
1012 | ||
6d38af25 | 1013 | config1 |= NFC_V2_CONFIG1_FP_INT; |
b8db2f51 | 1014 | |
f48d0f9a | 1015 | if (!host->devtype_data->irqpending_quirk) |
b8db2f51 | 1016 | config1 |= NFC_V1_V2_CONFIG1_INT_MSK; |
6e85dfdc | 1017 | |
6d38af25 | 1018 | if (mtd->writesize) { |
b8db2f51 SH |
1019 | uint16_t pages_per_block = mtd->erasesize / mtd->writesize; |
1020 | ||
1f42adc8 UKK |
1021 | if (nand_chip->ecc.mode == NAND_ECC_HW) |
1022 | config1 |= NFC_V1_V2_CONFIG1_ECC_EN; | |
1023 | ||
6e85dfdc SH |
1024 | host->eccsize = get_eccsize(mtd); |
1025 | if (host->eccsize == 4) | |
b8db2f51 SH |
1026 | config1 |= NFC_V2_CONFIG1_ECC_MODE_4; |
1027 | ||
1028 | config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6); | |
d4840180 | 1029 | } else { |
6e85dfdc | 1030 | host->eccsize = 1; |
d4840180 | 1031 | } |
6e85dfdc | 1032 | |
b8db2f51 | 1033 | writew(config1, NFC_V1_V2_CONFIG1); |
d4840180 IC |
1034 | /* preset operation */ |
1035 | ||
1036 | /* Unlock the internal RAM Buffer */ | |
1bc99180 | 1037 | writew(0x2, NFC_V1_V2_CONFIG); |
d4840180 IC |
1038 | |
1039 | /* Blocks to be unlocked */ | |
6d38af25 UKK |
1040 | writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0); |
1041 | writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1); | |
1042 | writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2); | |
1043 | writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3); | |
1044 | writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0); | |
1045 | writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1); | |
1046 | writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2); | |
1047 | writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3); | |
d4840180 IC |
1048 | |
1049 | /* Unlock Block Command for given address range */ | |
1bc99180 | 1050 | writew(0x4, NFC_V1_V2_WRPROT); |
d4840180 IC |
1051 | } |
1052 | ||
71ec5155 SH |
1053 | static void preset_v3(struct mtd_info *mtd) |
1054 | { | |
4bd4ebcc | 1055 | struct nand_chip *chip = mtd_to_nand(mtd); |
d699ed25 | 1056 | struct mxc_nand_host *host = nand_get_controller_data(chip); |
71ec5155 SH |
1057 | uint32_t config2, config3; |
1058 | int i, addr_phases; | |
1059 | ||
1060 | writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1); | |
1061 | writel(NFC_V3_IPC_CREQ, NFC_V3_IPC); | |
1062 | ||
1063 | /* Unlock the internal RAM Buffer */ | |
1064 | writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK, | |
1065 | NFC_V3_WRPROT); | |
1066 | ||
1067 | /* Blocks to be unlocked */ | |
1068 | for (i = 0; i < NAND_MAX_CHIPS; i++) | |
1b15b1f5 | 1069 | writel(0xffff << 16, NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2)); |
71ec5155 SH |
1070 | |
1071 | writel(0, NFC_V3_IPC); | |
1072 | ||
1073 | config2 = NFC_V3_CONFIG2_ONE_CYCLE | | |
1074 | NFC_V3_CONFIG2_2CMD_PHASES | | |
1075 | NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) | | |
1076 | NFC_V3_CONFIG2_ST_CMD(0x70) | | |
63f1474c | 1077 | NFC_V3_CONFIG2_INT_MSK | |
71ec5155 SH |
1078 | NFC_V3_CONFIG2_NUM_ADDR_PHASE0; |
1079 | ||
71ec5155 SH |
1080 | addr_phases = fls(chip->pagemask) >> 3; |
1081 | ||
1082 | if (mtd->writesize == 2048) { | |
1083 | config2 |= NFC_V3_CONFIG2_PS_2048; | |
1084 | config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases); | |
1085 | } else if (mtd->writesize == 4096) { | |
1086 | config2 |= NFC_V3_CONFIG2_PS_4096; | |
1087 | config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases); | |
1088 | } else { | |
1089 | config2 |= NFC_V3_CONFIG2_PS_512; | |
1090 | config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1); | |
1091 | } | |
1092 | ||
1093 | if (mtd->writesize) { | |
1f42adc8 UKK |
1094 | if (chip->ecc.mode == NAND_ECC_HW) |
1095 | config2 |= NFC_V3_CONFIG2_ECC_EN; | |
1096 | ||
71718a8e SH |
1097 | config2 |= NFC_V3_CONFIG2_PPB( |
1098 | ffs(mtd->erasesize / mtd->writesize) - 6, | |
1099 | host->devtype_data->ppb_shift); | |
71ec5155 SH |
1100 | host->eccsize = get_eccsize(mtd); |
1101 | if (host->eccsize == 8) | |
1102 | config2 |= NFC_V3_CONFIG2_ECC_MODE_8; | |
1103 | } | |
1104 | ||
1105 | writel(config2, NFC_V3_CONFIG2); | |
1106 | ||
1107 | config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) | | |
1108 | NFC_V3_CONFIG3_NO_SDMA | | |
1109 | NFC_V3_CONFIG3_RBB_MODE | | |
1110 | NFC_V3_CONFIG3_SBB(6) | /* Reset default */ | |
1111 | NFC_V3_CONFIG3_ADD_OP(0); | |
1112 | ||
1113 | if (!(chip->options & NAND_BUSWIDTH_16)) | |
1114 | config3 |= NFC_V3_CONFIG3_FW8; | |
1115 | ||
1116 | writel(config3, NFC_V3_CONFIG3); | |
1117 | ||
1118 | writel(0, NFC_V3_DELAY_LINE); | |
d4840180 IC |
1119 | } |
1120 | ||
34f6e157 SH |
1121 | /* Used by the upper layer to write command to NAND Flash for |
1122 | * different operations to be carried out on NAND Flash */ | |
1123 | static void mxc_nand_command(struct mtd_info *mtd, unsigned command, | |
1124 | int column, int page_addr) | |
1125 | { | |
4bd4ebcc | 1126 | struct nand_chip *nand_chip = mtd_to_nand(mtd); |
d699ed25 | 1127 | struct mxc_nand_host *host = nand_get_controller_data(nand_chip); |
34f6e157 | 1128 | |
289c0522 | 1129 | pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n", |
34f6e157 SH |
1130 | command, column, page_addr); |
1131 | ||
1132 | /* Reset command state information */ | |
1133 | host->status_request = false; | |
34f6e157 | 1134 | |
34f6e157 | 1135 | /* Command pre-processing step */ |
34f6e157 | 1136 | switch (command) { |
d4840180 | 1137 | case NAND_CMD_RESET: |
e4303b25 UKK |
1138 | host->devtype_data->preset(mtd); |
1139 | host->devtype_data->send_cmd(host, command, false); | |
d4840180 | 1140 | break; |
34f6e157 | 1141 | |
34f6e157 | 1142 | case NAND_CMD_STATUS: |
f8f9608d | 1143 | host->buf_start = 0; |
34f6e157 | 1144 | host->status_request = true; |
34f6e157 | 1145 | |
e4303b25 | 1146 | host->devtype_data->send_cmd(host, command, true); |
c4ca3997 UKK |
1147 | WARN_ONCE(column != -1 || page_addr != -1, |
1148 | "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n", | |
1149 | command, column, page_addr); | |
89121a6b | 1150 | mxc_do_addr_cycle(mtd, column, page_addr); |
34f6e157 SH |
1151 | break; |
1152 | ||
34f6e157 | 1153 | case NAND_CMD_READ0: |
34f6e157 | 1154 | case NAND_CMD_READOOB: |
89121a6b SH |
1155 | if (command == NAND_CMD_READ0) |
1156 | host->buf_start = column; | |
1157 | else | |
1158 | host->buf_start = column + mtd->writesize; | |
f8f9608d | 1159 | |
5ea32021 | 1160 | command = NAND_CMD_READ0; /* only READ0 is valid */ |
89121a6b | 1161 | |
e4303b25 | 1162 | host->devtype_data->send_cmd(host, command, false); |
c4ca3997 UKK |
1163 | WARN_ONCE(column < 0, |
1164 | "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n", | |
1165 | command, column, page_addr); | |
1166 | mxc_do_addr_cycle(mtd, 0, page_addr); | |
89121a6b | 1167 | |
2d69c7fa | 1168 | if (mtd->writesize > 512) |
e4303b25 UKK |
1169 | host->devtype_data->send_cmd(host, |
1170 | NAND_CMD_READSTART, true); | |
c5d23f1b | 1171 | |
e4303b25 | 1172 | host->devtype_data->send_page(mtd, NFC_OUTPUT); |
89121a6b | 1173 | |
096bcc23 SH |
1174 | memcpy32_fromio(host->data_buf, host->main_area0, |
1175 | mtd->writesize); | |
89121a6b | 1176 | copy_spare(mtd, true); |
34f6e157 SH |
1177 | break; |
1178 | ||
34f6e157 | 1179 | case NAND_CMD_SEQIN: |
5ea32021 SH |
1180 | if (column >= mtd->writesize) |
1181 | /* call ourself to read a page */ | |
1182 | mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr); | |
34f6e157 | 1183 | |
5ea32021 | 1184 | host->buf_start = column; |
89121a6b | 1185 | |
e4303b25 | 1186 | host->devtype_data->send_cmd(host, command, false); |
c4ca3997 UKK |
1187 | WARN_ONCE(column < -1, |
1188 | "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n", | |
1189 | command, column, page_addr); | |
1190 | mxc_do_addr_cycle(mtd, 0, page_addr); | |
34f6e157 SH |
1191 | break; |
1192 | ||
1193 | case NAND_CMD_PAGEPROG: | |
096bcc23 | 1194 | memcpy32_toio(host->main_area0, host->data_buf, mtd->writesize); |
f8f9608d | 1195 | copy_spare(mtd, false); |
e4303b25 UKK |
1196 | host->devtype_data->send_page(mtd, NFC_INPUT); |
1197 | host->devtype_data->send_cmd(host, command, true); | |
c4ca3997 UKK |
1198 | WARN_ONCE(column != -1 || page_addr != -1, |
1199 | "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n", | |
1200 | command, column, page_addr); | |
89121a6b | 1201 | mxc_do_addr_cycle(mtd, column, page_addr); |
34f6e157 SH |
1202 | break; |
1203 | ||
34f6e157 | 1204 | case NAND_CMD_READID: |
e4303b25 | 1205 | host->devtype_data->send_cmd(host, command, true); |
89121a6b | 1206 | mxc_do_addr_cycle(mtd, column, page_addr); |
e4303b25 | 1207 | host->devtype_data->send_read_id(host); |
c4ca3997 | 1208 | host->buf_start = 0; |
34f6e157 SH |
1209 | break; |
1210 | ||
89121a6b | 1211 | case NAND_CMD_ERASE1: |
34f6e157 | 1212 | case NAND_CMD_ERASE2: |
e4303b25 | 1213 | host->devtype_data->send_cmd(host, command, false); |
c4ca3997 UKK |
1214 | WARN_ONCE(column != -1, |
1215 | "Unexpected column value (cmd=%u, col=%d)\n", | |
1216 | command, column); | |
89121a6b SH |
1217 | mxc_do_addr_cycle(mtd, column, page_addr); |
1218 | ||
3d6e81c0 UKK |
1219 | break; |
1220 | case NAND_CMD_PARAM: | |
1221 | host->devtype_data->send_cmd(host, command, false); | |
1222 | mxc_do_addr_cycle(mtd, column, page_addr); | |
1223 | host->devtype_data->send_page(mtd, NFC_OUTPUT); | |
1224 | memcpy32_fromio(host->data_buf, host->main_area0, 512); | |
1225 | host->buf_start = 0; | |
34f6e157 | 1226 | break; |
98ebb521 UKK |
1227 | default: |
1228 | WARN_ONCE(1, "Unimplemented command (cmd=%u)\n", | |
1229 | command); | |
1230 | break; | |
34f6e157 SH |
1231 | } |
1232 | } | |
1233 | ||
f1372055 SH |
1234 | /* |
1235 | * The generic flash bbt decriptors overlap with our ecc | |
1236 | * hardware, so define some i.MX specific ones. | |
1237 | */ | |
1238 | static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' }; | |
1239 | static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' }; | |
1240 | ||
1241 | static struct nand_bbt_descr bbt_main_descr = { | |
1242 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
1243 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
1244 | .offs = 0, | |
1245 | .len = 4, | |
1246 | .veroffs = 4, | |
1247 | .maxblocks = 4, | |
1248 | .pattern = bbt_pattern, | |
1249 | }; | |
1250 | ||
1251 | static struct nand_bbt_descr bbt_mirror_descr = { | |
1252 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
1253 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
1254 | .offs = 0, | |
1255 | .len = 4, | |
1256 | .veroffs = 4, | |
1257 | .maxblocks = 4, | |
1258 | .pattern = mirror_pattern, | |
1259 | }; | |
1260 | ||
f48d0f9a | 1261 | /* v1 + irqpending_quirk: i.MX21 */ |
e4303b25 | 1262 | static const struct mxc_nand_devtype_data imx21_nand_devtype_data = { |
6d38af25 | 1263 | .preset = preset_v1, |
e4303b25 UKK |
1264 | .send_cmd = send_cmd_v1_v2, |
1265 | .send_addr = send_addr_v1_v2, | |
6d38af25 | 1266 | .send_page = send_page_v1, |
e4303b25 UKK |
1267 | .send_read_id = send_read_id_v1_v2, |
1268 | .get_dev_status = get_dev_status_v1_v2, | |
1269 | .check_int = check_int_v1_v2, | |
1270 | .irq_control = irq_control_v1_v2, | |
6d38af25 | 1271 | .get_ecc_status = get_ecc_status_v1, |
6dcdf99d UKK |
1272 | .ecclayout_512 = &nandv1_hw_eccoob_smallpage, |
1273 | .ecclayout_2k = &nandv1_hw_eccoob_largepage, | |
1274 | .ecclayout_4k = &nandv1_hw_eccoob_smallpage, /* XXX: needs fix */ | |
5e05a2d6 | 1275 | .select_chip = mxc_nand_select_chip_v1_v3, |
69d023be | 1276 | .correct_data = mxc_nand_correct_data_v1, |
f48d0f9a UKK |
1277 | .irqpending_quirk = 1, |
1278 | .needs_ip = 0, | |
1279 | .regs_offset = 0xe00, | |
1280 | .spare0_offset = 0x800, | |
1281 | .spare_len = 16, | |
1282 | .eccbytes = 3, | |
1283 | .eccsize = 1, | |
1284 | }; | |
1285 | ||
1286 | /* v1 + !irqpending_quirk: i.MX27, i.MX31 */ | |
1287 | static const struct mxc_nand_devtype_data imx27_nand_devtype_data = { | |
1288 | .preset = preset_v1, | |
1289 | .send_cmd = send_cmd_v1_v2, | |
1290 | .send_addr = send_addr_v1_v2, | |
1291 | .send_page = send_page_v1, | |
1292 | .send_read_id = send_read_id_v1_v2, | |
1293 | .get_dev_status = get_dev_status_v1_v2, | |
1294 | .check_int = check_int_v1_v2, | |
1295 | .irq_control = irq_control_v1_v2, | |
1296 | .get_ecc_status = get_ecc_status_v1, | |
1297 | .ecclayout_512 = &nandv1_hw_eccoob_smallpage, | |
1298 | .ecclayout_2k = &nandv1_hw_eccoob_largepage, | |
1299 | .ecclayout_4k = &nandv1_hw_eccoob_smallpage, /* XXX: needs fix */ | |
1300 | .select_chip = mxc_nand_select_chip_v1_v3, | |
1301 | .correct_data = mxc_nand_correct_data_v1, | |
1302 | .irqpending_quirk = 0, | |
1303 | .needs_ip = 0, | |
1304 | .regs_offset = 0xe00, | |
1305 | .spare0_offset = 0x800, | |
1306 | .axi_offset = 0, | |
1307 | .spare_len = 16, | |
1308 | .eccbytes = 3, | |
1309 | .eccsize = 1, | |
e4303b25 UKK |
1310 | }; |
1311 | ||
1312 | /* v21: i.MX25, i.MX35 */ | |
1313 | static const struct mxc_nand_devtype_data imx25_nand_devtype_data = { | |
6d38af25 | 1314 | .preset = preset_v2, |
e4303b25 UKK |
1315 | .send_cmd = send_cmd_v1_v2, |
1316 | .send_addr = send_addr_v1_v2, | |
6d38af25 | 1317 | .send_page = send_page_v2, |
e4303b25 UKK |
1318 | .send_read_id = send_read_id_v1_v2, |
1319 | .get_dev_status = get_dev_status_v1_v2, | |
1320 | .check_int = check_int_v1_v2, | |
1321 | .irq_control = irq_control_v1_v2, | |
6d38af25 | 1322 | .get_ecc_status = get_ecc_status_v2, |
6dcdf99d UKK |
1323 | .ecclayout_512 = &nandv2_hw_eccoob_smallpage, |
1324 | .ecclayout_2k = &nandv2_hw_eccoob_largepage, | |
1325 | .ecclayout_4k = &nandv2_hw_eccoob_4k, | |
5e05a2d6 | 1326 | .select_chip = mxc_nand_select_chip_v2, |
69d023be | 1327 | .correct_data = mxc_nand_correct_data_v2_v3, |
f48d0f9a UKK |
1328 | .irqpending_quirk = 0, |
1329 | .needs_ip = 0, | |
1330 | .regs_offset = 0x1e00, | |
1331 | .spare0_offset = 0x1000, | |
1332 | .axi_offset = 0, | |
1333 | .spare_len = 64, | |
1334 | .eccbytes = 9, | |
1335 | .eccsize = 0, | |
e4303b25 UKK |
1336 | }; |
1337 | ||
71718a8e | 1338 | /* v3.2a: i.MX51 */ |
e4303b25 UKK |
1339 | static const struct mxc_nand_devtype_data imx51_nand_devtype_data = { |
1340 | .preset = preset_v3, | |
1341 | .send_cmd = send_cmd_v3, | |
1342 | .send_addr = send_addr_v3, | |
1343 | .send_page = send_page_v3, | |
1344 | .send_read_id = send_read_id_v3, | |
1345 | .get_dev_status = get_dev_status_v3, | |
1346 | .check_int = check_int_v3, | |
1347 | .irq_control = irq_control_v3, | |
6d38af25 | 1348 | .get_ecc_status = get_ecc_status_v3, |
6dcdf99d UKK |
1349 | .ecclayout_512 = &nandv2_hw_eccoob_smallpage, |
1350 | .ecclayout_2k = &nandv2_hw_eccoob_largepage, | |
1351 | .ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */ | |
5e05a2d6 | 1352 | .select_chip = mxc_nand_select_chip_v1_v3, |
69d023be | 1353 | .correct_data = mxc_nand_correct_data_v2_v3, |
f48d0f9a UKK |
1354 | .irqpending_quirk = 0, |
1355 | .needs_ip = 1, | |
1356 | .regs_offset = 0, | |
1357 | .spare0_offset = 0x1000, | |
1358 | .axi_offset = 0x1e00, | |
1359 | .spare_len = 64, | |
1360 | .eccbytes = 0, | |
1361 | .eccsize = 0, | |
71718a8e SH |
1362 | .ppb_shift = 7, |
1363 | }; | |
1364 | ||
1365 | /* v3.2b: i.MX53 */ | |
1366 | static const struct mxc_nand_devtype_data imx53_nand_devtype_data = { | |
1367 | .preset = preset_v3, | |
1368 | .send_cmd = send_cmd_v3, | |
1369 | .send_addr = send_addr_v3, | |
1370 | .send_page = send_page_v3, | |
1371 | .send_read_id = send_read_id_v3, | |
1372 | .get_dev_status = get_dev_status_v3, | |
1373 | .check_int = check_int_v3, | |
1374 | .irq_control = irq_control_v3, | |
1375 | .get_ecc_status = get_ecc_status_v3, | |
1376 | .ecclayout_512 = &nandv2_hw_eccoob_smallpage, | |
1377 | .ecclayout_2k = &nandv2_hw_eccoob_largepage, | |
1378 | .ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */ | |
1379 | .select_chip = mxc_nand_select_chip_v1_v3, | |
1380 | .correct_data = mxc_nand_correct_data_v2_v3, | |
1381 | .irqpending_quirk = 0, | |
1382 | .needs_ip = 1, | |
1383 | .regs_offset = 0, | |
1384 | .spare0_offset = 0x1000, | |
1385 | .axi_offset = 0x1e00, | |
1386 | .spare_len = 64, | |
1387 | .eccbytes = 0, | |
1388 | .eccsize = 0, | |
1389 | .ppb_shift = 8, | |
e4303b25 UKK |
1390 | }; |
1391 | ||
4d62435f SG |
1392 | static inline int is_imx21_nfc(struct mxc_nand_host *host) |
1393 | { | |
1394 | return host->devtype_data == &imx21_nand_devtype_data; | |
1395 | } | |
1396 | ||
1397 | static inline int is_imx27_nfc(struct mxc_nand_host *host) | |
1398 | { | |
1399 | return host->devtype_data == &imx27_nand_devtype_data; | |
1400 | } | |
1401 | ||
1402 | static inline int is_imx25_nfc(struct mxc_nand_host *host) | |
1403 | { | |
1404 | return host->devtype_data == &imx25_nand_devtype_data; | |
1405 | } | |
1406 | ||
1407 | static inline int is_imx51_nfc(struct mxc_nand_host *host) | |
1408 | { | |
1409 | return host->devtype_data == &imx51_nand_devtype_data; | |
1410 | } | |
1411 | ||
1412 | static inline int is_imx53_nfc(struct mxc_nand_host *host) | |
1413 | { | |
1414 | return host->devtype_data == &imx53_nand_devtype_data; | |
1415 | } | |
1416 | ||
8d1e568d | 1417 | static const struct platform_device_id mxcnd_devtype[] = { |
4d62435f SG |
1418 | { |
1419 | .name = "imx21-nand", | |
1420 | .driver_data = (kernel_ulong_t) &imx21_nand_devtype_data, | |
1421 | }, { | |
1422 | .name = "imx27-nand", | |
1423 | .driver_data = (kernel_ulong_t) &imx27_nand_devtype_data, | |
1424 | }, { | |
1425 | .name = "imx25-nand", | |
1426 | .driver_data = (kernel_ulong_t) &imx25_nand_devtype_data, | |
1427 | }, { | |
1428 | .name = "imx51-nand", | |
1429 | .driver_data = (kernel_ulong_t) &imx51_nand_devtype_data, | |
1430 | }, { | |
1431 | .name = "imx53-nand", | |
1432 | .driver_data = (kernel_ulong_t) &imx53_nand_devtype_data, | |
1433 | }, { | |
1434 | /* sentinel */ | |
1435 | } | |
1436 | }; | |
1437 | MODULE_DEVICE_TABLE(platform, mxcnd_devtype); | |
1438 | ||
6436356b UKK |
1439 | #ifdef CONFIG_OF_MTD |
1440 | static const struct of_device_id mxcnd_dt_ids[] = { | |
1441 | { | |
1442 | .compatible = "fsl,imx21-nand", | |
1443 | .data = &imx21_nand_devtype_data, | |
1444 | }, { | |
1445 | .compatible = "fsl,imx27-nand", | |
1446 | .data = &imx27_nand_devtype_data, | |
1447 | }, { | |
1448 | .compatible = "fsl,imx25-nand", | |
1449 | .data = &imx25_nand_devtype_data, | |
1450 | }, { | |
1451 | .compatible = "fsl,imx51-nand", | |
1452 | .data = &imx51_nand_devtype_data, | |
71718a8e SH |
1453 | }, { |
1454 | .compatible = "fsl,imx53-nand", | |
1455 | .data = &imx53_nand_devtype_data, | |
6436356b UKK |
1456 | }, |
1457 | { /* sentinel */ } | |
1458 | }; | |
b33c35b1 | 1459 | MODULE_DEVICE_TABLE(of, mxcnd_dt_ids); |
6436356b UKK |
1460 | |
1461 | static int __init mxcnd_probe_dt(struct mxc_nand_host *host) | |
1462 | { | |
1463 | struct device_node *np = host->dev->of_node; | |
1464 | struct mxc_nand_platform_data *pdata = &host->pdata; | |
1465 | const struct of_device_id *of_id = | |
1466 | of_match_device(mxcnd_dt_ids, host->dev); | |
1467 | int buswidth; | |
1468 | ||
1469 | if (!np) | |
1470 | return 1; | |
1471 | ||
1472 | if (of_get_nand_ecc_mode(np) >= 0) | |
1473 | pdata->hw_ecc = 1; | |
1474 | ||
1475 | pdata->flash_bbt = of_get_nand_on_flash_bbt(np); | |
1476 | ||
1477 | buswidth = of_get_nand_bus_width(np); | |
1478 | if (buswidth < 0) | |
1479 | return buswidth; | |
1480 | ||
1481 | pdata->width = buswidth / 8; | |
1482 | ||
1483 | host->devtype_data = of_id->data; | |
1484 | ||
1485 | return 0; | |
1486 | } | |
1487 | #else | |
1488 | static int __init mxcnd_probe_dt(struct mxc_nand_host *host) | |
1489 | { | |
1490 | return 1; | |
1491 | } | |
1492 | #endif | |
1493 | ||
06f25510 | 1494 | static int mxcnd_probe(struct platform_device *pdev) |
34f6e157 SH |
1495 | { |
1496 | struct nand_chip *this; | |
1497 | struct mtd_info *mtd; | |
34f6e157 SH |
1498 | struct mxc_nand_host *host; |
1499 | struct resource *res; | |
d4ed8f12 | 1500 | int err = 0; |
34f6e157 SH |
1501 | |
1502 | /* Allocate memory for MTD device structure and private data */ | |
a5900554 HS |
1503 | host = devm_kzalloc(&pdev->dev, sizeof(struct mxc_nand_host), |
1504 | GFP_KERNEL); | |
34f6e157 SH |
1505 | if (!host) |
1506 | return -ENOMEM; | |
1507 | ||
a5900554 HS |
1508 | /* allocate a temporary buffer for the nand_scan_ident() */ |
1509 | host->data_buf = devm_kzalloc(&pdev->dev, PAGE_SIZE, GFP_KERNEL); | |
1510 | if (!host->data_buf) | |
1511 | return -ENOMEM; | |
f8f9608d | 1512 | |
34f6e157 SH |
1513 | host->dev = &pdev->dev; |
1514 | /* structures must be linked */ | |
1515 | this = &host->nand; | |
a008deb1 | 1516 | mtd = nand_to_mtd(this); |
87f39f04 | 1517 | mtd->dev.parent = &pdev->dev; |
1fbff0a6 | 1518 | mtd->name = DRIVER_NAME; |
34f6e157 SH |
1519 | |
1520 | /* 50 us command delay time */ | |
1521 | this->chip_delay = 5; | |
1522 | ||
d699ed25 | 1523 | nand_set_controller_data(this, host); |
a61ae81a | 1524 | nand_set_flash_node(this, pdev->dev.of_node), |
34f6e157 SH |
1525 | this->dev_ready = mxc_nand_dev_ready; |
1526 | this->cmdfunc = mxc_nand_command; | |
34f6e157 SH |
1527 | this->read_byte = mxc_nand_read_byte; |
1528 | this->read_word = mxc_nand_read_word; | |
1529 | this->write_buf = mxc_nand_write_buf; | |
1530 | this->read_buf = mxc_nand_read_buf; | |
34f6e157 | 1531 | |
24b82d3c | 1532 | host->clk = devm_clk_get(&pdev->dev, NULL); |
e4a09cbf SH |
1533 | if (IS_ERR(host->clk)) |
1534 | return PTR_ERR(host->clk); | |
34f6e157 | 1535 | |
71885b65 | 1536 | err = mxcnd_probe_dt(host); |
4d62435f | 1537 | if (err > 0) { |
453810b7 JH |
1538 | struct mxc_nand_platform_data *pdata = |
1539 | dev_get_platdata(&pdev->dev); | |
4d62435f SG |
1540 | if (pdata) { |
1541 | host->pdata = *pdata; | |
1542 | host->devtype_data = (struct mxc_nand_devtype_data *) | |
1543 | pdev->id_entry->driver_data; | |
1544 | } else { | |
1545 | err = -ENODEV; | |
1546 | } | |
1547 | } | |
71885b65 SH |
1548 | if (err < 0) |
1549 | return err; | |
1550 | ||
1551 | if (host->devtype_data->needs_ip) { | |
1552 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
b0de774c TR |
1553 | host->regs_ip = devm_ioremap_resource(&pdev->dev, res); |
1554 | if (IS_ERR(host->regs_ip)) | |
1555 | return PTR_ERR(host->regs_ip); | |
71885b65 SH |
1556 | |
1557 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1558 | } else { | |
1559 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1560 | } | |
1561 | ||
b0de774c TR |
1562 | host->base = devm_ioremap_resource(&pdev->dev, res); |
1563 | if (IS_ERR(host->base)) | |
1564 | return PTR_ERR(host->base); | |
34f6e157 | 1565 | |
c6de7e1b | 1566 | host->main_area0 = host->base; |
9467114e | 1567 | |
f48d0f9a UKK |
1568 | if (host->devtype_data->regs_offset) |
1569 | host->regs = host->base + host->devtype_data->regs_offset; | |
1570 | host->spare0 = host->base + host->devtype_data->spare0_offset; | |
1571 | if (host->devtype_data->axi_offset) | |
1572 | host->regs_axi = host->base + host->devtype_data->axi_offset; | |
1573 | ||
1574 | this->ecc.bytes = host->devtype_data->eccbytes; | |
1575 | host->eccsize = host->devtype_data->eccsize; | |
1576 | ||
1577 | this->select_chip = host->devtype_data->select_chip; | |
1578 | this->ecc.size = 512; | |
1579 | this->ecc.layout = host->devtype_data->ecclayout_512; | |
1580 | ||
6436356b | 1581 | if (host->pdata.hw_ecc) { |
34f6e157 SH |
1582 | this->ecc.calculate = mxc_nand_calculate_ecc; |
1583 | this->ecc.hwctl = mxc_nand_enable_hwecc; | |
69d023be | 1584 | this->ecc.correct = host->devtype_data->correct_data; |
34f6e157 | 1585 | this->ecc.mode = NAND_ECC_HW; |
34f6e157 | 1586 | } else { |
34f6e157 | 1587 | this->ecc.mode = NAND_ECC_SOFT; |
34f6e157 SH |
1588 | } |
1589 | ||
6436356b UKK |
1590 | /* NAND bus width determines access functions used by upper layer */ |
1591 | if (host->pdata.width == 2) | |
34f6e157 | 1592 | this->options |= NAND_BUSWIDTH_16; |
34f6e157 | 1593 | |
6436356b | 1594 | if (host->pdata.flash_bbt) { |
f1372055 SH |
1595 | this->bbt_td = &bbt_main_descr; |
1596 | this->bbt_md = &bbt_mirror_descr; | |
1597 | /* update flash based bbt */ | |
bb9ebd4e | 1598 | this->bbt_options |= NAND_BBT_USE_FLASH; |
34f6e157 SH |
1599 | } |
1600 | ||
63f1474c | 1601 | init_completion(&host->op_completion); |
d4840180 IC |
1602 | |
1603 | host->irq = platform_get_irq(pdev, 0); | |
26fbf48b FE |
1604 | if (host->irq < 0) |
1605 | return host->irq; | |
d4840180 | 1606 | |
63f1474c | 1607 | /* |
e4303b25 UKK |
1608 | * Use host->devtype_data->irq_control() here instead of irq_control() |
1609 | * because we must not disable_irq_nosync without having requested the | |
1610 | * irq. | |
63f1474c | 1611 | */ |
e4303b25 | 1612 | host->devtype_data->irq_control(host, 0); |
63f1474c | 1613 | |
e4a09cbf | 1614 | err = devm_request_irq(&pdev->dev, host->irq, mxc_nfc_irq, |
b1eb234f | 1615 | 0, DRIVER_NAME, host); |
d4840180 | 1616 | if (err) |
e4a09cbf SH |
1617 | return err; |
1618 | ||
dcedf628 FE |
1619 | err = clk_prepare_enable(host->clk); |
1620 | if (err) | |
1621 | return err; | |
e4a09cbf | 1622 | host->clk_act = 1; |
d4840180 | 1623 | |
63f1474c | 1624 | /* |
8556958a UKK |
1625 | * Now that we "own" the interrupt make sure the interrupt mask bit is |
1626 | * cleared on i.MX21. Otherwise we can't read the interrupt status bit | |
1627 | * on this machine. | |
63f1474c | 1628 | */ |
f48d0f9a | 1629 | if (host->devtype_data->irqpending_quirk) { |
8556958a | 1630 | disable_irq_nosync(host->irq); |
e4303b25 | 1631 | host->devtype_data->irq_control(host, 1); |
8556958a | 1632 | } |
63f1474c | 1633 | |
bd3fd62e | 1634 | /* first scan to find the device and get the page size */ |
4d62435f | 1635 | if (nand_scan_ident(mtd, is_imx25_nfc(host) ? 4 : 1, NULL)) { |
bd3fd62e VB |
1636 | err = -ENXIO; |
1637 | goto escan; | |
1638 | } | |
34f6e157 | 1639 | |
a5900554 HS |
1640 | /* allocate the right size buffer now */ |
1641 | devm_kfree(&pdev->dev, (void *)host->data_buf); | |
1642 | host->data_buf = devm_kzalloc(&pdev->dev, mtd->writesize + mtd->oobsize, | |
1643 | GFP_KERNEL); | |
1644 | if (!host->data_buf) { | |
1645 | err = -ENOMEM; | |
1646 | goto escan; | |
1647 | } | |
1648 | ||
6e85dfdc | 1649 | /* Call preset again, with correct writesize this time */ |
e4303b25 | 1650 | host->devtype_data->preset(mtd); |
6e85dfdc | 1651 | |
2d69c7fa | 1652 | if (mtd->writesize == 2048) |
6dcdf99d | 1653 | this->ecc.layout = host->devtype_data->ecclayout_2k; |
8eeb4c52 | 1654 | else if (mtd->writesize == 4096) { |
6dcdf99d | 1655 | this->ecc.layout = host->devtype_data->ecclayout_4k; |
8eeb4c52 BS |
1656 | if (get_eccsize(mtd) == 8) |
1657 | ecc_8bit_layout_4k(this->ecc.layout); | |
1658 | } | |
34f6e157 | 1659 | |
7e7e4730 BS |
1660 | /* |
1661 | * Experimentation shows that i.MX NFC can only handle up to 218 oob | |
1662 | * bytes. Limit used_oobsize to 218 so as to not confuse copy_spare() | |
1663 | * into copying invalid data to/from the spare IO buffer, as this | |
1664 | * might cause ECC data corruption when doing sub-page write to a | |
1665 | * partially written page. | |
1666 | */ | |
1667 | host->used_oobsize = min(mtd->oobsize, 218U); | |
1668 | ||
6a918bad | 1669 | if (this->ecc.mode == NAND_ECC_HW) { |
4d62435f | 1670 | if (is_imx21_nfc(host) || is_imx27_nfc(host)) |
6a918bad MD |
1671 | this->ecc.strength = 1; |
1672 | else | |
1673 | this->ecc.strength = (host->eccsize == 4) ? 4 : 8; | |
1674 | } | |
1675 | ||
4a43faf5 SH |
1676 | /* second phase scan */ |
1677 | if (nand_scan_tail(mtd)) { | |
1678 | err = -ENXIO; | |
1679 | goto escan; | |
1680 | } | |
1681 | ||
34f6e157 | 1682 | /* Register the partitions */ |
6436356b | 1683 | mtd_device_parse_register(mtd, part_probes, |
a61ae81a | 1684 | NULL, |
6436356b UKK |
1685 | host->pdata.parts, |
1686 | host->pdata.nr_parts); | |
34f6e157 SH |
1687 | |
1688 | platform_set_drvdata(pdev, host); | |
1689 | ||
1690 | return 0; | |
1691 | ||
1692 | escan: | |
c10d8ee3 LW |
1693 | if (host->clk_act) |
1694 | clk_disable_unprepare(host->clk); | |
34f6e157 SH |
1695 | |
1696 | return err; | |
1697 | } | |
1698 | ||
810b7e06 | 1699 | static int mxcnd_remove(struct platform_device *pdev) |
34f6e157 SH |
1700 | { |
1701 | struct mxc_nand_host *host = platform_get_drvdata(pdev); | |
1702 | ||
a008deb1 | 1703 | nand_release(nand_to_mtd(&host->nand)); |
8bfd4f7f WY |
1704 | if (host->clk_act) |
1705 | clk_disable_unprepare(host->clk); | |
34f6e157 SH |
1706 | |
1707 | return 0; | |
1708 | } | |
1709 | ||
34f6e157 SH |
1710 | static struct platform_driver mxcnd_driver = { |
1711 | .driver = { | |
1712 | .name = DRIVER_NAME, | |
6436356b | 1713 | .of_match_table = of_match_ptr(mxcnd_dt_ids), |
04dd0d3a | 1714 | }, |
4d62435f | 1715 | .id_table = mxcnd_devtype, |
ddf16d62 | 1716 | .probe = mxcnd_probe, |
5153b88c | 1717 | .remove = mxcnd_remove, |
34f6e157 | 1718 | }; |
ddf16d62 | 1719 | module_platform_driver(mxcnd_driver); |
34f6e157 SH |
1720 | |
1721 | MODULE_AUTHOR("Freescale Semiconductor, Inc."); | |
1722 | MODULE_DESCRIPTION("MXC NAND MTD driver"); | |
1723 | MODULE_LICENSE("GPL"); |