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mtd: mxc_nand: cleanup copy_spare function
[deliverable/linux.git] / drivers / mtd / nand / mxc_nand.c
CommitLineData
34f6e157
SH		 1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#include <linux/delay.h>
21#include <linux/slab.h>
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/mtd/mtd.h>
25#include <linux/mtd/nand.h>
26#include <linux/mtd/partitions.h>
27#include <linux/interrupt.h>
28#include <linux/device.h>
29#include <linux/platform_device.h>
30#include <linux/clk.h>
31#include <linux/err.h>
32#include <linux/io.h>
63f1474c
SH		 33#include <linux/irq.h>
34#include <linux/completion.h>
d367e37e 35#include <linux/of.h>
6436356b
UKK		 36#include <linux/of_device.h>
37#include <linux/of_mtd.h>
34f6e157
SH		 38
39#include <asm/mach/flash.h>
82906b13 40#include <linux/platform_data/mtd-mxc_nand.h>
34f6e157
SH		 41
42#define DRIVER_NAME "mxc_nand"
43
44/* Addresses for NFC registers */
1bc99180
SH		 45#define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
46#define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
47#define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
48#define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
49#define NFC_V1_V2_CONFIG (host->regs + 0x0a)
50#define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
51#define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
52#define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10)
53#define NFC_V1_V2_WRPROT (host->regs + 0x12)
54#define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14)
55#define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16)
d178e3e8
BS		 56#define NFC_V21_UNLOCKSTART_BLKADDR0 (host->regs + 0x20)
57#define NFC_V21_UNLOCKSTART_BLKADDR1 (host->regs + 0x24)
58#define NFC_V21_UNLOCKSTART_BLKADDR2 (host->regs + 0x28)
59#define NFC_V21_UNLOCKSTART_BLKADDR3 (host->regs + 0x2c)
60#define NFC_V21_UNLOCKEND_BLKADDR0 (host->regs + 0x22)
61#define NFC_V21_UNLOCKEND_BLKADDR1 (host->regs + 0x26)
62#define NFC_V21_UNLOCKEND_BLKADDR2 (host->regs + 0x2a)
63#define NFC_V21_UNLOCKEND_BLKADDR3 (host->regs + 0x2e)
1bc99180
SH		 64#define NFC_V1_V2_NF_WRPRST (host->regs + 0x18)
65#define NFC_V1_V2_CONFIG1 (host->regs + 0x1a)
66#define NFC_V1_V2_CONFIG2 (host->regs + 0x1c)
67
6e85dfdc 68#define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
1bc99180
SH		 69#define NFC_V1_V2_CONFIG1_SP_EN (1 << 2)
70#define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
71#define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
72#define NFC_V1_V2_CONFIG1_BIG (1 << 5)
73#define NFC_V1_V2_CONFIG1_RST (1 << 6)
74#define NFC_V1_V2_CONFIG1_CE (1 << 7)
b8db2f51
SH		 75#define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
76#define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9)
77#define NFC_V2_CONFIG1_FP_INT (1 << 11)
1bc99180
SH		 78
79#define NFC_V1_V2_CONFIG2_INT (1 << 15)
80
81/*
82 * Operation modes for the NFC. Valid for v1, v2 and v3
83 * type controllers.
84 */
85#define NFC_CMD (1 << 0)
86#define NFC_ADDR (1 << 1)
87#define NFC_INPUT (1 << 2)
88#define NFC_OUTPUT (1 << 3)
89#define NFC_ID (1 << 4)
90#define NFC_STATUS (1 << 5)
34f6e157 91
71ec5155
SH		 92#define NFC_V3_FLASH_CMD (host->regs_axi + 0x00)
93#define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04)
94
95#define NFC_V3_CONFIG1 (host->regs_axi + 0x34)
96#define NFC_V3_CONFIG1_SP_EN (1 << 0)
97#define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4)
98
99#define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38)
100
101#define NFC_V3_LAUNCH (host->regs_axi + 0x40)
102
103#define NFC_V3_WRPROT (host->regs_ip + 0x0)
104#define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0)
105#define NFC_V3_WRPROT_LOCK (1 << 1)
106#define NFC_V3_WRPROT_UNLOCK (1 << 2)
107#define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
108
109#define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04)
110
111#define NFC_V3_CONFIG2 (host->regs_ip + 0x24)
112#define NFC_V3_CONFIG2_PS_512 (0 << 0)
113#define NFC_V3_CONFIG2_PS_2048 (1 << 0)
114#define NFC_V3_CONFIG2_PS_4096 (2 << 0)
115#define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
116#define NFC_V3_CONFIG2_ECC_EN (1 << 3)
117#define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
118#define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5)
119#define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
71718a8e 120#define NFC_V3_CONFIG2_PPB(x, shift) (((x) & 0x3) << shift)
71ec5155
SH		 121#define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12)
122#define NFC_V3_CONFIG2_INT_MSK (1 << 15)
123#define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
124#define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
125
126#define NFC_V3_CONFIG3 (host->regs_ip + 0x28)
127#define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
128#define NFC_V3_CONFIG3_FW8 (1 << 3)
129#define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
130#define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12)
131#define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
132#define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
133
134#define NFC_V3_IPC (host->regs_ip + 0x2C)
135#define NFC_V3_IPC_CREQ (1 << 0)
136#define NFC_V3_IPC_INT (1 << 31)
137
138#define NFC_V3_DELAY_LINE (host->regs_ip + 0x34)
34f6e157 139
e4303b25
UKK		 140struct mxc_nand_host;
141
142struct mxc_nand_devtype_data {
143 void (*preset)(struct mtd_info *);
144 void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
145 void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
146 void (*send_page)(struct mtd_info *, unsigned int);
147 void (*send_read_id)(struct mxc_nand_host *);
148 uint16_t (*get_dev_status)(struct mxc_nand_host *);
149 int (*check_int)(struct mxc_nand_host *);
150 void (*irq_control)(struct mxc_nand_host *, int);
6d38af25 151 u32 (*get_ecc_status)(struct mxc_nand_host *);
6dcdf99d 152 struct nand_ecclayout *ecclayout_512, *ecclayout_2k, *ecclayout_4k;
5e05a2d6 153 void (*select_chip)(struct mtd_info *mtd, int chip);
69d023be
UKK		 154 int (*correct_data)(struct mtd_info *mtd, u_char *dat,
155 u_char *read_ecc, u_char *calc_ecc);
f48d0f9a
UKK		 156
157 /*
158 * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked
159 * (CONFIG1:INT_MSK is set). To handle this the driver uses
160 * enable_irq/disable_irq_nosync instead of CONFIG1:INT_MSK
161 */
162 int irqpending_quirk;
163 int needs_ip;
164
165 size_t regs_offset;
166 size_t spare0_offset;
167 size_t axi_offset;
168
169 int spare_len;
170 int eccbytes;
171 int eccsize;
71718a8e 172 int ppb_shift;
e4303b25
UKK		 173};
174
34f6e157
SH		 175struct mxc_nand_host {
176 struct mtd_info mtd;
177 struct nand_chip nand;
34f6e157
SH		 178 struct device *dev;
179
4b6f05e1
UKK		 180 void __iomem *spare0;
181 void __iomem *main_area0;
c6de7e1b
SH		 182
183 void __iomem *base;
34f6e157 184 void __iomem *regs;
71ec5155
SH		 185 void __iomem *regs_axi;
186 void __iomem *regs_ip;
34f6e157 187 int status_request;
34f6e157
SH		 188 struct clk *clk;
189 int clk_act;
190 int irq;
94f77e50 191 int eccsize;
d178e3e8 192 int active_cs;
34f6e157 193
63f1474c 194 struct completion op_completion;
34f6e157 195
f8f9608d
SH		 196 uint8_t *data_buf;
197 unsigned int buf_start;
5f97304e 198
e4303b25 199 const struct mxc_nand_devtype_data *devtype_data;
6436356b 200 struct mxc_nand_platform_data pdata;
34f6e157
SH		 201};
202
34f6e157 203/* OOB placement block for use with hardware ecc generation */
9467114e 204static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
34f6e157
SH		 205 .eccbytes = 5,
206 .eccpos = {6, 7, 8, 9, 10},
8c1fd89a 207 .oobfree = {{0, 5}, {12, 4}, }
bd3fd62e
VB		 208};
209
9467114e 210static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
bd3fd62e
VB		 211 .eccbytes = 20,
212 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
213 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
214 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
34f6e157
SH		 215};
216
9467114e
SH		 217/* OOB description for 512 byte pages with 16 byte OOB */
218static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
219 .eccbytes = 1 * 9,
220 .eccpos = {
221 7, 8, 9, 10, 11, 12, 13, 14, 15
222 },
223 .oobfree = {
224 {.offset = 0, .length = 5}
225 }
226};
227
228/* OOB description for 2048 byte pages with 64 byte OOB */
229static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
230 .eccbytes = 4 * 9,
231 .eccpos = {
232 7, 8, 9, 10, 11, 12, 13, 14, 15,
233 23, 24, 25, 26, 27, 28, 29, 30, 31,
234 39, 40, 41, 42, 43, 44, 45, 46, 47,
235 55, 56, 57, 58, 59, 60, 61, 62, 63
236 },
237 .oobfree = {
238 {.offset = 2, .length = 4},
239 {.offset = 16, .length = 7},
240 {.offset = 32, .length = 7},
241 {.offset = 48, .length = 7}
242 }
243};
244
2c1c5f19
BS		 245/* OOB description for 4096 byte pages with 128 byte OOB */
246static struct nand_ecclayout nandv2_hw_eccoob_4k = {
247 .eccbytes = 8 * 9,
248 .eccpos = {
249 7, 8, 9, 10, 11, 12, 13, 14, 15,
250 23, 24, 25, 26, 27, 28, 29, 30, 31,
251 39, 40, 41, 42, 43, 44, 45, 46, 47,
252 55, 56, 57, 58, 59, 60, 61, 62, 63,
253 71, 72, 73, 74, 75, 76, 77, 78, 79,
254 87, 88, 89, 90, 91, 92, 93, 94, 95,
255 103, 104, 105, 106, 107, 108, 109, 110, 111,
256 119, 120, 121, 122, 123, 124, 125, 126, 127,
257 },
258 .oobfree = {
259 {.offset = 2, .length = 4},
260 {.offset = 16, .length = 7},
261 {.offset = 32, .length = 7},
262 {.offset = 48, .length = 7},
263 {.offset = 64, .length = 7},
264 {.offset = 80, .length = 7},
265 {.offset = 96, .length = 7},
266 {.offset = 112, .length = 7},
267 }
268};
269
b2ac0376 270static const char * const part_probes[] = {
740bb0c4 271 "cmdlinepart", "RedBoot", "ofpart", NULL };
34f6e157 272
096bcc23
SH		 273static void memcpy32_fromio(void *trg, const void __iomem *src, size_t size)
274{
275 int i;
276 u32 *t = trg;
277 const __iomem u32 *s = src;
278
279 for (i = 0; i < (size >> 2); i++)
280 *t++ = __raw_readl(s++);
281}
282
33a87a15 283static inline void memcpy32_toio(void __iomem *trg, const void *src, int size)
096bcc23 284{
33a87a15
KV		 285 /* __iowrite32_copy use 32bit size values so divide by 4 */
286 __iowrite32_copy(trg, src, size / 4);
096bcc23
SH		 287}
288
71ec5155
SH		 289static int check_int_v3(struct mxc_nand_host *host)
290{
291 uint32_t tmp;
292
293 tmp = readl(NFC_V3_IPC);
294 if (!(tmp & NFC_V3_IPC_INT))
295 return 0;
296
297 tmp &= ~NFC_V3_IPC_INT;
298 writel(tmp, NFC_V3_IPC);
299
300 return 1;
301}
302
7aaf28ac
SH		 303static int check_int_v1_v2(struct mxc_nand_host *host)
304{
305 uint32_t tmp;
306
1bc99180
SH		 307 tmp = readw(NFC_V1_V2_CONFIG2);
308 if (!(tmp & NFC_V1_V2_CONFIG2_INT))
7aaf28ac
SH		 309 return 0;
310
f48d0f9a 311 if (!host->devtype_data->irqpending_quirk)
63f1474c 312 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
7aaf28ac
SH		 313
314 return 1;
315}
316
63f1474c
SH		 317static void irq_control_v1_v2(struct mxc_nand_host *host, int activate)
318{
319 uint16_t tmp;
320
321 tmp = readw(NFC_V1_V2_CONFIG1);
322
323 if (activate)
324 tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK;
325 else
326 tmp |= NFC_V1_V2_CONFIG1_INT_MSK;
327
328 writew(tmp, NFC_V1_V2_CONFIG1);
329}
330
331static void irq_control_v3(struct mxc_nand_host *host, int activate)
332{
333 uint32_t tmp;
334
335 tmp = readl(NFC_V3_CONFIG2);
336
337 if (activate)
338 tmp &= ~NFC_V3_CONFIG2_INT_MSK;
339 else
340 tmp |= NFC_V3_CONFIG2_INT_MSK;
341
342 writel(tmp, NFC_V3_CONFIG2);
343}
344
8556958a
UKK		 345static void irq_control(struct mxc_nand_host *host, int activate)
346{
f48d0f9a 347 if (host->devtype_data->irqpending_quirk) {
8556958a
UKK		 348 if (activate)
349 enable_irq(host->irq);
350 else
351 disable_irq_nosync(host->irq);
352 } else {
e4303b25 353 host->devtype_data->irq_control(host, activate);
8556958a
UKK		 354 }
355}
356
6d38af25
UKK		 357static u32 get_ecc_status_v1(struct mxc_nand_host *host)
358{
359 return readw(NFC_V1_V2_ECC_STATUS_RESULT);
360}
361
362static u32 get_ecc_status_v2(struct mxc_nand_host *host)
363{
364 return readl(NFC_V1_V2_ECC_STATUS_RESULT);
365}
366
367static u32 get_ecc_status_v3(struct mxc_nand_host *host)
368{
369 return readl(NFC_V3_ECC_STATUS_RESULT);
370}
371
8556958a
UKK		 372static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
373{
374 struct mxc_nand_host *host = dev_id;
375
e4303b25 376 if (!host->devtype_data->check_int(host))
8556958a
UKK		 377 return IRQ_NONE;
378
379 irq_control(host, 0);
380
381 complete(&host->op_completion);
382
383 return IRQ_HANDLED;
384}
385
34f6e157
SH		 386/* This function polls the NANDFC to wait for the basic operation to
387 * complete by checking the INT bit of config2 register.
388 */
e35d1d8a 389static int wait_op_done(struct mxc_nand_host *host, int useirq)
34f6e157 390{
e35d1d8a
UKK		 391 int ret = 0;
392
393 /*
394 * If operation is already complete, don't bother to setup an irq or a
395 * loop.
396 */
397 if (host->devtype_data->check_int(host))
398 return 0;
34f6e157
SH		 399
400 if (useirq) {
e35d1d8a
UKK		 401 unsigned long timeout;
402
403 reinit_completion(&host->op_completion);
404
405 irq_control(host, 1);
406
407 timeout = wait_for_completion_timeout(&host->op_completion, HZ);
408 if (!timeout && !host->devtype_data->check_int(host)) {
409 dev_dbg(host->dev, "timeout waiting for irq\n");
410 ret = -ETIMEDOUT;
34f6e157
SH		 411 }
412 } else {
e35d1d8a
UKK		 413 int max_retries = 8000;
414 int done;
7aaf28ac 415
e35d1d8a 416 do {
34f6e157 417 udelay(1);
e35d1d8a
UKK		 418
419 done = host->devtype_data->check_int(host);
420 if (done)
421 break;
422
423 } while (--max_retries);
424
425 if (!done) {
426 dev_dbg(host->dev, "timeout polling for completion\n");
427 ret = -ETIMEDOUT;
34f6e157 428 }
34f6e157 429 }
e35d1d8a
UKK		 430
431 WARN_ONCE(ret < 0, "timeout! useirq=%d\n", useirq);
432
433 return ret;
34f6e157
SH		 434}
435
71ec5155
SH		 436static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
437{
438 /* fill command */
439 writel(cmd, NFC_V3_FLASH_CMD);
440
441 /* send out command */
442 writel(NFC_CMD, NFC_V3_LAUNCH);
443
444 /* Wait for operation to complete */
445 wait_op_done(host, useirq);
446}
447
34f6e157
SH		 448/* This function issues the specified command to the NAND device and
449 * waits for completion. */
5f97304e 450static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
34f6e157 451{
289c0522 452 pr_debug("send_cmd(host, 0x%x, %d)\n", cmd, useirq);
34f6e157 453
1bc99180
SH		 454 writew(cmd, NFC_V1_V2_FLASH_CMD);
455 writew(NFC_CMD, NFC_V1_V2_CONFIG2);
34f6e157 456
f48d0f9a 457 if (host->devtype_data->irqpending_quirk && (cmd == NAND_CMD_RESET)) {
a47bfd2e
IC		 458 int max_retries = 100;
459 /* Reset completion is indicated by NFC_CONFIG2 */
460 /* being set to 0 */
461 while (max_retries-- > 0) {
1bc99180 462 if (readw(NFC_V1_V2_CONFIG2) == 0) {
a47bfd2e
IC		 463 break;
464 }
465 udelay(1);
466 }
467 if (max_retries < 0)
0a32a102 468 pr_debug("%s: RESET failed\n", __func__);
a47bfd2e
IC		 469 } else {
470 /* Wait for operation to complete */
471 wait_op_done(host, useirq);
472 }
34f6e157
SH		 473}
474
71ec5155
SH		 475static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
476{
477 /* fill address */
478 writel(addr, NFC_V3_FLASH_ADDR0);
479
480 /* send out address */
481 writel(NFC_ADDR, NFC_V3_LAUNCH);
482
483 wait_op_done(host, 0);
484}
485
34f6e157
SH		 486/* This function sends an address (or partial address) to the
487 * NAND device. The address is used to select the source/destination for
488 * a NAND command. */
5f97304e 489static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
34f6e157 490{
289c0522 491 pr_debug("send_addr(host, 0x%x %d)\n", addr, islast);
34f6e157 492
1bc99180
SH		 493 writew(addr, NFC_V1_V2_FLASH_ADDR);
494 writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
34f6e157
SH		 495
496 /* Wait for operation to complete */
c110eaf4 497 wait_op_done(host, islast);
34f6e157
SH		 498}
499
71ec5155
SH		 500static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
501{
502 struct nand_chip *nand_chip = mtd->priv;
503 struct mxc_nand_host *host = nand_chip->priv;
504 uint32_t tmp;
505
506 tmp = readl(NFC_V3_CONFIG1);
507 tmp &= ~(7 << 4);
508 writel(tmp, NFC_V3_CONFIG1);
509
510 /* transfer data from NFC ram to nand */
511 writel(ops, NFC_V3_LAUNCH);
512
513 wait_op_done(host, false);
514}
515
6d38af25
UKK		 516static void send_page_v2(struct mtd_info *mtd, unsigned int ops)
517{
518 struct nand_chip *nand_chip = mtd->priv;
519 struct mxc_nand_host *host = nand_chip->priv;
520
521 /* NANDFC buffer 0 is used for page read/write */
522 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
523
524 writew(ops, NFC_V1_V2_CONFIG2);
525
526 /* Wait for operation to complete */
527 wait_op_done(host, true);
528}
529
530static void send_page_v1(struct mtd_info *mtd, unsigned int ops)
34f6e157 531{
2d69c7fa
SH		 532 struct nand_chip *nand_chip = mtd->priv;
533 struct mxc_nand_host *host = nand_chip->priv;
c5d23f1b 534 int bufs, i;
34f6e157 535
6d38af25 536 if (mtd->writesize > 512)
c5d23f1b
SH		 537 bufs = 4;
538 else
539 bufs = 1;
34f6e157 540
c5d23f1b 541 for (i = 0; i < bufs; i++) {
34f6e157 542
c5d23f1b 543 /* NANDFC buffer 0 is used for page read/write */
d178e3e8 544 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
34f6e157 545
1bc99180 546 writew(ops, NFC_V1_V2_CONFIG2);
34f6e157 547
c5d23f1b 548 /* Wait for operation to complete */
c110eaf4 549 wait_op_done(host, true);
34f6e157 550 }
34f6e157
SH		 551}
552
71ec5155
SH		 553static void send_read_id_v3(struct mxc_nand_host *host)
554{
555 /* Read ID into main buffer */
556 writel(NFC_ID, NFC_V3_LAUNCH);
557
558 wait_op_done(host, true);
559
096bcc23 560 memcpy32_fromio(host->data_buf, host->main_area0, 16);
71ec5155
SH		 561}
562
34f6e157 563/* Request the NANDFC to perform a read of the NAND device ID. */
5f97304e 564static void send_read_id_v1_v2(struct mxc_nand_host *host)
34f6e157 565{
34f6e157 566 /* NANDFC buffer 0 is used for device ID output */
d178e3e8 567 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
34f6e157 568
1bc99180 569 writew(NFC_ID, NFC_V1_V2_CONFIG2);
34f6e157
SH		 570
571 /* Wait for operation to complete */
c110eaf4 572 wait_op_done(host, true);
34f6e157 573
096bcc23 574 memcpy32_fromio(host->data_buf, host->main_area0, 16);
34f6e157
SH		 575}
576
71ec5155
SH		 577static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
578{
579 writew(NFC_STATUS, NFC_V3_LAUNCH);
580 wait_op_done(host, true);
581
582 return readl(NFC_V3_CONFIG1) >> 16;
583}
584
34f6e157
SH		 585/* This function requests the NANDFC to perform a read of the
586 * NAND device status and returns the current status. */
5f97304e 587static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
34f6e157 588{
c29c607a 589 void __iomem *main_buf = host->main_area0;
34f6e157 590 uint32_t store;
f06368f7 591 uint16_t ret;
34f6e157 592
d178e3e8 593 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
34f6e157 594
c29c607a
SH		 595 /*
596 * The device status is stored in main_area0. To
597 * prevent corruption of the buffer save the value
598 * and restore it afterwards.
599 */
34f6e157 600 store = readl(main_buf);
34f6e157 601
1bc99180 602 writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
c110eaf4 603 wait_op_done(host, true);
34f6e157 604
34f6e157 605 ret = readw(main_buf);
c29c607a 606
34f6e157
SH		 607 writel(store, main_buf);
608
609 return ret;
610}
611
612/* This functions is used by upper layer to checks if device is ready */
613static int mxc_nand_dev_ready(struct mtd_info *mtd)
614{
615 /*
616 * NFC handles R/B internally. Therefore, this function
617 * always returns status as ready.
618 */
619 return 1;
620}
621
622static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
623{
624 /*
625 * If HW ECC is enabled, we turn it on during init. There is
626 * no need to enable again here.
627 */
628}
629
94f77e50 630static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat,
34f6e157
SH		 631 u_char *read_ecc, u_char *calc_ecc)
632{
633 struct nand_chip *nand_chip = mtd->priv;
634 struct mxc_nand_host *host = nand_chip->priv;
635
636 /*
637 * 1-Bit errors are automatically corrected in HW. No need for
638 * additional correction. 2-Bit errors cannot be corrected by
639 * HW ECC, so we need to return failure
640 */
6d38af25 641 uint16_t ecc_status = get_ecc_status_v1(host);
34f6e157
SH		 642
643 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
289c0522 644 pr_debug("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
34f6e157
SH		 645 return -1;
646 }
647
648 return 0;
649}
650
94f77e50
SH		 651static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat,
652 u_char *read_ecc, u_char *calc_ecc)
653{
654 struct nand_chip *nand_chip = mtd->priv;
655 struct mxc_nand_host *host = nand_chip->priv;
656 u32 ecc_stat, err;
657 int no_subpages = 1;
658 int ret = 0;
659 u8 ecc_bit_mask, err_limit;
660
661 ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
662 err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
663
664 no_subpages = mtd->writesize >> 9;
665
6d38af25 666 ecc_stat = host->devtype_data->get_ecc_status(host);
94f77e50
SH		 667
668 do {
669 err = ecc_stat & ecc_bit_mask;
670 if (err > err_limit) {
671 printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
672 return -1;
673 } else {
674 ret += err;
675 }
676 ecc_stat >>= 4;
677 } while (--no_subpages);
678
94f77e50
SH		 679 pr_debug("%d Symbol Correctable RS-ECC Error\n", ret);
680
681 return ret;
682}
683
34f6e157
SH		 684static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
685 u_char *ecc_code)
686{
687 return 0;
688}
689
690static u_char mxc_nand_read_byte(struct mtd_info *mtd)
691{
692 struct nand_chip *nand_chip = mtd->priv;
693 struct mxc_nand_host *host = nand_chip->priv;
f8f9608d 694 uint8_t ret;
34f6e157
SH		 695
696 /* Check for status request */
697 if (host->status_request)
e4303b25 698 return host->devtype_data->get_dev_status(host) & 0xFF;
34f6e157 699
3f410690
UKK		 700 if (nand_chip->options & NAND_BUSWIDTH_16) {
701 /* only take the lower byte of each word */
702 ret = *(uint16_t *)(host->data_buf + host->buf_start);
703
704 host->buf_start += 2;
705 } else {
706 ret = *(uint8_t *)(host->data_buf + host->buf_start);
707 host->buf_start++;
708 }
34f6e157 709
3f410690 710 pr_debug("%s: ret=0x%hhx (start=%u)\n", __func__, ret, host->buf_start);
34f6e157
SH		 711 return ret;
712}
713
714static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
715{
716 struct nand_chip *nand_chip = mtd->priv;
717 struct mxc_nand_host *host = nand_chip->priv;
f8f9608d 718 uint16_t ret;
34f6e157 719
f8f9608d
SH		 720 ret = *(uint16_t *)(host->data_buf + host->buf_start);
721 host->buf_start += 2;
34f6e157
SH		 722
723 return ret;
724}
725
726/* Write data of length len to buffer buf. The data to be
727 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
728 * Operation by the NFC, the data is written to NAND Flash */
729static void mxc_nand_write_buf(struct mtd_info *mtd,
730 const u_char *buf, int len)
731{
732 struct nand_chip *nand_chip = mtd->priv;
733 struct mxc_nand_host *host = nand_chip->priv;
f8f9608d
SH		 734 u16 col = host->buf_start;
735 int n = mtd->oobsize + mtd->writesize - col;
34f6e157 736
f8f9608d 737 n = min(n, len);
34f6e157 738
f8f9608d 739 memcpy(host->data_buf + col, buf, n);
34f6e157 740
f8f9608d 741 host->buf_start += n;
34f6e157
SH		 742}
743
744/* Read the data buffer from the NAND Flash. To read the data from NAND
745 * Flash first the data output cycle is initiated by the NFC, which copies
746 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
747 */
748static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
749{
750 struct nand_chip *nand_chip = mtd->priv;
751 struct mxc_nand_host *host = nand_chip->priv;
f8f9608d
SH		 752 u16 col = host->buf_start;
753 int n = mtd->oobsize + mtd->writesize - col;
34f6e157 754
f8f9608d 755 n = min(n, len);
34f6e157 756
5d9d9936 757 memcpy(buf, host->data_buf + col, n);
34f6e157 758
5d9d9936 759 host->buf_start += n;
34f6e157
SH		 760}
761
34f6e157
SH		 762/* This function is used by upper layer for select and
763 * deselect of the NAND chip */
5e05a2d6 764static void mxc_nand_select_chip_v1_v3(struct mtd_info *mtd, int chip)
34f6e157
SH		 765{
766 struct nand_chip *nand_chip = mtd->priv;
767 struct mxc_nand_host *host = nand_chip->priv;
768
d178e3e8 769 if (chip == -1) {
34f6e157
SH		 770 /* Disable the NFC clock */
771 if (host->clk_act) {
97c3213f 772 clk_disable_unprepare(host->clk);
34f6e157
SH		 773 host->clk_act = 0;
774 }
d178e3e8
BS		 775 return;
776 }
777
778 if (!host->clk_act) {
34f6e157 779 /* Enable the NFC clock */
97c3213f 780 clk_prepare_enable(host->clk);
d178e3e8
BS		 781 host->clk_act = 1;
782 }
5e05a2d6 783}
34f6e157 784
5e05a2d6
UKK		 785static void mxc_nand_select_chip_v2(struct mtd_info *mtd, int chip)
786{
787 struct nand_chip *nand_chip = mtd->priv;
788 struct mxc_nand_host *host = nand_chip->priv;
789
790 if (chip == -1) {
791 /* Disable the NFC clock */
792 if (host->clk_act) {
3d059693 793 clk_disable_unprepare(host->clk);
5e05a2d6
UKK		 794 host->clk_act = 0;
795 }
796 return;
797 }
34f6e157 798
5e05a2d6
UKK		 799 if (!host->clk_act) {
800 /* Enable the NFC clock */
3d059693 801 clk_prepare_enable(host->clk);
5e05a2d6 802 host->clk_act = 1;
34f6e157 803 }
5e05a2d6
UKK		 804
805 host->active_cs = chip;
806 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
34f6e157
SH		 807}
808
f8f9608d 809/*
35d5d20e
UKK		 810 * The controller splits a page into data chunks of 512 bytes + partial oob.
811 * There are writesize / 512 such chunks, the size of the partial oob parts is
812 * oobsize / #chunks rounded down to a multiple of 2. The last oob chunk then
813 * contains additionally the byte lost by rounding (if any).
814 * This function handles the needed shuffling between host->data_buf (which
815 * holds a page in natural order, i.e. writesize bytes data + oobsize bytes
816 * spare) and the NFC buffer.
f8f9608d
SH		 817 */
818static void copy_spare(struct mtd_info *mtd, bool bfrom)
34f6e157 819{
f8f9608d
SH		 820 struct nand_chip *this = mtd->priv;
821 struct mxc_nand_host *host = this->priv;
35d5d20e
UKK		 822 u16 i, oob_chunk_size;
823 u16 num_chunks = mtd->writesize / 512;
824
f8f9608d 825 u8 *d = host->data_buf + mtd->writesize;
4b6f05e1 826 u8 __iomem *s = host->spare0;
35d5d20e 827 u16 sparebuf_size = host->devtype_data->spare_len;
f8f9608d 828
35d5d20e
UKK		 829 /* size of oob chunk for all but possibly the last one */
830 oob_chunk_size = (mtd->oobsize / num_chunks) & ~1;
f8f9608d
SH		 831
832 if (bfrom) {
35d5d20e
UKK		 833 for (i = 0; i < num_chunks - 1; i++)
834 memcpy32_fromio(d + i * oob_chunk_size,
835 s + i * sparebuf_size,
836 oob_chunk_size);
837
838 /* the last chunk */
839 memcpy32_fromio(d + i * oob_chunk_size,
840 s + i * sparebuf_size,
841 mtd->oobsize - i * oob_chunk_size);
f8f9608d 842 } else {
35d5d20e
UKK		 843 for (i = 0; i < num_chunks - 1; i++)
844 memcpy32_toio(&s[i * sparebuf_size],
845 &d[i * oob_chunk_size],
846 oob_chunk_size);
847
848 /* the last chunk */
849 memcpy32_toio(&s[oob_chunk_size * sparebuf_size],
850 &d[i * oob_chunk_size],
851 mtd->oobsize - i * oob_chunk_size);
34f6e157 852 }
f8f9608d 853}
34f6e157 854
c4ca3997
UKK		 855/*
856 * MXC NANDFC can only perform full page+spare or spare-only read/write. When
857 * the upper layers perform a read/write buf operation, the saved column address
858 * is used to index into the full page. So usually this function is called with
859 * column == 0 (unless no column cycle is needed indicated by column == -1)
860 */
a3e65b64
SH		 861static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
862{
863 struct nand_chip *nand_chip = mtd->priv;
864 struct mxc_nand_host *host = nand_chip->priv;
34f6e157
SH		 865
866 /* Write out column address, if necessary */
867 if (column != -1) {
c4ca3997
UKK		 868 host->devtype_data->send_addr(host, column & 0xff,
869 page_addr == -1);
2d69c7fa 870 if (mtd->writesize > 512)
34f6e157 871 /* another col addr cycle for 2k page */
c4ca3997
UKK		 872 host->devtype_data->send_addr(host,
873 (column >> 8) & 0xff,
874 false);
34f6e157
SH		 875 }
876
877 /* Write out page address, if necessary */
878 if (page_addr != -1) {
879 /* paddr_0 - p_addr_7 */
e4303b25 880 host->devtype_data->send_addr(host, (page_addr & 0xff), false);
34f6e157 881
2d69c7fa 882 if (mtd->writesize > 512) {
bd3fd62e
VB		 883 if (mtd->size >= 0x10000000) {
884 /* paddr_8 - paddr_15 */
e4303b25
UKK		 885 host->devtype_data->send_addr(host,
886 (page_addr >> 8) & 0xff,
887 false);
888 host->devtype_data->send_addr(host,
889 (page_addr >> 16) & 0xff,
890 true);
bd3fd62e
VB		 891 } else
892 /* paddr_8 - paddr_15 */
e4303b25
UKK		 893 host->devtype_data->send_addr(host,
894 (page_addr >> 8) & 0xff, true);
34f6e157
SH		 895 } else {
896 /* One more address cycle for higher density devices */
897 if (mtd->size >= 0x4000000) {
898 /* paddr_8 - paddr_15 */
e4303b25
UKK		 899 host->devtype_data->send_addr(host,
900 (page_addr >> 8) & 0xff,
901 false);
902 host->devtype_data->send_addr(host,
903 (page_addr >> 16) & 0xff,
904 true);
34f6e157
SH		 905 } else
906 /* paddr_8 - paddr_15 */
e4303b25
UKK		 907 host->devtype_data->send_addr(host,
908 (page_addr >> 8) & 0xff, true);
34f6e157
SH		 909 }
910 }
a3e65b64
SH		 911}
912
6e85dfdc
SH		 913/*
914 * v2 and v3 type controllers can do 4bit or 8bit ecc depending
915 * on how much oob the nand chip has. For 8bit ecc we need at least
916 * 26 bytes of oob data per 512 byte block.
917 */
918static int get_eccsize(struct mtd_info *mtd)
919{
920 int oobbytes_per_512 = 0;
921
922 oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
923
924 if (oobbytes_per_512 < 26)
925 return 4;
926 else
927 return 8;
928}
929
6d38af25 930static void preset_v1(struct mtd_info *mtd)
d4840180
IC		 931{
932 struct nand_chip *nand_chip = mtd->priv;
933 struct mxc_nand_host *host = nand_chip->priv;
b8db2f51
SH		 934 uint16_t config1 = 0;
935
1f42adc8 936 if (nand_chip->ecc.mode == NAND_ECC_HW && mtd->writesize)
b8db2f51
SH		 937 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
938
f48d0f9a 939 if (!host->devtype_data->irqpending_quirk)
6d38af25
UKK		 940 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
941
942 host->eccsize = 1;
943
944 writew(config1, NFC_V1_V2_CONFIG1);
945 /* preset operation */
946
947 /* Unlock the internal RAM Buffer */
948 writew(0x2, NFC_V1_V2_CONFIG);
949
950 /* Blocks to be unlocked */
951 writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
952 writew(0xffff, NFC_V1_UNLOCKEND_BLKADDR);
953
954 /* Unlock Block Command for given address range */
955 writew(0x4, NFC_V1_V2_WRPROT);
956}
957
958static void preset_v2(struct mtd_info *mtd)
d4840180
IC		 959{
960 struct nand_chip *nand_chip = mtd->priv;
961 struct mxc_nand_host *host = nand_chip->priv;
b8db2f51
SH		 962 uint16_t config1 = 0;
963
6d38af25 964 config1 |= NFC_V2_CONFIG1_FP_INT;
b8db2f51 965
f48d0f9a 966 if (!host->devtype_data->irqpending_quirk)
b8db2f51 967 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
6e85dfdc 968
6d38af25 969 if (mtd->writesize) {
b8db2f51
SH		 970 uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
971
1f42adc8
UKK		 972 if (nand_chip->ecc.mode == NAND_ECC_HW)
973 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
974
6e85dfdc
SH		 975 host->eccsize = get_eccsize(mtd);
976 if (host->eccsize == 4)
b8db2f51
SH		 977 config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
978
979 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
d4840180 980 } else {
6e85dfdc 981 host->eccsize = 1;
d4840180 982 }
6e85dfdc 983
b8db2f51 984 writew(config1, NFC_V1_V2_CONFIG1);
d4840180
IC		 985 /* preset operation */
986
987 /* Unlock the internal RAM Buffer */
1bc99180 988 writew(0x2, NFC_V1_V2_CONFIG);
d4840180
IC		 989
990 /* Blocks to be unlocked */
6d38af25
UKK		 991 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0);
992 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1);
993 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2);
994 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3);
995 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0);
996 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1);
997 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2);
998 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3);
d4840180
IC		 999
1000 /* Unlock Block Command for given address range */
1bc99180 1001 writew(0x4, NFC_V1_V2_WRPROT);
d4840180
IC		 1002}
1003
71ec5155
SH		 1004static void preset_v3(struct mtd_info *mtd)
1005{
1006 struct nand_chip *chip = mtd->priv;
1007 struct mxc_nand_host *host = chip->priv;
1008 uint32_t config2, config3;
1009 int i, addr_phases;
1010
1011 writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
1012 writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
1013
1014 /* Unlock the internal RAM Buffer */
1015 writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
1016 NFC_V3_WRPROT);
1017
1018 /* Blocks to be unlocked */
1019 for (i = 0; i < NAND_MAX_CHIPS; i++)
1020 writel(0x0 | (0xffff << 16),
1021 NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
1022
1023 writel(0, NFC_V3_IPC);
1024
1025 config2 = NFC_V3_CONFIG2_ONE_CYCLE |
1026 NFC_V3_CONFIG2_2CMD_PHASES |
1027 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
1028 NFC_V3_CONFIG2_ST_CMD(0x70) |
63f1474c 1029 NFC_V3_CONFIG2_INT_MSK |
71ec5155
SH		 1030 NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
1031
71ec5155
SH		 1032 addr_phases = fls(chip->pagemask) >> 3;
1033
1034 if (mtd->writesize == 2048) {
1035 config2 |= NFC_V3_CONFIG2_PS_2048;
1036 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1037 } else if (mtd->writesize == 4096) {
1038 config2 |= NFC_V3_CONFIG2_PS_4096;
1039 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1040 } else {
1041 config2 |= NFC_V3_CONFIG2_PS_512;
1042 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
1043 }
1044
1045 if (mtd->writesize) {
1f42adc8
UKK		 1046 if (chip->ecc.mode == NAND_ECC_HW)
1047 config2 |= NFC_V3_CONFIG2_ECC_EN;
1048
71718a8e
SH		 1049 config2 |= NFC_V3_CONFIG2_PPB(
1050 ffs(mtd->erasesize / mtd->writesize) - 6,
1051 host->devtype_data->ppb_shift);
71ec5155
SH		 1052 host->eccsize = get_eccsize(mtd);
1053 if (host->eccsize == 8)
1054 config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
1055 }
1056
1057 writel(config2, NFC_V3_CONFIG2);
1058
1059 config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
1060 NFC_V3_CONFIG3_NO_SDMA |
1061 NFC_V3_CONFIG3_RBB_MODE |
1062 NFC_V3_CONFIG3_SBB(6) | /* Reset default */
1063 NFC_V3_CONFIG3_ADD_OP(0);
1064
1065 if (!(chip->options & NAND_BUSWIDTH_16))
1066 config3 |= NFC_V3_CONFIG3_FW8;
1067
1068 writel(config3, NFC_V3_CONFIG3);
1069
1070 writel(0, NFC_V3_DELAY_LINE);
d4840180
IC		 1071}
1072
34f6e157
SH		 1073/* Used by the upper layer to write command to NAND Flash for
1074 * different operations to be carried out on NAND Flash */
1075static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
1076 int column, int page_addr)
1077{
1078 struct nand_chip *nand_chip = mtd->priv;
1079 struct mxc_nand_host *host = nand_chip->priv;
34f6e157 1080
289c0522 1081 pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
34f6e157
SH		 1082 command, column, page_addr);
1083
1084 /* Reset command state information */
1085 host->status_request = false;
34f6e157 1086
34f6e157 1087 /* Command pre-processing step */
34f6e157 1088 switch (command) {
d4840180 1089 case NAND_CMD_RESET:
e4303b25
UKK		 1090 host->devtype_data->preset(mtd);
1091 host->devtype_data->send_cmd(host, command, false);
d4840180 1092 break;
34f6e157 1093
34f6e157 1094 case NAND_CMD_STATUS:
f8f9608d 1095 host->buf_start = 0;
34f6e157 1096 host->status_request = true;
34f6e157 1097
e4303b25 1098 host->devtype_data->send_cmd(host, command, true);
c4ca3997
UKK		 1099 WARN_ONCE(column != -1 || page_addr != -1,
1100 "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n",
1101 command, column, page_addr);
89121a6b 1102 mxc_do_addr_cycle(mtd, column, page_addr);
34f6e157
SH		 1103 break;
1104
34f6e157 1105 case NAND_CMD_READ0:
34f6e157 1106 case NAND_CMD_READOOB:
89121a6b
SH		 1107 if (command == NAND_CMD_READ0)
1108 host->buf_start = column;
1109 else
1110 host->buf_start = column + mtd->writesize;
f8f9608d 1111
5ea32021 1112 command = NAND_CMD_READ0; /* only READ0 is valid */
89121a6b 1113
e4303b25 1114 host->devtype_data->send_cmd(host, command, false);
c4ca3997
UKK		 1115 WARN_ONCE(column < 0,
1116 "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n",
1117 command, column, page_addr);
1118 mxc_do_addr_cycle(mtd, 0, page_addr);
89121a6b 1119
2d69c7fa 1120 if (mtd->writesize > 512)
e4303b25
UKK		 1121 host->devtype_data->send_cmd(host,
1122 NAND_CMD_READSTART, true);
c5d23f1b 1123
e4303b25 1124 host->devtype_data->send_page(mtd, NFC_OUTPUT);
89121a6b 1125
096bcc23
SH		 1126 memcpy32_fromio(host->data_buf, host->main_area0,
1127 mtd->writesize);
89121a6b 1128 copy_spare(mtd, true);
34f6e157
SH		 1129 break;
1130
34f6e157 1131 case NAND_CMD_SEQIN:
5ea32021
SH		 1132 if (column >= mtd->writesize)
1133 /* call ourself to read a page */
1134 mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
34f6e157 1135
5ea32021 1136 host->buf_start = column;
89121a6b 1137
e4303b25 1138 host->devtype_data->send_cmd(host, command, false);
c4ca3997
UKK		 1139 WARN_ONCE(column < -1,
1140 "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n",
1141 command, column, page_addr);
1142 mxc_do_addr_cycle(mtd, 0, page_addr);
34f6e157
SH		 1143 break;
1144
1145 case NAND_CMD_PAGEPROG:
096bcc23 1146 memcpy32_toio(host->main_area0, host->data_buf, mtd->writesize);
f8f9608d 1147 copy_spare(mtd, false);
e4303b25
UKK		 1148 host->devtype_data->send_page(mtd, NFC_INPUT);
1149 host->devtype_data->send_cmd(host, command, true);
c4ca3997
UKK		 1150 WARN_ONCE(column != -1 || page_addr != -1,
1151 "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n",
1152 command, column, page_addr);
89121a6b 1153 mxc_do_addr_cycle(mtd, column, page_addr);
34f6e157
SH		 1154 break;
1155
34f6e157 1156 case NAND_CMD_READID:
e4303b25 1157 host->devtype_data->send_cmd(host, command, true);
89121a6b 1158 mxc_do_addr_cycle(mtd, column, page_addr);
e4303b25 1159 host->devtype_data->send_read_id(host);
c4ca3997 1160 host->buf_start = 0;
34f6e157
SH		 1161 break;
1162
89121a6b 1163 case NAND_CMD_ERASE1:
34f6e157 1164 case NAND_CMD_ERASE2:
e4303b25 1165 host->devtype_data->send_cmd(host, command, false);
c4ca3997
UKK		 1166 WARN_ONCE(column != -1,
1167 "Unexpected column value (cmd=%u, col=%d)\n",
1168 command, column);
89121a6b
SH		 1169 mxc_do_addr_cycle(mtd, column, page_addr);
1170
3d6e81c0
UKK		 1171 break;
1172 case NAND_CMD_PARAM:
1173 host->devtype_data->send_cmd(host, command, false);
1174 mxc_do_addr_cycle(mtd, column, page_addr);
1175 host->devtype_data->send_page(mtd, NFC_OUTPUT);
1176 memcpy32_fromio(host->data_buf, host->main_area0, 512);
1177 host->buf_start = 0;
34f6e157 1178 break;
98ebb521
UKK		 1179 default:
1180 WARN_ONCE(1, "Unimplemented command (cmd=%u)\n",
1181 command);
1182 break;
34f6e157
SH		 1183 }
1184}
1185
f1372055
SH		 1186/*
1187 * The generic flash bbt decriptors overlap with our ecc
1188 * hardware, so define some i.MX specific ones.
1189 */
1190static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
1191static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
1192
1193static struct nand_bbt_descr bbt_main_descr = {
1194 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1195 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1196 .offs = 0,
1197 .len = 4,
1198 .veroffs = 4,
1199 .maxblocks = 4,
1200 .pattern = bbt_pattern,
1201};
1202
1203static struct nand_bbt_descr bbt_mirror_descr = {
1204 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1205 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1206 .offs = 0,
1207 .len = 4,
1208 .veroffs = 4,
1209 .maxblocks = 4,
1210 .pattern = mirror_pattern,
1211};
1212
f48d0f9a 1213/* v1 + irqpending_quirk: i.MX21 */
e4303b25 1214static const struct mxc_nand_devtype_data imx21_nand_devtype_data = {
6d38af25 1215 .preset = preset_v1,
e4303b25
UKK		 1216 .send_cmd = send_cmd_v1_v2,
1217 .send_addr = send_addr_v1_v2,
6d38af25 1218 .send_page = send_page_v1,
e4303b25
UKK		 1219 .send_read_id = send_read_id_v1_v2,
1220 .get_dev_status = get_dev_status_v1_v2,
1221 .check_int = check_int_v1_v2,
1222 .irq_control = irq_control_v1_v2,
6d38af25 1223 .get_ecc_status = get_ecc_status_v1,
6dcdf99d
UKK		 1224 .ecclayout_512 = &nandv1_hw_eccoob_smallpage,
1225 .ecclayout_2k = &nandv1_hw_eccoob_largepage,
1226 .ecclayout_4k = &nandv1_hw_eccoob_smallpage, /* XXX: needs fix */
5e05a2d6 1227 .select_chip = mxc_nand_select_chip_v1_v3,
69d023be 1228 .correct_data = mxc_nand_correct_data_v1,
f48d0f9a
UKK		 1229 .irqpending_quirk = 1,
1230 .needs_ip = 0,
1231 .regs_offset = 0xe00,
1232 .spare0_offset = 0x800,
1233 .spare_len = 16,
1234 .eccbytes = 3,
1235 .eccsize = 1,
1236};
1237
1238/* v1 + !irqpending_quirk: i.MX27, i.MX31 */
1239static const struct mxc_nand_devtype_data imx27_nand_devtype_data = {
1240 .preset = preset_v1,
1241 .send_cmd = send_cmd_v1_v2,
1242 .send_addr = send_addr_v1_v2,
1243 .send_page = send_page_v1,
1244 .send_read_id = send_read_id_v1_v2,
1245 .get_dev_status = get_dev_status_v1_v2,
1246 .check_int = check_int_v1_v2,
1247 .irq_control = irq_control_v1_v2,
1248 .get_ecc_status = get_ecc_status_v1,
1249 .ecclayout_512 = &nandv1_hw_eccoob_smallpage,
1250 .ecclayout_2k = &nandv1_hw_eccoob_largepage,
1251 .ecclayout_4k = &nandv1_hw_eccoob_smallpage, /* XXX: needs fix */
1252 .select_chip = mxc_nand_select_chip_v1_v3,
1253 .correct_data = mxc_nand_correct_data_v1,
1254 .irqpending_quirk = 0,
1255 .needs_ip = 0,
1256 .regs_offset = 0xe00,
1257 .spare0_offset = 0x800,
1258 .axi_offset = 0,
1259 .spare_len = 16,
1260 .eccbytes = 3,
1261 .eccsize = 1,
e4303b25
UKK		 1262};
1263
1264/* v21: i.MX25, i.MX35 */
1265static const struct mxc_nand_devtype_data imx25_nand_devtype_data = {
6d38af25 1266 .preset = preset_v2,
e4303b25
UKK		 1267 .send_cmd = send_cmd_v1_v2,
1268 .send_addr = send_addr_v1_v2,
6d38af25 1269 .send_page = send_page_v2,
e4303b25
UKK		 1270 .send_read_id = send_read_id_v1_v2,
1271 .get_dev_status = get_dev_status_v1_v2,
1272 .check_int = check_int_v1_v2,
1273 .irq_control = irq_control_v1_v2,
6d38af25 1274 .get_ecc_status = get_ecc_status_v2,
6dcdf99d
UKK		 1275 .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1276 .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1277 .ecclayout_4k = &nandv2_hw_eccoob_4k,
5e05a2d6 1278 .select_chip = mxc_nand_select_chip_v2,
69d023be 1279 .correct_data = mxc_nand_correct_data_v2_v3,
f48d0f9a
UKK		 1280 .irqpending_quirk = 0,
1281 .needs_ip = 0,
1282 .regs_offset = 0x1e00,
1283 .spare0_offset = 0x1000,
1284 .axi_offset = 0,
1285 .spare_len = 64,
1286 .eccbytes = 9,
1287 .eccsize = 0,
e4303b25
UKK		 1288};
1289
71718a8e 1290/* v3.2a: i.MX51 */
e4303b25
UKK		 1291static const struct mxc_nand_devtype_data imx51_nand_devtype_data = {
1292 .preset = preset_v3,
1293 .send_cmd = send_cmd_v3,
1294 .send_addr = send_addr_v3,
1295 .send_page = send_page_v3,
1296 .send_read_id = send_read_id_v3,
1297 .get_dev_status = get_dev_status_v3,
1298 .check_int = check_int_v3,
1299 .irq_control = irq_control_v3,
6d38af25 1300 .get_ecc_status = get_ecc_status_v3,
6dcdf99d
UKK		 1301 .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1302 .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1303 .ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */
5e05a2d6 1304 .select_chip = mxc_nand_select_chip_v1_v3,
69d023be 1305 .correct_data = mxc_nand_correct_data_v2_v3,
f48d0f9a
UKK		 1306 .irqpending_quirk = 0,
1307 .needs_ip = 1,
1308 .regs_offset = 0,
1309 .spare0_offset = 0x1000,
1310 .axi_offset = 0x1e00,
1311 .spare_len = 64,
1312 .eccbytes = 0,
1313 .eccsize = 0,
71718a8e
SH		 1314 .ppb_shift = 7,
1315};
1316
1317/* v3.2b: i.MX53 */
1318static const struct mxc_nand_devtype_data imx53_nand_devtype_data = {
1319 .preset = preset_v3,
1320 .send_cmd = send_cmd_v3,
1321 .send_addr = send_addr_v3,
1322 .send_page = send_page_v3,
1323 .send_read_id = send_read_id_v3,
1324 .get_dev_status = get_dev_status_v3,
1325 .check_int = check_int_v3,
1326 .irq_control = irq_control_v3,
1327 .get_ecc_status = get_ecc_status_v3,
1328 .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1329 .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1330 .ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */
1331 .select_chip = mxc_nand_select_chip_v1_v3,
1332 .correct_data = mxc_nand_correct_data_v2_v3,
1333 .irqpending_quirk = 0,
1334 .needs_ip = 1,
1335 .regs_offset = 0,
1336 .spare0_offset = 0x1000,
1337 .axi_offset = 0x1e00,
1338 .spare_len = 64,
1339 .eccbytes = 0,
1340 .eccsize = 0,
1341 .ppb_shift = 8,
e4303b25
UKK		 1342};
1343
4d62435f
SG		 1344static inline int is_imx21_nfc(struct mxc_nand_host *host)
1345{
1346 return host->devtype_data == &imx21_nand_devtype_data;
1347}
1348
1349static inline int is_imx27_nfc(struct mxc_nand_host *host)
1350{
1351 return host->devtype_data == &imx27_nand_devtype_data;
1352}
1353
1354static inline int is_imx25_nfc(struct mxc_nand_host *host)
1355{
1356 return host->devtype_data == &imx25_nand_devtype_data;
1357}
1358
1359static inline int is_imx51_nfc(struct mxc_nand_host *host)
1360{
1361 return host->devtype_data == &imx51_nand_devtype_data;
1362}
1363
1364static inline int is_imx53_nfc(struct mxc_nand_host *host)
1365{
1366 return host->devtype_data == &imx53_nand_devtype_data;
1367}
1368
8d1e568d 1369static const struct platform_device_id mxcnd_devtype[] = {
4d62435f
SG		 1370 {
1371 .name = "imx21-nand",
1372 .driver_data = (kernel_ulong_t) &imx21_nand_devtype_data,
1373 }, {
1374 .name = "imx27-nand",
1375 .driver_data = (kernel_ulong_t) &imx27_nand_devtype_data,
1376 }, {
1377 .name = "imx25-nand",
1378 .driver_data = (kernel_ulong_t) &imx25_nand_devtype_data,
1379 }, {
1380 .name = "imx51-nand",
1381 .driver_data = (kernel_ulong_t) &imx51_nand_devtype_data,
1382 }, {
1383 .name = "imx53-nand",
1384 .driver_data = (kernel_ulong_t) &imx53_nand_devtype_data,
1385 }, {
1386 /* sentinel */
1387 }
1388};
1389MODULE_DEVICE_TABLE(platform, mxcnd_devtype);
1390
6436356b
UKK		 1391#ifdef CONFIG_OF_MTD
1392static const struct of_device_id mxcnd_dt_ids[] = {
1393 {
1394 .compatible = "fsl,imx21-nand",
1395 .data = &imx21_nand_devtype_data,
1396 }, {
1397 .compatible = "fsl,imx27-nand",
1398 .data = &imx27_nand_devtype_data,
1399 }, {
1400 .compatible = "fsl,imx25-nand",
1401 .data = &imx25_nand_devtype_data,
1402 }, {
1403 .compatible = "fsl,imx51-nand",
1404 .data = &imx51_nand_devtype_data,
71718a8e
SH		 1405 }, {
1406 .compatible = "fsl,imx53-nand",
1407 .data = &imx53_nand_devtype_data,
6436356b
UKK		 1408 },
1409 { /* sentinel */ }
1410};
1411
1412static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
1413{
1414 struct device_node *np = host->dev->of_node;
1415 struct mxc_nand_platform_data *pdata = &host->pdata;
1416 const struct of_device_id *of_id =
1417 of_match_device(mxcnd_dt_ids, host->dev);
1418 int buswidth;
1419
1420 if (!np)
1421 return 1;
1422
1423 if (of_get_nand_ecc_mode(np) >= 0)
1424 pdata->hw_ecc = 1;
1425
1426 pdata->flash_bbt = of_get_nand_on_flash_bbt(np);
1427
1428 buswidth = of_get_nand_bus_width(np);
1429 if (buswidth < 0)
1430 return buswidth;
1431
1432 pdata->width = buswidth / 8;
1433
1434 host->devtype_data = of_id->data;
1435
1436 return 0;
1437}
1438#else
1439static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
1440{
1441 return 1;
1442}
1443#endif
1444
06f25510 1445static int mxcnd_probe(struct platform_device *pdev)
34f6e157
SH		 1446{
1447 struct nand_chip *this;
1448 struct mtd_info *mtd;
34f6e157
SH		 1449 struct mxc_nand_host *host;
1450 struct resource *res;
d4ed8f12 1451 int err = 0;
34f6e157
SH		 1452
1453 /* Allocate memory for MTD device structure and private data */
a5900554
HS		 1454 host = devm_kzalloc(&pdev->dev, sizeof(struct mxc_nand_host),
1455 GFP_KERNEL);
34f6e157
SH		 1456 if (!host)
1457 return -ENOMEM;
1458
a5900554
HS		 1459 /* allocate a temporary buffer for the nand_scan_ident() */
1460 host->data_buf = devm_kzalloc(&pdev->dev, PAGE_SIZE, GFP_KERNEL);
1461 if (!host->data_buf)
1462 return -ENOMEM;
f8f9608d 1463
34f6e157
SH		 1464 host->dev = &pdev->dev;
1465 /* structures must be linked */
1466 this = &host->nand;
1467 mtd = &host->mtd;
1468 mtd->priv = this;
1469 mtd->owner = THIS_MODULE;
87f39f04 1470 mtd->dev.parent = &pdev->dev;
1fbff0a6 1471 mtd->name = DRIVER_NAME;
34f6e157
SH		 1472
1473 /* 50 us command delay time */
1474 this->chip_delay = 5;
1475
1476 this->priv = host;
1477 this->dev_ready = mxc_nand_dev_ready;
1478 this->cmdfunc = mxc_nand_command;
34f6e157
SH		 1479 this->read_byte = mxc_nand_read_byte;
1480 this->read_word = mxc_nand_read_word;
1481 this->write_buf = mxc_nand_write_buf;
1482 this->read_buf = mxc_nand_read_buf;
34f6e157 1483
24b82d3c 1484 host->clk = devm_clk_get(&pdev->dev, NULL);
e4a09cbf
SH		 1485 if (IS_ERR(host->clk))
1486 return PTR_ERR(host->clk);
34f6e157 1487
71885b65 1488 err = mxcnd_probe_dt(host);
4d62435f 1489 if (err > 0) {
453810b7
JH		 1490 struct mxc_nand_platform_data *pdata =
1491 dev_get_platdata(&pdev->dev);
4d62435f
SG		 1492 if (pdata) {
1493 host->pdata = *pdata;
1494 host->devtype_data = (struct mxc_nand_devtype_data *)
1495 pdev->id_entry->driver_data;
1496 } else {
1497 err = -ENODEV;
1498 }
1499 }
71885b65
SH		 1500 if (err < 0)
1501 return err;
1502
1503 if (host->devtype_data->needs_ip) {
1504 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
b0de774c
TR		 1505 host->regs_ip = devm_ioremap_resource(&pdev->dev, res);
1506 if (IS_ERR(host->regs_ip))
1507 return PTR_ERR(host->regs_ip);
71885b65
SH		 1508
1509 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1510 } else {
1511 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1512 }
1513
b0de774c
TR		 1514 host->base = devm_ioremap_resource(&pdev->dev, res);
1515 if (IS_ERR(host->base))
1516 return PTR_ERR(host->base);
34f6e157 1517
c6de7e1b 1518 host->main_area0 = host->base;
9467114e 1519
f48d0f9a
UKK		 1520 if (host->devtype_data->regs_offset)
1521 host->regs = host->base + host->devtype_data->regs_offset;
1522 host->spare0 = host->base + host->devtype_data->spare0_offset;
1523 if (host->devtype_data->axi_offset)
1524 host->regs_axi = host->base + host->devtype_data->axi_offset;
1525
1526 this->ecc.bytes = host->devtype_data->eccbytes;
1527 host->eccsize = host->devtype_data->eccsize;
1528
1529 this->select_chip = host->devtype_data->select_chip;
1530 this->ecc.size = 512;
1531 this->ecc.layout = host->devtype_data->ecclayout_512;
1532
6436356b 1533 if (host->pdata.hw_ecc) {
34f6e157
SH		 1534 this->ecc.calculate = mxc_nand_calculate_ecc;
1535 this->ecc.hwctl = mxc_nand_enable_hwecc;
69d023be 1536 this->ecc.correct = host->devtype_data->correct_data;
34f6e157 1537 this->ecc.mode = NAND_ECC_HW;
34f6e157 1538 } else {
34f6e157 1539 this->ecc.mode = NAND_ECC_SOFT;
34f6e157
SH		 1540 }
1541
6436356b
UKK		 1542 /* NAND bus width determines access functions used by upper layer */
1543 if (host->pdata.width == 2)
34f6e157 1544 this->options |= NAND_BUSWIDTH_16;
34f6e157 1545
6436356b 1546 if (host->pdata.flash_bbt) {
f1372055
SH		 1547 this->bbt_td = &bbt_main_descr;
1548 this->bbt_md = &bbt_mirror_descr;
1549 /* update flash based bbt */
bb9ebd4e 1550 this->bbt_options |= NAND_BBT_USE_FLASH;
34f6e157
SH		 1551 }
1552
63f1474c 1553 init_completion(&host->op_completion);
d4840180
IC		 1554
1555 host->irq = platform_get_irq(pdev, 0);
26fbf48b
FE		 1556 if (host->irq < 0)
1557 return host->irq;
d4840180 1558
63f1474c 1559 /*
e4303b25
UKK		 1560 * Use host->devtype_data->irq_control() here instead of irq_control()
1561 * because we must not disable_irq_nosync without having requested the
1562 * irq.
63f1474c 1563 */
e4303b25 1564 host->devtype_data->irq_control(host, 0);
63f1474c 1565
e4a09cbf 1566 err = devm_request_irq(&pdev->dev, host->irq, mxc_nfc_irq,
b1eb234f 1567 0, DRIVER_NAME, host);
d4840180 1568 if (err)
e4a09cbf
SH		 1569 return err;
1570
dcedf628
FE		 1571 err = clk_prepare_enable(host->clk);
1572 if (err)
1573 return err;
e4a09cbf 1574 host->clk_act = 1;
d4840180 1575
63f1474c 1576 /*
8556958a
UKK		 1577 * Now that we "own" the interrupt make sure the interrupt mask bit is
1578 * cleared on i.MX21. Otherwise we can't read the interrupt status bit
1579 * on this machine.
63f1474c 1580 */
f48d0f9a 1581 if (host->devtype_data->irqpending_quirk) {
8556958a 1582 disable_irq_nosync(host->irq);
e4303b25 1583 host->devtype_data->irq_control(host, 1);
8556958a 1584 }
63f1474c 1585
bd3fd62e 1586 /* first scan to find the device and get the page size */
4d62435f 1587 if (nand_scan_ident(mtd, is_imx25_nfc(host) ? 4 : 1, NULL)) {
bd3fd62e
VB		 1588 err = -ENXIO;
1589 goto escan;
1590 }
34f6e157 1591
a5900554
HS		 1592 /* allocate the right size buffer now */
1593 devm_kfree(&pdev->dev, (void *)host->data_buf);
1594 host->data_buf = devm_kzalloc(&pdev->dev, mtd->writesize + mtd->oobsize,
1595 GFP_KERNEL);
1596 if (!host->data_buf) {
1597 err = -ENOMEM;
1598 goto escan;
1599 }
1600
6e85dfdc 1601 /* Call preset again, with correct writesize this time */
e4303b25 1602 host->devtype_data->preset(mtd);
6e85dfdc 1603
2d69c7fa 1604 if (mtd->writesize == 2048)
6dcdf99d
UKK		 1605 this->ecc.layout = host->devtype_data->ecclayout_2k;
1606 else if (mtd->writesize == 4096)
1607 this->ecc.layout = host->devtype_data->ecclayout_4k;
34f6e157 1608
6a918bad 1609 if (this->ecc.mode == NAND_ECC_HW) {
4d62435f 1610 if (is_imx21_nfc(host) || is_imx27_nfc(host))
6a918bad
MD		 1611 this->ecc.strength = 1;
1612 else
1613 this->ecc.strength = (host->eccsize == 4) ? 4 : 8;
1614 }
1615
4a43faf5
SH		 1616 /* second phase scan */
1617 if (nand_scan_tail(mtd)) {
1618 err = -ENXIO;
1619 goto escan;
1620 }
1621
34f6e157 1622 /* Register the partitions */
6436356b
UKK		 1623 mtd_device_parse_register(mtd, part_probes,
1624 &(struct mtd_part_parser_data){
1625 .of_node = pdev->dev.of_node,
1626 },
1627 host->pdata.parts,
1628 host->pdata.nr_parts);
34f6e157
SH		 1629
1630 platform_set_drvdata(pdev, host);
1631
1632 return 0;
1633
1634escan:
c10d8ee3
LW		 1635 if (host->clk_act)
1636 clk_disable_unprepare(host->clk);
34f6e157
SH		 1637
1638 return err;
1639}
1640
810b7e06 1641static int mxcnd_remove(struct platform_device *pdev)
34f6e157
SH		 1642{
1643 struct mxc_nand_host *host = platform_get_drvdata(pdev);
1644
34f6e157 1645 nand_release(&host->mtd);
8bfd4f7f
WY		 1646 if (host->clk_act)
1647 clk_disable_unprepare(host->clk);
34f6e157
SH		 1648
1649 return 0;
1650}
1651
34f6e157
SH		 1652static struct platform_driver mxcnd_driver = {
1653 .driver = {
1654 .name = DRIVER_NAME,
6436356b 1655 .of_match_table = of_match_ptr(mxcnd_dt_ids),
04dd0d3a 1656 },
4d62435f 1657 .id_table = mxcnd_devtype,
ddf16d62 1658 .probe = mxcnd_probe,
5153b88c 1659 .remove = mxcnd_remove,
34f6e157 1660};
ddf16d62 1661module_platform_driver(mxcnd_driver);
34f6e157
SH		 1662
1663MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1664MODULE_DESCRIPTION("MXC NAND MTD driver");
1665MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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