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34f6e157 SH |
1 | /* |
2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * Copyright 2008 Sascha Hauer, kernel@pengutronix.de | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
17 | * MA 02110-1301, USA. | |
18 | */ | |
19 | ||
20 | #include <linux/delay.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/mtd/mtd.h> | |
25 | #include <linux/mtd/nand.h> | |
26 | #include <linux/mtd/partitions.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/device.h> | |
29 | #include <linux/platform_device.h> | |
30 | #include <linux/clk.h> | |
31 | #include <linux/err.h> | |
32 | #include <linux/io.h> | |
63f1474c SH |
33 | #include <linux/irq.h> |
34 | #include <linux/completion.h> | |
34f6e157 SH |
35 | |
36 | #include <asm/mach/flash.h> | |
37 | #include <mach/mxc_nand.h> | |
9467114e | 38 | #include <mach/hardware.h> |
34f6e157 SH |
39 | |
40 | #define DRIVER_NAME "mxc_nand" | |
41 | ||
9467114e | 42 | #define nfc_is_v21() (cpu_is_mx25() || cpu_is_mx35()) |
a47bfd2e | 43 | #define nfc_is_v1() (cpu_is_mx31() || cpu_is_mx27() || cpu_is_mx21()) |
c97926dd | 44 | #define nfc_is_v3_2() (cpu_is_mx51() || cpu_is_mx53()) |
71ec5155 | 45 | #define nfc_is_v3() nfc_is_v3_2() |
9467114e | 46 | |
34f6e157 | 47 | /* Addresses for NFC registers */ |
1bc99180 SH |
48 | #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00) |
49 | #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04) | |
50 | #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06) | |
51 | #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08) | |
52 | #define NFC_V1_V2_CONFIG (host->regs + 0x0a) | |
53 | #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c) | |
54 | #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e) | |
55 | #define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10) | |
56 | #define NFC_V1_V2_WRPROT (host->regs + 0x12) | |
57 | #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14) | |
58 | #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16) | |
d178e3e8 BS |
59 | #define NFC_V21_UNLOCKSTART_BLKADDR0 (host->regs + 0x20) |
60 | #define NFC_V21_UNLOCKSTART_BLKADDR1 (host->regs + 0x24) | |
61 | #define NFC_V21_UNLOCKSTART_BLKADDR2 (host->regs + 0x28) | |
62 | #define NFC_V21_UNLOCKSTART_BLKADDR3 (host->regs + 0x2c) | |
63 | #define NFC_V21_UNLOCKEND_BLKADDR0 (host->regs + 0x22) | |
64 | #define NFC_V21_UNLOCKEND_BLKADDR1 (host->regs + 0x26) | |
65 | #define NFC_V21_UNLOCKEND_BLKADDR2 (host->regs + 0x2a) | |
66 | #define NFC_V21_UNLOCKEND_BLKADDR3 (host->regs + 0x2e) | |
1bc99180 SH |
67 | #define NFC_V1_V2_NF_WRPRST (host->regs + 0x18) |
68 | #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a) | |
69 | #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c) | |
70 | ||
6e85dfdc | 71 | #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0) |
1bc99180 SH |
72 | #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2) |
73 | #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3) | |
74 | #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4) | |
75 | #define NFC_V1_V2_CONFIG1_BIG (1 << 5) | |
76 | #define NFC_V1_V2_CONFIG1_RST (1 << 6) | |
77 | #define NFC_V1_V2_CONFIG1_CE (1 << 7) | |
b8db2f51 SH |
78 | #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8) |
79 | #define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9) | |
80 | #define NFC_V2_CONFIG1_FP_INT (1 << 11) | |
1bc99180 SH |
81 | |
82 | #define NFC_V1_V2_CONFIG2_INT (1 << 15) | |
83 | ||
84 | /* | |
85 | * Operation modes for the NFC. Valid for v1, v2 and v3 | |
86 | * type controllers. | |
87 | */ | |
88 | #define NFC_CMD (1 << 0) | |
89 | #define NFC_ADDR (1 << 1) | |
90 | #define NFC_INPUT (1 << 2) | |
91 | #define NFC_OUTPUT (1 << 3) | |
92 | #define NFC_ID (1 << 4) | |
93 | #define NFC_STATUS (1 << 5) | |
34f6e157 | 94 | |
71ec5155 SH |
95 | #define NFC_V3_FLASH_CMD (host->regs_axi + 0x00) |
96 | #define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04) | |
97 | ||
98 | #define NFC_V3_CONFIG1 (host->regs_axi + 0x34) | |
99 | #define NFC_V3_CONFIG1_SP_EN (1 << 0) | |
100 | #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4) | |
101 | ||
102 | #define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38) | |
103 | ||
104 | #define NFC_V3_LAUNCH (host->regs_axi + 0x40) | |
105 | ||
106 | #define NFC_V3_WRPROT (host->regs_ip + 0x0) | |
107 | #define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0) | |
108 | #define NFC_V3_WRPROT_LOCK (1 << 1) | |
109 | #define NFC_V3_WRPROT_UNLOCK (1 << 2) | |
110 | #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6) | |
111 | ||
112 | #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04) | |
113 | ||
114 | #define NFC_V3_CONFIG2 (host->regs_ip + 0x24) | |
115 | #define NFC_V3_CONFIG2_PS_512 (0 << 0) | |
116 | #define NFC_V3_CONFIG2_PS_2048 (1 << 0) | |
117 | #define NFC_V3_CONFIG2_PS_4096 (2 << 0) | |
118 | #define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2) | |
119 | #define NFC_V3_CONFIG2_ECC_EN (1 << 3) | |
120 | #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4) | |
121 | #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5) | |
122 | #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6) | |
123 | #define NFC_V3_CONFIG2_PPB(x) (((x) & 0x3) << 7) | |
124 | #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12) | |
125 | #define NFC_V3_CONFIG2_INT_MSK (1 << 15) | |
126 | #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24) | |
127 | #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16) | |
128 | ||
129 | #define NFC_V3_CONFIG3 (host->regs_ip + 0x28) | |
130 | #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0) | |
131 | #define NFC_V3_CONFIG3_FW8 (1 << 3) | |
132 | #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8) | |
133 | #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12) | |
134 | #define NFC_V3_CONFIG3_RBB_MODE (1 << 15) | |
135 | #define NFC_V3_CONFIG3_NO_SDMA (1 << 20) | |
136 | ||
137 | #define NFC_V3_IPC (host->regs_ip + 0x2C) | |
138 | #define NFC_V3_IPC_CREQ (1 << 0) | |
139 | #define NFC_V3_IPC_INT (1 << 31) | |
140 | ||
141 | #define NFC_V3_DELAY_LINE (host->regs_ip + 0x34) | |
34f6e157 | 142 | |
e4303b25 UKK |
143 | struct mxc_nand_host; |
144 | ||
145 | struct mxc_nand_devtype_data { | |
146 | void (*preset)(struct mtd_info *); | |
147 | void (*send_cmd)(struct mxc_nand_host *, uint16_t, int); | |
148 | void (*send_addr)(struct mxc_nand_host *, uint16_t, int); | |
149 | void (*send_page)(struct mtd_info *, unsigned int); | |
150 | void (*send_read_id)(struct mxc_nand_host *); | |
151 | uint16_t (*get_dev_status)(struct mxc_nand_host *); | |
152 | int (*check_int)(struct mxc_nand_host *); | |
153 | void (*irq_control)(struct mxc_nand_host *, int); | |
6d38af25 | 154 | u32 (*get_ecc_status)(struct mxc_nand_host *); |
6dcdf99d | 155 | struct nand_ecclayout *ecclayout_512, *ecclayout_2k, *ecclayout_4k; |
5e05a2d6 | 156 | void (*select_chip)(struct mtd_info *mtd, int chip); |
e4303b25 UKK |
157 | }; |
158 | ||
34f6e157 SH |
159 | struct mxc_nand_host { |
160 | struct mtd_info mtd; | |
161 | struct nand_chip nand; | |
34f6e157 SH |
162 | struct device *dev; |
163 | ||
c6de7e1b SH |
164 | void *spare0; |
165 | void *main_area0; | |
c6de7e1b SH |
166 | |
167 | void __iomem *base; | |
34f6e157 | 168 | void __iomem *regs; |
71ec5155 SH |
169 | void __iomem *regs_axi; |
170 | void __iomem *regs_ip; | |
34f6e157 | 171 | int status_request; |
34f6e157 SH |
172 | struct clk *clk; |
173 | int clk_act; | |
174 | int irq; | |
94f77e50 | 175 | int eccsize; |
d178e3e8 | 176 | int active_cs; |
34f6e157 | 177 | |
63f1474c | 178 | struct completion op_completion; |
34f6e157 | 179 | |
f8f9608d SH |
180 | uint8_t *data_buf; |
181 | unsigned int buf_start; | |
182 | int spare_len; | |
5f97304e | 183 | |
e4303b25 | 184 | const struct mxc_nand_devtype_data *devtype_data; |
8556958a UKK |
185 | |
186 | /* | |
187 | * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked | |
188 | * (CONFIG1:INT_MSK is set). To handle this the driver uses | |
189 | * enable_irq/disable_irq_nosync instead of CONFIG1:INT_MSK | |
190 | */ | |
191 | int irqpending_quirk; | |
34f6e157 SH |
192 | }; |
193 | ||
34f6e157 | 194 | /* OOB placement block for use with hardware ecc generation */ |
9467114e | 195 | static struct nand_ecclayout nandv1_hw_eccoob_smallpage = { |
34f6e157 SH |
196 | .eccbytes = 5, |
197 | .eccpos = {6, 7, 8, 9, 10}, | |
8c1fd89a | 198 | .oobfree = {{0, 5}, {12, 4}, } |
bd3fd62e VB |
199 | }; |
200 | ||
9467114e | 201 | static struct nand_ecclayout nandv1_hw_eccoob_largepage = { |
bd3fd62e VB |
202 | .eccbytes = 20, |
203 | .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26, | |
204 | 38, 39, 40, 41, 42, 54, 55, 56, 57, 58}, | |
205 | .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, } | |
34f6e157 SH |
206 | }; |
207 | ||
9467114e SH |
208 | /* OOB description for 512 byte pages with 16 byte OOB */ |
209 | static struct nand_ecclayout nandv2_hw_eccoob_smallpage = { | |
210 | .eccbytes = 1 * 9, | |
211 | .eccpos = { | |
212 | 7, 8, 9, 10, 11, 12, 13, 14, 15 | |
213 | }, | |
214 | .oobfree = { | |
215 | {.offset = 0, .length = 5} | |
216 | } | |
217 | }; | |
218 | ||
219 | /* OOB description for 2048 byte pages with 64 byte OOB */ | |
220 | static struct nand_ecclayout nandv2_hw_eccoob_largepage = { | |
221 | .eccbytes = 4 * 9, | |
222 | .eccpos = { | |
223 | 7, 8, 9, 10, 11, 12, 13, 14, 15, | |
224 | 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
225 | 39, 40, 41, 42, 43, 44, 45, 46, 47, | |
226 | 55, 56, 57, 58, 59, 60, 61, 62, 63 | |
227 | }, | |
228 | .oobfree = { | |
229 | {.offset = 2, .length = 4}, | |
230 | {.offset = 16, .length = 7}, | |
231 | {.offset = 32, .length = 7}, | |
232 | {.offset = 48, .length = 7} | |
233 | } | |
234 | }; | |
235 | ||
2c1c5f19 BS |
236 | /* OOB description for 4096 byte pages with 128 byte OOB */ |
237 | static struct nand_ecclayout nandv2_hw_eccoob_4k = { | |
238 | .eccbytes = 8 * 9, | |
239 | .eccpos = { | |
240 | 7, 8, 9, 10, 11, 12, 13, 14, 15, | |
241 | 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
242 | 39, 40, 41, 42, 43, 44, 45, 46, 47, | |
243 | 55, 56, 57, 58, 59, 60, 61, 62, 63, | |
244 | 71, 72, 73, 74, 75, 76, 77, 78, 79, | |
245 | 87, 88, 89, 90, 91, 92, 93, 94, 95, | |
246 | 103, 104, 105, 106, 107, 108, 109, 110, 111, | |
247 | 119, 120, 121, 122, 123, 124, 125, 126, 127, | |
248 | }, | |
249 | .oobfree = { | |
250 | {.offset = 2, .length = 4}, | |
251 | {.offset = 16, .length = 7}, | |
252 | {.offset = 32, .length = 7}, | |
253 | {.offset = 48, .length = 7}, | |
254 | {.offset = 64, .length = 7}, | |
255 | {.offset = 80, .length = 7}, | |
256 | {.offset = 96, .length = 7}, | |
257 | {.offset = 112, .length = 7}, | |
258 | } | |
259 | }; | |
260 | ||
34f6e157 | 261 | static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL }; |
34f6e157 | 262 | |
71ec5155 SH |
263 | static int check_int_v3(struct mxc_nand_host *host) |
264 | { | |
265 | uint32_t tmp; | |
266 | ||
267 | tmp = readl(NFC_V3_IPC); | |
268 | if (!(tmp & NFC_V3_IPC_INT)) | |
269 | return 0; | |
270 | ||
271 | tmp &= ~NFC_V3_IPC_INT; | |
272 | writel(tmp, NFC_V3_IPC); | |
273 | ||
274 | return 1; | |
275 | } | |
276 | ||
7aaf28ac SH |
277 | static int check_int_v1_v2(struct mxc_nand_host *host) |
278 | { | |
279 | uint32_t tmp; | |
280 | ||
1bc99180 SH |
281 | tmp = readw(NFC_V1_V2_CONFIG2); |
282 | if (!(tmp & NFC_V1_V2_CONFIG2_INT)) | |
7aaf28ac SH |
283 | return 0; |
284 | ||
8556958a | 285 | if (!host->irqpending_quirk) |
63f1474c | 286 | writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2); |
7aaf28ac SH |
287 | |
288 | return 1; | |
289 | } | |
290 | ||
63f1474c SH |
291 | static void irq_control_v1_v2(struct mxc_nand_host *host, int activate) |
292 | { | |
293 | uint16_t tmp; | |
294 | ||
295 | tmp = readw(NFC_V1_V2_CONFIG1); | |
296 | ||
297 | if (activate) | |
298 | tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK; | |
299 | else | |
300 | tmp |= NFC_V1_V2_CONFIG1_INT_MSK; | |
301 | ||
302 | writew(tmp, NFC_V1_V2_CONFIG1); | |
303 | } | |
304 | ||
305 | static void irq_control_v3(struct mxc_nand_host *host, int activate) | |
306 | { | |
307 | uint32_t tmp; | |
308 | ||
309 | tmp = readl(NFC_V3_CONFIG2); | |
310 | ||
311 | if (activate) | |
312 | tmp &= ~NFC_V3_CONFIG2_INT_MSK; | |
313 | else | |
314 | tmp |= NFC_V3_CONFIG2_INT_MSK; | |
315 | ||
316 | writel(tmp, NFC_V3_CONFIG2); | |
317 | } | |
318 | ||
8556958a UKK |
319 | static void irq_control(struct mxc_nand_host *host, int activate) |
320 | { | |
321 | if (host->irqpending_quirk) { | |
322 | if (activate) | |
323 | enable_irq(host->irq); | |
324 | else | |
325 | disable_irq_nosync(host->irq); | |
326 | } else { | |
e4303b25 | 327 | host->devtype_data->irq_control(host, activate); |
8556958a UKK |
328 | } |
329 | } | |
330 | ||
6d38af25 UKK |
331 | static u32 get_ecc_status_v1(struct mxc_nand_host *host) |
332 | { | |
333 | return readw(NFC_V1_V2_ECC_STATUS_RESULT); | |
334 | } | |
335 | ||
336 | static u32 get_ecc_status_v2(struct mxc_nand_host *host) | |
337 | { | |
338 | return readl(NFC_V1_V2_ECC_STATUS_RESULT); | |
339 | } | |
340 | ||
341 | static u32 get_ecc_status_v3(struct mxc_nand_host *host) | |
342 | { | |
343 | return readl(NFC_V3_ECC_STATUS_RESULT); | |
344 | } | |
345 | ||
8556958a UKK |
346 | static irqreturn_t mxc_nfc_irq(int irq, void *dev_id) |
347 | { | |
348 | struct mxc_nand_host *host = dev_id; | |
349 | ||
e4303b25 | 350 | if (!host->devtype_data->check_int(host)) |
8556958a UKK |
351 | return IRQ_NONE; |
352 | ||
353 | irq_control(host, 0); | |
354 | ||
355 | complete(&host->op_completion); | |
356 | ||
357 | return IRQ_HANDLED; | |
358 | } | |
359 | ||
34f6e157 SH |
360 | /* This function polls the NANDFC to wait for the basic operation to |
361 | * complete by checking the INT bit of config2 register. | |
362 | */ | |
c110eaf4 | 363 | static void wait_op_done(struct mxc_nand_host *host, int useirq) |
34f6e157 | 364 | { |
a47bfd2e | 365 | int max_retries = 8000; |
34f6e157 SH |
366 | |
367 | if (useirq) { | |
e4303b25 | 368 | if (!host->devtype_data->check_int(host)) { |
63f1474c | 369 | INIT_COMPLETION(host->op_completion); |
8556958a | 370 | irq_control(host, 1); |
63f1474c | 371 | wait_for_completion(&host->op_completion); |
34f6e157 SH |
372 | } |
373 | } else { | |
374 | while (max_retries-- > 0) { | |
e4303b25 | 375 | if (host->devtype_data->check_int(host)) |
34f6e157 | 376 | break; |
7aaf28ac | 377 | |
34f6e157 SH |
378 | udelay(1); |
379 | } | |
43950a60 | 380 | if (max_retries < 0) |
0a32a102 | 381 | pr_debug("%s: INT not set\n", __func__); |
34f6e157 SH |
382 | } |
383 | } | |
384 | ||
71ec5155 SH |
385 | static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq) |
386 | { | |
387 | /* fill command */ | |
388 | writel(cmd, NFC_V3_FLASH_CMD); | |
389 | ||
390 | /* send out command */ | |
391 | writel(NFC_CMD, NFC_V3_LAUNCH); | |
392 | ||
393 | /* Wait for operation to complete */ | |
394 | wait_op_done(host, useirq); | |
395 | } | |
396 | ||
34f6e157 SH |
397 | /* This function issues the specified command to the NAND device and |
398 | * waits for completion. */ | |
5f97304e | 399 | static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq) |
34f6e157 | 400 | { |
289c0522 | 401 | pr_debug("send_cmd(host, 0x%x, %d)\n", cmd, useirq); |
34f6e157 | 402 | |
1bc99180 SH |
403 | writew(cmd, NFC_V1_V2_FLASH_CMD); |
404 | writew(NFC_CMD, NFC_V1_V2_CONFIG2); | |
34f6e157 | 405 | |
8556958a | 406 | if (host->irqpending_quirk && (cmd == NAND_CMD_RESET)) { |
a47bfd2e IC |
407 | int max_retries = 100; |
408 | /* Reset completion is indicated by NFC_CONFIG2 */ | |
409 | /* being set to 0 */ | |
410 | while (max_retries-- > 0) { | |
1bc99180 | 411 | if (readw(NFC_V1_V2_CONFIG2) == 0) { |
a47bfd2e IC |
412 | break; |
413 | } | |
414 | udelay(1); | |
415 | } | |
416 | if (max_retries < 0) | |
0a32a102 | 417 | pr_debug("%s: RESET failed\n", __func__); |
a47bfd2e IC |
418 | } else { |
419 | /* Wait for operation to complete */ | |
420 | wait_op_done(host, useirq); | |
421 | } | |
34f6e157 SH |
422 | } |
423 | ||
71ec5155 SH |
424 | static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast) |
425 | { | |
426 | /* fill address */ | |
427 | writel(addr, NFC_V3_FLASH_ADDR0); | |
428 | ||
429 | /* send out address */ | |
430 | writel(NFC_ADDR, NFC_V3_LAUNCH); | |
431 | ||
432 | wait_op_done(host, 0); | |
433 | } | |
434 | ||
34f6e157 SH |
435 | /* This function sends an address (or partial address) to the |
436 | * NAND device. The address is used to select the source/destination for | |
437 | * a NAND command. */ | |
5f97304e | 438 | static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast) |
34f6e157 | 439 | { |
289c0522 | 440 | pr_debug("send_addr(host, 0x%x %d)\n", addr, islast); |
34f6e157 | 441 | |
1bc99180 SH |
442 | writew(addr, NFC_V1_V2_FLASH_ADDR); |
443 | writew(NFC_ADDR, NFC_V1_V2_CONFIG2); | |
34f6e157 SH |
444 | |
445 | /* Wait for operation to complete */ | |
c110eaf4 | 446 | wait_op_done(host, islast); |
34f6e157 SH |
447 | } |
448 | ||
71ec5155 SH |
449 | static void send_page_v3(struct mtd_info *mtd, unsigned int ops) |
450 | { | |
451 | struct nand_chip *nand_chip = mtd->priv; | |
452 | struct mxc_nand_host *host = nand_chip->priv; | |
453 | uint32_t tmp; | |
454 | ||
455 | tmp = readl(NFC_V3_CONFIG1); | |
456 | tmp &= ~(7 << 4); | |
457 | writel(tmp, NFC_V3_CONFIG1); | |
458 | ||
459 | /* transfer data from NFC ram to nand */ | |
460 | writel(ops, NFC_V3_LAUNCH); | |
461 | ||
462 | wait_op_done(host, false); | |
463 | } | |
464 | ||
6d38af25 UKK |
465 | static void send_page_v2(struct mtd_info *mtd, unsigned int ops) |
466 | { | |
467 | struct nand_chip *nand_chip = mtd->priv; | |
468 | struct mxc_nand_host *host = nand_chip->priv; | |
469 | ||
470 | /* NANDFC buffer 0 is used for page read/write */ | |
471 | writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR); | |
472 | ||
473 | writew(ops, NFC_V1_V2_CONFIG2); | |
474 | ||
475 | /* Wait for operation to complete */ | |
476 | wait_op_done(host, true); | |
477 | } | |
478 | ||
479 | static void send_page_v1(struct mtd_info *mtd, unsigned int ops) | |
34f6e157 | 480 | { |
2d69c7fa SH |
481 | struct nand_chip *nand_chip = mtd->priv; |
482 | struct mxc_nand_host *host = nand_chip->priv; | |
c5d23f1b | 483 | int bufs, i; |
34f6e157 | 484 | |
6d38af25 | 485 | if (mtd->writesize > 512) |
c5d23f1b SH |
486 | bufs = 4; |
487 | else | |
488 | bufs = 1; | |
34f6e157 | 489 | |
c5d23f1b | 490 | for (i = 0; i < bufs; i++) { |
34f6e157 | 491 | |
c5d23f1b | 492 | /* NANDFC buffer 0 is used for page read/write */ |
d178e3e8 | 493 | writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR); |
34f6e157 | 494 | |
1bc99180 | 495 | writew(ops, NFC_V1_V2_CONFIG2); |
34f6e157 | 496 | |
c5d23f1b | 497 | /* Wait for operation to complete */ |
c110eaf4 | 498 | wait_op_done(host, true); |
34f6e157 | 499 | } |
34f6e157 SH |
500 | } |
501 | ||
71ec5155 SH |
502 | static void send_read_id_v3(struct mxc_nand_host *host) |
503 | { | |
504 | /* Read ID into main buffer */ | |
505 | writel(NFC_ID, NFC_V3_LAUNCH); | |
506 | ||
507 | wait_op_done(host, true); | |
508 | ||
509 | memcpy(host->data_buf, host->main_area0, 16); | |
510 | } | |
511 | ||
34f6e157 | 512 | /* Request the NANDFC to perform a read of the NAND device ID. */ |
5f97304e | 513 | static void send_read_id_v1_v2(struct mxc_nand_host *host) |
34f6e157 SH |
514 | { |
515 | struct nand_chip *this = &host->nand; | |
34f6e157 SH |
516 | |
517 | /* NANDFC buffer 0 is used for device ID output */ | |
d178e3e8 | 518 | writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR); |
34f6e157 | 519 | |
1bc99180 | 520 | writew(NFC_ID, NFC_V1_V2_CONFIG2); |
34f6e157 SH |
521 | |
522 | /* Wait for operation to complete */ | |
c110eaf4 | 523 | wait_op_done(host, true); |
34f6e157 | 524 | |
f7b66e5e JO |
525 | memcpy(host->data_buf, host->main_area0, 16); |
526 | ||
34f6e157 | 527 | if (this->options & NAND_BUSWIDTH_16) { |
34f6e157 | 528 | /* compress the ID info */ |
f7b66e5e JO |
529 | host->data_buf[1] = host->data_buf[2]; |
530 | host->data_buf[2] = host->data_buf[4]; | |
531 | host->data_buf[3] = host->data_buf[6]; | |
532 | host->data_buf[4] = host->data_buf[8]; | |
533 | host->data_buf[5] = host->data_buf[10]; | |
34f6e157 SH |
534 | } |
535 | } | |
536 | ||
71ec5155 SH |
537 | static uint16_t get_dev_status_v3(struct mxc_nand_host *host) |
538 | { | |
539 | writew(NFC_STATUS, NFC_V3_LAUNCH); | |
540 | wait_op_done(host, true); | |
541 | ||
542 | return readl(NFC_V3_CONFIG1) >> 16; | |
543 | } | |
544 | ||
34f6e157 SH |
545 | /* This function requests the NANDFC to perform a read of the |
546 | * NAND device status and returns the current status. */ | |
5f97304e | 547 | static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host) |
34f6e157 | 548 | { |
c29c607a | 549 | void __iomem *main_buf = host->main_area0; |
34f6e157 | 550 | uint32_t store; |
f06368f7 | 551 | uint16_t ret; |
34f6e157 | 552 | |
d178e3e8 | 553 | writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR); |
34f6e157 | 554 | |
c29c607a SH |
555 | /* |
556 | * The device status is stored in main_area0. To | |
557 | * prevent corruption of the buffer save the value | |
558 | * and restore it afterwards. | |
559 | */ | |
34f6e157 | 560 | store = readl(main_buf); |
34f6e157 | 561 | |
1bc99180 | 562 | writew(NFC_STATUS, NFC_V1_V2_CONFIG2); |
c110eaf4 | 563 | wait_op_done(host, true); |
34f6e157 | 564 | |
34f6e157 | 565 | ret = readw(main_buf); |
c29c607a | 566 | |
34f6e157 SH |
567 | writel(store, main_buf); |
568 | ||
569 | return ret; | |
570 | } | |
571 | ||
572 | /* This functions is used by upper layer to checks if device is ready */ | |
573 | static int mxc_nand_dev_ready(struct mtd_info *mtd) | |
574 | { | |
575 | /* | |
576 | * NFC handles R/B internally. Therefore, this function | |
577 | * always returns status as ready. | |
578 | */ | |
579 | return 1; | |
580 | } | |
581 | ||
582 | static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode) | |
583 | { | |
584 | /* | |
585 | * If HW ECC is enabled, we turn it on during init. There is | |
586 | * no need to enable again here. | |
587 | */ | |
588 | } | |
589 | ||
94f77e50 | 590 | static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat, |
34f6e157 SH |
591 | u_char *read_ecc, u_char *calc_ecc) |
592 | { | |
593 | struct nand_chip *nand_chip = mtd->priv; | |
594 | struct mxc_nand_host *host = nand_chip->priv; | |
595 | ||
596 | /* | |
597 | * 1-Bit errors are automatically corrected in HW. No need for | |
598 | * additional correction. 2-Bit errors cannot be corrected by | |
599 | * HW ECC, so we need to return failure | |
600 | */ | |
6d38af25 | 601 | uint16_t ecc_status = get_ecc_status_v1(host); |
34f6e157 SH |
602 | |
603 | if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) { | |
289c0522 | 604 | pr_debug("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n"); |
34f6e157 SH |
605 | return -1; |
606 | } | |
607 | ||
608 | return 0; | |
609 | } | |
610 | ||
94f77e50 SH |
611 | static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat, |
612 | u_char *read_ecc, u_char *calc_ecc) | |
613 | { | |
614 | struct nand_chip *nand_chip = mtd->priv; | |
615 | struct mxc_nand_host *host = nand_chip->priv; | |
616 | u32 ecc_stat, err; | |
617 | int no_subpages = 1; | |
618 | int ret = 0; | |
619 | u8 ecc_bit_mask, err_limit; | |
620 | ||
621 | ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf; | |
622 | err_limit = (host->eccsize == 4) ? 0x4 : 0x8; | |
623 | ||
624 | no_subpages = mtd->writesize >> 9; | |
625 | ||
6d38af25 | 626 | ecc_stat = host->devtype_data->get_ecc_status(host); |
94f77e50 SH |
627 | |
628 | do { | |
629 | err = ecc_stat & ecc_bit_mask; | |
630 | if (err > err_limit) { | |
631 | printk(KERN_WARNING "UnCorrectable RS-ECC Error\n"); | |
632 | return -1; | |
633 | } else { | |
634 | ret += err; | |
635 | } | |
636 | ecc_stat >>= 4; | |
637 | } while (--no_subpages); | |
638 | ||
639 | mtd->ecc_stats.corrected += ret; | |
640 | pr_debug("%d Symbol Correctable RS-ECC Error\n", ret); | |
641 | ||
642 | return ret; | |
643 | } | |
644 | ||
34f6e157 SH |
645 | static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, |
646 | u_char *ecc_code) | |
647 | { | |
648 | return 0; | |
649 | } | |
650 | ||
651 | static u_char mxc_nand_read_byte(struct mtd_info *mtd) | |
652 | { | |
653 | struct nand_chip *nand_chip = mtd->priv; | |
654 | struct mxc_nand_host *host = nand_chip->priv; | |
f8f9608d | 655 | uint8_t ret; |
34f6e157 SH |
656 | |
657 | /* Check for status request */ | |
658 | if (host->status_request) | |
e4303b25 | 659 | return host->devtype_data->get_dev_status(host) & 0xFF; |
34f6e157 | 660 | |
f8f9608d SH |
661 | ret = *(uint8_t *)(host->data_buf + host->buf_start); |
662 | host->buf_start++; | |
34f6e157 SH |
663 | |
664 | return ret; | |
665 | } | |
666 | ||
667 | static uint16_t mxc_nand_read_word(struct mtd_info *mtd) | |
668 | { | |
669 | struct nand_chip *nand_chip = mtd->priv; | |
670 | struct mxc_nand_host *host = nand_chip->priv; | |
f8f9608d | 671 | uint16_t ret; |
34f6e157 | 672 | |
f8f9608d SH |
673 | ret = *(uint16_t *)(host->data_buf + host->buf_start); |
674 | host->buf_start += 2; | |
34f6e157 SH |
675 | |
676 | return ret; | |
677 | } | |
678 | ||
679 | /* Write data of length len to buffer buf. The data to be | |
680 | * written on NAND Flash is first copied to RAMbuffer. After the Data Input | |
681 | * Operation by the NFC, the data is written to NAND Flash */ | |
682 | static void mxc_nand_write_buf(struct mtd_info *mtd, | |
683 | const u_char *buf, int len) | |
684 | { | |
685 | struct nand_chip *nand_chip = mtd->priv; | |
686 | struct mxc_nand_host *host = nand_chip->priv; | |
f8f9608d SH |
687 | u16 col = host->buf_start; |
688 | int n = mtd->oobsize + mtd->writesize - col; | |
34f6e157 | 689 | |
f8f9608d | 690 | n = min(n, len); |
34f6e157 | 691 | |
f8f9608d | 692 | memcpy(host->data_buf + col, buf, n); |
34f6e157 | 693 | |
f8f9608d | 694 | host->buf_start += n; |
34f6e157 SH |
695 | } |
696 | ||
697 | /* Read the data buffer from the NAND Flash. To read the data from NAND | |
698 | * Flash first the data output cycle is initiated by the NFC, which copies | |
699 | * the data to RAMbuffer. This data of length len is then copied to buffer buf. | |
700 | */ | |
701 | static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) | |
702 | { | |
703 | struct nand_chip *nand_chip = mtd->priv; | |
704 | struct mxc_nand_host *host = nand_chip->priv; | |
f8f9608d SH |
705 | u16 col = host->buf_start; |
706 | int n = mtd->oobsize + mtd->writesize - col; | |
34f6e157 | 707 | |
f8f9608d | 708 | n = min(n, len); |
34f6e157 | 709 | |
5d9d9936 | 710 | memcpy(buf, host->data_buf + col, n); |
34f6e157 | 711 | |
5d9d9936 | 712 | host->buf_start += n; |
34f6e157 SH |
713 | } |
714 | ||
715 | /* Used by the upper layer to verify the data in NAND Flash | |
716 | * with the data in the buf. */ | |
717 | static int mxc_nand_verify_buf(struct mtd_info *mtd, | |
718 | const u_char *buf, int len) | |
719 | { | |
720 | return -EFAULT; | |
721 | } | |
722 | ||
723 | /* This function is used by upper layer for select and | |
724 | * deselect of the NAND chip */ | |
5e05a2d6 | 725 | static void mxc_nand_select_chip_v1_v3(struct mtd_info *mtd, int chip) |
34f6e157 SH |
726 | { |
727 | struct nand_chip *nand_chip = mtd->priv; | |
728 | struct mxc_nand_host *host = nand_chip->priv; | |
729 | ||
d178e3e8 | 730 | if (chip == -1) { |
34f6e157 SH |
731 | /* Disable the NFC clock */ |
732 | if (host->clk_act) { | |
733 | clk_disable(host->clk); | |
734 | host->clk_act = 0; | |
735 | } | |
d178e3e8 BS |
736 | return; |
737 | } | |
738 | ||
739 | if (!host->clk_act) { | |
34f6e157 | 740 | /* Enable the NFC clock */ |
d178e3e8 BS |
741 | clk_enable(host->clk); |
742 | host->clk_act = 1; | |
743 | } | |
5e05a2d6 UKK |
744 | } |
745 | ||
746 | static void mxc_nand_select_chip_v2(struct mtd_info *mtd, int chip) | |
747 | { | |
748 | struct nand_chip *nand_chip = mtd->priv; | |
749 | struct mxc_nand_host *host = nand_chip->priv; | |
750 | ||
751 | if (chip == -1) { | |
752 | /* Disable the NFC clock */ | |
753 | if (host->clk_act) { | |
754 | clk_disable(host->clk); | |
755 | host->clk_act = 0; | |
756 | } | |
757 | return; | |
758 | } | |
34f6e157 | 759 | |
5e05a2d6 UKK |
760 | if (!host->clk_act) { |
761 | /* Enable the NFC clock */ | |
762 | clk_enable(host->clk); | |
763 | host->clk_act = 1; | |
34f6e157 | 764 | } |
5e05a2d6 UKK |
765 | |
766 | host->active_cs = chip; | |
767 | writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR); | |
34f6e157 SH |
768 | } |
769 | ||
f8f9608d SH |
770 | /* |
771 | * Function to transfer data to/from spare area. | |
772 | */ | |
773 | static void copy_spare(struct mtd_info *mtd, bool bfrom) | |
34f6e157 | 774 | { |
f8f9608d SH |
775 | struct nand_chip *this = mtd->priv; |
776 | struct mxc_nand_host *host = this->priv; | |
777 | u16 i, j; | |
778 | u16 n = mtd->writesize >> 9; | |
779 | u8 *d = host->data_buf + mtd->writesize; | |
c6de7e1b | 780 | u8 *s = host->spare0; |
f8f9608d SH |
781 | u16 t = host->spare_len; |
782 | ||
783 | j = (mtd->oobsize / n >> 1) << 1; | |
784 | ||
785 | if (bfrom) { | |
786 | for (i = 0; i < n - 1; i++) | |
787 | memcpy(d + i * j, s + i * t, j); | |
788 | ||
789 | /* the last section */ | |
790 | memcpy(d + i * j, s + i * t, mtd->oobsize - i * j); | |
791 | } else { | |
792 | for (i = 0; i < n - 1; i++) | |
793 | memcpy(&s[i * t], &d[i * j], j); | |
34f6e157 | 794 | |
f8f9608d SH |
795 | /* the last section */ |
796 | memcpy(&s[i * t], &d[i * j], mtd->oobsize - i * j); | |
34f6e157 | 797 | } |
f8f9608d | 798 | } |
34f6e157 | 799 | |
a3e65b64 SH |
800 | static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr) |
801 | { | |
802 | struct nand_chip *nand_chip = mtd->priv; | |
803 | struct mxc_nand_host *host = nand_chip->priv; | |
34f6e157 SH |
804 | |
805 | /* Write out column address, if necessary */ | |
806 | if (column != -1) { | |
807 | /* | |
808 | * MXC NANDFC can only perform full page+spare or | |
809 | * spare-only read/write. When the upper layers | |
177b241d GE |
810 | * perform a read/write buf operation, the saved column |
811 | * address is used to index into the full page. | |
34f6e157 | 812 | */ |
e4303b25 | 813 | host->devtype_data->send_addr(host, 0, page_addr == -1); |
2d69c7fa | 814 | if (mtd->writesize > 512) |
34f6e157 | 815 | /* another col addr cycle for 2k page */ |
e4303b25 | 816 | host->devtype_data->send_addr(host, 0, false); |
34f6e157 SH |
817 | } |
818 | ||
819 | /* Write out page address, if necessary */ | |
820 | if (page_addr != -1) { | |
821 | /* paddr_0 - p_addr_7 */ | |
e4303b25 | 822 | host->devtype_data->send_addr(host, (page_addr & 0xff), false); |
34f6e157 | 823 | |
2d69c7fa | 824 | if (mtd->writesize > 512) { |
bd3fd62e VB |
825 | if (mtd->size >= 0x10000000) { |
826 | /* paddr_8 - paddr_15 */ | |
e4303b25 UKK |
827 | host->devtype_data->send_addr(host, |
828 | (page_addr >> 8) & 0xff, | |
829 | false); | |
830 | host->devtype_data->send_addr(host, | |
831 | (page_addr >> 16) & 0xff, | |
832 | true); | |
bd3fd62e VB |
833 | } else |
834 | /* paddr_8 - paddr_15 */ | |
e4303b25 UKK |
835 | host->devtype_data->send_addr(host, |
836 | (page_addr >> 8) & 0xff, true); | |
34f6e157 SH |
837 | } else { |
838 | /* One more address cycle for higher density devices */ | |
839 | if (mtd->size >= 0x4000000) { | |
840 | /* paddr_8 - paddr_15 */ | |
e4303b25 UKK |
841 | host->devtype_data->send_addr(host, |
842 | (page_addr >> 8) & 0xff, | |
843 | false); | |
844 | host->devtype_data->send_addr(host, | |
845 | (page_addr >> 16) & 0xff, | |
846 | true); | |
34f6e157 SH |
847 | } else |
848 | /* paddr_8 - paddr_15 */ | |
e4303b25 UKK |
849 | host->devtype_data->send_addr(host, |
850 | (page_addr >> 8) & 0xff, true); | |
34f6e157 SH |
851 | } |
852 | } | |
a3e65b64 SH |
853 | } |
854 | ||
6e85dfdc SH |
855 | /* |
856 | * v2 and v3 type controllers can do 4bit or 8bit ecc depending | |
857 | * on how much oob the nand chip has. For 8bit ecc we need at least | |
858 | * 26 bytes of oob data per 512 byte block. | |
859 | */ | |
860 | static int get_eccsize(struct mtd_info *mtd) | |
861 | { | |
862 | int oobbytes_per_512 = 0; | |
863 | ||
864 | oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize; | |
865 | ||
866 | if (oobbytes_per_512 < 26) | |
867 | return 4; | |
868 | else | |
869 | return 8; | |
870 | } | |
871 | ||
6d38af25 | 872 | static void preset_v1(struct mtd_info *mtd) |
d4840180 IC |
873 | { |
874 | struct nand_chip *nand_chip = mtd->priv; | |
875 | struct mxc_nand_host *host = nand_chip->priv; | |
b8db2f51 SH |
876 | uint16_t config1 = 0; |
877 | ||
878 | if (nand_chip->ecc.mode == NAND_ECC_HW) | |
879 | config1 |= NFC_V1_V2_CONFIG1_ECC_EN; | |
880 | ||
6d38af25 UKK |
881 | if (!host->irqpending_quirk) |
882 | config1 |= NFC_V1_V2_CONFIG1_INT_MSK; | |
883 | ||
884 | host->eccsize = 1; | |
885 | ||
886 | writew(config1, NFC_V1_V2_CONFIG1); | |
887 | /* preset operation */ | |
888 | ||
889 | /* Unlock the internal RAM Buffer */ | |
890 | writew(0x2, NFC_V1_V2_CONFIG); | |
891 | ||
892 | /* Blocks to be unlocked */ | |
893 | writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR); | |
894 | writew(0xffff, NFC_V1_UNLOCKEND_BLKADDR); | |
895 | ||
896 | /* Unlock Block Command for given address range */ | |
897 | writew(0x4, NFC_V1_V2_WRPROT); | |
898 | } | |
899 | ||
900 | static void preset_v2(struct mtd_info *mtd) | |
901 | { | |
902 | struct nand_chip *nand_chip = mtd->priv; | |
903 | struct mxc_nand_host *host = nand_chip->priv; | |
904 | uint16_t config1 = 0; | |
905 | ||
906 | if (nand_chip->ecc.mode == NAND_ECC_HW) | |
907 | config1 |= NFC_V1_V2_CONFIG1_ECC_EN; | |
908 | ||
909 | config1 |= NFC_V2_CONFIG1_FP_INT; | |
b8db2f51 | 910 | |
8556958a | 911 | if (!host->irqpending_quirk) |
b8db2f51 | 912 | config1 |= NFC_V1_V2_CONFIG1_INT_MSK; |
6e85dfdc | 913 | |
6d38af25 | 914 | if (mtd->writesize) { |
b8db2f51 SH |
915 | uint16_t pages_per_block = mtd->erasesize / mtd->writesize; |
916 | ||
6e85dfdc SH |
917 | host->eccsize = get_eccsize(mtd); |
918 | if (host->eccsize == 4) | |
b8db2f51 SH |
919 | config1 |= NFC_V2_CONFIG1_ECC_MODE_4; |
920 | ||
921 | config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6); | |
d4840180 | 922 | } else { |
6e85dfdc | 923 | host->eccsize = 1; |
d4840180 | 924 | } |
6e85dfdc | 925 | |
b8db2f51 | 926 | writew(config1, NFC_V1_V2_CONFIG1); |
d4840180 IC |
927 | /* preset operation */ |
928 | ||
929 | /* Unlock the internal RAM Buffer */ | |
1bc99180 | 930 | writew(0x2, NFC_V1_V2_CONFIG); |
d4840180 IC |
931 | |
932 | /* Blocks to be unlocked */ | |
6d38af25 UKK |
933 | writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0); |
934 | writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1); | |
935 | writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2); | |
936 | writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3); | |
937 | writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0); | |
938 | writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1); | |
939 | writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2); | |
940 | writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3); | |
d4840180 IC |
941 | |
942 | /* Unlock Block Command for given address range */ | |
1bc99180 | 943 | writew(0x4, NFC_V1_V2_WRPROT); |
d4840180 IC |
944 | } |
945 | ||
71ec5155 SH |
946 | static void preset_v3(struct mtd_info *mtd) |
947 | { | |
948 | struct nand_chip *chip = mtd->priv; | |
949 | struct mxc_nand_host *host = chip->priv; | |
950 | uint32_t config2, config3; | |
951 | int i, addr_phases; | |
952 | ||
953 | writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1); | |
954 | writel(NFC_V3_IPC_CREQ, NFC_V3_IPC); | |
955 | ||
956 | /* Unlock the internal RAM Buffer */ | |
957 | writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK, | |
958 | NFC_V3_WRPROT); | |
959 | ||
960 | /* Blocks to be unlocked */ | |
961 | for (i = 0; i < NAND_MAX_CHIPS; i++) | |
962 | writel(0x0 | (0xffff << 16), | |
963 | NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2)); | |
964 | ||
965 | writel(0, NFC_V3_IPC); | |
966 | ||
967 | config2 = NFC_V3_CONFIG2_ONE_CYCLE | | |
968 | NFC_V3_CONFIG2_2CMD_PHASES | | |
969 | NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) | | |
970 | NFC_V3_CONFIG2_ST_CMD(0x70) | | |
63f1474c | 971 | NFC_V3_CONFIG2_INT_MSK | |
71ec5155 SH |
972 | NFC_V3_CONFIG2_NUM_ADDR_PHASE0; |
973 | ||
974 | if (chip->ecc.mode == NAND_ECC_HW) | |
975 | config2 |= NFC_V3_CONFIG2_ECC_EN; | |
976 | ||
977 | addr_phases = fls(chip->pagemask) >> 3; | |
978 | ||
979 | if (mtd->writesize == 2048) { | |
980 | config2 |= NFC_V3_CONFIG2_PS_2048; | |
981 | config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases); | |
982 | } else if (mtd->writesize == 4096) { | |
983 | config2 |= NFC_V3_CONFIG2_PS_4096; | |
984 | config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases); | |
985 | } else { | |
986 | config2 |= NFC_V3_CONFIG2_PS_512; | |
987 | config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1); | |
988 | } | |
989 | ||
990 | if (mtd->writesize) { | |
991 | config2 |= NFC_V3_CONFIG2_PPB(ffs(mtd->erasesize / mtd->writesize) - 6); | |
992 | host->eccsize = get_eccsize(mtd); | |
993 | if (host->eccsize == 8) | |
994 | config2 |= NFC_V3_CONFIG2_ECC_MODE_8; | |
995 | } | |
996 | ||
997 | writel(config2, NFC_V3_CONFIG2); | |
998 | ||
999 | config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) | | |
1000 | NFC_V3_CONFIG3_NO_SDMA | | |
1001 | NFC_V3_CONFIG3_RBB_MODE | | |
1002 | NFC_V3_CONFIG3_SBB(6) | /* Reset default */ | |
1003 | NFC_V3_CONFIG3_ADD_OP(0); | |
1004 | ||
1005 | if (!(chip->options & NAND_BUSWIDTH_16)) | |
1006 | config3 |= NFC_V3_CONFIG3_FW8; | |
1007 | ||
1008 | writel(config3, NFC_V3_CONFIG3); | |
1009 | ||
1010 | writel(0, NFC_V3_DELAY_LINE); | |
d4840180 IC |
1011 | } |
1012 | ||
34f6e157 SH |
1013 | /* Used by the upper layer to write command to NAND Flash for |
1014 | * different operations to be carried out on NAND Flash */ | |
1015 | static void mxc_nand_command(struct mtd_info *mtd, unsigned command, | |
1016 | int column, int page_addr) | |
1017 | { | |
1018 | struct nand_chip *nand_chip = mtd->priv; | |
1019 | struct mxc_nand_host *host = nand_chip->priv; | |
34f6e157 | 1020 | |
289c0522 | 1021 | pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n", |
34f6e157 SH |
1022 | command, column, page_addr); |
1023 | ||
1024 | /* Reset command state information */ | |
1025 | host->status_request = false; | |
34f6e157 | 1026 | |
34f6e157 | 1027 | /* Command pre-processing step */ |
34f6e157 | 1028 | switch (command) { |
d4840180 | 1029 | case NAND_CMD_RESET: |
e4303b25 UKK |
1030 | host->devtype_data->preset(mtd); |
1031 | host->devtype_data->send_cmd(host, command, false); | |
d4840180 | 1032 | break; |
34f6e157 | 1033 | |
34f6e157 | 1034 | case NAND_CMD_STATUS: |
f8f9608d | 1035 | host->buf_start = 0; |
34f6e157 | 1036 | host->status_request = true; |
34f6e157 | 1037 | |
e4303b25 | 1038 | host->devtype_data->send_cmd(host, command, true); |
89121a6b | 1039 | mxc_do_addr_cycle(mtd, column, page_addr); |
34f6e157 SH |
1040 | break; |
1041 | ||
34f6e157 | 1042 | case NAND_CMD_READ0: |
34f6e157 | 1043 | case NAND_CMD_READOOB: |
89121a6b SH |
1044 | if (command == NAND_CMD_READ0) |
1045 | host->buf_start = column; | |
1046 | else | |
1047 | host->buf_start = column + mtd->writesize; | |
f8f9608d | 1048 | |
5ea32021 | 1049 | command = NAND_CMD_READ0; /* only READ0 is valid */ |
89121a6b | 1050 | |
e4303b25 | 1051 | host->devtype_data->send_cmd(host, command, false); |
89121a6b SH |
1052 | mxc_do_addr_cycle(mtd, column, page_addr); |
1053 | ||
2d69c7fa | 1054 | if (mtd->writesize > 512) |
e4303b25 UKK |
1055 | host->devtype_data->send_cmd(host, |
1056 | NAND_CMD_READSTART, true); | |
c5d23f1b | 1057 | |
e4303b25 | 1058 | host->devtype_data->send_page(mtd, NFC_OUTPUT); |
89121a6b | 1059 | |
c6de7e1b | 1060 | memcpy(host->data_buf, host->main_area0, mtd->writesize); |
89121a6b | 1061 | copy_spare(mtd, true); |
34f6e157 SH |
1062 | break; |
1063 | ||
34f6e157 | 1064 | case NAND_CMD_SEQIN: |
5ea32021 SH |
1065 | if (column >= mtd->writesize) |
1066 | /* call ourself to read a page */ | |
1067 | mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr); | |
34f6e157 | 1068 | |
5ea32021 | 1069 | host->buf_start = column; |
89121a6b | 1070 | |
e4303b25 | 1071 | host->devtype_data->send_cmd(host, command, false); |
89121a6b | 1072 | mxc_do_addr_cycle(mtd, column, page_addr); |
34f6e157 SH |
1073 | break; |
1074 | ||
1075 | case NAND_CMD_PAGEPROG: | |
c6de7e1b | 1076 | memcpy(host->main_area0, host->data_buf, mtd->writesize); |
f8f9608d | 1077 | copy_spare(mtd, false); |
e4303b25 UKK |
1078 | host->devtype_data->send_page(mtd, NFC_INPUT); |
1079 | host->devtype_data->send_cmd(host, command, true); | |
89121a6b | 1080 | mxc_do_addr_cycle(mtd, column, page_addr); |
34f6e157 SH |
1081 | break; |
1082 | ||
34f6e157 | 1083 | case NAND_CMD_READID: |
e4303b25 | 1084 | host->devtype_data->send_cmd(host, command, true); |
89121a6b | 1085 | mxc_do_addr_cycle(mtd, column, page_addr); |
e4303b25 | 1086 | host->devtype_data->send_read_id(host); |
9467114e | 1087 | host->buf_start = column; |
34f6e157 SH |
1088 | break; |
1089 | ||
89121a6b | 1090 | case NAND_CMD_ERASE1: |
34f6e157 | 1091 | case NAND_CMD_ERASE2: |
e4303b25 | 1092 | host->devtype_data->send_cmd(host, command, false); |
89121a6b SH |
1093 | mxc_do_addr_cycle(mtd, column, page_addr); |
1094 | ||
34f6e157 SH |
1095 | break; |
1096 | } | |
1097 | } | |
1098 | ||
f1372055 SH |
1099 | /* |
1100 | * The generic flash bbt decriptors overlap with our ecc | |
1101 | * hardware, so define some i.MX specific ones. | |
1102 | */ | |
1103 | static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' }; | |
1104 | static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' }; | |
1105 | ||
1106 | static struct nand_bbt_descr bbt_main_descr = { | |
1107 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
1108 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
1109 | .offs = 0, | |
1110 | .len = 4, | |
1111 | .veroffs = 4, | |
1112 | .maxblocks = 4, | |
1113 | .pattern = bbt_pattern, | |
1114 | }; | |
1115 | ||
1116 | static struct nand_bbt_descr bbt_mirror_descr = { | |
1117 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
1118 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
1119 | .offs = 0, | |
1120 | .len = 4, | |
1121 | .veroffs = 4, | |
1122 | .maxblocks = 4, | |
1123 | .pattern = mirror_pattern, | |
1124 | }; | |
1125 | ||
e4303b25 UKK |
1126 | /* v1: i.MX21, i.MX27, i.MX31 */ |
1127 | static const struct mxc_nand_devtype_data imx21_nand_devtype_data = { | |
6d38af25 | 1128 | .preset = preset_v1, |
e4303b25 UKK |
1129 | .send_cmd = send_cmd_v1_v2, |
1130 | .send_addr = send_addr_v1_v2, | |
6d38af25 | 1131 | .send_page = send_page_v1, |
e4303b25 UKK |
1132 | .send_read_id = send_read_id_v1_v2, |
1133 | .get_dev_status = get_dev_status_v1_v2, | |
1134 | .check_int = check_int_v1_v2, | |
1135 | .irq_control = irq_control_v1_v2, | |
6d38af25 | 1136 | .get_ecc_status = get_ecc_status_v1, |
6dcdf99d UKK |
1137 | .ecclayout_512 = &nandv1_hw_eccoob_smallpage, |
1138 | .ecclayout_2k = &nandv1_hw_eccoob_largepage, | |
1139 | .ecclayout_4k = &nandv1_hw_eccoob_smallpage, /* XXX: needs fix */ | |
5e05a2d6 | 1140 | .select_chip = mxc_nand_select_chip_v1_v3, |
e4303b25 UKK |
1141 | }; |
1142 | ||
1143 | /* v21: i.MX25, i.MX35 */ | |
1144 | static const struct mxc_nand_devtype_data imx25_nand_devtype_data = { | |
6d38af25 | 1145 | .preset = preset_v2, |
e4303b25 UKK |
1146 | .send_cmd = send_cmd_v1_v2, |
1147 | .send_addr = send_addr_v1_v2, | |
6d38af25 | 1148 | .send_page = send_page_v2, |
e4303b25 UKK |
1149 | .send_read_id = send_read_id_v1_v2, |
1150 | .get_dev_status = get_dev_status_v1_v2, | |
1151 | .check_int = check_int_v1_v2, | |
1152 | .irq_control = irq_control_v1_v2, | |
6d38af25 | 1153 | .get_ecc_status = get_ecc_status_v2, |
6dcdf99d UKK |
1154 | .ecclayout_512 = &nandv2_hw_eccoob_smallpage, |
1155 | .ecclayout_2k = &nandv2_hw_eccoob_largepage, | |
1156 | .ecclayout_4k = &nandv2_hw_eccoob_4k, | |
5e05a2d6 | 1157 | .select_chip = mxc_nand_select_chip_v2, |
e4303b25 UKK |
1158 | }; |
1159 | ||
1160 | /* v3: i.MX51, i.MX53 */ | |
1161 | static const struct mxc_nand_devtype_data imx51_nand_devtype_data = { | |
1162 | .preset = preset_v3, | |
1163 | .send_cmd = send_cmd_v3, | |
1164 | .send_addr = send_addr_v3, | |
1165 | .send_page = send_page_v3, | |
1166 | .send_read_id = send_read_id_v3, | |
1167 | .get_dev_status = get_dev_status_v3, | |
1168 | .check_int = check_int_v3, | |
1169 | .irq_control = irq_control_v3, | |
6d38af25 | 1170 | .get_ecc_status = get_ecc_status_v3, |
6dcdf99d UKK |
1171 | .ecclayout_512 = &nandv2_hw_eccoob_smallpage, |
1172 | .ecclayout_2k = &nandv2_hw_eccoob_largepage, | |
1173 | .ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */ | |
5e05a2d6 | 1174 | .select_chip = mxc_nand_select_chip_v1_v3, |
e4303b25 UKK |
1175 | }; |
1176 | ||
34f6e157 SH |
1177 | static int __init mxcnd_probe(struct platform_device *pdev) |
1178 | { | |
1179 | struct nand_chip *this; | |
1180 | struct mtd_info *mtd; | |
1181 | struct mxc_nand_platform_data *pdata = pdev->dev.platform_data; | |
1182 | struct mxc_nand_host *host; | |
1183 | struct resource *res; | |
d4ed8f12 | 1184 | int err = 0; |
34f6e157 SH |
1185 | |
1186 | /* Allocate memory for MTD device structure and private data */ | |
f8f9608d SH |
1187 | host = kzalloc(sizeof(struct mxc_nand_host) + NAND_MAX_PAGESIZE + |
1188 | NAND_MAX_OOBSIZE, GFP_KERNEL); | |
34f6e157 SH |
1189 | if (!host) |
1190 | return -ENOMEM; | |
1191 | ||
f8f9608d | 1192 | host->data_buf = (uint8_t *)(host + 1); |
f8f9608d | 1193 | |
34f6e157 SH |
1194 | host->dev = &pdev->dev; |
1195 | /* structures must be linked */ | |
1196 | this = &host->nand; | |
1197 | mtd = &host->mtd; | |
1198 | mtd->priv = this; | |
1199 | mtd->owner = THIS_MODULE; | |
87f39f04 | 1200 | mtd->dev.parent = &pdev->dev; |
1fbff0a6 | 1201 | mtd->name = DRIVER_NAME; |
34f6e157 SH |
1202 | |
1203 | /* 50 us command delay time */ | |
1204 | this->chip_delay = 5; | |
1205 | ||
1206 | this->priv = host; | |
1207 | this->dev_ready = mxc_nand_dev_ready; | |
1208 | this->cmdfunc = mxc_nand_command; | |
34f6e157 SH |
1209 | this->read_byte = mxc_nand_read_byte; |
1210 | this->read_word = mxc_nand_read_word; | |
1211 | this->write_buf = mxc_nand_write_buf; | |
1212 | this->read_buf = mxc_nand_read_buf; | |
1213 | this->verify_buf = mxc_nand_verify_buf; | |
1214 | ||
e65fb009 | 1215 | host->clk = clk_get(&pdev->dev, "nfc"); |
8541c118 VB |
1216 | if (IS_ERR(host->clk)) { |
1217 | err = PTR_ERR(host->clk); | |
34f6e157 | 1218 | goto eclk; |
8541c118 | 1219 | } |
34f6e157 SH |
1220 | |
1221 | clk_enable(host->clk); | |
1222 | host->clk_act = 1; | |
1223 | ||
1224 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1225 | if (!res) { | |
1226 | err = -ENODEV; | |
1227 | goto eres; | |
1228 | } | |
1229 | ||
c6de7e1b SH |
1230 | host->base = ioremap(res->start, resource_size(res)); |
1231 | if (!host->base) { | |
8541c118 | 1232 | err = -ENOMEM; |
34f6e157 SH |
1233 | goto eres; |
1234 | } | |
1235 | ||
c6de7e1b | 1236 | host->main_area0 = host->base; |
9467114e | 1237 | |
e4303b25 UKK |
1238 | if (nfc_is_v1()) { |
1239 | host->devtype_data = &imx21_nand_devtype_data; | |
63f1474c | 1240 | if (cpu_is_mx21()) |
8556958a | 1241 | host->irqpending_quirk = 1; |
938cf997 | 1242 | host->regs = host->base + 0xe00; |
9467114e SH |
1243 | host->spare0 = host->base + 0x800; |
1244 | host->spare_len = 16; | |
9467114e | 1245 | this->ecc.bytes = 3; |
71ec5155 | 1246 | host->eccsize = 1; |
e4303b25 UKK |
1247 | } else if (nfc_is_v21()) { |
1248 | host->devtype_data = &imx25_nand_devtype_data; | |
1249 | host->regs = host->base + 0x1e00; | |
1250 | host->spare0 = host->base + 0x1000; | |
1251 | host->spare_len = 64; | |
e4303b25 | 1252 | this->ecc.bytes = 9; |
71ec5155 | 1253 | } else if (nfc_is_v3_2()) { |
e4303b25 | 1254 | host->devtype_data = &imx51_nand_devtype_data; |
71ec5155 SH |
1255 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
1256 | if (!res) { | |
1257 | err = -ENODEV; | |
1258 | goto eirq; | |
1259 | } | |
1260 | host->regs_ip = ioremap(res->start, resource_size(res)); | |
1261 | if (!host->regs_ip) { | |
1262 | err = -ENOMEM; | |
1263 | goto eirq; | |
1264 | } | |
1265 | host->regs_axi = host->base + 0x1e00; | |
1266 | host->spare0 = host->base + 0x1000; | |
1267 | host->spare_len = 64; | |
9467114e SH |
1268 | } else |
1269 | BUG(); | |
13e1add1 | 1270 | |
5e05a2d6 | 1271 | this->select_chip = host->devtype_data->select_chip; |
13e1add1 | 1272 | this->ecc.size = 512; |
6dcdf99d | 1273 | this->ecc.layout = host->devtype_data->ecclayout_512; |
13e1add1 | 1274 | |
34f6e157 SH |
1275 | if (pdata->hw_ecc) { |
1276 | this->ecc.calculate = mxc_nand_calculate_ecc; | |
1277 | this->ecc.hwctl = mxc_nand_enable_hwecc; | |
94f77e50 SH |
1278 | if (nfc_is_v1()) |
1279 | this->ecc.correct = mxc_nand_correct_data_v1; | |
1280 | else | |
1281 | this->ecc.correct = mxc_nand_correct_data_v2_v3; | |
34f6e157 | 1282 | this->ecc.mode = NAND_ECC_HW; |
34f6e157 | 1283 | } else { |
34f6e157 | 1284 | this->ecc.mode = NAND_ECC_SOFT; |
34f6e157 SH |
1285 | } |
1286 | ||
34f6e157 | 1287 | /* NAND bus width determines access funtions used by upper layer */ |
13e1add1 | 1288 | if (pdata->width == 2) |
34f6e157 | 1289 | this->options |= NAND_BUSWIDTH_16; |
34f6e157 | 1290 | |
f1372055 SH |
1291 | if (pdata->flash_bbt) { |
1292 | this->bbt_td = &bbt_main_descr; | |
1293 | this->bbt_md = &bbt_mirror_descr; | |
1294 | /* update flash based bbt */ | |
bb9ebd4e | 1295 | this->bbt_options |= NAND_BBT_USE_FLASH; |
34f6e157 SH |
1296 | } |
1297 | ||
63f1474c | 1298 | init_completion(&host->op_completion); |
d4840180 IC |
1299 | |
1300 | host->irq = platform_get_irq(pdev, 0); | |
1301 | ||
63f1474c | 1302 | /* |
e4303b25 UKK |
1303 | * Use host->devtype_data->irq_control() here instead of irq_control() |
1304 | * because we must not disable_irq_nosync without having requested the | |
1305 | * irq. | |
63f1474c | 1306 | */ |
e4303b25 | 1307 | host->devtype_data->irq_control(host, 0); |
63f1474c | 1308 | |
a47bfd2e | 1309 | err = request_irq(host->irq, mxc_nfc_irq, IRQF_DISABLED, DRIVER_NAME, host); |
d4840180 IC |
1310 | if (err) |
1311 | goto eirq; | |
1312 | ||
63f1474c | 1313 | /* |
8556958a UKK |
1314 | * Now that we "own" the interrupt make sure the interrupt mask bit is |
1315 | * cleared on i.MX21. Otherwise we can't read the interrupt status bit | |
1316 | * on this machine. | |
63f1474c | 1317 | */ |
8556958a UKK |
1318 | if (host->irqpending_quirk) { |
1319 | disable_irq_nosync(host->irq); | |
e4303b25 | 1320 | host->devtype_data->irq_control(host, 1); |
8556958a | 1321 | } |
63f1474c | 1322 | |
bd3fd62e | 1323 | /* first scan to find the device and get the page size */ |
d178e3e8 | 1324 | if (nand_scan_ident(mtd, nfc_is_v21() ? 4 : 1, NULL)) { |
bd3fd62e VB |
1325 | err = -ENXIO; |
1326 | goto escan; | |
1327 | } | |
34f6e157 | 1328 | |
6e85dfdc | 1329 | /* Call preset again, with correct writesize this time */ |
e4303b25 | 1330 | host->devtype_data->preset(mtd); |
6e85dfdc | 1331 | |
2d69c7fa | 1332 | if (mtd->writesize == 2048) |
6dcdf99d UKK |
1333 | this->ecc.layout = host->devtype_data->ecclayout_2k; |
1334 | else if (mtd->writesize == 4096) | |
1335 | this->ecc.layout = host->devtype_data->ecclayout_4k; | |
bd3fd62e VB |
1336 | |
1337 | /* second phase scan */ | |
1338 | if (nand_scan_tail(mtd)) { | |
34f6e157 SH |
1339 | err = -ENXIO; |
1340 | goto escan; | |
1341 | } | |
1342 | ||
6a918bad MD |
1343 | if (this->ecc.mode == NAND_ECC_HW) { |
1344 | if (nfc_is_v1()) | |
1345 | this->ecc.strength = 1; | |
1346 | else | |
1347 | this->ecc.strength = (host->eccsize == 4) ? 4 : 8; | |
1348 | } | |
1349 | ||
34f6e157 | 1350 | /* Register the partitions */ |
42d7fbe2 AB |
1351 | mtd_device_parse_register(mtd, part_probes, NULL, pdata->parts, |
1352 | pdata->nr_parts); | |
34f6e157 SH |
1353 | |
1354 | platform_set_drvdata(pdev, host); | |
1355 | ||
1356 | return 0; | |
1357 | ||
1358 | escan: | |
b258fd8d | 1359 | free_irq(host->irq, host); |
34f6e157 | 1360 | eirq: |
71ec5155 SH |
1361 | if (host->regs_ip) |
1362 | iounmap(host->regs_ip); | |
c6de7e1b | 1363 | iounmap(host->base); |
34f6e157 SH |
1364 | eres: |
1365 | clk_put(host->clk); | |
1366 | eclk: | |
1367 | kfree(host); | |
1368 | ||
1369 | return err; | |
1370 | } | |
1371 | ||
51eeb878 | 1372 | static int __devexit mxcnd_remove(struct platform_device *pdev) |
34f6e157 SH |
1373 | { |
1374 | struct mxc_nand_host *host = platform_get_drvdata(pdev); | |
1375 | ||
1376 | clk_put(host->clk); | |
1377 | ||
1378 | platform_set_drvdata(pdev, NULL); | |
1379 | ||
1380 | nand_release(&host->mtd); | |
b258fd8d | 1381 | free_irq(host->irq, host); |
71ec5155 SH |
1382 | if (host->regs_ip) |
1383 | iounmap(host->regs_ip); | |
c6de7e1b | 1384 | iounmap(host->base); |
34f6e157 SH |
1385 | kfree(host); |
1386 | ||
1387 | return 0; | |
1388 | } | |
1389 | ||
34f6e157 SH |
1390 | static struct platform_driver mxcnd_driver = { |
1391 | .driver = { | |
1392 | .name = DRIVER_NAME, | |
8d1fd16d | 1393 | .owner = THIS_MODULE, |
04dd0d3a | 1394 | }, |
daa0f15a | 1395 | .remove = __devexit_p(mxcnd_remove), |
34f6e157 SH |
1396 | }; |
1397 | ||
1398 | static int __init mxc_nd_init(void) | |
1399 | { | |
8541c118 | 1400 | return platform_driver_probe(&mxcnd_driver, mxcnd_probe); |
34f6e157 SH |
1401 | } |
1402 | ||
1403 | static void __exit mxc_nd_cleanup(void) | |
1404 | { | |
1405 | /* Unregister the device structure */ | |
1406 | platform_driver_unregister(&mxcnd_driver); | |
1407 | } | |
1408 | ||
1409 | module_init(mxc_nd_init); | |
1410 | module_exit(mxc_nd_cleanup); | |
1411 | ||
1412 | MODULE_AUTHOR("Freescale Semiconductor, Inc."); | |
1413 | MODULE_DESCRIPTION("MXC NAND MTD driver"); | |
1414 | MODULE_LICENSE("GPL"); |